Semiconductor device and manufacturing process for it
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- MAGNACHIP SEMICON LTD
- Filing Date
- 2018-07-12
- Publication Date
- 2026-07-30
Smart Images
Figure 00000000_0000_ABST
Abstract
Claims
Semiconductor device comprising: a substrate (10); a first doping region (40) of a first conductivity type formed in a trough region (30) of a first conductivity type in the substrate (10); a second doping region (50) of a second conductivity type formed in the trough region of a first conductivity type (30) in the substrate (10) such that it is spaced apart from the first doping region of a first conductivity type; a source region (80) enclosed by the first doping region (40) of a first conductivity type; a drain region (90) enclosed by the second doping region (50) of a second conductivity type; a gate insulating film (310, 320) formed between the source region (80) and the drain region (90) and comprising: a first insulating region (110), a second insulating region (120) and a third isolation region (130),which are formed in the substrate (10); a gate insulating film (310) with a first thickness that is formed closer to the source region (80) than to the drain region (90); a gate insulating film (320) with a second thickness that is formed closer to the drain region (90) than to the source region (80), wherein the gate insulating film (320) with the second thickness has a greater thickness than the gate insulating film (310) with the first thickness; and a gate electrode (350) formed on the gate insulating film (310, 320), wherein the second insulating region (120) borders the first doping region (40) of a first conductivity type, and the third insulating region (130) borders the second doping region (50) of a second conductivity type, and wherein a lower part of the second insulating region (120) and a lower part of the third insulating region (130) are in contact with the trough region (30) of a first conductivity type,and the trough region (30) of a first conductivity type is arranged between the second insulating region (120) and the third insulating region (130), wherein the first to third insulating regions (110, 120, 130) are deeper than the first doping region (40) of a first conductivity type and the second doping region (50), the semiconductor device further comprising: a deep trough region (20) of a second conductivity type formed between the first and third insulating regions (110, 130); and a heavily doped region (60) of a second conductivity type formed between the first and second insulating regions (110, 120) and in contact with the deep trough region (20) of a second conductivity type. Semiconductor device according to claim 1, wherein the semiconductor device further comprises a connecting insulating film (330) arranged between the gate insulating film (310) of a first thickness and the gate insulating film (320) of a second thickness, wherein a bottom surface of the gate insulating film of the first thickness and a bottom surface of the gate insulating film of the second thickness are coplanar and wherein the thickness of the connecting insulating film varies from a thickness of the gate insulating film (310) of the first thickness to a thickness of the gate insulating film of the second thickness. Semiconductor device according to claim 1 or 2, wherein the gate electrode (350) covers more than half the length of the gate insulating film (320) of the second thickness. Semiconductor device according to claim 2 or 3, wherein a top surface of the interconnect insulating film (330) has a slope and wherein a top surface of the gate insulating film (310) with the first thickness and of the gate insulating film (320) with the second thickness are coplanar. Semiconductor device according to one of the preceding claims, wherein the first doping region (40) of a first conductivity type is configured such that it is extended to a partial length of the gate insulating film with the first thickness in a direction from the source region (80) to the drain region (90). Semiconductor device according to one of the preceding claims, wherein the second doping region (50) of a second conductivity type is configured such that it is extended to a partial length of the gate insulating film with the first thickness in a direction from the drain region (90) to the source region (80). Semiconductor device according to claim 6, wherein the second doping region (50) of a second conductivity type is configured such that it is extended only to a partial length of the gate insulating film (320) of the second thickness in a direction from the drain region (90) to the source region (80), and / or wherein the second doping region (50) of a second conductivity type traverses the gate insulating film (320) of the second thickness such that it is extended to a partial length of the interconnect insulating film (330) in a direction from the drain region (90) to the source region (80). Semiconductor device according to one of claims 2 to 7, wherein the connecting insulating film (330) connects the gate insulating film of the first thickness and the gate insulating film (320) of the second thickness. Semiconductor device according to one of the preceding claims, wherein the drain region (90) is spaced apart from the gate insulating film (320) of the second thickness. Semiconductor device according to one of the preceding claims, comprising: a silicide-blocking insulating film (270) arranged between the drain region (90) and the gate insulating film (320) of the second thickness, wherein the silicide-blocking insulating film (270) contacts a top surface of the substrate (10), and / or wherein the second doping region (50) of a second conductivity type contacts the silicide-blocking insulating film (270). Semiconductor device according to one of the preceding claims, comprising: a silicide (210, 220, 230) formed on the gate electrode (350), the source region (80) and the drain region (90). A method for fabricating a semiconductor device, comprising: forming a first well region (30) of a first conductivity type in a substrate (10); forming a first doping region (40) of a first conductivity type in the first well region (30); forming a second doping region (50) of a second conductivity type in the first well region (30); forming a first gate insulating film on the first well region (30), wherein the first gate insulating film comprises a gate insulating film of a first thickness and a gate insulating film of a second thickness, the second thickness being greater than the first thickness, and wherein a bottom surface of the gate insulating film of the first thickness and a bottom surface of the gate insulating film of the second thickness (320) are coplanar to each other; forming a first gate electrode (350) on the first gate insulating film; and forming a source region (80) and a drain region (90) in the substrate. (10)Forming a first insulating region (110), a second insulating region (120), and a third insulating region (130) in the substrate, wherein the gate insulating film of the first thickness is formed closer to the source region (80) than to the drain region, and the gate insulating film (120) of the second thickness is formed closer to the drain region (90) than to the source region (80), wherein the second insulating region (120) borders the first doping region (40) of the first conductivity type, and the third insulating region (130) borders the second doping region (50) of the second conductivity type, wherein a lower part of the second insulating region (120) and a lower part of the third insulating region (130) are in contact with the first trough region (30), and the first trough region (30) is arranged between the second insulating region (120) and the third insulating region (130), wherein the first to third Isolation region (110, 120,130) are formed deeper than the first doping region (40) and the second doping region (50), wherein the semiconductor device further comprises: a deep trough region (20) of a second conductivity type formed between the first and the third insulating region (110, 130); and a heavily doped region (60) of the second conductivity type formed between the first and the second insulating region (110, 120) and in contact with the deep trough region (20) of the second conductivity type. Method for manufacturing the semiconductor device according to claim 12, wherein the first gate insulating film further comprises a connecting insulating film that connects the gate insulating film (310) of the first thickness and the gate insulating film (320) of the second thickness, wherein the connecting insulating film is arranged between the gate insulating film (310) of the first thickness and the gate insulating film (320) of the second thickness, and wherein the thickness of the connecting insulating film varies from the thickness of the gate insulating film (310) of the first thickness to the thickness of the gate insulating film (320) of the second thickness. Method for manufacturing the semiconductor device according to claim 12 or 13, wherein the first gate electrode (350) covers more than half the length of the gate insulating film (320) with the second thickness. Method for manufacturing the semiconductor device according to one of claims 12 to 14, further comprising: forming the first doping region (40) of a first conductivity type and the second doping region (50) of a second conductivity type in the first trough region (30), wherein the source region (80) and the drain region are formed in the first doping region (40) of a first conductivity type and the second doping region of a second conductivity type, respectively. Method for manufacturing the semiconductor device according to any one of claims 12 to 15, further comprising: forming a second trough region of a first conductivity type, which is spaced apart from the first trough region (30); forming a second drift region of a second conductivity type in the second trough region of a first conductivity type; and forming a second gate insulating film in the second trough region of a first conductivity type, which has a thickness corresponding to the thickness of the gate insulating film (320) with the second thickness. Method for manufacturing the semiconductor device according to one of claims 12 to 16, further comprising: forming a third well region of a first conductivity type, which is spaced apart from the first well region (30); and forming a third gate insulating film in the third well region of a first conductivity type, which has a thickness corresponding to the thickness of the gate insulating film with the first thickness.