Base removal using metal cutting processes

Abstract

A method (200) comprising:forming (212) a gate stack (60) comprising:a first portion (60A) over a portion of a first semiconductor fin (66A);a second portion (60B) over a portion of a second semiconductor fin (66B); and a third section (69) connecting the first section (60A) to the second section (60B); performing an anisotropic etch (218) on the third section (69) of the gate stack (60) to form an opening (72) between the first section (60A) and the second section (60B), wherein a base section (60') of the third section (69) remains after the anisotropic etch (218); performing an additional isotropic etch (220) to thin a polymer layer (70) on a sidewall of the base section (60') and to expose the base section (60'); performing an isotropic etch (222) to remove a metal gate section (56) of the base section (60');andfilling (226) the opening (72) with a dielectric material;

Claims

[1] Method (200) comprising: Forming (212) a gate stack (60), comprising: a first portion (60A) over a portion of a first semiconductor fin (66A); a second portion (60B) over a portion of a second semiconductor fin (66B); and a third section (69) connecting the first section (60A) to the second section (60B); Performing an anisotropic etch (218) on the third portion (69) of the gate stack (60) to form an opening (72) between the first portion (60A) and the second portion (60B), leaving a pedestal portion (60') of the third portion (69) after the anisotropic etch (218); Performing an additional isotropic etching (220) to thin a polymer layer (70) on a sidewall of the base portion (60') and to expose the base portion (60'); Performing an isotropic etching (222) to remove a metal gate portion (56) of the base portion (60'); and Filling (226) the opening (72) with a dielectric material. [2] The method (200) of claim 1, wherein the isotropic etching (222) comprises a wet etching using a chemical solution containing ammonium fluoride (NH4F). [3] The method (200) of claim 1, wherein the isotropic etching (222) comprises dry etching using a process gas containing NF3. [4] The method (200) of any one of claims 1 to 3, wherein the additional isotropic etching (220) is performed using diluted HF and during the additional isotropic etching (220) the base portion (60') remains substantially unetched. [5] The method (200) of any preceding claim, wherein the isotropic etching (222) removes both a high-k dielectric portion (52) and a metal gate electrode portion (56) in the base portion (60') of the gate stack (60). [6] The method (200) of any one of claims 1 to 4, wherein the isotropic etching (222) removes a metal gate portion (56) of the base portion (60') of the gate stack (60) and leaves a high-k dielectric portion (52) of the base portion (60') of the gate stack (60). [7] The method (200) of claim 6, wherein the dielectric material is in contact with the high-k dielectric portion (52). [8] Method (200) comprising: Forming (212) a gate stack (60) between a first gate spacer (38) and a second gate spacer (38), the gate stack (60) comprising: a gate dielectric (54); and a metal electrode (56) over the gate dielectric (54); Etching (218) a first portion (69) of the gate stack (60) to expose sidewalls of the first gate spacer (38) and the second gate spacer (38); Depositing (218) a polymer layer (70) on the sidewalls of the first gate spacer (38) and the second gate spacer (38); Thinning (220) the polymer layer (70) to expose a base portion (60') of the gate stack (60), wherein the base portion (60') is overlapped by a portion of the first gate spacer (38); and Etching (222) a remaining portion of the metal electrode (56) in the base portion (60'). [9] The method (200) of claim 8, wherein after etching (222) the remaining portion of the metal electrode (56), a portion of the gate dielectric (54) remains in the base portion (60'). [10] The method (200) of claim 8 or 9, wherein the thinning (220) of the polymer layer (70) is performed using dilute HF solution as an etchant. [11] The method (200) of any one of claims 8 to 10, wherein the base portion (60') remains substantially unetched during the thinning (220) of the polymer layer (70). [12] The method (200) of any one of claims 8 to 11, wherein etching (222) the remaining portion of the metal electrode (56) comprises a first etching step (74) using NF3 as an etching gas. [13] The method (200) of claim 12, further comprising after the first etching step (74): Carrying out a curing step using oxygen as a process gas, wherein a remaining portion of the gate stack (60) is exposed to oxygen; and Performing a second etching step using NF3 as an etching gas. [14] The method (200) of any one of claims 8 to 13, further comprising filling (226) a dielectric material into an opening (72) left by etching the first portion (69) of the gate stack (60). [15] The method (200) of any one of claims 8 to 14, wherein the gate stack (60) further comprises a second portion (60A) and a third portion (60B) connected by the first portion (69), and both the second portion (60A) and the third portion (60B) are a gate electrode of a transistor (66A, 66B). [16] Method (200) comprising: Forming (212) a gate stack (60) comprising a gate dielectric (54) and a gate electrode (56) over the gate dielectric (54), wherein both the gate dielectric (54) and the gate electrode (56) comprise: a first portion (60A) over a portion of a first semiconductor fin (66A); a second portion (60B) over a portion of a second semiconductor fin (66B); and a third section (69) connecting the first section (60A) to the second section (60B); Etching (218, 222) the third portion (69) of the gate electrode (56) to electrically separate the first portion (60A) of the gate electrode (60) from the second portion (60B) of the gate electrode (60), wherein the third portion (69) of the gate dielectric (54) comprises a portion remaining after the etching (218, 222), and wherein the first portion (60A) of the gate dielectric (54) is physically connected to the second portion (60B) of the gate dielectric (54) through the remaining portion of the third portion of the gate dielectric, wherein the etching comprises a plurality of etch-deposition cycles; and Filling (226) an opening (72) left by the third portion (69) of the gate electrode (56) with a dielectric material. [17] The method (200) of claim 16, further comprising forming a gate spacer (38) on a sidewall of the gate stack (60), wherein the remaining portion of the third portion (69) of the gate dielectric (54) is overlapped by the gate spacer (38). [18] The method (200) of claim 16 or 17, wherein etching (218, 222) of the third portion (69) of the gate electrode (56) comprises: an anisotropic etching (218) for forming the opening (72), wherein the anisotropic etching (218) is performed until an upper surface of a shallow trench isolation region (22) is reached, which lies below the gate electrode (56); and an isotropic etching (222) for removing a remaining portion of the gate electrode (56). [19] The method of claim 18, wherein the isotropic etching (222) is performed using NF3 as an etching gas.

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