Broadcast Sampling Network

Abstract

A distributed test circuit comprising: a plurality of circuit partitions arranged in series to form a sampling path; wherein each of the circuit partitions comprises a sampling multiplexer, a test data register, and a segment insertion bit circuit; wherein the sampling multiplexer of each of the circuit partitions provides inputs for a corresponding test data register of each of the circuit partitions; control logic for generating a broadcast mode selection signal for the sampling multiplexer of each of the circuit partitions to put the test circuit into a broadcast mode when the broadcast mode selection signal is assured, and to put the test circuit into a daisy mode when the broadcast mode selection signal is not assured; and wherein each segment insertion bit circuit is operable to include or bypass the corresponding circuit partition from the sampling path.

Description

BACKGROUND

[0001] Daisy-chained Joint Test Action Group (JTAG) registers result in long read / write times because moving even a small amount of typical test data across multiple registers requires moving the entire chain. Chained JTAG registers also lead to long test data write cycles, even when replicating a small amount of test data across multiple JTAG registers.

[0002] Two simple broadcast network designs were discussed in the IEEE 1687 standard documentation. One of the designs (Fig. E.16, p. 232 of the IEEE 1687 standard document) offers the following configuration options for the sampling chain: a) all of the sampling segments (JTAG register instances) configured in broadcast mode, or b) all of the sampling segments configured in daisy-chain mode. Another design (Fig. E.15, p. 231 of the IEEE 1687 standard document) offers only the following configuration options for the sampling chain: a) all of the sampling segments (JTAG register instances) configured in broadcast mode, or b) exclusive reading from only one sampling segment at a time. SHORT DESCRIPTION

[0003] A new test sampling network circuit for use in integrated circuits is disclosed. It supports both broadcast and daisy sampling modes and allows selective bypassing of any test partition or partition cluster in both modes. The sampling network is IEEE 1687 compliant and includes an improved segment insertion bit (SIB) locking / unlocking function and an option to force-reset SIB displacement cells. Compared to conventional designs, these improvements reduce the time required to switch between broadcast and daisy sampling modes. The new sampling network also supports the creation of distributed designs for test and test circuit hierarchies. List of characters

[0004] To make it easy to identify the discussion of each particular element or action, the highest-value number(s) in a reference sign refer to the number of the character in which that element is first introduced. Fig. Figure 1 illustrates a sampling network 100 according to one exemplary embodiment. Fig. Figure 2 illustrates a cluster network 200 according to one exemplary embodiment. Fig. Figure 3 illustrates a conventional broadcast control bit circuit 300 . Fig. Figure 4 illustrates a segment introduction bit circuit 400 according to one exemplary embodiment. Fig. Figure 5 illustrates a time diagram for a SIB 500 according to one exemplary embodiment. Fig. Figure 6 illustrates a distributed DFT 600 according to one exemplary embodiment. Fig.Figure 7 illustrates a modified IEEE1500 Client 700 according to an exemplary implementation. Fig. Figure 8 illustrates a cluster wrapper connector 800 according to one exemplary embodiment. Fig. Figure 9 illustrates a sampling network 900 according to one exemplary embodiment. Fig. Figure 10 illustrates a cluster network 1000 according to one exemplary embodiment. DETAILED DESCRIPTION

[0005] In this context, “IEEE 1149” refers to correspondingly numbered IEEE specifications for a test access port and boundary scan architecture, also known as daisy-chained JTAG.

[0006] In this context, "IEEE 1500" refers to the IEEE 1500 standard for embedded core test, a scalable architecture specification that enables the reuse and integration of tests for embedded cores and associated circuitry. It avoids addressing analog circuits and focuses on facilitating efficient testing of digital aspects of systems-on-a-chip (SoCs). IEEE 1500 describes serial and parallel test access mechanisms (TAMs) and a set of instructions suitable for testing cores, SoC interconnects, and circuit layouts. Furthermore, IEEE 1500 defines features that enable core isolation and core protection.

[0007] In this context, "IEEE 1687" refers to the IEEE 1687 standard for accessing and controlling instrumentation embedded in a semiconductor device. This standard describes a methodology for accessing instrumentation embedded in a semiconductor device, without defining the instruments or their features themselves, via the IEEE 1149.1 test access port (TAP) and / or other signals. The elements of the methodology include a hardware architecture for the on-chip network connecting the instruments to the chip pins, a hardware description language for describing this network, and a software language and protocol for communicating with the instruments over this network.

[0008] In this context, "JTAG" refers to a hardware test and boundary sampling description originally written by the Joint Test Action Group. JTAG implements standards for on-chip instrumentation in electronic design automation (EDA) as a complementary tool to digital simulation. It specifies the use of a dedicated debug port, which implements a serial communication interface for low-overhead access without requiring direct external access to the system's address and data buses. This interface connects to an on-chip test access port (TAP), which implements a stateful protocol to access a set of test registers representing chip logic layers and device functions of different partitions. IEEE Standard 1149.1-1990 provides a specification for the implementation of JTAG in integrated circuits.

[0009] In this context, "wrapper" refers to logic at the boundary of a functional unit (i.e., a logic block that implements a defined function) within an integrated circuit. The wrapper allows various test circuits to be connected to the functional unit. The use of wrappers enables modular or partition-based debugging, diagnostics, and testing of the functional units.

[0010] Unless otherwise specified, the signal and register names and conventions used herein refer to the signals and registers of the same names referenced in the IEEE 1500 standard.

[0011] An efficient broadcast sampling network design, combined with a conventional daisy sampling network, can help improve test times. An efficient broadcast sampling network design can improve overall test time by reducing the time required to write common data to multiple JTAG registers. A network where JTAG registers can be used in both daisy and broadcast (parallel) modes, along with the option to selectively bypass any JTAG register in either mode, offers flexibility during read / write operations and reduces overall test time.

[0012] The new test sampling circuit(s) disclosed herein utilize aspects of the IEEE 1687 standard. The new broadcast sampling circuit is implemented as an IEEE 1500-based JTAG network for distributed DFT (Design for Test). However, it can be used in any test network that supports the IEEE 1687 standard. Compared to a simple JTAG network built on chip-level configurations (e.g., for a custom purpose), a distributed DFT architecture (built on chiplet / partition-level configurations) implemented with an IEEE 1500-based JTAG network offers improvements such as reduced top-level routing and congestion, easy insertion of test logic, hierarchical test network capability, and reusable test logic for different IP module instances.Furthermore, the distributed DFT architecture described herein improves the test process by reducing the verification effort and the completion time effort for each new IP module instantiation.

[0013] The new distributed DFT circuit features multiple IEEE 1500 clusters. Each of these clusters is associated with a functional unit such as a chiplet, sub-chiplet, padlet, user-defined unit, or IP module. In addition to the JTAG registers required for IEEE 1500 compliance, a cluster can also include automatically generated registers instantiated within the IEEE 1500 client logic. The IEEE 1500 clients within the clusters and the clusters within the chip are interconnected.

[0014] The new sampling network circuit therefore supports both broadcast sampling mode and daisy-chained sampling mode, and also allows for the selective bypassing of any test data register (TDR) or JTAG register in the sampling chain for both modes.

[0015] Furthermore, a new IEEE 1687-compliant segment insertion bit (SIB) circuit is disclosed, featuring an improved SIB locking / unlocking function (pipelined UpdateEn for the update cell) and an option to force a reset of the SIB displacement cells. These design improvements reduce the time required to switch between broadcast and daisy-chain sampling modes.

[0016] The new circuit enables the selective transmission of test data to some clients / clusters during broadcast mode, while bypassing the remaining clients / clusters. Exiting broadcast mode and entering daisy mode results in a deterministic daisy chain configuration. The daisy chain configuration upon exiting broadcast mode is independent of the previous broadcast mode configuration or the data moved during the last broadcast sample. Conventional solutions do not offer this feature. With existing solutions, the daisy chain configuration after exiting broadcast mode depends on the broadcast mode configuration or the data moved during the last broadcast sample.

[0017] The deterministic configuration of the daisy chain circuit has a minimum possible sample length when exiting broadcast mode. This reduces the time required to reconfigure the sample path for the next daisy-mode operation following the preceding broadcast mode operation.

[0018] The new sampling network circuit enables hierarchical test circuit designs while maintaining the aforementioned functionality. This allows sampling network circuits for JTAG registers to be implemented at the partition level within a cluster on a single chip and at the chip level between different clusters.

[0019] Fig. Figure 1 illustrates a sampling network 100 according to one exemplary implementation. The scanning network 100 includes a partition broadcast control bit 102 , parts or partitions 104 , a partition sampling multiplexer 106, a partition test data register 108 and partition segment insertion bits 110 .

[0020] The sampling network 100 based on the IEEE standard 1687 The sampling network 100 It can be operated in both broadcast mode and chain / daisy mode. The partition broadcast control bit 102 This generates in Fig. 1. Broadcast control signal (BCB_Out) shown. BCB_Out is used as a selection signal for each partition sampling multiplexer. 106 uses and supplies each partition test data register 108 with the broadcast test data input BROADCAST_TDI. The sampling network 100 It operates in broadcast mode when the BCB_Out signal is present or guaranteed, and switches to daisy mode when BCB_Out is deactivated or not guaranteed. During broadcast mode, the BROADCAST_TDI test data is simultaneously sent to all partition test data registers.108 Applied in parallel, and Test Data Out (TDO) performs the sample output data from the last partition (Par_D).

[0021] DAISY_TDI refers to test data that is in the sampling network. 100 starting from an immediately preceding partition and linked to a subsequent partition, or chained together with it.

[0022] The partition test data register 108 In each partition, using the partition segment insertion bits, 110 (SIB) can be bypassed or added to the active sampling path. The SIB design enables the correct and intended operation of the sampling network. 100 in broadcast mode and also reduces the time required to scan the network 100 to reconfigure after switching from broadcast mode to daisy mode.

[0023] Fig. Figure 2 illustrates a cluster network 200according to an example implementation. The cluster network 200 includes a cluster broadcast control bit 202 , cluster 204 , a cluster sampling multiplexer 206 , partitions 208 and cluster segment insertion bits 210 .

[0024] The sampling network introduced above 100 It also supports a network hierarchy. The one in Fig. 1 different partitions shown 104 can be like in Fig. 2 shown for clusters 204 be grouped. Fig. 2. The sampling network uses the cluster broadcast control bit. 202 , to enable broadcast and daisy modes at the chip level between the clusters 204 to support each of the clusters 204 includes a cluster sampling multiplexer 206 , partitions 208 and cluster segment insertion bits 210 Thus, the partition broadcast control bit can be used. 102and the cluster broadcast control bit 202 They can be used cooperatively to create a test hierarchy circuit.

[0025] Within each of the clusters 204 It can be like in Fig. Figure 1 shows a broadcast and daisy mode at the cluster level (by operating each of the cluster sampling multiplexers). 206 ) between the partitions. Each of the clusters 204 can be bypassed or added to the active sampling path by using the cluster SIBs (cluster segment insertion bits). 210 ) are used, which are similar to the partition segment insertion bits. 110 each sampling network 100 within the clusters, but at a partition-cluster level and not at the partition level.

[0026] During broadcast write operations at the chip level, the cluster segment insertion bits are 210 within each of the clusters 204locked. Therefore, the cluster segment insertion bits change. 210 their values ​​are not updated during broadcast write operations at the chip level.

[0027] Fig. Figure 3 illustrates a conventional broadcast control bit circuit 300 The broadcast control bit circuit 300 includes a multiplexer 302 , the inputs for a displacement cell 304 provides a multiplexer 306 , the inputs for an update cell 308 provides, and a gate 310 .

[0028] The broadcast control bit circuit 300 from Fig. 3 implements the ScanRegister module described in the IEEE1687 standard and controls the (operates the selection signal of the) in Fig. 1 partition sampling multiplexer shown 106 In a hierarchical network, the signal BCB_Out is derived from the cluster broadcast control bit. 202 used to control the partition broadcast control bit102 to lock in a similar way, but at the cluster level.

[0029] Fig. Figure 4 illustrates an improved segment insertion bit circuit. 400 According to one embodiment. The segment insertion bit circuit. 400 works with a test data register 410 In this embodiment, the segment insertion bit circuit comprises 400 a multiplexer 414 and a multiplexer 416 , the inputs for a displacement cell 418 provide a multiplexer 420 , the inputs for an update cell 422 provides, and furthermore an update pipeline 424 and a gate 426 , the inputs for controlling the multiplexer 420 provides. Table 1. SIB states SIB status Update cell SIB blocking (or BCB_Out) Test data register Test circuit mode Open and not stopped 1 0 Active Daisy Closed and not stopped 0 0 Bypass Daisy bypass Open and stopped 1 1 Active Broadcast Closed and suspended 0 1 Bypass Broadcast bypass

[0030] The in Fig. 4 improved segment insertion bit circuits shown 400is designed to implement the functions of the new sampling network 100 to support the segment insertion bit circuit. 400 can be based on the SIB_Freeze (BCB_Out) signal and the information in the update cell 422 stored value in the states shown in Table 1.

[0031] If the segment insertion bit circuit 400 If set to "open", it puts the partition into non-bypass mode and adds the test data register. 410 to the active sampling path. The segment insertion bit circuit 400 can be accessed by shifting a 1 (for example) into its shift cell. 418 and then an UpdateEn signal is performed, opening the gate. The UpdateEn signal feeds the gate. 426 and the gate exit 426 controls the selection input of the multiplexer 420 , which is the update cell 422 provided.

[0032] The update cell 422 ensures the SIB_Select signal, which controls the multiplexer 414 caused to select the input associated with the TDO2 signal, which is then processed via the multiplexer 416 to the displacement cell 418 is being managed.

[0033] In the closed state, the segment insertion bit circuit is active. 400 as a 1-bit bypass register. The segment insertion bit circuit 400 is achieved by shifting a value 0 into the displacement cell 418 (For example) closed, followed by an UpdateEn operation. This deactivates or prevents the SIB_Select signal from being guaranteed. The BCB_Out signal is broadcast to the gate. 426 routed. With regard to the SIB, the signal BCB_Out is in Fig. 4 is referred to as SIB_Freeze.

[0034] The SIB_Freeze signal prevents the UpdateEn signal from reaching the update cell. 422is applied. Thus, the segment insertion bit circuit 400 does not change its open or closed state (signal SIB_Select) during broadcast write mode, even if a different value is entered into the shift cell during the broadcast shift. 418 is shifted. The sampling network 100 is achieved through pipelining (e.g., using the update pipeline). 424 ) of the UpdateEn signal to the update cell 422 to eliminate an additional shift sequence that would be required to implement the segment insertion bit switching 400 Improved reconfiguration after a broadcast operation.

[0035] Using the update pipeline 424 to direct UpdateEn to the update cell 422 enables an end to broadcast write mode (and thus an unlocking of all partitioning segment insertion bits). 110) and an update of all unlocked SIBs using the same JTAG UpdateDR cycle.

[0036] Fig. Figure 5 illustrates a time series diagram for the SIB 500 for the segment insertion bit circuit 400 according to an exemplary implementation. The time history diagram for the SIB. 500 includes the timeline or timing for a SIB without a pipeline 502 and the timeline for a SIB with incoming UpdateDR 504.

[0037] Fig. Figure 5 shows the time sequence diagram for generating the selection input of the multiplexer. 420 in the segment insertion bit circuit 400 (designated as SIB_UpdateMux_Sel). The BCB that generates the BCB_Out (or SIB_Freeze) signal is set to zero ( 0The BCB is set to exit broadcast write mode. Exit is complete once the BCB receives an UpdateEn signal. This prevents the BCB_Out (or SIB_Freeze) signal from being guaranteed, thus disabling any partition broadcast control bit. 102 is unlocked and the next UpdateEn signal can be propagated to the SIB_UpdateMux_Sel input.

[0038] With an incoming UpdateEn signal, the same UpdateEn signal that updated the BCB to its reset value reaches the blocking gate (e.g., the gate) with a delay of one clock cycle. 426 ) the segment insertion bit circuit 400 . At this point, the SIB_Freeze signal was already deactivated or not guaranteed due to the BCB reset process in the previous cycle.

[0039] When exiting broadcast mode, the network switches to daisy mode. Therefore, any reconfiguration of the sampling path involves a shift through the daisy sampling chain. If all SIBs are in the closed state at this time (all TDRs are bypassed), reconfiguring the sampling chain requires a smaller sampling pattern, the size of which corresponds to the number of SIBs in the network. Therefore, when exiting broadcast write mode, the shift cells of the SIBs should contain zero. After the SIB_Freeze signal is disabled (as a result of exiting broadcast mode), the UpdateEn signal enters the update cell of the SIBs, and all SIBs will close. Thus, the length of the resulting daisy sampling chain after a broadcast sample does not depend on the last broadcast sampling configuration.This is achieved by overwriting the feedback signal to the displacement cell during UpdateDR (UpdateEn=1) with a zero when SIB_Freeze is enabled. Thus, at the time the forwarded signal UpdateEn arrives at the SIB, the SIB is in the following state: . i. The displacement cell 418 the segment insertion bit circuit 400 contains the value zero (as previously described). ii. The SIB_Freeze signal is deactivated and the update cell is unlocked. 422 the segment insertion bit circuit 400 .

[0040] Fig. Figure 6 illustrates a distributed DFT 600 according to one embodiment. The distributed DFT 600It includes a TestMaster-to-1500 converter 602, various wrapper connectors, and various wrapper clusters. Each wrapper cluster typically includes at least one IEEE1500 client 620 (typically more than one), organized in a chain.

[0041] The distributed DFT 600 It implements the IEEE 1500 test protocol. Fig. In diagrams 6 and others, WSI is the serial test data input to the wrapper, WSO is the serial data output of the wrapper, and WSC refers to serial control signals. All IEEE 1500 clusters (e.g., the IEEE 1500 wrapper / cluster) 612 , the IEEE1500 wrapper / cluster 614 , the IEEE1500 wrapper / cluster 616 ... the IEEE1500 wrapper / cluster 618 ) are created using wrapper connectors (e.g., the wrapper connector) 604 , of the wrapper connector 606 , of the wrapper connector 608 ... of the wrapper connector 610The IEEE 1500 clients (e.g., the IEEE 1500 client 620) within these clusters are chained together, and the IEEE 1500 clients (e.g., the IEEE 1500 client 620) (partition) within these clusters are also chained together. Each cluster is associated with a functional unit (logic block) of the chip under test. The wrapper connectors include IEEE 1500-compliant modules (e.g., the wrapper bypass register WBY or the wrapper instruction register WIR) that can be used to bypass the corresponding bypass associated with a particular wrapper connector. Each wrapper connector is connected to the TestMaster-to-1500 converter 602. The 1500 converter is a submodule of TestMaster, a component that accepts IEEE 1149-compliant JTAG signals. The 1500 converter transforms these signals from the IEEE 1149 protocol to the IEEE 1500 protocol. The output of TestMaster and all downstream modules operate with signals of the 1500 protocol.

[0042] The in Fig.The six depicted configurations of IEEE1500 clients (partition level), wrapper connectors, client network (cluster level) and cluster network (chip level) are modified to implement the improved IEEE1687 sampling network (e.g. sampling network). 100 ) to include. This enables the distributed DFT. 600 with efficient broadcast and daisy sampling modes, as previously described. The distributed DFT 600 The included modifications should not increase / decrease the JTAG register lengths compared to conventional approaches.

[0043] Fig. Figure 7 illustrates a modified IEEE1500 client 700 (e.g. the IEEE1500 client) 620 ) according to an exemplary implementation. The modified IEEE1500 client 700 includes a multiplexer 702 , a wrapper command register 704 , a register 706 , a register 708 , a wrapper border register 710 , a register 712, a gate 714 , a multiplexer 716 , a segment insertion bit 718 , a multiplexer 720 , a gate 722 , a gate 724 and an updateWR pipeline 726 .

[0044] At the partition level, the modified IEEE1500 client includes 700 the in Fig. 4. Illustration of the segment insertion bit circuit 400 The IEEE1500-compliant wrapper bypass (WBY) register was enhanced by the improved segment insertion bit. 718 replaced. The segment insertion bit 718 only adds the displacement cell 418 into the active sampling path, so that the sampling length does not change. On the new segment insertion bit. 718 It can be accessed on every data register shift because the segment insertion bit 718 always resides in the client's data path. These clients can now be used in a network such as the sampling network.100 be used.

[0045] Fig. Figure 8 illustrates a cluster wrapper connector 800 according to one embodiment. The cluster wrapper connector 800 includes a broadcast control bit 802 , a Shadow_WE 804 , a multiplexer 806 , a multiplexer 808 , an interface 810 and an interface 812 As mentioned above, WIR refers to a wrapper instruction register, and WBY refers to a wrapper bypass register.

[0046] Each IEEE 1500 cluster has a corresponding cluster wrapper connector. The cluster wrapper connector 800 is modified to replace the bypass register (WBY) in the conventional wrapper connector with the BCB (e.g., the broadcast control bit). 802 to replace the broadcast control bit. 802This is used to generate the BCB_Out signal for the IEEE 1500 clients in the cluster. The value of the broadcast control bit 802 can only be changed by using the cluster wrapper connector 800 by moving the WS_BYPASS instruction into the Shadow_WIR 804 is put into WBY mode.

[0047] Fig. Figure 9 illustrates a sampling network 900 according to one exemplary implementation. The scanning network 900 includes a partition test data register 902 , a client broadcast control bit 904 , a partition 906 , a partition sampling multiplexer 908 , a partition segment insertion bit 910 and a wrapper connector 912 .

[0048] The sampling network 900 in Fig. 9 is similar to the one in Fig. 1 shown sampling network 100 At the cluster level, the sampling network can 900Both broadcast and daisy modes are supported on the clients in the cluster. The cluster's wrapper connector includes the BCB for the clients (e.g., the client broadcast control bit). 904 ). Each partition test data register 902 This includes the JTAG registers from the IEEE 1500 clients. The instruction registers (IRs) of all clients within a cluster are always in broadcast mode. Therefore, all clients within a cluster select the same JTAG register for the active sampling path.

[0049] Fig. Figure 10 illustrates a cluster network 1000 according to an implementation example. The cluster network 1000 includes a client broadcast control bit 1002 , a cluster broadcast control bit 1004 , cluster 1006 , a cluster sampling multiplexer 1008, a pipeline 1010 , a multiplexer 1012 , a WBY 1014 , a multiplexer 1016, a 1500-client 1018 and a converter 1020 . Table 2. Hierarchical sampling network modules. Hierarchy level Contains TDR Bypass control Broadcast control Partition IEEE 1500 client with client SIBs Partition TDR Partition SIB - Cluster Client BCB in the wrapper connector and client network All partition TDRs Shadow-WIR in wrapper connector=WS_BYPASS Client-BCB chip Cluster BCB and cluster network All clusters - Cluster-BCB

[0050] Table 2 above summarizes the hierarchical modules of the IEEE1500 network with the IEEE1687-based broadcast sampling design.

[0051] The in Fig. 10 shown cluster networks 1000 differs slightly from the one in Fig. 2 hierarchical cluster network shown 200 The cluster network 1000 does not use SIBs for the clusters 1006 This is because each cluster has its own wrapper connector, which can be used to bypass the cluster. The instruction registers of all wrapper connectors are chained. Consequently, different instructions can be moved to different clusters.

[0052] The cluster BCB at the chip level controls the broadcast mode for all clusters. The cluster BCB can be accessed as a JTAG register in the chip's top-level IEEE 1500 client using the CHIP_BROADCAST_WRITE command.

[0053] The cluster BCB can be operated to lock the client BCBs at the chip level during broadcast.

[0054] When a cluster is in bypass mode, it allows access to the client BCB at the cluster level via the wrapper connector. This enables the client BCB within bypass clusters to be updated when chip-level broadcast write operations are performed on other, non-bypassed clusters. Because these client BCBs belong to bypassed clusters, they will not affect the actual test data.

[0055] In certain test scenarios, however, this can lead to increased test time during the transition from one group of transferred clusters to another group of clusters that needs to be transferred. For example, suppose that clusters I and II were bypassed at the chip level during the preceding chip-level broadcast write operation on other clusters. In the preceding chip-level broadcast, the client BCBs of clusters I and II may change their value. This could cause clusters I and II to transition from broadcast bypass mode to daisy-pass mode. Now, if clusters I and II are used in the next broadcast operation, it would be necessary to reconfigure their client BCBs to put clusters I and II back into broadcast mode.

[0056] To avoid this drawback, the client BCBs can be locked (similar to the previously discussed locks for the SIBs), preventing the client BCBs of bypassed clusters from being updated with new values ​​during chip-level transmission. The `cluster_broadcast_ctrl` signal from the parent cluster BCB at the chip level can be used to lock all client BCBs at the cluster level. Interpretation and terminology

[0057] References to “an embodiment” or, more generally, “an embodiment” do not necessarily refer to the same embodiment, although this may be the case. Unless the context clearly requires otherwise, the words “comprise,” “comprehensive,” and the like are to be interpreted in an inclusive sense as opposed to an exclusive or exhaustive one; that is, in the sense of “including but not limited to.” Words using the singular or the plural include the plural or the singular respectively, unless they are expressly limited to simple or multiple singular forms. Furthermore, the words “herein,” “foreword,” “following,” and words of similar meaning, when used in this application, refer to this application as a whole and not to specific parts thereof.When the claims use the word "or" in relation to a list of two or more elements, this word covers all of the following interpretations: any one of the elements in the list, all of the elements in the list, and any combination of the elements in the list, unless expressly limited to one or the other. Any terms not expressly defined herein have their conventional meaning as generally understood by a person skilled in the art.

[0058] The various logical function operations described herein can be implemented in a logic that refers to a noun or noun phrase reflecting the operation or function. For example, a comparison or comparison can be performed by a "comparator," and so on.

[0059] In this context, "circuit" refers to electrical circuits with at least one discrete electrical circuit, electrical circuits with at least one integrated circuit, electrical circuits with at least one application-specific integrated circuit, circuits forming a general-purpose computing device configured by a computer program (for example, a general-purpose computer configured by a computer program that performs at least some of the processes or devices described herein, or a microprocessor configured by a computer program that performs at least some of the processes or devices described herein), a circuit arrangement forming a storage device (for example, forms of random-access memory), or a circuit arrangement forming a communication device (for example, a modem,a communication device or an opto-electrical device).

[0060] In this context, "comparator" refers to a logic element that compares two or more inputs to produce one or more outputs that reflect the similarity or difference of the inputs. An example of a hardware comparator is an operational amplifier that outputs a signal indicating whether one input is greater than, less than, or approximately equal to another. An example of a software or firmware comparator is: `if (input1 == input2) output = val1; else if (input1 > input2) output = val2; else output = val3;` Many other examples of comparators are obvious to the person skilled in the art without excessive experimentation.

[0061] In this context, "firmware" refers to software logic that is executed as processor-executable instructions stored in read-only memory or media.

[0062] In this context, "hardware" refers to logic implemented as an analog or digital circuit.

[0063] In this context, "logic" refers to machine memory circuits, non-volatile machine-readable media, and / or circuit arrangements that, in their material and / or material-energy configuration, include control and / or process signals and / or settings and values ​​(such as resistance, impedance, capacitance, inductance, current / voltage values, etc.) that can be used to influence the operation of a device. Magnetic media, electronic circuits, electrical and optical storage (both volatile and non-volatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (but does not exclude machine memories that include software and thereby form material configurations).

[0064] In this context, "software" refers to logic that is implemented as processor-executable instructions in machine memory (for example, reading / writing volatile or non-volatile memory or media). QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited non-patent literature

[0000] IEEE1687 [0002, 0003, 0007] IEEE 1500 [0006, 0013] IEEE 1149.1

[0007] IEEE Standard 1149.1-1990

[0008]

Claims

[1] Distributed test circuit, comprising: a multitude of circuit partitions arranged in series to form a sampling path; wherein each of the circuit partitions comprises a sampling multiplexer, a test data register and a segment insertion bit circuit; wherein the sampling multiplexer of each of the circuit partitions provides inputs for a corresponding test data register of each of the circuit partitions; Control logic for generating a broadcast mode selection signal for the sampling multiplexer of each of the circuit partitions, to put the test circuit into a broadcast mode if the broadcast mode selection signal is assured, and to switch the test circuit into a daisy mode if the broadcast mode selection signal is not assured; and where each segment insertion bit circuit can be operated to either include or bypass the corresponding circuit partition from the sampling path. [2] Distributed test circuit according to claim 1, further comprising: the test circuit, which in broadcast mode is configured to apply test data for each of the circuit partitions simultaneously to each corresponding test data register; and the test circuit, which is configured in daisy mode to move the test data sequentially along the row arrangement of circuit partitions. [3] Distributed test circuit according to claim 1 or 2, wherein each segment insertion bit circuit comprises: a shift cell that is coupled to receive test data from the test data register; an update cell that is coupled to receive the test data from the displacement cell; an update pipeline coupled to provide a shift signal for the shift cell; and a control circuit that is coupled to halt the operation of the displacement cell during broadcast mode. [4] Distributed test circuit according to claim 3, wherein the control circuit comprises a gate that receives the broadcast mode selection signal and an output of the update pipeline, wherein the gate is coupled to select a test data input for the update cell. [5] Distributed test circuit according to claim 3 or 4, wherein each segment insertion bit circuit has operating states as given by the following table: SIB status Update cell Broadcast mode selection signal Test data register Test circuit mode Open and not stopped 1 0 Active Daisy Closed and not stopped 0 0 Bypass Daisy bypass Open and stopped 1 1 Active Broadcast Closed and suspended 0 1 Bypass Broadcast bypass [6] Distributed test circuit, comprehensive: a multitude of circuit clusters arranged in series to form a sampling path; wherein each of the circuit clusters comprises a sampling multiplexer, a segment insertion bit circuit and a serial arrangement of circuit partitions; wherein each circuit partition of each circuit cluster includes a test data register; wherein the sampling multiplexer of each of the circuit clusters provides inputs for a first circuit partition of the serial arrangement of circuit partitions; Control logic for placing the test circuit in broadcast mode when a broadcast mode selection signal is guaranteed, and for switching the test circuit to daisy mode when the broadcast mode selection signal is not guaranteed; and where each segment insertion bit circuit can be operated to either include or bypass the corresponding circuit cluster from the sampling path. [7] Distributed test circuit according to claim 6, further comprising: the test circuit, which in broadcast mode is configured to apply test data for each of the circuit partitions simultaneously to each corresponding test data register; and the test circuit, which is configured in daisy mode to move the test data sequentially along the serial arrangement of circuit partitions. [8] Distributed test circuit according to claim 6 or 7, wherein each circuit partition comprises: a partition-level sampling multiplexer, the test data register and a partition-level segment insertion bit circuit, wherein the partition-level sampling multiplexer provides inputs for the test data register. [9] Distributed test circuit according to claim 8, wherein each of the series arrangements of circuit partitions further comprises each of the circuit clusters: Partition level control logic for generating a partition level broadcast selection signal for the partition level sampling multiplexer of each of the circuit partitions in the array of circuit partitions, to put each circuit partition of the array of circuit partitions into broadcast mode when the partition level broadcast selection signal is assured, and to put each circuit partition of the array of circuit partitions into daisy mode when the partition level broadcast selection signal is not assured; and The partition level segment insertion bit circuit can be operated to include or bypass the corresponding circuit partition of the serial arrangement of circuit partitions from the sampling path. [10] Distributed test circuit according to claim 8 or 9, wherein each partition level segment insertion bit circuit comprises: a shift cell that is coupled to receive test data from the test data register; an update cell that is coupled to receive the test data from the displacement cell; an update pipeline coupled to provide a shift signal for the shift cell; and a control circuit that is coupled to stop the operation of the displacement cell during broadcast mode. [11] Distributed test circuit according to claim 10, wherein the control circuit comprises a gate that receives the broadcast mode selection signal and an output of the update pipeline, wherein the gate is coupled to select a test data input for the update cell. [12] Distributed test circuit according to claim 10 or 11, wherein each partition-level segment insertion bit circuit has operating states as given by the following table: SIB status Update cell Broadcast mode selection signal Test data register Test circuit mode Open and not stopped 1 0 Active Daisy Closed and not stopped 0 0 Bypass Daisy bypass Open and held 1 1 Active Broadcast Closed and suspended 0 1 Bypass Broadcast bypass