OPERATING METHOD OF A SIGNAL RECEIVER, PULSE WIDTH CONTROL AND ELECTRONIC DEVICE WITH THE SAME

Abstract

Operating procedure of a signal receiver, comprising the following steps: successive reception (S110) of a zero bit and a first bit through a signal line (DQ); and selective matching (S150, S160) of a width of either a first duration of a high state or a first duration of a low state of a first signal corresponding to the first bit, based on values ​​of the zero bit and the first bit, based on whether the values ​​of the zero bit and the first bit are identical.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from Korean Patent Applications No. 10-2017-0155874, filed on November 21, 2017, and No. 10-2018-0051570, filed on May 4, 2018, filed in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. BACKGROUND

[0002] Exemplary embodiments of the inventive concepts described herein relate to an electronic device and, in particular, relate to an operating method of a signal receiver, a pulse width controller, and / or an electronic device comprising the signal receiver and the pulse width controller.

[0003] Electronic devices can exchange data with an external device (e.g., a memory controller) by transmitting an electrical signal to the external device through a signal line. For example, a semiconductor memory device can transmit data to the memory controller in synchronization with a data strobe signal. In this case, signals may be distorted depending on the characteristics of lines between the semiconductor memory device and the memory controller. The signal distortion may cause a reduction in data transmission speed and / or a reduction in data reliability. SUMMARY

[0004] Exemplary embodiments of the inventive concepts provide an operating method of a signal receiver having improved reliability by adjusting a pulse width of a data signal corresponding to a current data bit based on previous data bits, a pulse width controller, and / or an electronic device comprising the signal receiver and the pulse width controller.

[0005] According to an exemplary embodiment, a method of operation of a signal receiver comprises sequentially receiving a zeroth bit and a first bit through a signal line and selectively adjusting a width of either a first high state duration or a first low state duration of a first signal corresponding to the first bit based on values ​​of the zeroth bit and the first bit based on whether the values ​​of the zeroth bit and the first bit are identical.

[0006] According to an exemplary embodiment, a pulse width controller includes an interface configured to receive a signal and processing circuitry configured to sample an output signal to output a zeroth feedback signal, delay the zeroth feedback signal to output a first feedback signal, and adjust a width of either a high state duration or a low state duration of the output signal when values ​​of the zeroth feedback signal and the first feedback signal are identical.

[0007] According to an exemplary embodiment, an electronic device comprises a delay signal generator configured to sequentially receive a signal having a zeroth bit, a first bit, and a second bit, and to delay the signal to generate a plurality of delay signals, and a pulse width controlled decision feedback equalizer configured to adjust a width of either a high state duration or a low state duration of an output signal based on the plurality of delay signals when the zeroth bit and the first bit are identical, or when the first bit and the second bit are identical.

[0008] According to an exemplary embodiment, a signal transmitter includes a delay signal generator configured to receive a signal having a zeroth bit, a first bit, and a second bit and to generate a plurality of delay signals by delaying the signal, and a pulse width adjuster configured to adjust a width of either a high state duration or a low state duration of an output signal to generate an adjusted output signal when the zeroth bit and the first bit are identical or when the first bit and the second bit are identical, and to output the adjusted output signal through a data line to an external device. List of characters

[0009] The foregoing and other objects and features of the inventive concepts will become apparent by describing some exemplary embodiments thereof in detail with reference to the accompanying drawings. Fig. 1A and Fig. 1B are block diagrams illustrating a memory system according to an example embodiment of the inventive concepts. Fig. 2A and Fig. 2B are timing diagrams showing data signals according to different data patterns. Fig. 3 is a flowchart showing an operation of a pulse width controller of Fig. 1A and Fig. 1B. Fig. 4A and Fig. 4B are diagrams for describing an operating procedure of Fig. 3 in detail. Fig. 5 is a block diagram showing a hardware configuration of a pulse width controller of Fig. 1A and Fig. 1B. Fig. 6 is a block diagram illustrating a pulse width controlled decision feedback equalizer (PWC-DFE) of Fig. 5 in detail. Fig. 7 is a circuit diagram showing a pulse width adjuster of Fig. 6 represents. Fig. Fig. 8 is a timing chart for describing an operation of a pulse width adjuster of Fig. 7. Fig. 9 is a block diagram showing a pulse width adjuster of Fig. 6 represents. Fig. 10 is a timing chart for describing an operation of a pulse width adjuster of Fig. 9. Fig. 11 is a block diagram illustrating a pulse width controller according to an exemplary embodiment of the inventive concepts. Fig. 12 is a timing chart for describing an operation of a pulse width controller of Fig. 11. Fig. 13 is a block diagram illustrating a pulse width controller according to an exemplary embodiment of the inventive concepts. Fig. 14 is a block diagram illustrating a zeroth pulse width adjuster of Fig. 13 represents. Fig. 15 is a timing chart for describing an operation of a pulse width controller of Fig. 13. Fig. 16A and Fig. 16B are block diagrams illustrating a memory system according to an example embodiment of the inventive concepts. Fig. 17 is a block diagram illustrating a pulse width control of Fig. 16 represents. Fig. 18 is a timing chart for describing an operation of a pulse width adjuster. Fig. 19A to Fig. 19C are block diagrams illustrating electronic devices having pulse width control according to the inventive concepts. Fig. 20 is a block diagram illustrating an electronic system to which a transmitter and a receiver having pulse width control according to an exemplary embodiment of the inventive concepts are applied. DETAILED DESCRIPTION

[0010] In the following, some exemplary embodiments of the inventive ideas can be described in detail and clearly to such an extent that a person skilled in the art can easily implement the inventive ideas.

[0011] The terms "unit," "module," etc., used below, and functional blocks depicted in the drawings may be implemented as a software component, a hardware component, or a combination thereof. To clearly describe the exemplary embodiments of the inventive concepts, descriptions associated with identical components will be omitted.

[0012] Fig. 1A and Fig. 1B are block diagrams illustrating a memory system according to an example embodiment of the inventive concepts.

[0013] Referring to Fig. 1A can be a storage system 10 a storage device 11 and a memory controller 12 The memory device may be a dynamic random access memory (DRAM) device. However, the inventive concepts are not limited thereto. The memory device 11 may, for example, be a volatile memory device or a non-volatile memory device.

[0014] Under a control of the memory control 12 the storage device 11 Store data “DATA” and / or can transfer the stored data “DATA” to the memory controller 12 transferred. The storage device 11 can, for example, respond to a command CMD and an address ADDR from the memory control 12 Data “DATA” to the memory controller 12 In this case, the storage device 11 In response to a data strobe signal provided by a data strobe line DQS, the data “DATA” is sent to the memory controller 12 In an exemplary embodiment, the data “DATA” may be transmitted through a plurality of data lines DQ and the data notice line DQS between the storage device 11 and memory control 12 be replaced.

[0015] The memory control 12 the data “DATA” can be transmitted through the data lines DQ from the storage device 11 received. The memory control 12 For example, the data “DATA” that is transmitted through the data lines DQ received based on a signal from the data reference line DQS identify.

[0016] In an exemplary embodiment, the storage device 11 and the memory control 12 based on a double data rate ( DDR -) interface. However, the inventive ideas are not limited to this. The storage device 11 and the memory control 12For example, they can communicate with each other based on at least one of various interfaces, such as a Universal Serial Bus (USB) interface, a Multimedia Card (MMC) interface, a Peripheral Component Interconnection (PCI) interface, a PCI Express (PCI-E) interface, an Advanced Technology Attachment (ATA) interface, a Serial ATA (SATA) interface, a Parallel ATA (PATA) interface, a Small Computer Small Interface (SCSI) interface, an Enhanced Small Disk (ESDI) interface, an Integrated Drive Electronics (IDE) interface, a Mobile Industry Processor Interface (MIPI), a Nonvolatile Memory Express (NVM-e) interface, and a NAND interface.

[0017] The memory control 12 a pulse width control 100 The pulse width control 100may be configured to generate a pulse width corresponding to a current data bit based on data received from the memory device 11 The pulse width control 100 For example, it can adjust a pulse width corresponding to a current bit based on a pattern of the received data. The pulse width control 100 Alternatively, adjust a pulse width corresponding to a current data bit based on whether previously received data bits have changed. An operating method and structure of the pulse width control 100 according to an exemplary embodiment of the inventive ideas will be described more fully with reference to the following drawings.

[0018] Referring to Fig. 1B can be a storage system 10' a storage device 11' and a memory controller 12'Unlike the embodiment of Fig. 1A may, in an exemplary embodiment of Fig. 1B the storage device 11' a pulse width control 100' and the same may be configured to, based on data stored by the storage device 11' received, to adapt a pulse width corresponding to a current data bit. Other components are similar to those of Fig. 1A, and additional description will thus be omitted to avoid redundancy.

[0019] As described above, the pulse width control 100 adapt a pulse width corresponding to a current data bit based on previous data bits. In this respect, an effective margin for identifying a data bit at a receiving stage of the memory controller 12 be adequately secured. The memory control 12that supports a high-speed interface can accordingly transfer data from the storage device 11 received normally, and thus the reliability of the memory control 12 improved.

[0020] In the following, for convenience of description, exemplary embodiments of the inventive ideas are described with reference to the pulse width control 100 (ie the embodiment of Fig. 1A), which refers to the memory control 12 In an exemplary embodiment, the configurations of the memory device described above are 11 and memory control 12 merely to describe exemplary embodiments of the inventive concepts. However, exemplary embodiments of the inventive concepts are not limited thereto. The pulse width control 100According to the inventive concepts, it can be applied, for example, to a signal transmitter, a signal receiver, or various electronic devices (e.g., a memory device) that are configured to transmit / receive various information through a signal line. The pulse width control 100 According to the inventive ideas, it can also be used for a data line or to receive or transmit various signals as well as a data signal.

[0021] Fig. 2A and Fig. 2B are timing diagrams illustrating data signals according to various data patterns. Further, in order to clearly describe the technical spirit of the inventive concepts, exemplary embodiments of the inventive concepts will be described below with reference to a data signal or a data pattern received through a data line DQ.

[0022] It is further assumed that a data bit of "1" indicates a data signal with a logic high state, and a data bit of "0" indicates a data signal with a logic low state. A data pattern DP means a combination of data bits transmitted through a data line DQ received consecutively. However, exemplary embodiments of the inventive concepts are not limited thereto.

[0023] Referring to Fig. 1A, Fig. 1B, Fig. 2A and Fig. 2B can control the memory 12 different data patterns DP1 until DP8 from the storage device 11 received. As in Fig. 2A and Fig. As shown in Figure 2B, the memory control 12 for example, the first to eighth data patterns DP1 until DP8 from the storage device 11 received. The first to fourth data patterns DP1 until DP4 can specify patterns “1101”, “0101”, “1001” and “0001” respectively, and the fifth to eighth data patterns DP5 until DP8 can be patterns “0010”, “1010”, “0110” or “ 1110 " indicate.

[0024] In an exemplary embodiment, the timing diagrams shown in Fig. 2A and Fig. 2B, data signals corresponding to a third bit and a fourth bit in the first to eighth data patterns DP1 until DP8 That is, data signals of the first to fourth data patterns DP1 until DP4 that change from a data bit with “0” to a data bit with “1” are Fig. 2A, and data signals of the fifth to eighth data patterns DP5 until DP8 that change from a data bit with “1” to a data bit with “0” are Fig. 2B.

[0025] As in Fig. 2A, in the case of the first to fourth data patterns DP1 until DP4 the data signals increase at the first to fourth times t1 to t4, respectively. As in Fig. 2B, in the case of the fifth to eighth data patterns DP5 until DP8 the data signals drop at the fifth to eighth times t5 to t8, respectively.

[0026] That is, a rise time and a fall time of a data signal may differ from each other depending on a data pattern (or a preceding data bit). The difference between the rise time and the fall time may make it difficult to ensure an effective margin of each data bit. In this respect, the memory controller 12 Data not received normally.

[0027] As in Fig. 2A and Fig. 2B, the pulse width control 100According to an exemplary embodiment of the inventive concepts, adjust a pulse width of a data signal corresponding to a current data bit based on a data pattern (or previous data bits). In the case of each of the first to fourth data patterns DP1 until DP4 For example, pulse width control 100 adjust a pulse width of a data signal corresponding to a current data bit or a next data bit such that the data signal at the second time t2 increases (e.g., is closer to a logical one than a logical zero). In the case of each of the fifth to eighth data patterns DP5 until DP8 Alternatively, the pulse width control 100 adjust a pulse width of a data signal corresponding to a current data bit or a next data bit such that the data signal at the sixth time t6drops (e.g. is closer to a logical zero than a logical one).

[0028] In an exemplary embodiment, the second time t2 a rise time of a data signal corresponding to the second data pattern DP2 with “0101”, and the sixth time tb may indicate a fall time of a data signal corresponding to the sixth data pattern DP6 with “1010”. The pulse width control 100 In other words, it can adjust a pulse width of a data signal with respect to a rise time and a fall time of a data signal according to a specific data pattern. In an exemplary embodiment, the specific data pattern may be a pattern (e.g., " 0101 " or " 1010 “), where one data bit is changed in each period.

[0029] Fig. 3 is a flowchart showing an operation of the pulse width control 100from Fig. 1A and Fig. 1B.

[0030] Hereinafter, for convenience of description, the term "state of a data bit or a data pattern" is used. The "state of a data bit" indicates whether a specific data bit or a preceding data bit of the specific data bit has changed. That is, in the case where a state of a first data bit indicates a transition state, the first data bit and an immediately preceding data bit (i.e., a preceding data bit) of the first data bit may be different from each other. That is, in the case where the state of the first data bit indicates a non-transition state, the first data bit and the immediately preceding data bit (i.e., the preceding data bit) of the first data bit may be identical to each other. In other words, a transition state of a data bit indicates whether a change has been made between data bits that are adjacent to each other (in time).

[0031] For the sake of simplicity of description, it is assumed in the following that the pulse width control 100 four data bits having a data pattern, consecutively receives and adjusts a pulse width of a third data bit of the four data bits. In other words, depending on an operating method to be described below, the pulse width control 100 control a pulse width of a data signal between a third data bit and a fourth data bit.

[0032] The expressions and assumptions described above may be used to readily describe exemplary embodiments of the inventive concepts, and the inventive concepts are not limited thereto.

[0033] Referring to Fig. 1A, Fig. 1B and Fig. 3 can be used in a process S110 the pulse width control 100 receive a data pattern. The pulse width control 100For example, different data patterns (e.g. the first to eighth data patterns DP1 until DP8 ) is received. The pulse width control 100 may alternatively receive a plurality of data bits consecutively.

[0034] During a process S120 the pulse width control 100 determine a transition state of each data bit based on the received data pattern. In the case where the pulse width control 100 the second data pattern DP2 (ie “0101”) (referring to Fig. 2A), for example, since all adjacent data bits are changed, a state of each data bit of the second data pattern DP2 be a transitional state.

[0035] In the case where the pulse width control 100 the third data pattern DP3 (ie "1001"), in contrast, since second and third data bits are "0", a state of the third data bit can be a non-transition state.

[0036] During a process S130 the pulse width control 100 determine whether a data bit is in a non-transition state. The pulse width control 100 In other words, it can determine that adjacent data bits in the received data pattern have the same value.

[0037] In the case where a data bit of the non-transition state exists, an operation S140 the pulse width control 100 determine whether the data bit of the non-transition state is “1” or “0”.

[0038] In the case where the data bit of the non-transition state is “1”, an operation S150 the pulse width control 100a duration corresponding to a data bit with “0”. In the case where the pulse width control 100 the seventh data pattern DP7 (ie, "0110"), for example, since a second data bit and a third data bit adjacent to the second data bit are "1", a data bit of the non-transition state may be "1". In this case, the pulse width control 100 increase a pulse width of a duration (a duration of a low state) corresponding to a data bit with "0" or decrease a pulse width of a duration (ie, a duration of a high state) corresponding to a data bit with "1". In this case, as in the seventh data pattern DP7 , which is in Fig. 2B, a fall time from a third data bit to a fourth data bit at the sixth time t6 be aligned.

[0039] In the case where the data bit of the non-transition state is “0”, the pulse width control 100 in the process S150 a duration corresponding to a data bit with "1". In the case where the pulse width control 100 the third data pattern DP3 (ie, "1001"), for example, since a second data bit and a third data bit adjacent to the second data bit are "0", a data bit of the non-transition state may be "0". In this case, the pulse width control 100 may increase a pulse width of a duration (a duration of a high state) corresponding to a data bit with "1" or may decrease a pulse width of a duration (ie a duration of a low state) corresponding to a data bit with "0". In this case, as in the third data pattern DP3 , which is in Fig. 2A, a rise time from a third data bit to a fourth data bit at the second time t2 be aligned.

[0040] In the case where a data bit of the non-transition state does not exist, the pulse width control 100 cannot perform pulse width control operation. In the case where the pulse width control 100 the second data pattern DP2 with “0101”, for example, since each data bit of the second data pattern DP2 has a value that is different from a value of an adjacent data bit, each data bit may have the transition state. In this case, the pulse width control 100 do not perform separate pulse width control operation.

[0041] As described above, the pulse width control 100According to an exemplary embodiment of the inventive concepts, determine that adjacent data bits having the same value are present in the received data bits. In the case where adjacent data bits having the same value are present in the received data bits, a high state duration or a low state duration of a current time is increased or decreased based on a data bit of the same value.

[0042] In an exemplary embodiment, the pulse width control 100 according to an exemplary embodiment of the inventive concepts, adjust (e.g., increase) a width of a high state duration or a width of a low state duration depending on the number of adjacent data bits having the same value.

[0043] Fig. 4A and Fig. 4B are diagrams for describing an operating procedure of Fig. 3 in detail. An exemplary embodiment of the data patterns DP1 until DP4 , where a current data bit D[n] “0”, with reference to Fig. 4A, and an exemplary embodiment of the data patterns DP5 until DP8 where the current data bit D[n] “1” is determined by reference to Fig. 4B. For each of the data patterns DP1 until DP8 returns the current data bit D[n] a third data bit.

[0044] For the sake of simplicity of description, a pulse width control operation of a point X[n] be described. The point X[n] can specify a point at which a change from the current data bit D[n] to the next data bit D[n+1] This means that the pulse width control 100can be a pulse width of a high state duration or a low state duration at the point X[n] zoom in / out.

[0045] As in Fig. 4A and Fig. As shown in Figure 4B, the pulse width control 100 the first to eighth data patterns DP1 until DP8 received. A data signal can have a signal level corresponding to a data bit of each of the data patterns DP1 until DP4 corresponds.

[0046] In an exemplary embodiment, the second data pattern DP2 or the sixth data pattern DP6 have an ideal signal level during the duration of each data bit. The second data pattern DP2 and the sixth data pattern DP6 For example, they may have data bits that repeat (or change) periodically. That is, the second data pattern DP2 and the sixth data pattern DP6 may have a data signal (ie, a high level or a low level) that is continuous during periods of second and first preceding data bits D[n-2] and D[n-1] , of the current data bit D[n] and the next data bit D[n+1] changes periodically.

[0047] The remaining data patterns DP1 , DP3 , DP4 , DP5 , DP7 and DP8 In contrast, may have a data signal that has a phase that is different with respect to the second and sixth data patterns DP2 and DP6 is advanced or delayed.

[0048] In the case of the first data pattern DP1 For example, a pulse width can be determined with respect to the point X[n] through a first period ta1 be reduced. In the case of the first data pattern DP1 In other words, a data signal can be transmitted around the first time ta1 earlier than the point X[n] increase. In the case of the third data pattern DP3 In contrast, a pulse width can be determined by a second time ta2 regarding the point X[n] be enlarged. In the case of the third data pattern DP3 In other words, a data signal can be received after the second time ta2 regarding the point X[n] increase. In the case of the fourth data pattern DP4 a pulse width can be divided by a third time ta3 regarding the point X[n] be enlarged. In the case of the fourth data pattern DP4 In other words, a data signal can be received after the third time ta3 regarding the point X[n] rise.

[0049] The pulse width control 100 According to exemplary embodiments of the inventive concepts, a pulse width of a low state duration / a high state duration can be determined by the first time ta1 in the case of the first data pattern DP1 increase / decrease a pulse width of a high state duration / a low state duration by the second time ta2 in the case of the third data pattern DP3 increase / decrease, and can increase / decrease a pulse width of a high state duration / a low state duration by the third time ta3 in the case of the fourth data pattern DP4 zoom in / out.

[0050] In the case of the first data pattern DP1 For example, with “1101” the first and second preceding data bits D[n-1] and D[n-2] the same value, that is, “1”. That is, the first data pattern DP1 has a data bit of "1" as a data bit of the non-transition state. In this case, as described with reference to Fig. 3, the pulse width control 100a pulse width (ie a width of a duration of a low state) corresponding to the data bit with “0” at the current time X[n] enlarge.

[0051] In the case of the third data pattern DP3 with “1001” have a second preceding data bit D[n-2] and a current data bit D[n] the same value, that is, “0”. That is, the third data pattern DP3 has a data bit of "0" as a data bit of the non-transition state. In this case, as described with reference to Fig. 3, the pulse width control 100 a pulse width (ie a width of a duration of a high state) corresponding to the data bit with “1” at the current time X[n] enlarge.

[0052] In the case of the fourth data pattern DP4 with “0001” have first and second preceding data bits D[n-1] and D[n-2] and a current data bit D[n] the same value, that is, “0”. That is, the fourth data pattern DP4 has a data bit of "0" as a data bit of the non-transition state. In this case, as described with reference to Fig. 3, the pulse width control 100 a pulse width (ie a width of a duration of a high state) corresponding to the data bit with “1” at the current time X[n] enlarge.

[0053] In an exemplary embodiment, the third and fourth data patterns DP3 and DP4 Data bits with "0" as one data bit of the non-transition state, but the pulse widths to be adjusted may differ. The number of data bits with "0" that constitute the third data pattern DP3 as a data bit of the non-transition state is “1”, and the number of data bits with “0” that the fourth data pattern DP4 as a data bit of the non-transition state is “2”.

[0054] That is, the third and fourth data patterns DP3 and DP4 may have data bits with “0” as a data bit of the non-transition state, the number of data bits of the non-transition state that the third data pattern DP3 may differ from the number of data bits of the non-transition state, which the fourth data pattern DP4 The pulse width control 100 According to exemplary embodiments of the inventive concepts, a pulse width adjustment may be adjusted based on the number of data bits of the non-transition state. In an exemplary embodiment, the pulse width adjustment may increase as the number of data bits of the non-transition state increases.

[0055] The principle of adjusting pulse widths of the fifth to eighth data patterns DP5 until DP8 is identical to the one corresponding to the first to fourth data patterns DP1 until DP4 is assigned, except that data bits of the fifth to eighth data patterns DP5 until DP8 of data bits of the first to fourth data patterns DP1 until DP4 differ, and thus an additional description will be omitted to avoid redundancy.

[0056] As described above, in each data pattern based on a combination of the current data bit D[n] , of the first preceding data bit D[n-1] and the second data bit D[n-2] a state of each data bit can be determined.

[0057] The pulse width control 100 For example, an AND operation and an OR operation can be performed on the current data bit D[n] , the first preceding data bit D[n-1] and the second preceding data bit D[n-2] and a first pull-up bit Xpu[n-1] , a first pull-down or pull-down bit Xpd[n-1] , a second pull-up bit Xpu[n-2] and second pull-down bit Xpd[n-2] generate.

[0058] The first pull-up bit Xpu[n-1] can have a value that is determined by performing the OR operation on the current data bit D[n] and the first preceding data bit D[n-1] is obtained, the first pull-down bit Xpd[n-1] can have a value that is determined by performing the AND operation on the current data bit D[n] and the first preceding data bit D[n-1] is received, the second pull-up bit Xpu[n-2] can have a value that is determined by performing the OR operation on the first preceding data bit D[n-1] and the second preceding data bit D[n-2] is obtained, and the second pull-down bit Xpd[n-2] can have a value that is determined by performing the AND operation on the first preceding data bit D[n-1] and the second preceding data bit D[n-2] Results of performing the AND operation and the OR operation on the data patterns DP1 until DP8 will be in Fig. 4A and Fig. 4B, and a description thereof will be omitted.

[0059] The pulse width control 100 can be based on the first and second pull-down bits Xpd[n-1] and Xpd[n-2] increase the duration of a low state. As in Fig. 4A and Fig. 4B, at least either the first pull-down bit Xpd[n-1] or the second pull-down bit Xpd[n-2] that correspond to each of the first, seventh and eighth data patterns DP1 , DP7 and DP8 assigned to them, be “1”, and the first pull-down bit Xpd[n-1] and the second pull-down bit Xpd[n-2] that each of the remaining data patterns DP2 , DP3 , DP4 , DP5 and DP6 assigned to the inputs can be “0”. In this case, the pulse width control 100 a pulse width of a data signal (ie, a duration of a low state) corresponding to a low level at the point X[n] with regard to the first, seventh and eighth data patterns DP1 , DP7 and DP8 enlarge.

[0060] The pulse width control 100 In contrast, based on the first and second pull-up bits Xpu[n-1] and Xpu[n-2] increase the duration of a high state. As in Fig. 4A and Fig. 4B, for example, at least either the first pull-up bit Xpu[n-1] or the second pull-up bit Xpu[n-2] that correspond to each of the third, fourth and fifth data patterns DP3 , DP4 and DP5 assigned to them, be “0”, and both the first pull-up bit Xpu[n-1] as well as the second pull-up bit Xpu[n-2] that each of the remaining data patterns DP1 , DP2 , DP6 , DP7 and DP8 assigned to the inputs can be "1". In this case, the pulse width control 100 a pulse width of a data signal (ie, a duration of a high state) corresponding to a high level at the point X[n] with regard to the third, fourth and fifth data patterns DP3 , DP4 and DP5 enlarge.

[0061] As described above, the pulse width control 100 based on a data pattern (i.e. a current data bit and previous data bits) a pulse width at a specific point (e.g. X[n] ). In this respect, since there is an effective scope for data identification in the memory control 12enlarged, a memory control 12 which has improved reliability.

[0062] In an exemplary embodiment, the operating method described with reference to Fig. 4A and Fig. 4B is intended to describe the principle of adjusting a pulse width, and the inventive concepts are not limited thereto. The exemplary embodiments of the inventive concepts may be variously changed or modified without departing from the scope and spirit of the inventive concepts.

[0063] In the exemplary embodiments described above, the current data bit D[n] and two previous data bits D[n-1] and D[n-2] used to determine a pulse width at the current time X[n] However, the inventive ideas are not limited to this. The pulse width control 100 can be a current data bit and “k “ preceding data bits D[n] until D[n-k] (where k is an integer) for the purpose of adjusting a pulse width at the current time X[n] use.

[0064] Fig. 5 is a block diagram showing a hardware configuration of the pulse width control 100 from Fig. 1A and Fig. 1B. For a brief description, components that are unnecessary to provide a structure and operation of the pulse width control 100 to describe, be omitted.

[0065] Referring to Fig. 1A, Fig. 1B and Fig. 5 the pulse width control 100 a plurality of delay signal generators 110 - 1 until 110-n , a plurality of pulse width controlled decision feedback equalizers 120 - 1 until 120-n(hereinafter referred to as “PWC-DFE”), a tax logic 130 and a delay circuit 140 have.

[0066] The majority of delay signal generators 110 - 1 until 110-n can be connected by a plurality of data lines DQ1 until DQn Data “DATA” from the storage device 11 received and can output a plurality of delay signals based on the received data “DATA”.

[0067] The majority of PWC DFEs 120 - 1 until 120-n the plurality of delay signals from the plurality of delay signal generators 110 - 1 until 110-n and can generate a plurality of output signals based on the received delay signals Youtl until Youtn spend.

[0068] The tax logic 130the majority of delay signal generators 110 - 1 until 110-n and the majority of PWC DFEs 120 - 1 until 120-n control. The control logic 130 For example, delay coefficients for generating the plurality of delay signals can be supplied to the plurality of delay signal generators 110 - 1 until 110-n and can provide adjustment coefficients for adjusting a pulse width to the plurality of PWC-DFEs 120 - 1 until 120-n delivery.

[0069] In an exemplary embodiment, the plurality of delay signal generators 110 - 1 until 110-n based on the delay coefficients from the control logic 130 generate the plurality of delay signals, and each of the plurality of PWC-DFEs 120 - 1 until 120-ncan be based on the adjustment coefficients of the control logic 130 and preceding data bits, adjust a pulse width of a data signal corresponding to a current data bit.

[0070] The delay circuit 140 may be configured to transmit a signal through the data indication line DQS is received. The majority of PWC DFEs 120 - 1 until 120-n can be based on a delay signal from the delay circuit 140 the output signals Youtl until Youtn spend.

[0071] In an exemplary embodiment, a pulse width control operation described with reference to Fig. 2 to Fig. 4B, by the plurality of delay signal generators 110 - 1 until 110-n and the majority of PWC DFEs 120 - 1 until 120-nA configuration and operating method will be described more fully with reference to the following drawings.

[0072] Fig. Figure 6 is a block diagram illustrating a PWC-DFE of Fig. 5 in detail. For convenience of description, an exemplary embodiment of the inventive ideas will be described below with reference to a data line DQ , a delay signal generator 110 and a PWC-DFE 120 However, the inventive concepts are not limited thereto. For example, a plurality of delay signal generators and a plurality of PWC DFEs may be in operation based on exemplary embodiments to be described below.

[0073] The pulse width control 100 can the delay signal generator 110 , the PWC-DFE 120 and the control logic 130The delay signal generator 110 can be transmitted via the data line DQ a data pattern DP0 received and by delaying a data signal according to the received data pattern DP0 a plurality of delay signals S(t0) until S(tn) In an exemplary embodiment, each of the plurality of delay signals S(t0) until S(tn) be a signal that is based on a delay coefficient Cd from the control logic 130 is delayed.

[0074] The PWC DFE 120 can use a pulse width adjuster 121 , a scanner 122 and a plurality of delay devices 123-1 to 123-m.

[0075] The scanner 122 can be configured to output the final output signal Yout from the pulse width adjuster 121 to sample. A zeroth feedback signal Y[0], which is detected by the scanner 122 has been sampled, can be sent to the first delay device 123 - 1 The first to m-th delay devices 123 - 1 until 123-m can be connected in series with each other and can delay outputs from preceding stages to generate first to m-th feedback signals Y[1] until Y[m] to deliver. The zeroth to m -th feedback signals Y[0] until Y[m] can be detected by the scanner 122 and the first to m -th delay devices 123 - 1 until 123-m to the pulse width adjuster 121 be fed back.

[0076] The pulse width adjuster 121 can be based on the zeroth to mth feedback signals Y[0] until Y[m] output the final output signal Yout. The pulse width adjuster 121can be calculated based on the zeroth to mth feedback signals Y[0] until Y[m] , adjustment coefficients Cp and the plurality of delay signals S(t0) until S(tn) from the delay signal generator 110 perform the pulse width adjustment operation described above. The final output signal Yout can specify a data signal whose pulse width is adjusted as described above.

[0077] The zeroth feedback signal Y[0] can be, for example, a signal that corresponds to the current data bit D[n] corresponds to the first feedback signal Y[1] can be a signal that precedes the first data bit D[n-1] corresponds, and the second feedback signal Y[2] can be a signal that precedes the second data bit D[n-2] The pulse width adjuster 121As described above, a pulse width can be calculated based on the zeroth to mth feedback signals Y[0] until Y[m] In this case, the pulse width adjuster 121 by combining (or adding) the plurality of delay signals S(t0) until S(tn) by using the adjustment coefficients Cp adjust a pulse width of the final output signal Yout. A structure of the pulse width adjuster 121 is made with reference to Fig. 7 can be described more fully.

[0078] In an exemplary embodiment, values ​​and the numbers of the delay coefficient Cd and the adjustment coefficients Cp depending on the way the pulse width adjuster 121 to be implemented, may be changed or modified in various ways. The number of delay devices in the PWC_DFE 120may also depend on the way in which the PWC-DFE 120 to be implemented may be changed or modified in various ways. In the case where the PWC-DFE 120 is implemented with a 1-TAP structure, for example, the PWC-DFE 120 only the first delay device 123 - 1 in the case where the PWC-DFE 120 implemented with a 2-TAP structure, the PWC-DFE 120 only the first and second delay devices 123 - 1 and 123 - 2 In the case where the PWC-DFE 120 implemented with an m-TAP structure, the PWC-DFE 120 the first to m-th delay devices 123 - 1 until 123-m have.

[0079] Fig. 7 is a circuit diagram showing the pulse width adjuster 121 from Fig. 6 represents. Fig. 8 is a timing chart for describing an operation of the pulse width adjuster 121 from Fig. 7. For a brief description, it is assumed that the delay signal generator 110 three delay signals S(t0) , S(t1) and S(t2) The circuit diagram of the pulse width adjuster 121 , which is in Fig. 7 is further provided as an example, and exemplary embodiments of the inventive concepts are not limited thereto. The pulse width adjuster 121 may further include any other components such as an output buffer circuit.

[0080] An exemplary embodiment of Fig. 8 is further explained with reference to a specific data pattern DP0 be described with “00010”. This means that it will be Fig. 8 with regard to data bits D[n-3] , D[n-2] , D[n-1] , D[n] and D[n+1] the specific data pattern DP0 assumed that D[n-3] “0” is D[n-2] “0” is D[n-1] “0” is D[n] is “1” and D[n+2] is “0”.

[0081] Although the pulse width adjuster 121 , which has the m-TAP structure, also in Fig. 7, for convenience of description, an operation of the pulse width adjuster 121 with reference to the 2-TAP structure. However, the inventive concepts are not limited thereto. As in Fig. 7, for example, the pulse width adjuster 121 with a 1-tap or multi-tap structure that includes a plurality of pull-up units PU and a plurality of pull-down units PD be implemented.

[0082] Referring to Fig. 7 and Fig. 8 the pulse width adjuster 121 Inverter circuits INV1 until INV3 , a pull-up driver PUD and a pull-down driver PDD The inverter circuits INV1 until INV3 can be configured to receive the zeroth to second delay signals S(t0) , S(t1) and S(t2) to receive and the zeroth to second delay signals S(t0) , S(t1) and S(t2) to invert to output the same respectively.

[0083] In an exemplary embodiment, the zeroth delay signal S(t0) a signal that only requires a delay through the data line DQ or an internal circuit without a separate intentional delay. For the specific data pattern DP0 the zeroth delay signal S(t0) be a signal that is in a section (e.g. tb1 ) of the duration " D[n] “ has a high level, as in Fig. 8. As shown in Fig. 8, the first delay signal can S(t1) be a signal whose phase is equal to a first time ta1 with respect to the zeroth delay signal S(t0) As it is in Fig. 8, the second delay signal S(t2) be a signal whose phase varies with a time ta2 with respect to the zeroth delay signal S(t0) is delayed.

[0084] In an exemplary embodiment, both the zeroth, first and second delay signals S(t0) , S(t1) and S(t2) be a signal that is based on the delay coefficient Cd by the delay signal generator 110-1 is generated. Phases of the first and second delay signals S(t1) and S(t2) can be determined by the delay coefficient Cd the control logic 130In an exemplary embodiment, in the case where the delay signal generator 110 three delay signal signals S(t0) , S(t1) and S(t2) generates phase differences between the delay signals S(t0) , S(t1) and S(t2) be determined to satisfy the following equation 1. t a 1 + t b 1 + t a 2 > T t a 1 ≤ t b 1 t a 2 ≤ t b 1

[0085] Referring to equation 1, ta1 a delay time of the first delay signal S(t1) represents, ta2 represents a delay time of the second delay signal S(t2) represents, tb1 represents a length of a duration of a high state of the zeroth delay signal S(t0) and " T “ represents one period of a data signal. As described above, the control logic 130 the delay coefficients Cd to satisfy equation 1.

[0086] As in Fig. 7, the pull-up driver PUD and the pull-down driver PDD based on signals from the inverter circuits INV1 until INV3 and the zeroth to mth feedback signals Y[0] until Y[m] output the final output signal Yout.

[0087] The pull-up driver PUD For example, a voltage of an output node connected to the final output signal Yout can be determined based on the signals from the inverter circuits INV1 until INV3 and the zeroth to mth feedback signals Y[0] until Y[m] This means that a pulse width of a high state duration can be increased by operating the pull-up driver PUD be enlarged.

[0088] The pull-down driver PDD can be a voltage of the output node, which is connected to the final output signal Yout based on the signals from the inverter circuits INV1 until INV3 and the zeroth to mth feedback signals Y[0] until Y[m] That is, a pulse width of a low state duration can be reduced by operating the pull-down driver PDD be enlarged.

[0089] The pull-up driver PUD can be a plurality of pull-up units PU0 until PUm2 and the pull-down driver PDD can have a plurality of pull-down units PD0 until PDm2 Each of the majority of pull-up units PU0 until PUm2 can output a high-level signal when all input signals are "0". Each of the plurality of pull-down units PD0 until PDm2 can output a low level signal when all input signals are "1".

[0090] For example, in Fig. 8, the zeroth, first and second feedback signals Y[0] , Y[1] and Y[2] D[n-1] , D[n-2] and D[n-3] at one point X[n-1] That is, at the point X[n-1] the zeroth, first and second feedback signals Y[0] , Y[1] and Y[2] have a value of “0”. In this case, referring to a pull-up driver of the 2-TAP structure before the point X[n-1] , since all inputs of the pull-up units PU11 and PU21 “0”, the pull-up units PU11 and PU21 each output signals with a high level. That is, at the point X[n-1] The final output signal Yout can be adjusted by the pull-up driver PUD be set to the high level. In other words, during a first period tpost, the high level of the final output signal Yout can be maintained by the pull-up driver PUD This can mean that a duration of a high state is interrupted by the first duration tpost by the pull-up driver PUD is increased because data bits of the non-transition state have a value of “0”.

[0091] In an exemplary embodiment, the zeroth, first and second feedback signals Y[0] , Y[1] and Y[2] in synchronization with a clock signal CK In an exemplary embodiment, the clock signal CK the data advisory signal DQS be.

[0092] Up to the point X[n] The final output signal can then Yout through the pull-up driver PUD maintain the high level. At that point X[n] For example, the zeroth, first and second feedback signals Y[0] , Y[1] and Y[2] D[n] , D[n-1] and D[n-2] That is, at the point X[n] the zeroth, first and second feedback signals Y[0] , Y[1] and Y[2] have values ​​of "1", "0" or "0". In this case, at the point X[n] , since all inputs ( Y[1] , Y[2] and an inverted version of a second delay signal) of the pull-up unit PU22 “0”, the pull-up unit PU22 output a high level signal. That is, at the point X[n] a level of the final output signal Yout be the high level. In other words, a duration of a high state can be replaced by a second duration tpre by the pull-up driver PUD be increased because data bits of the non-transition state have a value of “0”.

[0093] Compared to the zeroth delay signal S(t0) As a result, the final output signal Yout can be determined by the time tpost at the point X[n-1] be compensated and can be determined by the time tpre at the point X[n] This may mean that a high level pulse is added to the output signal Yout at the time tpost at the point X[n-1] and with time tpre at the point X[n] is added.

[0094] In an exemplary embodiment, output signals of the plurality of pull-up units PU0 until PUm2 and the majority of pull-down units PD0 until PDm2 to the output node associated with the final output signal Yout, after being adjusted by appropriate adaptation coefficients Cpu0 until Cpum2 and Cpd0 until Cpdm2 In an exemplary embodiment, adaptation coefficients assigned to the plurality of pull-up units PU0 until PUm2 and the majority of pull-down units PD0 until PDm2 In an exemplary embodiment, the adaptation coefficients Cpu0 until Cpum2 and Cpd0 until Cpdm2 from the control logic 130 and can be set through an initialization process or can be set in advance by a manufacturer's firmware.

[0095] As described above, the pulse width control 100According to exemplary embodiments of the inventive concepts, a pulse width of a high state duration or a low state duration at a current point can be increased / decreased based on the values ​​of previous data bits. As such, since an effective margin for identifying data is increased, a memory controller with improved reliability is provided.

[0096] Fig. 9 is a block diagram showing a pulse width adjuster of Fig. 6 represents. Fig. 10 is a timing chart for describing an operation of a pulse width adjuster of Fig. 9. For convenience of description, the description given with reference to the components described above will not be repeated here. For a brief description, as in the previous description, embodiments of Fig. 9 and Fig. 10 with reference to the data pattern DP0 be described with “00010”.

[0097] Referring to Fig. 9 and Fig. 10 can be a pulse width adjuster 121' a plurality of inverter circuits, the pull-up driver PUD and the pull-down driver PDD Unlike the pulse width adjuster 121 from Fig. 7 the pulse width adjuster 121' from Fig. 9 seven deceleration signals S(t0) until S(t6) received.

[0098] The delay signal generator 110 can be based on the delay coefficient Cd from the control logic 130 the majority of delay signals S(t0) until S(t6) Each of the plurality of delay signals S(t0) until S(t6) can be a delay signal whose phase is a given time with respect to the zeroth delay signal S(t0) is advanced or delayed. As in Fig. 10, for example, phases of the second and fourth delay signals S(t2) and S(t4) first and second times ta1 and ta2 with respect to the zeroth delay signal S(t0) One phase of the sixth deceleration signal S(t6) can be extended for a third time ta3 with respect to the zeroth delay signal S(t0) Although it is not in Fig. 10, a phase of each of the remaining delay signals can be shifted by a given time with respect to the zeroth delay signal S(t0) be advanced or delayed. A phase of each delay signal can be determined by the delay coefficient Cd from the control logic 130 be set.

[0099] As in the previous description, the pull-up driver PUD and the pull-down driver PDD based on signals from the plurality of inverter circuits and the zeroth to second feedback signals Y[0] until Y[2] adjust a level of the final output signal Yout. The pull-up driver PUD For example, a plurality of pull-up units PU0 until PU22 and each of the plurality of pull-up units PU0 until PU22 can output a high-level signal when all input signals are "0". The pull-down driver PDD can have a plurality of pull-down units PD0 until PD22 and each of the plurality of pull-down units PD0 until PD22 can output a low-level signal when all input signals are "1". The operation of the pull-up driver PUD and the pull-down driver PDD has been described above, and additional description will be omitted to avoid redundancy.

[0100] In an exemplary embodiment, an output signal of the pull-up unit PU0 with the pull-up driver PUD and an output signal of the pull-down unit PD0 in the pull-down driver PDD by a first adjustment coefficient Cp1 amplified, and output signals of the remaining pull-up units PU11 until PU22 with the pull-up driver PUD and output signals of the remaining pull-down units PD11 until PD22 in the pull-down driver PDD can be adjusted by a second adjustment coefficient Cp2 In this case, the value of the second adjustment coefficient Cp2 be set to be compared with the first adjustment coefficient Cp1 to be considerably larger (ie Cp2 » Cp1 ). This is to implement accurate compensation by making the strength of pull-up and pull-down units that operate in response to delay signals large.

[0101] As in Fig. 10, the final output signal can Yout through the pull-up driver PUD during a first duration tpost at a point X[n-1] and during a second duration tpre at a point X[n] be compensated. The pull-up driver PUD In other words, during the first period tpost by using the second and fourth delay signals S(t2) and S(t4) and the zeroth to second feedback signals Y[0] until Y[2] output a high level signal, and the pull-up driver PUD can be achieved during the second period tpre by using the sixth delay signal S(t6) and the zeroth to second feedback signalsY[0] until Y[2] output a high level signal. This means that the preceding data bits D[n-1] , D[n-2] and D[n-3] the same value, that is “0”, at the point X[n-1] and the preceding data bits D[n-1] and D[n-2] have the same value, ie “0” (ie D[n-1] , D[n-2] and D[n-3] have the same value, that is, “0”), a pulse width of a high duration is increased at each point.

[0102] Although it is not in Fig. 9 and Fig. 10, as in the operating method described with reference to Fig. 6 to Fig. 10, a pulse width adjustment operation may be performed on the remaining data patterns. A configuration for adjusting a pulse width of a high state duration (i.e., a duration corresponding to a data bit of "1") is described, for example, with reference to Fig. 6 to Fig. 10. However, the configuration can be applied to adjust a pulse width to a low state duration (i.e., a duration corresponding to a data bit containing "0"). In this case, a level of the final output signal Yout by the evasion driver PDD be adjusted.

[0103] Fig. 11 is a block diagram showing a pulse width control 200 according to an exemplary embodiment of the inventive ideas.

[0104] In an exemplary embodiment, the pulse width control 100 , which, with reference to Fig. 1A to Fig. 10, a data reception stage of a full-rate structure (ie a single data rate ( SDR -) Data reception stage). The pulse width control 200 from Fig. In contrast, Figure 11 shows a data reception stage of a half-rate structure (i.e. a double data rate ( DDR -) Data reception stage). That is, the pulse width control 100 , which, with reference to Fig. 1A to Fig. 10, one data bit per period of the clock signal CK (or the data indication signal DQS ) receive or identify; the pulse width control 200 from Fig. 11, in contrast, one data bit per half period of the clock signal CK (or the data indication signal DQS ) receive or identify.

[0105] Referring to Fig. 11 the pulse width control 200 a delay signal generator 210 , first and second pulse width adjusters 221 and 222 and first to fourth flip-flops or bistable multivibrators FF1 until FF4 The first and second pulse width adjusters 221 and 222 and the first to fourth flip-flops FF1 until FF4 can justify the PWC-DFE described above.

[0106] The delay signal generator 210 can be transmitted via the data line DQ a specific data pattern DP0 received and can be based on the received data pattern DP0 a plurality of delay signals S(t0) until S(tn) output. The delay signal generator 210 has been described above, and thus a detailed description of it will not be repeated here.

[0107] The first flip-flop FF1 can be controlled by the second pulse width adjuster 222 a second final output signal Yout2 received and can respond to the clock signal CK a first feedback signal Y[1] output. The second flip-flop FF2 can be controlled by the first pulse width adjuster 221 a first final output signal Youtl received and can respond to the inverted clock signal CKB a second feedback signal Y[2] output. The third flip-flop FF3 can be from the first flip-flop FF1 the first feedback signal Y[1] received and can respond to an inverted clock signal CKB a third feedback signal Y[3] output. The fourth flip-flop FF4 can be from the second flip-flop FF2 the second feedback signal Y[2] received and can respond to the clock signal CK a fourth feedback signal Y[4] spend.

[0108] The first and second pulse width adjusters 221 and 222 can be based on the plurality of delay signals S(t0) until S(tn) from the delay signal generator 210 and the first to fourth feedback signals Y[1 ] until Y[4] the first or second final output signal Youtl and Yout2 In an exemplary embodiment, configurations of the first and second pulse width adjusters 221 and 222 similar to the configuration of pulse width adjusters described with reference to Fig. 7 or Fig. 9. In an exemplary embodiment, the first and second pulse width adjusters 221 and 222 be implemented with the 2-TAP structure.

[0109] That is, each of the first and second pulse width adjusters 221 and 222 can use the pull-up driver PUD and the pull-down driver PDD and the pull-up driver PUD and the pull-down driver PDD at each of the first and second pulse width adjusters 221 and 222 can be based on input signals levels of the first and second final output signals Youtl and Yout2 adjust.

[0110] In an exemplary embodiment, each of the first and second pulse width adjusters 221 and 222 based on the first and second feedback signals Y[1] and Y[2] receive a state (ie transition information) of a data bit before one period from a current time and can be based on the third and fourth feedback signals Y[3] and Y[4] receive a state (ie, transition information) of a data bit two periods ago from the current time. In an exemplary embodiment, each of the first and second pulse width adjusters 221 and 222 by using first and second feedback signals delayed by a given time (e.g., a time corresponding to one half of the period), obtain a state (i.e., transition information) of a data bit two periods ago.

[0111] Fig. 12 is a timing chart for describing an operation of the pulse width control 200 from Fig. 11. For brevity of illustration and convenience of description, a delay (e.g., a flip-flop setup time, etc.) due to actual operation in each circuit is not precisely applied to the timing diagram. However, the inventive concepts are not limited to this. Some signals may have a delay due to, for example, an internal circuit configuration.

[0112] For the sake of simplicity of description, it is further assumed that the second pulse width adjuster 222 a pulse width adjuster which, based on the plurality of delay signals S(t0) until S(t6) is in operation, as described with reference to Fig. 9. An exemplary embodiment of Fig. 12 is further described with reference to the second final output signal Yout2 the second pulse width adjuster 222 However, the inventive ideas are not limited to this.

[0113] Referring to Fig. 11 and Fig. 12 can control the pulse width 200 received a data pattern with “00010”. This means, D[n-3] can be “0”, D[n-2] can be “0”, D[n-1] can be “0”, D[n] can be “1” and D[n+1] can be “0”. As described in the description made with reference to Fig. 9 and Fig. 10, the pulse width control can 200 the zeroth to sixth deceleration signals S(t0) until S(t6) received. The first, third and fifth delay signals S(t1) , S(t3) and S(t5) are unnecessary to operate the two pulse width adjusters 222 to describe, and a description of them will be omitted. The zeroth to sixth delay signals S(t0) until S(t6) were furthermore referred to Fig. 9 and Fig. 10, and an additional description will thus be omitted to avoid redundancy.

[0114] At one point X[n-1] the first to fourth feedback signals Y[1] to Y[4] D[n-2] , D[n-1] , D[n-2] and D[n-3] At one point X[n] Furthermore, the first to fourth feedback signals Y[1] until Y[4] D[n] , D[n-1] , D[n-2] and D[n-1] As in the previous description, the second pulse width adjuster 222 based on the first to fourth feedback signals Y[1] until Y[4] at the point X[n-1] and the point X[n] a pulse width of the second final output signal Yout2 adjust.

[0115] In an exemplary embodiment, the second final output signal Yout2 be a signal that has been delayed by a control delay time tc. The control delay time tc may be a delay time due to the second pulse width adjuster 222 In an exemplary embodiment, the control delay time may tc be determined to satisfy equation 2. t f f = t c ≤ 1 2 T

[0116] In equation 2, tff represents a delay time due to a flip-flop, tc represents a delay time due to the second pulse width adjuster 222 and " T “ represents one period of the second final output signal Yout2 or half the period of a clock signal.

[0117] In an exemplary embodiment, at the point X[n-1] the pulse width control 200 the first and second feedback signals Y[1] and Y[2]for the purpose of determining a state of a first preceding data bit and may use the third and fourth feedback signals Y[3] and Y[4] for the purpose of determining a state of a second preceding data bit. At the point X[n-1] For example, pulse width control 200 the first and second feedback signals Y[1] and Y[2] , the D[n-2] and D[n-1] are, for the purpose of determining a state of a first preceding data bit D[n-1] and can use the third and fourth feedback signals Y[3] and Y[4] , the D[n-2] and D[n-1] are, for the purpose of determining a state of a second preceding data bit D[n-2] In an exemplary embodiment, each of the first to fourth feedback signals Y[1] and Y[4] be a signal that at a given time tff regarding the beat CK and the inverted clock signal CKB The given time tff may be a delay time due to the flip-flops FF1 until FF4 be.

[0118] In an exemplary embodiment, at the point X[n] first and second delayed feedback signals Y[1]_d and Y[2]_d , which is achieved by delaying the first and second feedback signals Y[1] and Y[2] obtained by a delay time td are used to determine a state of the second preceding data bit. At the point X[n] For example, pulse width control 200 the first and second delayed feedback signals Y[1]_d and Y[2]_d , the D[n-2] and D[n-1] are, for the purpose of determining a state of a second preceding data bit D[n-1] The first and second delayed feedback signals Y[1]_d and Y[2]_d may have different signal delays, such as a delay due to a separate delay circuit and a delay due to internal wiring.

[0119] As in Fig. 12, the second pulse width adjuster 222 based on the first to fourth feedback signals Y[1] and Y[4] and the plurality of delay signals S(t0) until S(t6) the second final output signals Yout2 As in Fig. 12, a duration of a high state of the second final output signal Yout2 at the point X[n-1] and the point X[n] be increased or compensated. Since operation of the second pulse width adjuster 222 similar to an operation of a pulse width adjuster described with reference to Fig. 9 and Fig. 10, additional description will be omitted to avoid redundancy.

[0120] Fig. 13 is a block diagram showing a pulse width control 300 according to an exemplary embodiment of the inventive ideas. Fig. 14 is a diagram showing a zeroth pulse width adjuster 320 from Fig. 13. For the sake of brevity, a description associated with the components described above will not be repeated here.

[0121] Referring to Fig. 13 and Fig. 14 the pulse width control 300 a delay signal generator 310 , zeroth to second pulse width adjuster 320 until 322 , first and second multiplexers MUX1 and MUX2 and first and second flip-flops FF1 until FF2 have.

[0122] The delay signal generator 310 can be from the data line DQ a specific data pattern DP0 receive and can receive a plurality of delay signals S(t0) until S(tn) output. The delay signal generator 310 has been described above, and thus additional description will be omitted to avoid redundancy.

[0123] Each of the zeroth to second pulse width adjusters 320 until 322 the majority of delay signals S(t0) until S(tn) received, and the zeroth to second pulse width adjusters 320 until 322 Based on the received delay signals, zeroth to second intermediate signals can be Y0 until Y2 spend.

[0124] As in Fig. 14, for example, the zeroth pulse width adjuster 320 a pull-up driver PUD and a pull-down driver PDD As described above, the pull-up driver PUD may have pull-up units PU, and each of the pull-up units PU can output a high-level signal when all input signals are "0". The pull-down driver PDD can have a plurality of pull-down units PD and each of the pull-down units PD can output a low level signal when all input signals are "1".

[0125] An output signal of the pull-up unit PU0 with the pull-up driver PUD and an output signal of the pull-down unit PD0 in the pull-down driver PDD can be adjusted by a first adjustment coefficient Cp1 amplified, and an output signal of the pull-up unit PU1 with the pull-up driver PUD and an output signal of the pull-down unit PD11 in the pull-down driver PDD can be adjusted by a second adjustment coefficient Cp2 The value of the second adjustment coefficient Cp2 can be compared with the first adjustment coefficient Cp1 be considerably larger. In an exemplary embodiment, structures of the first and second pulse width adjusters 321 and 322 similar to the structure of the zeroth pulse width adjuster 320 from Fig. be 14.

[0126] A ground voltage VSS and a power supply voltage VDD can be connected to the zeroth and first input terminals Z[0] and Z[1] of the zeroth pulse width adjuster 320 be applied, the ground voltage VSS can be connected to the zeroth and first input terminals Z[0] and Z[1] of the first pulse width adjuster 321 and the power supply voltage VDD can be connected to the zeroth and first input terminals Z[0] and Z[1] the second pulse width adjuster 322 be created.

[0127] In this case, the zeroth intermediate signal Y0 of the zeroth pulse width adjuster 320 be equal to an output signal for a data pattern that has data bits of "01" or "10". The first intermediate signal Y1 of the first pulse width adjuster 321 can be equal to an output signal for a data pattern that has preceding data bits with "00". The second intermediate signal Y2 the second pulse width adjuster 322 can be equal to an output signal for a data pattern that has preceding data bits with "11". Since an operating method of the zeroth to second pulse width adjusters 320 until 322 similar to an operating method of a pulse width adjuster described with reference to Fig. 1A to Fig. 12, additional description will be omitted to avoid redundancy.

[0128] The first flip-flop FF1 can receive the first final output signal Youtl and can respond to the clock signal CK the first feedback signal Y[1] output. The second flip-flop FF2 the second final output signal Yout2 received and can respond to the inverted clock signal CKB the second feedback signal Y[2] spend.

[0129] The first multiplexer MUX1 can be based on the first and second feedback signals Y[1] and Y[2] one of the zeroth to second intermediate signals Y0 until Y2 select to output the first final output signal Youtl; the second multiplexer MUX2 can be based on the first and second feedback signals Y[1] and Y[2]one of the zeroth to second intermediate signals Y0 until Y2 to select the second final output signal Yout2 In the case where the first and second feedback signals Y[1] and Y[2] If you specify data bits with “10” or “01”, for example, the first and second multiplexers MUX1 and MUX2 the zeroth intermediate signal Y0 the zeroth to second intermediate signals Y0 until Y2 select; in the case where the first and second feedback signals Y[1] and Y[2] If you specify data bits with “00”, the first and second multiplexers MUX1 and MUX2 the first intermediate signal Y1 the zeroth to second intermediate signals Y0 until Y2 select; in the case where the first and second feedback signals Y[1] and Y[2] Data bits with " 11 “, the first and second multiplexers MUY1 and MUX2 the second intermediate signal Y2 the zeroth to second intermediate signals Y0 until Y2 choose.

[0130] As described above, the pulse width control 300 generate a plurality of intermediate signals whose pulse widths are adjusted with respect to a specific data pattern, and can select any one of the plurality of intermediate signals based on values ​​of preceding data bits and output the selected signal as a final output signal.

[0131] Fig. 15 is a timing chart for describing an operation of the pulse width control 300 from Fig. 13. An exemplary embodiment in which the first final output signal Youtl is generated with respect to a data pattern of “1101” will be described with reference to Fig. 15. For a brief description, delay times due to pulse width control components 300 in Fig. 15 is not shown. However, the inventive concepts are not limited thereto.

[0132] Referring to Fig. 13 and Fig. 15 the delay signal generator 310 the zeroth and the first deceleration signals S(t0) and S(t1) generate. The zeroth delay signal S(t0) can be used for a part of D[n] have a low level, and a phase of the first delay signal S(t1) can be extended for a first time ta1 with respect to the zeroth delay signal S(t0) get ahead.

[0133] As described above, the zeroth intermediate signal Y0 identical to the zeroth delay signal S(t0) The reason for this is that a separate pulse width control on the zeroth intermediate signal Y0 , which is associated with the case where preceding data bits are "01" or "10", is not applied. The first intermediate signal Y1 may have a data pulse whose duration of a low state is reduced, as in Fig. 15. The reason for this is that the first intermediate signal Y1 , which is assigned to the case where preceding data bits are "00", a separate pulse width control is applied. The second intermediate signal Y2 may have a data pulse that has a low level for a duration of D[n], as shown in Fig. 15. The reason for this is that the second intermediate signal Y2 , which is associated with the case where preceding data bits " 11 “, a separate pulse width control is applied.

[0134] That is, at one point X[n-1] can, since preceding data bits “ 11 “, the second intermediate signal Y2 as the first final output signal Youtl. In an exemplary embodiment, at a specific time ts, the zeroth intermediate signal Y0 as the first final output signal Youtl. At the specific time ts For example, the first feedback signal Y[1] from D[n-2] on D[n] In this case, the first and second feedback signals Y[1] and Y[2] which are fed into the first multiplexer MUX1 entered, change from D[n-2] / D[n-1] to D[n] / D[n-1].

[0135] In an exemplary embodiment, at the specific time ts, a signal coming from the first multiplexer MUX1 is output to the zeroth intermediate signal Y0change the first final output signal Youtl can be output normally. Since preceding data bits “10” or “01” with respect to a time X[n] In other words, separate pulse width compensation may not be necessary. In this respect, pulse width control 300 of the inventive ideas output a final output signal normally even though a feedback signal changes during a specific data period.

[0136] Fig. 16A and Fig. 16B are block diagrams illustrating a memory system according to an exemplary embodiment of the inventive concepts. Referring to Fig. 16A can be a storage system 40 a storage device 41 and a memory controller 42 The memory control 42 can issue a command CMD and an address ADDR to the storage device 41 send. The memory control42 can be transmitted via the data line DQ and the data notice line DQS Data “DATA” to the storage device 41 send.

[0137] In an exemplary embodiment, the memory controller 42 a pulse width control 400 The pulse width controls 100 , 200 and 300 from Fig. 1A to Fig. 15 are configured, for example, to control a pulse width of a received data signal in an input stage of a memory controller. The pulse width control 400 from Fig. 16, in contrast, a pulse width of a data signal in an output stage of the memory controller 42 and can send the data signal with the adjusted pulse width to the storage device 41 In the case where a data signal is transmitted depending on the load of the data line DQ cannot oscillate completely normally, an effective margin can be secured by adjusting a pulse width in advance to send a data signal.

[0138] Referring to Fig. 16B can be a storage system 40' a storage device 41' and a memory controller 42' The memory control 41' and the memory control 42' have been described above, and thus additional description will be omitted to avoid redundancy.

[0139] In an exemplary embodiment, the memory controller 42' a pulse width control 400' The pulse width control 400' can adjust a pulse width of a data signal in advance and can transmit the data signal with the adjusted pulse width through the data line DQ to the memory control 42' send.

[0140] That is, the storage device 41' or the memory control 42 can, as in Fig. 16A and Fig. 16B, may be configured to adjust a pulse width of a data signal in advance and transmit the data signal having the adjusted pulse width.

[0141] Fig. 17 is a block diagram showing a pulse width control 400 from Fig. 16 represents. Fig. 18 is a timing chart for describing an operation of the pulse width control 400 For a brief description, an exemplary embodiment will be described with reference to the pulse width control 400 described, but the inventive concepts are not limited thereto. With reference to Fig. 17 and Fig. 18 the pulse width control 400 a delay signal generator 410 and a pulse width adjuster 420 have.

[0142] The delay signal generator 410 can be based on an input data signal S(t0) a plurality of delay signals S(t1) until S(t5) output. The delay signal generator 410 For example, first to fifth delay devices 411 until 415 Each of the first to fifth delay devices 411 until 415 can delay and output an input signal by a given time.

[0143] The first delay device 411 the input signal can S(t0) delay by a first time and can send the first delay signal S(t1) In an exemplary embodiment, the first delay signal S(t1) Input data D[n] The second delay device 412 the first delay signal S(t1) delay by a second time and can send a second delay signal S(t2) This means that timing adjustments of the input signal S( t0 ) and the first and second delay signals S(t1) and S(t2) can in Fig. 18 are shown.

[0144] The third delay device 413 the first delay signal S(t1) , which corresponds to the input data D[n] by half the period time and can generate a third delay signal S( t3 ). The fourth delay device 414 the third delay signal S(t3) by one period and can receive a fourth delay signal S(t4) output. The fifth delay device 415 the fourth delay signal S(t4) by one period and can receive a fifth delay signal S(t5) That is, timing of the third to fifth delay signals S(t3) until S(t5) can in Fig. 18 are shown.

[0145] That is, in the case where input data has a data pattern with “00010”, the input signal S(t0) and the first to fifth deceleration signals S(t1) to S( t5 ) have curves that are Fig. 18 are shown.

[0146] The pulse width adjuster 420 the input signal S( t0 ) and the first to fifth deceleration signals S(t1) until S(t5) and can determine a pulse width of a signal on the data line based on the received signals DQ For example, in the case where the input data has a data pattern with “00010”, the pulse width adjuster 420 adjust a pulse width during a duration corresponding to a data bit with “1”, such that a signal of the data line DQ has a duration of a high state that is longer than one period.

[0147] In this respect, a signal margin according to an RC load of the data line DQ In the case where a pulse width is not adjusted, for example, a signal according to the RC load may have a curve shown by a dashed line in Fig. 18. In this case, the effective margin may be a first time T1 In the case where a pulse width is controlled by the pulse width control 400 In contrast, according to an exemplary embodiment of the inventive concepts, a signal according to the RC load may have a curve represented by a solid line in Fig. 18; in this case, the effective margin may have a second time T2 be longer than the first time T1That is, a signal margin can be secured by adjusting a pulse width corresponding to a data bit to be currently delivered based on a data bit previously sent to a memory device.

[0148] Fig. 19A to Fig. 19C are block diagrams illustrating electronic devices having a pulse width controller PWC according to the inventive concepts. For the sake of brevity, a description given with reference to the preceding components will not be repeated here.

[0149] Referring to Fig. 19A can be a system 1000 first and second devices 1100 and 1200 The first and second devices 1100 and 1200may be devices that transmit information signals, such as a data signal, an electrical signal, an analog signal or a digital signal, in the system 1000 In an exemplary embodiment, each of the first and second devices 1100 and 1200 an information processing device, such as a signal transmitter, a signal receiver, a block of intellectual property (IP), an electronic module, or an electronic circuit.

[0150] The first and second devices 1100 and 1200 Pulse width controls can 1110 or 1210 Each of the pulse width controls 1110 and 1210 may be a pulse width control, which with reference to Fig. 1A to Fig. 15. That is, the pulse width controls 1110 / 1210may be configured to control a pulse width of a signal received from the devices 1200 / 1100 is received.

[0151] Referring to Fig. 19B can be a system 2000 first and second devices 2100 and 2200 and the first and second devices 2100 and 2200 Pulse width controls can 2110 or 2210 Each of the pulse width controls 2110 and 2210 may be a pulse width control, which with reference to Fig. 16A to Fig. 18. That is, each of the first and second devices 2100 and 2200 can be configured to adjust a pulse width of a signal in advance and send the signal having the adjusted pulse width.

[0152] Referring to Fig. 19C can be a system 3000 first and second devices 3100and 3200 and the first device 3100 can first and second pulse width controls 3110 and 3120 The first pulse width control 3110 may be a pulse width control, which with reference to Fig. 16A to Fig. 18, and the second pulse width control 3120 may be a pulse width control, which with reference to Fig. 1A to Fig. 15. That is, the first device 3100 may be configured to adjust a pulse width of a signal in advance and transmit the signal having the adjusted pulse width, or may be configured to adjust a pulse width at a current point based on preceding bit values ​​of a received signal.

[0153] Fig. 20 is a block diagram illustrating an electronic system to which a transmitter and a receiver having pulse width control according to an exemplary embodiment of the inventive concepts are applied. Referring to Fig. 20, in an exemplary embodiment, an electronic system 4000 be implemented in the form of a portable communication device, a personal digital assistant (PDA), a portable multimedia player (PM), a smartphone or a transportable device, or in the form of a computing system such as a personal computer, a server, a workstation or a notebook computer.

[0154] The electrical system 4000 can use an application processor 4100 (or a central processing unit), a display 4220 and an image sensor 4230 The application processor 4100 can use a DigRF master 4110, a Display Serial Interface (DSI) host 4120 , a Camera Serial Interface (CSI) host 4130 and a physical layer 4140 have.

[0155] The DSI host 4120 can be done by the DSI with a DSI device 4225 the ad 4220 In an exemplary embodiment, an optical serial converter SER in the DSI host 4120 For example, an optical serial converter DES can be implemented in the DSI device 4225 be implemented. The CSI host 4130 can be done by the CSI with a CSI device 4235 of the image sensor 4230 In an exemplary embodiment, an optical serial converter DES in the CSI host 4130 An optical serial converter SER can be implemented, for example, in the CSI device 4235 be implemented.

[0156] The electronic system4000 can also contain a radio frequency (RF) chip 4240 to communicate with the application processor 4100 The RF chip 4240 can be a physical layer 4242 , a DigRF slave 4244 and an antenna 4246 In an exemplary embodiment, the physical layer 4242 of the RF chip 4240 and the physical layer 4140 of the application processor 4100 exchange data with each other via a MIPI-DigRF interface.

[0157] The electronic system 4000 can also have a memory 4250 and an embedded / map data store 4255 The RAM 4250 and the embedded / map data storage 4255 may be data that is transmitted by the application processor 4100 received. The RAM 4250 and the embedded / map data storage 4255the data stored therein can be transferred to the application processor 4100 delivery.

[0158] The RAM 4250 may process data transmitted by the application processor 4100 are being processed or are to be processed. The main memory 4250 may comprise volatile memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous DRAM (SDRAM), or non-volatile memory, such as flash memory, PRAM, MRAM, ReRAM, or FRAM. The embedded / card data memory 4255 may store data regardless of whether a service is provided.

[0159] The electronic system 4000 can be achieved through Worldwide Interoperability for Microwave Access (WiMAC) 4260 , a wireless local area network (WLAN) 4262and an ultra-wideband (UWB) 4264 communicate with an external system.

[0160] The electronic system 4000 can also have a loudspeaker 4270 and a microphone 4275 for processing speech information. The electronic system 4000 may also include a Global Positioning System (GPS) device 4280 for processing position information. The electronic system 4000 can also have a bridge chip 4290 to manage connections between peripheral devices.

[0161] In an exemplary embodiment, each of the components of the electronic system 400or each unit having the components can adjust a pulse width of a received signal by using a pulse width control according to the inventive concepts, or can adjust a pulse width of a signal in advance by using a pulse width control according to the inventive concepts, and can transmit the signal having the adjusted pulse width.

[0162] According to an exemplary embodiment of the inventive concepts, an electronic device can adjust a pulse width of a data signal corresponding to a current data bit based on previous data bits. An operating method of a signal receiver having improved reliability, a pulse width controller, and an electronic device including the signal receiver and the pulse width controller are accordingly provided.

[0163] According to one or more exemplary embodiments, the units and / or devices described above, including pulse width control elements 100 , 200 , 300 , 400 , such as the control logic, delay signal generators and pulse width controlled decision feedback generators (PWC-DFEs) and sub-elements thereof (e.g., the pulse width adjuster, the sampler, the first to m-th delay devices), may be implemented using hardware, a combination of hardware and software, or a non-transitory storage medium storing software executable to perform the functions thereof.

[0164] Hardware may be implemented using processing circuitry, such as, but not limited to, one or more processors, one or more central processing units (CPUs), one or more controllers, one or more arithmetic logic units (ALUs), one or more digital signal processors (DSPs), one or more microcomputers, one or more field-programmable gate arrays (FPGAs), one or more systems on a chip (SoCs), one or more programmable logic units (PLUs), one or more microprocessors,one or more application-specific integrated circuits (ASICs) or any other device or devices capable of responding to and executing instructions in a defined manner.

[0165] Software may include a computer program, program code, instructions, or a combination thereof for independently or collectively instructing or configuring a hardware device to operate as desired. The computer program and / or program code may include a program or computer-readable instructions, software components, software modules, data files, data structures, etc., that is or are capable of being implemented by one or more hardware devices, such as one or more of the hardware devices mentioned above. Examples of program code include both machine code generated by a compiler and higher-level program code executed using an interpreter.

[0166] For example, if a hardware device is a computer processing device (e.g., one or more processors, one or more CPUs, one or more controllers, one or more ALUs, one or more DSPs, one or more microcomputers, one or more microprocessors, etc.), the computer processing device may be configured to execute the program code by performing arithmetic, logical, and input / output operations according to the program code. Once the program code has been loaded into a computer processing device, the computer processing device may be programmed to execute the program code, thereby converting the computer processing device into a special-purpose computer processing device.In one specific example, when the program code is loaded into a processor, the processor is programmed to execute the program code and operations corresponding thereto, thereby converting the processor into a special-purpose processor. In another example, the hardware device may be an integrated circuit customized as special-purpose processing circuitry (e.g., an ASIC).

[0167] A hardware device, such as a computer processing device, may run an operating system (OS) and one or more software applications running on the OS. The computer processing device may further access, store, manipulate, process, and create data in response to the execution of the software. For simplicity, one or more example embodiments may be illustrated as a computer processing device; however, those skilled in the art will appreciate that a hardware device may include multiple processing elements and multiple types of processing elements. For example, a hardware device may include multiple processors or a processor and a controller. Other processing configurations are additionally possible, such as parallel processors.

[0168] Software and / or data may be permanently or temporarily embodied as any type of storage medium, including, but not limited to, a machine, component, physical or virtual equipment, or a computer storage medium or device capable of delivering instructions or data to or interpreting them through a hardware device. The software may further be distributed across network-coupled computer systems such that the software is stored and executed in a distributed manner. In particular, software and data may be stored, for example, by one or more computer-readable recording media, including tangible or non-transitory computer-readable storage media, as discussed herein.

[0169] Storage media may further comprise one or more storage devices in units and / or devices according to one or more example embodiments. The one or more storage devices may be tangible or non-transitory computer-readable storage media, for example, random access memory (RAM), read-only memory (ROM), a permanent mass storage device (such as a disk drive), and / or any other similar data storage means capable of storing and recording data.The one or more storage devices may be configured to store computer programs, program code, instructions, or a combination thereof for one or more operating systems and / or for implementing the exemplary embodiments described herein. The computer programs, program code, instructions, or a combination thereof may further be loaded from a separate computer-readable storage medium into the one or more storage devices and / or the one or more computer processing devices using a drive device.Such a separate computer-readable storage medium may include a Universal Serial Bus (USB) flash drive, a memory stick, a Blu-ray / DVD / CD-ROM drive, a memory card, and / or similar computer-readable storage media. The computer programs, program code, instructions, or combinations thereof may be loaded into the one or more storage devices and / or the one or more computer processing devices from a remote data storage device via a network interface, rather than via a computer-readable storage medium.The computer programs, program code, instructions, or a combination thereof may additionally be loaded into the one or more storage devices and / or the one or more processors by a remote computing system configured to transmit and / or distribute the computer programs, program code, instructions, or a combination thereof over a network. The remote computing system may transmit and / or distribute the computer programs, program code, instructions, or a combination thereof over a wired interface, an over-the-air interface, and / or any other similar medium.

[0170] The one or more hardware devices, storage medium, computer programs, program code, instructions, or a combination thereof may be specifically designed and constructed for the purposes of the exemplary embodiments, or they may be known devices that have been altered and / or modified for the purposes of exemplary embodiments.

[0171] Although exemplary embodiments of the inventive concepts have been described with reference to some exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 1020170155874

[0001] KR 1020180051570

[0001]

Claims

[1] Operating procedure of a signal receiver, with the following steps: successively receiving (S110) a zeroth bit and a first bit through a signal line (DQ); and selectively adjusting (S150, S160) a width of either a first high state duration or a first low state duration of a first signal corresponding to the first bit based on values ​​of the zeroth bit and the first bit based on whether the values ​​of the zeroth bit and the first bit are identical. [2] The method of claim 1, wherein the first duration of a low state of the first signal increases when the values ​​of the zeroth bit and the first bit are logically high, and the first duration of a high state of the first signal increases when the zeroth bit and the first bit are logically low. [3] The method of claim 1, further comprising the steps of: Receiving a second bit after receiving the zeroth bit and the first bit; adjusting the width of either a second high-state duration or a second low-state duration of a second signal corresponding to the second bit based on the values ​​of the zeroth bit and the first bit in response to the zeroth bit and the first bit being identical; and Adjusting the width of either the second high state duration or the second low state duration of the second signal based on the value of the first bit and a value of the second bit responsive to the first bit and the second bit being identical. [4] The method of claim 3, wherein the second duration of a low state of the second signal increases when the values ​​of the zeroth bit and the first bit are logically high, or when the values ​​of the first bit and the second bit are logically high, and the second duration of a high state of the second signal increases when the values ​​of the zeroth bit and the first bit are logically low, or when the values ​​of the first bit and the second bit are logically low. [5] The method of claim 3, wherein the width of either the second high state duration or the second low state duration of the second signal increases by a first amount when the zeroth bit to the second bit have an equal value, and the width of either the second high state duration or the second low state duration of the signal increases by a second amount shorter than the first amount when any of the zeroth bit to the second bit of remaining bits differs. [6] The method of claim 3, wherein the width of the second high state duration and the width of the second low state duration of the second signal are not adjusted when the zeroth bit and the first bit are different from each other and the first bit and the second bit are different from each other. [7] Pulse width control (100; 200; 300; 400; 1110; 1210; 2110, 2210; 3110, 3120) with: an interface configured to receive a signal; and a processing circuit arrangement (120) configured to to sample an output signal (Yout) to output a zeroth feedback signal (Y[0]), to delay the zeroth feedback signal (Y[0]) to output a first feedback signal (Y[1]), to adjust a width of either a high state duration or a low state duration of the output signal (Yout) when values ​​of the zeroth feedback signal (Y[0]) and the first feedback signal (Y[1]) are identical. [8] Pulse width controller (100; 200; 300; 400; 1110; 1210; 2110, 2210; 3110, 3120) according to claim 7, wherein the signal is associated with a plurality of bits received through the same line (DQ), the processing circuitry being configured to to output a plurality of delay signals (S(t0)-S(tn)) based on the signal. [9] Pulse width controller (100) according to claim 8, wherein the processing circuitry (120) has the following features: a plurality of inverter circuits (INV1, INV2, INV3) configured to receive respective ones of the plurality of delay signals (S(t0)-S(tn)) and to output respective ones of a plurality of inverted delay signals; a pull-up driver (PUD) configured to adjust a width of the duration of a high state of the output signal (Yout) based on the plurality of inverted delay signals, the zeroth feedback signal (Y[0]), and the first feedback signal (Y[1]); and a pull-down driver (PDD) configured to adjust a width of the duration of a low state of the output signal (Yout) based on the plurality of inverted delay signals, the zeroth feedback signal (Y[0]), and the first feedback signal (Y[1]). [10] Pulse width controller (100) according to claim 9, wherein the processing circuitry is configured to to generate at least one delay coefficient (Cd) and at least one adaptation coefficient (Cp), and to output the plurality of delay signals (S(t0)-S(tn)) based on the at least one delay coefficient (Cd), and wherein the pull-up driver (PUD) and the pull-down driver (PDD) control the width of the duration of a high state and the width of the duration of a low state based on the at least one adaptation coefficient (Cp). [11] Pulse width controller (100) according to claim 8, wherein the processing circuitry (120) is configured to based on the plurality of delay signals (S(t0)-S(tn)), to increase a width of the duration of a low state of the output signal (Yout) when the zeroth feedback signal (Y[0]) and the first feedback signal (Y[1]) are both logic high, and based on the plurality of delay signals (S(t0)-S(tn)), to increase a width of the duration of a high state of the output signal (Yout) when the zeroth feedback signal (Y[0]) and the first feedback signal (Y[1]) are both logic low. [12] Pulse width controller (100) according to claim 8, wherein the processing circuitry is further configured to to delay the first feedback signal (Y[1]) to output a second feedback signal (Y[2]). based on the plurality of delay signals (S(t0)-S(tn)), to increase a width of the duration of a low state of the output signal (Yout) when the zeroth feedback signal (Y[0]) and the first feedback signal (Y[1]) are logically high, or when the first feedback signal (Y[1]) and the second feedback signal (Y[2]) are logically high, and based on the plurality of delay signals (S(t0)-S(tn)), to increase a width of the duration of a high state of the output signal (Yout) when the zeroth feedback signal (Y[0]) and the first feedback signal (Y[1]) are logically low, or when the first feedback signal (Y[1]) and the second feedback signal (Y[2]) are logically low. [13] Pulse width controller (100) according to claim 12, wherein the plurality of bits comprises a zeroth bit, a first bit and a second bit, the zeroth bit up to the second bit are received consecutively via the interface through the same line, and the zeroth feedback signal (Y[0]) corresponds to the second bit, the first feedback signal (Y[1]) corresponds to the first bit and the second feedback signal (Y[2]) corresponds to the zeroth bit. [14] Electronic device (1100, 1200; 2100, 2200; 3100) comprising: a delay signal generator (110; 210; 310; 410) configured to sequentially receive a signal having a zeroth bit, a first bit, and a second bit, and to delay the signal to generate a plurality of delay signals (S(t0)-S(tn)); and a pulse width controlled decision feedback equalizer (120) configured to adjust a width of either a high state duration or a low state duration of an output signal (Yout) based on the plurality of delay signals (S(t0)-S(tn)) when the zeroth bit and the first bit are identical, or when the first bit and the second bit are identical. [15] The electronic device (1100, 1200; 2100, 2200; 3100) of claim 14, wherein the pulse width controlled decision feedback equalizer (120) is configured to to increase a width of the duration of a low state of the output signal (Yout) when the zeroth bit and the first bit are logically high, or when the first bit and the second bit are logically high, and to increase a width of the duration of a high state of the output signal (Yout) when a zeroth feedback signal (Y[0]) and a first feedback signal (Y[1]) are logic low, or when the first feedback signal (Y[1]) and a second feedback signal (Y[2]) are logic low. [16] The electronic device (1100, 1200; 2100, 2200; 3100) of claim 14, wherein the pulse width controlled decision feedback equalizer (120) is configured to increasing a width of either the duration of a high state or the duration of a low state of the output signal (Yout) by a first amount if the zeroth bit to the second bit are identical, and to increase a width of either the high state duration or the low state duration of the output signal (Yout) by a second amount shorter than the first amount, (i) when the zeroth bit and the first bit are identical and the first bit and the second bit are different, or (ii) when the zeroth bit and the first bit are different and the first bit and the second bit are identical. [17] Electronic device (1100, 1200; 2100, 2200; 3100) according to claim 14, further comprising: a control logic (130) configured to provide at least one delay coefficient (Cd) to the delay signal generator (110) and to provide at least one adjustment coefficient (Cp) to the pulse width controlled decision feedback equalizer (120), wherein the delay signal generator (110) is configured to output the plurality of delay signals (S(t0)-S(tn)) based on the at least one delay coefficient (Cd), and the pulse width controlled decision feedback equalizer (120) is configured to adjust a width of either the duration of a high state or the duration of a low state based on the at least one adjustment coefficient (Cp). [18] The electronic device (1100, 1200; 2100, 2200; 3100) of claim 14, wherein the pulse width controlled decision feedback equalizer (120) comprises: a sampler (122) configured to sample the output signal (Yout) to output a zeroth feedback signal (Y[0]) corresponding to the second bit; a first delay device (123-1) configured to delay the zeroth feedback signal (Y[0]) to output a first feedback signal (Y[1]) corresponding to the first bit; a second delay device (123-2) configured to delay the first feedback signal (Y[1]) to output a second feedback signal (Y[2]) corresponding to the zeroth bit; and a pulse width controller (121) configured to to receive the plurality of delay signals (S(t0)-S(tn)) and the zeroth to second feedback signals (Y[0]-Y[2]), and to adapt a width of either the duration of a high state or the duration of a low state of the output signal (Yout) when the zeroth feedback signal (Y[0]) and the first feedback signal (Y[1]) are identical, or when the first feedback signal (Y[1]) and the second feedback signal (Y[2]) are identical. [19] The electronic device (1100, 1200; 2100, 2200; 3100) of claim 14, wherein the pulse width controlled decision feedback equalizer comprises: a first flip-flop (FF1) configured to receive a first output signal (Yout2) of the output signal (Yout) and to output a first feedback signal (Y[1]) in response to a clock signal (CK); a second flip-flop (FF2) configured to receive a second output signal (Yout1) of the output signal (Yout) and to output a second feedback signal (Y[2]) in response to an inverted clock signal (CKB) obtained by inverting the clock signal (CK); a third flip-flop (FF3) configured to receive the first feedback signal (Y[1]) and to output a third feedback signal (Y[3]) in response to the inverted clock signal (CKB); a fourth flip-flop (FF4) configured to receive the second feedback signal (Y[2]) and to output a fourth feedback signal (Y[4]) in response to the clock signal (CK); a first pulse width controller (222) configured to output the first output signal (Yout2) based on the first feedback signal (Y[1]), the second feedback signal (Y[2]), the third feedback signal (Y[3]), the fourth feedback signal (Y[4]), and the plurality of delay signals (S(t0)-S(tn)); and a second pulse width controller (221) configured to output the second output signal (Yout1) based on the first feedback signal (Y[1]), the second feedback signal (Y[2]), the third feedback signal (Y[3]), the fourth feedback signal (Y[4]), and the plurality of delay signals (S(t0)-S(tn)). [20] The electronic device (1100, 1200; 2100, 2200; 3100) of claim 14, wherein the pulse width controlled decision feedback equalizer comprises: a zeroth pulse width controller (320) configured to generate a zeroth intermediate signal (Y0) based on the plurality of delay signals (S(t0)-S(tn)) in response to a ground voltage (VSS) and a power supply voltage (VDD); a first pulse width controller (322) configured to generate a first intermediate signal (Y2) based on the plurality of delay signals (S(t0)-S(tn)) in response to the power supply voltage (VDD); a second pulse width controller (321) configured to generate a second intermediate signal (Y1) based on the plurality of delay signals (S(t0)-S(tn)) in response to the ground voltage (VSS); a first flip-flop (FF1) configured to receive a first output signal (Yout1) of the output signal (Yout) and to output a first feedback signal (Y[1]) in response to a clock signal (CK); a second flip-flop (FF2) configured to receive a second output signal (Yout2) of the output signal (Yout) and to output a second feedback signal (Y[2]) in response to an inverted clock signal (CKB) obtained by inverting the clock signal (CK); a first multiplexer (MUX1) configured to output, based on the first feedback signal (Y[1]) and the second feedback signal (Y[1]), either the zeroth intermediate signal (Y0), the first intermediate signal (Y1), or the second intermediate signal (Y2) as the first output signal (Yout1); and a second multiplexer (MUX2) configured to output one of the zeroth intermediate signal (Y0), the first intermediate signal (Y1), and the second intermediate signal (Y2) as the second output signal (Yout2) based on the first feedback signal (Y[1]) and the second feedback signal (Y[1]). [21] The electronic device (1100, 1200; 2100, 2200; 3100) of claim 14, wherein the plurality of delay signals (S(t0)-S(tn)) comprises first to fifth delay signals (S(t1)-S(t5)), and wherein the delay signal generator (410) comprises: a first delay device (411) configured to generate the first delay signal (S(t1)) by delaying the signal; a second delay device (412) configured to generate the second delay signal (S(t2)) by delaying the first delay signal (S(t1)); a third delay device (413) configured to generate the third delay signal (S(t3)) by delaying the first delay signal (S(t1)) by one half of a period of the signal; a fourth delay device (414) configured to generate the fourth delay signal (S(t4)) by delaying the third delay signal (S(t3)) by one period of the signal; and a fifth delay device (415) configured to generate the fifth delay signal (S(t5)) by delaying the fourth delay signal (S(t4)) by the one period of the signal. [22] The electronic device (1100, 1200; 2100, 2200; 3100) of claim 21, wherein the pulse width controlled decision feedback equalizer is configured to based on the signal and the first to fifth delay signals (S(t1)-S(t5)), adjust a width of either the duration of a high state or the duration of a low state of the output signal (Yout) to produce an adjusted output signal; and to send the adjusted output signal to an external device. [23] Signal transmitter with: a delay signal generator (110; 210; 310; 410) configured to receive a signal having a zeroth bit, a first bit, and a second bit, and to generate a plurality of delay signals (S(t0)-S(tn)) by delaying the signal; and a pulse width adjuster (121; 221; 222; 320; 321; 322; 420) configured to adjust a width of either a high state duration or a low state duration of an output signal (Yout) to produce an adjusted output signal when the zeroth bit and the first bit are identical, or when the first bit and the second bit are identical, and output the adjusted output signal through a data line to an external device.

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