Semiconductor device and method for its manufacture

Abstract

Semiconductor device comprising: redistribution structures (105) connected to external terminals (157); a first semiconductor device (109) connected to the redistribution structures (105); an antenna substrate (141) located above the redistribution structures (105); and electrical terminals (147) separate from the first semiconductor device (109), the first semiconductor device (109) being electrically connected to the antenna substrate (141) through the redistribution structures (105) and the electrical terminals (147);and an antenna assembly (137) which is connected to the redistribution structures (105), wherein the antenna assembly (137) comprises the antenna substrate (141) and a first antenna (171) which is formed along outer side walls of the antenna substrate (141), wherein the first antenna (171) is connected to the redistribution structures (105) by a second antenna which is located between the redistribution structures (105) and the antenna substrate (141).

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US patent application No. 62 / 674,337, entitled “Semiconductor Device and Method of Manufacture”, filed on May 21, 2018, which application is hereby incorporated in its entirety by reference. GENERAL STATE OF THE ART

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density largely stems from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards a node below 20 nm), allowing for the integration of more components into a given area. As the demand for miniaturization, higher speed, and greater bandwidth has increased recently, a need has arisen for smaller and more innovative packaging techniques for semiconductor dies.

[0003] With the further advancement of semiconductor technologies, stacked and bonded semiconductor devices have emerged as an effective alternative to further miniaturizing the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, and the like are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device. Such bonding processes employ sophisticated techniques, and improvements are desired. List of characters

[0004] The aspects of this disclosure are best understood from the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as appropriate for the clarity of the discussion. Fig. 1A to Fig. Figure 1G illustrates an integrated antenna in an integrated fan-out configuration according to some embodiments. Fig. 2A to Fig. Figure 2F illustrates thermal vias incorporated into the integrated fan-out structure according to some embodiments. Fig. 3A to Fig. 3G illustrates vias incorporated into the integrated fan-out structure according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, of carrying out various features of the invention. Certain examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially related terms such as "below," "under," "below," "above," "over," and the like may be used here for the sake of simplicity to describe the relationship of one element or feature to another element(s) or feature(s) as depicted in the figures. These spatially related terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially related terms used here may be interpreted accordingly.

[0007] Embodiments are described below in connection with a specific application that uses a heterogeneous fan-out setup for millimeter-wave radio frequency applications. However, the embodiments are not limited to these embodiments and can be used in a wide variety of applications.

[0008] With reference to the following Fig. 1A are a carrier substrate 101 , an adhesive layer 103 , and a first redistribution layer 105 above the carrier substrate 101 illustrated. In one embodiment, the support substrate comprises 101 For example, silicon-based materials such as glass or silicon dioxide, or other materials such as aluminum oxide, combinations of any of these materials, or the like. The support substrate 101 is flat, in order to prevent the formation of the first redistribution layer 105to accommodate.

[0009] The adhesive layer 103 can be applied over the carrier substrate 101 They are arranged to prevent the formation of overlying structures on the substrate. 101 to support. In one embodiment, the adhesive layer 103 a die-attach film (DAF) such as an epoxy resin, a phenolic resin, acrylic rubber, a silicon dioxide filler, or a combination thereof, and it is applied using a lamination technique. In one embodiment, the adhesive layer can 103 a separating film such as a light-to-heat conversion (LTHC) film. In yet another embodiment, the adhesive layer can be 103It could be a double layer, comprising a release film along with an overlying polymer layer to provide a surface for further processing. However, any other suitable material and formation process can be used.

[0010] After the adhesive layer 103 ordered, can above the detention layer 103 optional underbump metallization layers and the first redistribution layers 105in one embodiment, the underbump metallization layers may comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, a person skilled in the art will recognize that there are many suitable arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, that are suitable for forming the underbump metallization layers. It is entirely intended that any suitable materials or layers of materials that can be used for the underbump metallization layers are included in the scope of the embodiments.

[0011] In one embodiment, the underbump metallization layers are formed by creating each layer above the adhesive layer. 103The formation of each layer can be carried out using a plating process such as electrochemical plating, although other formation processes such as sputtering, vapor deposition, or a PECVD process can also be used depending on the desired materials. The underbump metallization layers can be formed to have a thickness between approximately 0.7 µm and approximately 10 µm, such as approximately 5 µm.

[0012] In one embodiment, the first redistribution layers comprise 105 a series of leading layers 133 (such as two or three conductive layers) that are divided into a series of dielectric layers 135(such as three or four dielectric layers) are embedded and are used not only to provide conductive routing for signals, but can also be used to provide structures such as integrated inductors or capacitors. In one embodiment, a first of the series of dielectric layers is 135 above the adhesive layer 103 formed, and can be the first in a series of dielectric layers 135 It could be a material such as polybenzoxazole (PBO), although any suitable material such as polyimide or a polyimide derivative can be used. The first in the series of dielectric layers. 135 can be arranged, for example, using a centrifugal coating process, although any suitable method can be used.

[0013] After the first of the series of dielectric layers 135The layers formed can be removed by eliminating parts of the first series of dielectric layers. 135 Openings are created within it. The openings can be formed using a suitable photolithographic masking and etching process, although any suitable process can be used to create the first of the series of dielectric layers. 135 to structure.

[0014] After the first of the series of dielectric layers 135 The first of the series of dielectric layers, which was formed and structured, is located above it. 135 and through the openings that are in the first of the series of dielectric layers 135 are formed, a first in the series of leading layers 133 formed. In one embodiment, the first of the series of conductive layers can be 133This can be achieved by initially forming a seed layer of a titanium-copper alloy through a suitable formation process such as CVD or sputtering. A photoresist can then be formed to cover the seed layer, and this photoresist can subsequently be structured to expose those parts of the seed layer that are located where the first of the series of conductive layers is situated. 133 is to be located.

[0015] After the photoresist has been formed and structured, a conductive material such as copper can be deposited onto the seed layer using a deposition process such as plating. The conductive material can be formed to have a thickness between approximately 1 µm and 10 µm, for example, 5 µm. However, although the materials and processes discussed are suitable for forming the conductive material, these are merely examples. Any other suitable materials, such as AlCu or Au, and any other suitable formation processes, such as CVD or PVD, can be used to create the first series of conductive layers. 133to form. Once the conductive material has formed, the photoresist can be removed by a suitable removal process such as ashing. Furthermore, after the photoresist has been removed, those parts of the nucleus layer that were covered by the photoresist can be removed, for example, by a suitable etching process using the conductive material as a mask.

[0016] After the first of the series of leading layers 133 Once a second layer of dielectric layers has been formed, repeating the steps can create a second layer. 135 and a second from the series of leading layers 133 , the first in the series of dielectric layers 135 and the first in the series of leading layers 133 similar, are formed. These steps can be repeated as desired to create each of the series of conducting layers. 133electrically with an underlying series of conductive layers 133 to connect, and can be repeated as often as desired until a topmost of the series of conductive layers is reached. 133 and one uppermost of the series of dielectric layers 135 was formed. In one embodiment, the deposition and structuring of the series of conductive layers can be achieved. 133 and the series of dielectric layers 135 to continue until the first redistribution layers 105 have a desired number of layers, although any suitable number of individual layers can be used.

[0017] Fig. Figure 1B illustrates a connection of a first semiconductor device 109 and a second semiconductor device 111 with the first redistribution layers 105 In one embodiment, the first semiconductor device 109a semiconductor device that provides logic functions to the structures. For example, the first semiconductor device could be 109 It may be an integrated power management integrated circuit (PMIC), although any suitable logic function or other functions may be used. In some embodiments, the first semiconductor device may be 109 the same as the second semiconductor device 111 be, for example, an RFFE, an IC, an RF chip, or a power amplifier (PA).

[0018] In one embodiment, the first semiconductor device comprises 109A first substrate, first active devices, first metallization layers, first contact pads, and first external connections. The first substrate can be solid silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or combinations thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or hybrid alignment substrates.

[0019] The first active devices encompass a wide variety of active and passive devices such as capacitors, resistors, inductors, or the like, which can be used to meet the desired structural and functional design requirements for the first semiconductor device. 109to generate. The first active devices can be formed using any method, either in or on the first substrate.

[0020] The first metallization layers of the first semiconductor device 109The first metallization layers are formed above the first substrate and the first active devices and are designed to connect the various active devices to form a functional circuit arrangement. In one embodiment, the first metallization layers are formed from alternating layers of a dielectric and a conductive material and can be formed by any suitable process (such as deposition, damascene, dual-damascene, etc.). In one embodiment, four layers of a metallization can be separated from the first substrate by at least one interlayer dielectric layer (ILD), but the exact number of first metallization layers depends on the design of the first semiconductor device. 109 away.

[0021] The first contact pads can be formed above and within an electrical contact with the first metallization layers. These first contact pads can comprise aluminum, but other materials such as copper can also be used. The first contact pads can be formed using a deposition process such as sputtering to create a layer of the material (not shown), after which portions of the material layer can be removed by a suitable process (such as photolithographic masking and etching) to form the first contact pads. However, any other suitable process can be used to form the first contact pads. The first contact pads can be formed to have a thickness between approximately 0.5 µm and approximately 10 µm, such as approximately 7 µm.

[0022] The first external connections can be formed to create conductive areas for contact between the first contact connection surfaces and the first redistribution layers. 105to provide. The first external connections can be conductive bumps (e.g., micro-bumps) or conductive pillars using materials such as solder and copper. In an embodiment where the first external connections are contact bumps, the first external connections can comprise a material such as tin, or other suitable materials such as silver, lead-free tin, or copper. In an embodiment where the first external connections are tin solder bumps, the first external connections can be formed by initially forming a layer of tin to a thickness of, for example, about 20 µm using commonly used methods such as vapor deposition, electroplating, printing, solder transfer, ball arrangement, etc. After a tin layer has been formed on the assembly, a reflow can be performed to shape the material into the desired bump shape.

[0023] In embodiments where the first external connections are conductive pillars, these connections can be formed by initially placing a photoresist and then structuring the photoresist into the desired structure for the conductive pillars. A plating process is then used to bond the conductive material (e.g., copper) to the first contact surfaces. However, any suitable method can be used.

[0024] As an average person skilled in the art will recognize, the processes described above for forming the first external connections are merely descriptive and are not intended to restrict the embodiments to these specific processes. Rather, the described processes are intended to be illustrative, since any suitable process for forming the first external connections can be used.

[0025] Once it has been formed, the first semiconductor device can 109 e.g. using a capture and arrangement tool on the first redistribution layers 105 can be arranged. For example, the first external connections of the first semiconductor device can be 109 with corresponding positions in the first redistribution layers 109 They must be aligned and brought into physical contact. Once in physical contact, a reflow process can be performed to melt the first external leads and create the first semiconductor device. 109 to the first redistribution layers 105 to bond. In some embodiments, before arranging the first semiconductor device 109 an optional UBM on the first redistribution layers 105 be formed.

[0026] The second semiconductor device 111can be used to provide functionality to the entire setup, for example by using radio frequency front-end devices such as low-noise amplifiers (LNAs), low-loss filters, power amplifiers (PAs), baseband modules (BBs), switching functions, signal conditioning, combinations thereof, or the like. The second semiconductor device 111 can the first semiconductor device 109 The two semiconductor substrates must be similar in that they have approximately a similar thickness and a second semiconductor substrate, second active and / or passive devices formed on the second semiconductor substrate, second contact pads, and second external connections, each similar to the first semiconductor substrate, first active devices, first contact pads, and first external connections. However, any suitable configuration may be used.

[0027] Furthermore, the second semiconductor device 111 e.g. using a capture and arrangement tool on the first redistribution layers 105 can be arranged. For example, the second external connections of the semiconductor device can be 111 with corresponding positions in the first redistribution layers 109 They must be aligned and brought into physical contact. Once in physical contact, a reflow process can be performed to melt the second external leads and encapsulate the second semiconductor device. 111 to the first redistribution layers 105 to bond.

[0028] After the first semiconductor device 109 and the second semiconductor device 111 If the components were bonded (either simultaneously or separately), an underfill material can be used. 115 between the first redistribution layers 105and both the first semiconductor device 109 as well as the second semiconductor device 111 They are arranged to help protect and insulate the devices. In one embodiment, the underfill material is 115 a protective material used to create the first semiconductor device 109 and the second semiconductor device 111 to mitigate and bear the impact of operational and environmental damage, such as stresses caused by heat generation during operation. The underfill material 115 It can, for example, comprise a liquid epoxy or other protective material, which is then cured and solidified, and can be distributed, for example, by injection.

[0029] Fig. 1C illustrates the construction of a first antenna structure. 137 and a second antenna setup 139 , which are attached to the first redistribution layers105 be bonded. Although they are in Fig. 1C are shown as separate from each other, the first antenna structure can be seen 137 and the second antenna setup 139 In embodiments, the antennas are located in the same component and are manufactured simultaneously. In one embodiment, the first antenna assembly comprises 137 a first antenna substrate 141 , a second redistribution layer 143 , a first passivation layer 145 above the second redistribution layer 143 , second external ports 147 , a feed-in element 149 , a first upper antenna layer 151 , and a second passivation layer 153 .

[0030] In one embodiment, the first antenna substrate 141The substrate may consist of one or more layers of a substrate material such as an organic polymer material (e.g., a polymer such as a resin, benzocyclobutene (BCB), or a prepreg material), a glass material (e.g., silicon dioxide), a ceramic material, solid silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid alignment substrates. Any suitable substrate material may be used.

[0031] Optionally, the first antenna substrate can be 141 with conductive tracks (e.g. metal tracks) or paths that extend into the first antenna substrate 141The conductive pathways are incorporated to allow for additional routing. In such an embodiment, the conductive pathways can be formed by depositing a seed layer over one of the layers of the polymer material, and then arranging and structuring a photoresist over the seed layer. After structuring in the shape of the desired conductive pathways has been performed, a plating process utilizing the seed layer can be used to form the conductive pathways, the photoresist can be removed, and the seed layer can be etched. This process can be repeated on each layer of the polymer material, forming overlying layers of conductive pathways in electrical contact with the underlying layers. However, any other suitable processes, such as Damascene or dual-Damascene processes, can also be used.

[0032] A feed-in element 149can be done through the first antenna substrate 141 through which the first upper antenna layer is formed. 151 on one side of the first antenna substrate 141 electrically with the second external connections 147 on a second side of the first antenna substrate opposite the first side 141 to connect. In one embodiment, the feed-in element can 149 For example, a through-substrate via (TSV) connection that extends from one side of the first antenna substrate. 141 to a second side of the antenna substrate 141 The process can be carried out and formed by initially creating openings in the first antenna substrate. 141 The openings can be formed by applying and developing a suitable photoresist and removing sections of the first antenna substrate. 141Openings are formed that are exposed to the desired depth. These openings can be designed to extend to a depth greater than the final desired height of the first antenna substrate. 141 is, into the first antenna substrate 141 extend.

[0033] After the openings in the first antenna substrate 141Once formed, the openings can be lined with a coating. The coating can be, for example, an oxide formed from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material can be used. The coating can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, although other suitable processes such as physical vapor deposition or a thermal process can be used. Furthermore, the coating can be formed to have a thickness between approximately 0.1 µm and approximately 5 µm, such as approximately 1 µm.

[0034] After the lining has been formed along the sidewalls and bottom of the openings, a barrier layer (also not shown independently) can be formed, and the remainder of the openings can be filled with a primary conductive material. The primary conductive material may include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, or the like may be used. The primary conductive material can be formed by electroplating copper onto a nucleation layer (not shown), filling, and overfilling the openings. Once the openings are filled, the excess lining, barrier layer, nucleation layer, and primary conductive material outside the openings can be removed by a planarization process such as chemical-mechanical polishing (CMP), although any suitable removal process may be used.

[0035] After the feed-in element 149 Once formed, the second redistribution layer can be established. 143 can be formed. In one embodiment, a first section of the second redistribution layer can be formed. 143 in an electrical connection with the feed-in element 149 formed to provide a connection for signals coming from the first upper antenna layer 151 on the opposite side of the first antenna substrate 141 to be sent and received. In addition, a second section of the second redistribution layer is to be provided. 143 electrically connected to the earth (e.g. through the second external connections) 147 ) and acts as a grounded element or grounding plane.

[0036] In one embodiment, the second redistribution layer 143This can be achieved by initially forming a nucleation layer (not shown) of a titanium-copper alloy through a suitable formation process such as CVD or sputtering. A photoresist (also not shown) can then be formed to cover the nucleation layer, and the photoresist can subsequently be structured to expose those sections of the nucleation layer that are located where the second redistribution layer is situated. 143 is to be located.

[0037] After the photoresist has been formed and structured, a conductive material such as copper can be deposited onto the seed layer via a deposition process such as plating. The conductive material can be formed to have a thickness between approximately 1 µm and approximately 20 µm, such as 15 µm. However, although the material and processes discussed are suitable for forming the conductive material, these materials are merely examples. Any other suitable materials, such as AlCu or Au, and any other suitable formation processes, such as CVD or PVD, can be used to form the second redistribution layer. 143 to form.

[0038] Once the conductive material has formed, the photoresist can be removed by a suitable removal process such as chemical stripping and / or ashing. Furthermore, after the photoresist has been removed, those sections of the nucleation layer that were covered by the photoresist can be removed, for example, by a suitable etching process using the conductive material as a mask.

[0039] Although, incidentally, a process that includes photoresist and plating is one embodiment for forming the second redistribution layer 143 As described above, this description is intended to be explanatory and not limiting. Rather, any suitable method for producing the second redistribution layer can be used. 143 can be used. For example, the second redistribution layer can be used. 143They can also be produced using a top layer deposition process followed by a subsequent photolithographic structuring and etching process. It is entirely intended that this process, and any other suitable process, is included in the scope of the embodiments.

[0040] After the second redistribution layer 143 Once formed, the first passivation layer can be applied. 145 above the second redistribution layer 143 can be formed. In one embodiment, the first passivation layer can be polybenzoxazole (PBO), although any suitable material such as polyimide or a polyimide derivative, for example a low-temperature cured polyimide, can be used. The first passivation layer 145It can be arranged, for example, using a centrifugal coating process, to have a thickness between about 5 µm and about 20 µm, such as about 15 µm, although any suitable method and any suitable thickness can be used.

[0041] After the first passivation layer 145 Once formed, the first passivation layer can be applied. 145 to be structured to include sections of the second redistribution layer 143 to expose, and can second external ports 147 formed or otherwise in an electrical connection with the second redistribution layer 143 In one embodiment, the first passivation layer can be brought 145 For example, they can be structured using a photolithographic masking and etching process. However, any suitable method can be used.

[0042] The second external ports 147can pass through the first passivation layer 145 through which they are formed or arranged and can be a ball grid array (BGA) comprising a eutectic material such as solder, although any suitable material can be used. In one embodiment, where the second external connections 147 Solder metal balls are available for the second external connections 147 They can be formed by a ball-drop process, such as a direct ball-drop process. In another embodiment, the solder balls can be formed by initially forming a layer of tin by any suitable method, such as vapor deposition, electroplating, printing, or solder transfer, and then performing a reflow to shape the material into the desired bump shape. After the second external connections 147Once the structures have been formed, an inspection can be carried out to ensure that the structure is suitable for further processing.

[0043] On the other side of the first antenna substrate 141 The first upper antenna layer will be 151 on the first antenna 141 formed in an electrical connection with the feed element. The first upper antenna layer. 151 is combined with the grounded element (in the second redistribution layer) 143 ) is used to act as the antenna. In particular, the first upper antenna layer is used. 151 after receiving signals from, e.g., the first semiconductor device 109 or the second semiconductor device 111 act as an excited and radiating element, causing an interaction between the first upper antenna layer 151 and the grounded element in the second redistribution layer 143An electric field is generated. During operation, the generated electric field is separated between the first upper antenna layer. 151 and the grounded element in the second redistribution layer 143 oscillate, causing a disturbance between the first upper antenna layer. 151 and the grounded element in the second redistribution layer 143 Standing waves are generated. The standing waves originate from the area between the first upper antenna layer. 151 and the grounded element in the second redistribution layer 143 escape, causing an electromagnetic wave to be transmitted.

[0044] In one embodiment, the first upper antenna layer 151 in a similar way to the second redistribution layer 143 formed. For example, the first upper antenna layer can 151The first upper antenna layer can be formed using a process such as plating on a seed layer or, alternatively, by depositing a cover layer followed by a structuring process. However, any manufacturing process can be used to create the first upper antenna layer. 151 to form.

[0045] In addition, the first upper antenna layer 151 based on the desired electric field that exists between the first upper antenna layer 151 and the grounded element in the second redistribution layer 143 The dimensions are determined to achieve the desired effect. For example, the first upper antenna layer can be dimensioned. 151It must be dimensioned such that the generated electric field oscillates with a fundamental mode of the desired radiation pattern. Furthermore, the dimensions will also depend on a number of desired parameters, such as the desired operating frequency and the type of antenna. In a particular embodiment where the antenna is a patch antenna, the first upper antenna layer can 151 It can be manufactured so that it has a length that is half the wavelength of the signal whose transmission is desired. Similarly, in this embodiment, the width of the first upper antenna layer can be adjusted. 151 It can be manufactured to have a width that provides a desired input impedance. However, any suitable parameters can be used.

[0046] In a particular embodiment, where the signal to be transmitted and / or received has a wavelength of approximately 10.6 mm, the first upper antenna layer can 151 a first length L1 between approximately 2.6 mm and approximately 5.3 mm, such as 5 mm. Furthermore, the first upper antenna layer can 151 so formed that they have an initial width W1 (in Fig. (1C not shown separately, as it extends into and out of the figure) have dimensions between approximately 2.6 mm and approximately 5.3 mm, such as approximately 5 mm. However, any suitable dimensions may be used.

[0047] After the first upper antenna layer 151 Once formed, the second passivation layer can be applied. 153 They are formed to help protect the underlying structures. In one embodiment, the second passivation layer can be 153 the first passivation layer 143It could be similar in that it is, for example, a dielectric material that is distributed using a centrifugal process. However, any suitable process can be used.

[0048] Furthermore, the second passivation layer can 153 after the formation of the second passivation layer 153 be structured to form the first upper antenna layer 151 to expose for operation. In one embodiment, the second passivation layer can 153 For example, they can be structured using a photolithographic masking and etching process. However, any suitable method can be used.

[0049] The second antenna setup 139 can be used for the first antenna setup 137 They can be similar. For example, the second antenna setup can be... 139 likewise a second antenna substrate 161 (the first antenna substrate) 141similarly), a third redistribution layer 163 (the second redistribution layer 143 similarly, and also with a grounded element), a third passivation layer 165 (the first passivation layer) 145 similar), third external ports 167 (the second external ports 147 similar), a second feed element 169 (the feed-in element 149 similar), a second upper antenna layer 177 (the first upper antenna layer) 151 similarly), and a fourth passivation layer 175 (the second passivation layer) 153 similar). However, any suitable setup can be used.

[0050] Fig. Figure 1D illustrates the assembly of the first antenna. 137 and the second antenna setup 139 into an electrical connection with the first redistribution layers 105In one embodiment, the second external connections 147 (at the first antenna setup) 137 ) and the third external ports 167 (at the second antenna setup) 139 ) e.g. using a recording and arrangement process into physical contact with the first redistribution layers 105 Once they are in physical contact, a reflow process can be used to build up the initial antenna structure. 137 and the second antenna setup 139 to the first redistribution layers 105 to bond.

[0051] Furthermore, the initial antenna setup can 137 and the second antenna setup 139 arranged so that there is an opening in between for the second semiconductor device 111 will be left as is. While, in particular, the first antenna setup was based on the first semiconductor device. 109can extend, the second semiconductor device can 111 into the opening between the first antenna structure 137 and the second antenna setup 139 extend. Thus, the first antenna setup can be completed. 137 in one embodiment by a first distance D1 between approximately 4 mm and approximately 10 mm, such as approximately 8 mm, from the second antenna assembly 139 They must be spaced apart. However, any dimensions can be used.

[0052] In another embodiment, the first antenna structure 137 and the second antenna setup 139 as a single structure. In this embodiment, the opening can be formed by the structure in such a way that the single structure surrounds the opening. In this embodiment, the opening can be the first distance D1 exhibit any suitable dimensions for the openings that allow the mounting of the second semiconductor device111 enable them to be used.

[0053] After the initial antenna setup 137 and the second antenna setup 139 to the first redistribution layers 105 Once connected, the first antenna setup can begin. 137 , the second antenna setup 139 , the first semiconductor device 109 and the second semiconductor device 111 in an encapsulation material 127 to be encapsulated. In one embodiment, the encapsulation material can be a molding compound and arranged using a molding device. For example, the support substrate can be 101 The encapsulation material is arranged in a cavity of the mold and can be hermetically sealed. 127The encapsulation material can either be placed in the cavity before it is hermetically sealed, or alternatively, injected into the cavity through an injection port. In one embodiment, the encapsulation material can be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat-resistant crystalline resin, combinations thereof, or the like.

[0054] After the encapsulation material 127 was arranged in the cavity in such a way that the encapsulation material 127 the areas between the first antenna setup 137 , the second antenna setup 139 , the first semiconductor device 109 and the second semiconductor device 111 surrounding, the encapsulation material 127 must be hardened to harden the encapsulation material 127to cure for optimal protection. Although the exact curing process depends at least in part on the specific material used as the encapsulation material. 127 The choice depends on the hardening process used in an embodiment where a molding compound serves as the encapsulation material. 127 was chosen through a process such as heating the encapsulation material. 127 at temperatures between approximately 100 °C and approximately 130 °C, such as 125 °C, for approximately 60 s to approximately 3000 s, such as 600 s. Furthermore, [further details omitted] can occur in the encapsulation material. 127 It may contain initiators and / or catalysts to better control the hardening process.

[0055] However, as any expert will recognize, the curing process described above is merely an example and is not intended to limit the present embodiments. Other curing processes can be used, such as irradiation with UV radiation or even allowing the encapsulation material to harden naturally. 127 at room temperature. Any suitable curing process can be used, and it is quite intended that all such processes are included in the scope of the embodiments discussed here.

[0056] Fig. 1D also illustrates the detachment of the carrier substrate. 101 and an arrangement of fourth external ports 157 In one embodiment, the carrier substrate can be 101 e.g. using a thermal process to improve the adhesion of the adhesive layer 103 to change the structure that formed the first semiconductor device109 The adhesive layer is removed. In a specific embodiment, an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser is used to remove the adhesive layer. 103 to irradiate and heat until the adhesive layer 103 at least some of its adhesive properties are lost. After the procedure, the carrier substrate can 101 and the adhesive layer 103 physically separated and removed from the structure.

[0057] The fourth external ports 157 can be in an electrical connection with the first redistribution layers 105 They can be formed or arranged and may be a ball grid array (BGA) comprising a eutectic material such as solder, although any suitable material may be used. In one embodiment, the fourth external connections 157Solder metal balls are available for the fourth external connections 157 They can be formed by a ball-drop process, such as a direct ball-drop process. In another embodiment, the solder balls can be formed by initially forming a layer of tin by any suitable method, such as vapor deposition, electroplating, printing, or solder transfer, and then performing a reflow to shape the material into the desired bump shape. After the fourth external connections 157 Once the structures have been formed, an inspection can be carried out to ensure that the structure is suitable for further processing.

[0058] After the fourth external ports 157Once formed or arranged, the assembly can be separated into a discrete package. In one embodiment, the assembly can be separated using one or more saw blades that cut the assembly into discrete pieces. However, any suitable separation method can also be used, including laser ablation or one or more wet etching processes.

[0059] By constructing the setup as described, the first antenna setup can be achieved. 137 and the second antenna setup 139 It can be integrated into a smaller structure at a lower cost. For example, the entire structure can be integrated by incorporating the first antenna assembly. 137 and the second antenna setup 139 together with the first semiconductor device 109 and the second semiconductor device 111It can be designed to have smaller dimensions. In a particular embodiment, the entire structure can have a second length. L , between approximately 5 mm and approximately 20 mm, such as approximately 13 mm, and it can have a second width W2 (not shown separately, as it extends into and out of the figure) between approximately 5 mm and approximately 20 mm, such as approximately 13 mm. Furthermore, the overall height of the package can be reduced by approximately 20% compared to the use of flip chips, and it can have an initial height H1 (excluding the fourth external port) 157 ) between approximately 350 µm and approximately 1.2 mm, such as approximately 1.1 mm. However, any suitable dimensions can be used.

[0060] Furthermore, the second semiconductor device remains 111 In this embodiment, it is exposed and separate from the first antenna structure. 137 and the second antenna setup 139uncovered. Since it remains uncovered, the heat generated by the second semiconductor device 111 The heat generated takes a direct path outside the structure and is not obstructed by other materials. This allows the heat to dissipate more easily, resulting in better operation.

[0061] Fig. Figure 1E illustrates another embodiment in which the first antenna assembly 137 and the second antenna setup 139 not only in the areas affected by the first redistribution layers 105 are facing away, include antennas (as above with reference to Fig. 1A to Fig. (as described in 1D), but also a third antenna 171 , which run along the outer side walls of the first antenna structure 137 is formed, and a fourth antenna 173 , which run along the outer side walls of the second antenna structure 139The system is formed by using multiple antennas in different orientations. A dipole can be used to improve the transmit / receive capabilities of the entire device.

[0062] In one embodiment, the third antenna can 171 and the fourth antenna 173 each an upper antenna layer (which is separated by the second redistribution layer) 143 is connected to a corresponding feed line), which is part of the first antenna layer 151 and the second antenna layer 171 similar to an earthing plane (which is formed by the second redistribution layer) 143 to the earth). Each of the upper antenna layers and each of its corresponding grounding levels can be connected using processes related to the above in connection with the feed element. 149 are similar to those described, in the first antenna substrate 141can be formed. For example, in the first antenna substrate 141 Openings are created, these openings can be filled with a conductive material, and then planarization processes can be used to integrate the conductive material into the first antenna substrate. 171 to embed. However, any suitable method can be used.

[0063] In another embodiment, the third antenna can 171 and the fourth antenna 173 simultaneously with the conductive paths or trails that lead into the first antenna substrate 141 They can be built in or formed. For example, when several layers of conductive tracks and dielectric materials are formed, parts of the third antenna can be created. 171 and the fourth antenna 173 with the conductive traces. However, any suitable method for constructing the third antenna can be used. 171and the fourth antenna 173 can be used.

[0064] By forming the third antenna as described 171 and the fourth antenna 173 Anyone can learn from the first antenna setup 137 and the second antenna setup 139 This includes multiple antennas with multiple positions and orientations. For example, the third antenna could... 171 have an upper antenna layer that is at a right angle to the first upper antenna layer 151 is aligned. By using multiple antennas and multiple orientations, the transmission and reception of signals can be improved.

[0065] Fig. Figure 1F illustrates yet another embodiment that uses multiple antennas with multiple orientations. In this embodiment, the third antenna is 171 and the fourth antenna 173 however, instead of (or in addition to) the formation of the third antenna171 and the fourth antenna 173 in the first antenna setup 137 and the second antenna setup 139 in the first redistribution layers 105 formed. In this embodiment, the upper antenna layers and the grounding planes of the third antenna can be formed. 171 and the fourth antenna 173 at the same time and in the same way as each of the first redistribution layers 105 These can be formed, for example, by using a series of nucleation and plating processes, which are used to create successive layers of a conductive and a dielectric material, to form the upper antenna layers and the grounding planes. However, any suitable method for fabricating the upper antenna layers and grounding planes of the third antenna can be used. 171 and the fourth antenna 173 can be used.

[0066] Additionally, in this embodiment, the upper antenna layers of the third antenna can be 171 and the fourth antenna 173 through the first redistribution layers 105 with the first semiconductor device 109 and the second semiconductor device 111 can be connected without using the second external ports 147 and the third external ports 167 to have to run. Similarly, the grounding planes of the third antenna can 171 and the fourth antenna 173 also through the first redistribution layers 105 to be connected to the earth without going through the second external connections 147 and the third external ports 167 These connections help to reduce signal paths and enable more efficient signal transmission.

[0067] Fig. 1G illustrates another embodiment in which the conductive columns 155 used to help create the first redistribution layers 105 to the first antenna setup 137 and the second antenna setup 139 to connect. In one embodiment, the conductive columns can be connected. 155 before the arrangement of the first antenna setup 137 and the second antenna setup 139 are formed and are initiated by establishing a nucleation layer in electrical contact with the first redistribution layers. 105 is formed. Then a photoresist can be positioned and structured over the nucleation layer, where the conductive columns are located. 155To form the nucleus, a plating process is used to plate and deposit a conductive material, such as copper, onto the exposed portions of the nucleus layer. After formation, the photoresist can be removed, and the exposed portions of the nucleus layer (e.g., the portions not covered by the conductive material) are removed using an etching process.

[0068] Furthermore, during the process of forming the guiding pillars 155 also the third antenna 171 and the fourth antenna 173 are formed in such a way that they are located between the first redistribution layers 105 and the first antenna setup 137 and the second antenna setup 139In particular, the photoresist can also be structured during the structuring of the photoresist to form openings for the plating process, in order to create openings with the desired shape and dimensions for the arrangement of the third antenna. 171 and the fourth antenna 173 to form. After the openings have been formed, the material of the third antenna can be added. 171 and the fourth antenna 173 together with the conductive material of the conductive columns 155 If the photoresist is plated onto the nucleus layer, it can be removed, and the nucleus layer can be etched. However, any suitable method for forming the third antenna can be used. 171 and the fourth antenna 173 can be used. In some embodiments, the third antenna can be used. 171 and the fourth antenna 173 of the first antenna setup 137 and the second antenna setup 139through the third antenna 171 and the fourth antenna 173 , which are located between the first redistribution layers 105 and the first antenna setup 137 and the second antenna setup 139 are located, with the first redistribution layers 105 They can be connected to form an antenna with a larger side wall (not shown in the figure).

[0069] By using the embodiments described here, the limitations on the fan-out ratio for antenna setups can be eliminated while maintaining good package distortion characteristics.

[0070] Fig. 2A to Fig. 2D illustrates another embodiment, in which the first antenna structure 137 is used together with thermal vias, which are formed by the first antenna structure. 137extend to provide additional heat transfer capabilities and may or may not be electrically isolated from the rest of the structure. If initially Fig. 2A is considered as above with reference to Fig. 1B already describes the first redistribution layers 105 bonded first semiconductor device 109 However, as illustrated, in one embodiment only a single first semiconductor device is used. 109 (where all desired functionalities are contained in the single first semiconductor device) 109 are designed) are used, while in other embodiments two semiconductor devices (e.g. as in Fig. 1B shows the first semiconductor device 109 and the second semiconductor device 111) or more semiconductor devices can be used. Any suitable number of semiconductor devices can be used to achieve any desired functionality.

[0071] Fig. Figure 2B illustrates the construction of the first antenna structure. 137 together with the thermal vias 201 , which are formed by the first antenna substrate 141 The process can proceed. In one embodiment, the first antenna substrate 141 , the second redistribution layer 143 , the first passivation layer 145 above the second redistribution layer 143 , the second external connections 147 , the feed-in element 149 , the first upper antenna layer 151 , and the second passivation layer 153 as above with reference to Fig. 1C can be described. However, any suitable method can be used.

[0072] Furthermore, in this embodiment, during the formation of the feed-in element, 149 including the thermal contacts 201 can be formed. In particular, thermal vias can be used. 201 simultaneously with the feed-in elements 149 and are formed using the same processes as these, such as forming an opening, filling the opening with a conductive material, and then planarizing the conductive material to create the thermal vias. 201 to form. However, any suitable method for producing the thermal vias can be used. 201 can be used.

[0073] In one embodiment, the thermal vias are 201 dimensioned to help reduce heat buildup due to the heat generated by the first semiconductor device 109 The generated heat is dissipated. This allows the thermal vias to be used for heat dissipation. 201They should be dimensioned to have a first diameter Di between approximately 50 µm and approximately 300 µm, such as approximately 150 µm. However, any suitable diameter can be used.

[0074] Furthermore, in this embodiment, initial heat caps can be used. 203 and second heat caps 205 in a thermal and a physical connection with the thermal vias 201 , which are formed by the first antenna substrate 141 They can be formed. In one embodiment, the first heat caps can be 203 simultaneously with the second redistribution layer 143 and are formed using similar processes as in this one. For example, a nucleation layer can be formed and covered to create a structure, and then a plating process can be used to create both the second redistribution layer. 147 as well as the first thermal caps 203to form. However, any suitable process can be used to create the first heat caps. 203 to form.

[0075] The second heat caps can also be used. 205 simultaneously with the first upper antenna layer 151 and are formed using similar processes to this one. For example, a nucleation layer can be formed and covered to create a structure, and then a plating process can be used to create both the first upper antenna layer. 151 as well as the second heat caps 205 to form. However, any suitable process can be used to form the second heat caps. 205 to form.

[0076] The first thermal caps 203 and the second heat caps 205 can be formed in such a way that they have larger dimensions than the thermal vias 201They feature design elements to improve heat collection and dissipation. Thus, the first heat caps can be used. 203 and the second heat caps 205 in one embodiment they are formed in such a way that they have a second diameter D2 They have diameters between approximately 100 µm and approximately 350 µm, such as 200 µm. However, any suitable diameter can be used.

[0077] After the thermal vias 201 , the first heat caps 203 and the second heat caps 205 The first passivation layer can be formed. 145 over both the second redistribution layer 143 as well as the first thermal caps 203 can be arranged. In addition, the first passivation layer can be 145 to be structured in order to include parts of the second redistribution layer 143 for connection to the second external ports 147 to expose, and the second external ports147 are arranged. In some embodiments, the first passivation layer 147 leave it so that they are the first heat caps 203 covered, while the first passivation layer 147 in other embodiments it can be structured to include some or all of the first heat caps 203 to uncover.

[0078] Furthermore, the second passivation layer can 153 so that they form the first upper antenna layer 151 as well as the second heat caps 205 covers. In one embodiment, the second passivation layer can 153 then be structured to form the first upper antenna layer 151 to expose while the second heat caps 205 The second passivation layer can remain covered. In other embodiments, the second passivation layer can be removed. 153 be structured to accommodate some or all of the second heat caps 205 to uncover.

[0079] Fig. Figure 2C illustrates that the first antenna setup 137 after completing the first antenna setup 137 with the thermal through-holes 201 to the first redistribution layers 105 can be bonded. In one embodiment, the first antenna assembly can be 137 as above with reference to Fig. 1D described bonding and encapsulation. For example, the first antenna structure can be 137 can be positioned, and then a reflow process can be used to build up the initial antenna structure. 137 to the first redistribution layers 105 to bond. However, any suitable process can be used.

[0080] Furthermore, the first semiconductor device 109 after bonding the first antenna assembly 137 are encapsulated by the encapsulation material. In one embodiment, the first semiconductor device can be 109as above with reference to Fig. 1D described, encapsulated. For example, the carrier substrate can be 101 are arranged in a molding chamber and the encapsulation material 127 They can be applied and hardened. However, any suitable process can be used.

[0081] Fig. 2C further illustrates that the carrier substrate 101 can be removed after the encapsulation material has been arranged and hardened, and the fourth external connections 157 can be arranged. In one embodiment, the removal of the support substrate is possible. 101 and the arrangement of the fourth external ports 157 as above with reference to Fig. This can be done as described in 1D. However, any suitable process can be used.

[0082] After the encapsulation material 127Once the assembly has been arranged and hardened, it can be separated into a discrete package. In one embodiment, the assembly can be separated using one or more saw blades that cut the assembly into discrete pieces. However, any suitable separation method can also be used, including laser ablation or one or more wet etching processes.

[0083] By forming thermal vias 201 can the operation of the first semiconductor device 109 and thus the entire device is improved. In particular, it is improved by providing a heat path for dissipating the heat generated by the first semiconductor device. 109 This results in less heat build-up in the package, which supports performance and also helps to prevent temperature-related failure.

[0084] Fig. Figure 2D illustrates another embodiment in which the second semiconductor device 111 together with the first semiconductor device 109 is used. However, in this embodiment, the first antenna structure can 137 about both the first semiconductor device 109 as well as the second semiconductor device 111 extend, instead of the second semiconductor device 111 through the first antenna construction 137 (and / or the second antenna setup) 139 ) extends to radiate its own heat. To help transfer heat away from the second semiconductor device. 111 to dissipate heat, the thermal vias can 201 (along with the first heat caps) 203 and the second heat caps 205 ) are thus formed and arranged in such a way that the thermal vias 201 above the second semiconductor device 111to help in the process of the second semiconductor device 111 to dissipate the generated heat.

[0085] Fig. 2E illustrates another embodiment in which heat columns 207 together with the thermal vias 201 , the first heat caps 203 and the second heat caps 205 can be used to help remove an even greater amount of heat from the second semiconductor device 111 to dissipate. In one embodiment, the heat columns can 207 It could be a thermally conductive material such as a metal like copper. However, any suitable material can be used.

[0086] In one embodiment, the heat columns can 207 after the formation of the first passivation layer 145 above the second redistribution layer 143 can be formed. In this embodiment, the first passivation layer can be formed. 145e.g. using a photolithographic masking and etching process in the desired shape of the heat columns 207 be structured to protect the underlying first heat caps 203 to expose. After the first passivation layer 145 Once structured, a patting process can be used to create openings in the first passivation layer. 145 and to fill the photoresist to the heat columns 207 to form, after which the photoresist can be removed using a process such as ashing.

[0087] In one embodiment, the heat columns 207 dimensioned to dissipate heat from the second semiconductor device 111 dissipate heat. In some designs, the heat columns 207 arranged so that they direct heat away from the second semiconductor device 111conduct away by either coming into physical contact with the second semiconductor device 111 or in a thermal connection with the second semiconductor device 111 In one embodiment, the heat columns can be positioned. 207 a third diameter D3 between approximately 50 µm and approximately 300 µm, such as approximately 150 µm. Furthermore, the heat columns can 207 so formed that they extend to a second height H2 between approximately 10 µm and approximately 60 µm, such as approximately 15 µm, from the first passivation layer 145 extend away. However, any suitable dimensions can be used.

[0088] After the heat columns 207 Once the first antenna assembly has been formed, the rest of the initial antenna setup can be completed. 137 to be completed and the first antenna installation can begin. 137 as above with reference to Fig. 1D described at the first redistribution layers 105can be bonded. In addition, the encapsulation material can be 127 between the first semiconductor device 109 , the second semiconductor device 111 and the first antenna setup 137 are arranged in such a way that the encapsulation material makes physical contact with the heat columns. 207 manufactures.

[0089] Fig. Figure 2F illustrates yet another embodiment, which includes the heat columns. 207 used, but in the first semiconductor device 109 without the second semiconductor device 111 is used. For example, the first semiconductor device 109 a combination device in which the functionalities of the second semiconductor device 111 into the first semiconductor device 111 They are incorporated to form a combination device. In this embodiment, the heat columns are 207formed and then arranged so that they are positioned above the first semiconductor device 109 are located. Thus, the heat columns can be used to dissipate heat emanating from the first semiconductor device. 109 to subtract what is generated.

[0090] Fig. 3A to Fig. 3F illustrates another embodiment in which vias 301 before the formation of the first redistribution layers 105 in an integrated fan-out (INFO) package. In this embodiment, instead of forming the first redistribution layers, 15 on the adhesive layer 103 above the carrier substrate 101 a polymer layer 303 and a first germ layer 305 above the adhesive layer 103formed. In one embodiment, the polymer layer can be polybenzoxazole (PBO), although any suitable material such as polyimide or a polyimide derivative can be used. A solder resistance (SR) or an Ajinomoto build-up film (ABF) can be used. The polymer layer 303 It can be arranged, for example, using a centrifugal coating process at a thickness between about 2 µm and about 15 µm, such as about 5 µm, although any other method and any other thickness can be used.

[0091] The first germ layer 305 is applied over the polymer layer 303 formed. In one embodiment, the first germ layer 305 A thin layer of conductive material that aids in the formation of a thicker layer during subsequent processing steps. The first nucleation layer 305This could be a layer of titanium approximately 1,000 Å thick, followed by a layer of copper approximately 5,000 Å thick. The first nucleation layer 305 Depending on the desired materials, it can be produced using processes such as sputtering, evaporation, or PECVD processes. The first nucleation layer 305 can be formed in such a way that it has a thickness between about 0.3 µm and about 1 µm, such as about 0.5 µm.

[0092] After the first germ layer 305 Once formed, it can be found above the first germinal layer 305 A photoresist can be arranged and structured. In one embodiment, the photoresist can be applied to the first nucleation layer, for example, using a spin-coating technique, with a height between approximately 50 µm and approximately 250 µm, such as approximately 120 µm. 305The photoresist is arranged in a specific position. Once in place, it can be structured by exposing it to a structured energy source (e.g., a structured light source) to induce a chemical reaction, causing a physical change in those sections of the photoresist exposed to the energy source. A developer is then applied to the exposed photoresist to exploit these physical changes, selectively removing either the exposed or unexposed portion of the photoresist, depending on the desired structure.

[0093] In one embodiment, the structure formed in the photoresist is a structure for through-holes. 301 The vias 301are arranged in such a way that they are located on opposite sides of subsequently attached devices such as the first semiconductor device 109 and the second semiconductor device 111 (if present). However, any suitable arrangement for the via structure is acceptable. 301 can be used, such as arranging them so that the first semiconductor device 109 and the second semiconductor device 111 on opposite sides of the vias 301 be ordered.

[0094] In one embodiment, the vias are 301 formed in the photoresist. In one embodiment, the vias comprise 301one or more conductive materials such as copper, tungsten, other conductive materials, or the like, and they can be formed, for example, by electroplating, electroless plating, or the like. In one embodiment, an electroplating process is used, wherein the first nucleation layer 305 and the photoresist is immersed or submerged in an electroplating solution. The surface of the first nucleation layer 305 It is electrically connected to the negative side of an external DC power supply so that the first germ layer 305 In the electroplating process, the anode acts as the cathode. A solid, conductive anode, such as a copper anode, is also immersed in the solution and attached to the positive side of the power supply. The atoms from the anode dissolve into the solution, from which the cathode, e.g., the first nucleation layer, is formed. 305, the dissolved atoms obtained, thereby exposing the conductive regions of the first germ layer 305 to be plated in the opening of the photoresist.

[0095] After the vias 301 using the photoresist and the first germ layer 305 Once formed, the photoresist can be removed using any suitable removal process. In one embodiment, a plasma ashing process can be used to remove the photoresist, whereby the temperature of the photoresist can be increased until it undergoes thermal decomposition and can be removed. However, any suitable process, such as wet stripping, can be used. Removal of the photoresist can affect the underlying sections of the first nucleation layer. 305 uncover.

[0096] Once exposed, the exposed sections of the first germinal layer can be removed. 305 This can be carried out. In one embodiment, the exposed sections of the first germ layer can be 305 (e.g., those sections that are not connected vias) 301 (are covered) can be removed, for example, by a wet or dry etching process. For example, in a dry etching process, reagents can be removed using the vias. 301 as masks to the first germ layer 305 can be directed. In another embodiment, etching agents can be applied to the first germ layer. 305 sprayed or otherwise brought into contact with it to expose the exposed sections of the first germ layer 305 to eliminate. After the exposed part of the first germ layer 305 What was etched away is part of the polymer layer 303 between the vias 301exposed.

[0097] Fig. 3A also illustrates an arrangement of the first semiconductor device 109 on the polymer layer 303 In one embodiment, the first semiconductor device 109 e.g. using a pickup and arrangement process on the polymer layer 303 can be arranged, for example by a die-attach film on the polymer layer 303 can be held. However, any other method for arranging the first semiconductor device can also be used. 109 can be used. In some embodiments, the rear redistribution layer is placed on the polymer layer. 303 (not shown) formed and can then form the grounding plane or grounding line for the first antenna setup 137 The rear redistribution layer can then be penetrated by the first germination layer. 305 and the vias 301to the first redistribution layer 105 to be connected, and the first redistribution layer 105 can be used to help with the initial antenna setup 137 to provide an electrical ground.

[0098] Fig. 3B illustrates an encapsulation of the vias 301 and the first semiconductor device 109 The encapsulation can be carried out in a molding device that may comprise an upper mold section and a lower mold section that can be separated from the upper mold section. When the upper mold section is lowered so that it rests against the lower mold section, a mold cavity for the support substrate can be formed. 101 , the vias 301 and the first semiconductor device 109 be formed.

[0099] During the encapsulation process, the upper mold section can be positioned adjacent to the lower mold section, thereby encapsulating the carrier substrate. 101 , the vias 301 and the first semiconductor device 109 They are enclosed within the mold cavity. Once enclosed, the upper and lower mold sections can form an airtight seal to control the inflow and outflow of gases from the mold cavity. After sealing, an encapsulation material can be applied. 309 are arranged in the mold cavity. Regarding the encapsulation material... 309 It could be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat-resistant crystalline resin, combinations thereof, or the like. The encapsulation material 309It can be placed in the mold cavity before aligning the upper and lower mold sections, or otherwise injected into the mold cavity through an injection opening.

[0100] After the encapsulation material 309 was arranged in the mold cavity in such a way that the encapsulation material 309 the carrier substrate 101 , the vias 301 and the first semiconductor device 109 encapsulated, the encapsulation material can 309 must be hardened to harden the encapsulation material 309 to cure for optimal protection. Although the exact curing process depends at least in part on the specific material used for the encapsulation material. 309 The choice depends on the hardening in an embodiment where a molding compound is used as an encapsulation material. 309 was chosen through a process such as heating the encapsulation material.309 at temperatures between approximately 100 °C and approximately 130 °C, such as 125 °C, for approximately 60 s to approximately 3000 s, such as 600 s. Furthermore, the encapsulation material can be used for... 309 It may contain initiators and / or catalysts to better control the hardening process.

[0101] However, as any expert will recognize, the curing process described above is merely an example and is not intended to limit the present embodiments. Other curing processes can be used, such as irradiation with UV radiation or even allowing the encapsulation material to harden naturally. 309 at room temperature. Any suitable curing process can be used, and it is entirely intended that all such processes are included in the scope of the embodiments discussed here.

[0102] Fig. Figure 3B also illustrates a dilution of the encapsulation material. 309 , to the vias 301 and the first semiconductor device 109 to expose the encapsulation material. Thinning can be achieved, for example, by using a mechanical grinding or a chemical-mechanical polishing (CMP) process, employing chemical etchants and abrasives that are compatible with the encapsulation material. 309 and the first semiconductor device 109 react and grind them away until the vias 301 and the first external connections (e.g. copper columns surrounded by a dielectric layer) to the first semiconductor device 109 were exposed. Thus, the first semiconductor device can be identified. 109 and the vias 301 have a flat surface that is also coplanar with the encapsulating agent.

[0103] However, although the CMP process described above is shown as an illustrative example, it is not intended to be a limitation for the embodiments. Any other suitable disposal process can be used to remove the encapsulation material. 309 and the first semiconductor device 109 to thin the material and expose the vias. This process, and any other suitable process, can be used to thin the encapsulation material. 309 and the first semiconductor device 109 to dilute, and it is entirely intended that all these processes are included in the scope of the embodiments.

[0104] After the encapsulation material 309 was diluted and the vias 301 Once exposed, the first redistribution layers can be identified. 105 via and in an electrical connection with the vias 301and the first semiconductor device 109 can be formed. In one embodiment, the first redistribution layers can be formed. 105 as above with reference to Fig. 1A can be described. For example, a seed layer can be formed and covered to provide a structure, and then a plating process can be used to form the conductive sections of each layer from a conductive material, which layer is then covered by an overlying dielectric layer. However, any suitable process can be used to form the first redistribution layers. 105 can be used.

[0105] Furthermore, after the formation of the first redistribution layers 105 fourth external ports 157 in contact with the first redistribution layers or formed in such a way as to be possible. In one embodiment, the fourth external connections can be arranged as above with reference to Fig. The 1D described form can be created. However, any suitable process and any suitable materials can be used to create the fourth external connection. 157 to form.

[0106] Fig. Figure 3C also illustrates the detachment of the carrier substrate. 101 and structuring the polymer layer 303 In one embodiment, the carrier substrate can be 101 using, for example, a thermal process to improve the adhesion of the adhesive layer 103 to change the structure that formed the first semiconductor device 109 The adhesive layer is removed. In a specific embodiment, an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser is used to remove the adhesive layer. 103 to irradiate and heat until the adhesive layer 103at least some of its adhesive properties are lost. After the procedure, the carrier substrate can 101 and the adhesive layer 103 physically separated and removed from the structure.

[0107] After the carrier substrate 101 Once removed, the polymer layer can 303 be structured to facilitate the through-hole connections 301 (together with the associated first germ layer) 305 ) to expose. In one embodiment, the polymer layer can be 303 For example, it can be structured using a laser drilling process. During the laser drilling process, the drilling energy can range from 0.1 mJ to approximately 30 mJ, and the drilling angle can be approximately 0 degrees (perpendicular to the polymer layer). 303 ) to approximately 85 degrees to the normal of the polymer layer 303 in one embodiment, the structure can be formed to accommodate the vias. 301To form openings with a width between approximately 100 µm and approximately 300 µm, such as approximately 200 µm.

[0108] In another embodiment, the polymer layer 303 They can be structured by initially applying a photoresist to the polymer layer. 303 A photoresist is applied and exposed to a structured energy source (e.g., a structured light source) to induce a chemical reaction, causing a physical change in those sections of the photoresist exposed to the structured energy source. A developer is then applied to the exposed photoresist to exploit these physical changes, depending on the desired structure, and to selectively remove either the exposed or unexposed portion of the photoresist, revealing the underlying exposed sections of the polymer layer. 303e.g., removed by a dry etching process. However, any other suitable method for structuring the polymer layer can be used. 303 can be used.

[0109] Fig. 3D illustrates that the first antenna setup 137 after exposing the vias 301 to the vias 301 can be bonded. In one embodiment, the first antenna assembly can be 137 by aligning the second external ports 147 with the vias 301 and arranging the second external ports 147 in physical contact with the through-holes 301 through the polymer layer 303 They are bonded. Once they are in physical contact, a reflow process can be used to build the initial antenna structure. 137 to the vias 301to bond. In some embodiments, the additional rear-side redistribution layer is applied to the polymer layer. 303 formed before the first antenna construction 137 (not shown) is arranged, and this rear redistribution layer can then be the grounding plane or grounding line for the first antenna assembly. 137 The rear redistribution layer can then be penetrated by the first germination layer. 305 and the vias 301 to the first redistribution layer 105 to be connected, and the first redistribution layer 105 can be used to help with the initial antenna setup 137 to provide an electrical ground.

[0110] Fig. 3D additionally illustrates the arrangement of a backer rod material. 307 between the first antenna setup 137 and the polymer layer 303 In one embodiment, the underfill material 307a protective material used to protect the antenna structure 137 to mitigate and bear the impact of operational and environmental damage, such as stresses caused by heat generation during operation. The underfill material 307 It can, for example, comprise a liquid epoxy or other protective material, which is then cured and solidified, and can be distributed, for example, by injection.

[0111] Fig. 3D also illustrates the singulation of the assembly into a discrete package. In one embodiment, the assembly can be singulated using one or more saw blades that separate the assembly into discrete pieces. However, any suitable singulation method can also be used, including laser ablation or one or more wet etching processes.

[0112] Fig. 3E illustrates another embodiment, which together with the vias 301 Several antenna configurations with multiple orientations are used. In this embodiment, however, instead of (or in addition to) the antenna used in the first antenna configuration, a different antenna configuration is used. 137 is formed, the third antenna 171 and the fourth antenna 173 in the first redistribution layers 105 formed. In one embodiment, the third antenna can be 171 and the fourth antenna 173 as above with reference to Fig. 1F can be described. For example, the third antenna can be formed. 171 and the fourth antenna 173 at the same time and in the same way as each of the first redistribution layers 105 They can be formed, for example, by using a series of nucleation layers and plating processes. However, any suitable method for producing the third antenna can be used.171 and the fourth antenna 173 can be used.

[0113] Fig. Figure 3F illustrates yet another embodiment, in which the third antenna 171 and the fourth antenna 173 not in the first antenna setup 137 or the first redistribution layers 105 are formed, but together with the vias 301 can be formed. In particular, the photoresist can also be structured during the structuring of the photoresist to form openings for the plating process, in order to create openings of the desired shape and dimensions for the arrangement of the third antenna. 171 and the fourth antenna 173 to form. After the openings have been formed, the material of the third antenna can be added. 171 and the fourth antenna 173 together with the conductive material of the vias 301If the photoresist is plated onto the nucleus layer, it can be removed, and the nucleus layer can be etched. However, any suitable method for forming the third antenna can be used. 171 and the fourth antenna 173 can be used.

[0114] Fig. 3G illustrates yet another embodiment, in which the third antenna 171 and the fourth antenna 173 in the first antenna setup 137 can be formed. In one embodiment, the third antenna can be 171 and the fourth antenna 173 as above with reference to Fig. 1E can be described. For example, the structures of the third antenna can be formed. 171 and the fourth antenna 173 simultaneously either with the feed-in element 149 or the one in the first antenna substrate 141The third antenna can be formed by the existing conductive pathways. However, any suitable manufacturing process can be used to create the third antenna. 171 and the fourth antenna 173 to form.

[0115] By using the embodiments described here, a multilayer antenna is produced that is located on both the top surface and the side walls of the entire structure, while still maintaining a smaller form factor in every direction (e.g., the X, Y, and Z directions). Such antennas can be formed directly on the solder ball traces (SBT) without additional metallization or lithographic processes, thereby reducing costs by approximately 30% and simplifying layouts for customers. Furthermore, by performing the first redistribution layers 105A smaller redistribution path may be present as the connection paths, leading to improved performance. Furthermore, by incorporating components such as inductors into the first redistribution layers, it is possible to achieve this. 105 An overall power saving of approximately 10% can be achieved, while still maintaining a reduction in silicon area of ​​approximately 10%.

[0116] In one embodiment, a semiconductor device comprises redistribution structures connected to external terminals; a first semiconductor device connected to the redistribution structures; an antenna substrate located on a side of the first semiconductor device opposite the redistribution structures; and electrical terminals separate from the first semiconductor device, wherein the first semiconductor device is electrically connected to the antenna substrate via the redistribution structures and the electrical terminals. In one embodiment, the semiconductor device further comprises an antenna assembly located within the redistribution structures. In another embodiment, the semiconductor device further comprises an antenna assembly located within the electrical terminals.In one embodiment, the semiconductor device further comprises several antenna assemblies located in the antenna substrate. In another embodiment, the semiconductor device further comprises a thermal via extending through the antenna substrate. In another embodiment, the electrical connections are substrate vias. In another embodiment, the first semiconductor device is a radio frequency chip.

[0117] In another embodiment, a method comprises forming a redistribution array over a carrier wafer; attaching a first semiconductor device to the redistribution array; electrically connecting an antenna substrate to the redistribution array, wherein the first semiconductor device is located between the antenna substrate and the redistribution array; and removing the carrier wafer. In one embodiment, the formation of the redistribution array simultaneously forms an antenna within the redistribution array. In one embodiment, the first semiconductor device is a radio frequency chip. In one embodiment, the electrical connection of the antenna substrate comprises electrically connecting a first antenna layer and a second antenna layer to the redistribution array, wherein the first antenna layer is oriented at a right angle to the second antenna layer.In one embodiment, the method further comprises encapsulating the first semiconductor device after electrically connecting the antenna substrate to the redistribution assembly. In another embodiment, attaching the antenna substrate further comprises forming electrical connections separate from the first semiconductor device; and bonding the antenna substrate to the electrical connections. In another embodiment, the formation of the electrical connections simultaneously forms an antenna.

[0118] In yet another embodiment, a method comprises forming substrate vias over a polymer layer; attaching a first semiconductor device to the polymer layer; encapsulating the substrate vias and the first semiconductor device with an encapsulation material; planarizing the encapsulation material until the first semiconductor device, the encapsulation material, and the substrate vias are flat; forming a redistribution stack over the encapsulation material, the interposer vias, and the first semiconductor device; structuring the polymer layer after forming the redistribution stack; and bonding an antenna substrate to the substrate vias through the polymer layer. In one embodiment, the formation of the redistribution stack simultaneously forms an antenna.In one embodiment, the formation of the substrate vias simultaneously with the interposer vias forms an antenna. In another embodiment, the first semiconductor device is a radio frequency chip. In another embodiment, the antenna substrate has multiple top antenna layers, each of which is oriented in a different direction. In yet another embodiment, the method further comprises the application of an underfill material between the antenna substrate and the polymer layer.

[0119] The above outlines features of several embodiments to help those skilled in the art better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and setups to achieve the same purposes and / or the same advantages as the embodiments presented herein. They should also recognize that such equivalent setups do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications therein without departing from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62674337

[0001]

Claims

[ ] IS RECLAMED: [1] Semiconductor device comprising: Redistribution setups connected to external ports; a first semiconductor device connected to the redistribution setups; an antenna substrate located on a side of the first semiconductor device opposite the redistribution structures; and electrical connections that are separate from the first semiconductor device, wherein the first semiconductor device is electrically connected to the antenna substrate via the redistribution structures and the electrical connections. [2] Semiconductor device according to claim 1, further comprising an antenna assembly located in the redistribution structures. [3] Semiconductor device according to claim 1 or 2, further comprising an antenna assembly located in the electrical terminals. [4] Semiconductor device according to one of the preceding claims, wherein the antenna assembly comprises multiple antenna assemblies. [5] Semiconductor device according to one of the preceding claims, further comprising a thermal via extending through the antenna substrate. [6] Semiconductor device according to one of the preceding claims, wherein the electrical connections are substrate vias. [7] Semiconductor device according to any of the preceding claims, wherein the first semiconductor device is a radio frequency chip. [8] Method for manufacturing a semiconductor device, wherein the method forming a redistribution setup over a carrier wafer; the attachment of a first semiconductor device to the redistribution setup; the electrical connection of an antenna substrate to the redistribution setup, wherein the first semiconductor device is located between the antenna substrate and the redistribution setup; and the removal of the carrier wafer includes. [9] Method according to claim 8, wherein forming the redistribution setup includes simultaneously forming an antenna in the redistribution setup. [10] Method according to claim 8 or 9, wherein the first semiconductor device is a radio frequency chip. [11] Method according to any one of the preceding claims 8 to 10, wherein the electrical connecting of the antenna substrate comprises the electrical connecting of a first antenna layer and a second antenna layer to the redistribution structure, wherein the first antenna layer is oriented at a right angle to the second antenna layer. [12] Method according to any one of the preceding claims 8 to 11, further comprising encapsulating the first semiconductor device after electrically connecting the antenna substrate to the redistribution setup. [13] Method according to any one of the preceding claims 8 to 12, wherein the application of the antenna substrate further the formation of electrical connections separate from the first semiconductor device; and This includes bonding the antenna substrate to the electrical connections. [14] Method according to claim 13, wherein the formation of the electrical connections simultaneously forms an antenna. [15] Method for manufacturing a semiconductor device, wherein the method the formation of substrate vias over a polymer layer; the attachment of a first semiconductor device to the polymer layer; the encapsulation of the substrate vias and the first semiconductor device with an encapsulation material; planarizing the encapsulation material until the first semiconductor device, the encapsulation material, and the substrate vias are flat against each other; forming a redistribution setup over the encapsulation material, the interposer vias and the first semiconductor device; the structuring of the polymer layer after the formation of the redistribution structure; and bonding an antenna substrate to the substrate vias through the polymer layer includes. [16] Method according to claim 15, wherein forming the redistribution setup includes simultaneously forming an antenna with the redistribution setup. [17] Method according to claim 15 or 16, wherein the formation of the substrate vias simultaneously with the interposer vias forms an antenna. [18] Method according to any one of the preceding claims 15 to 17, wherein the first semiconductor device is a radio frequency chip. [19] Method according to any one of the preceding claims 15 to 18, wherein the antenna substrate has several upper antenna layers, wherein one of the several upper antenna layers is oriented in a different direction than another of the several upper antenna layers. [20] Method according to any one of the preceding claims 15 to 19, further comprising the application of a backer material between the antenna substrate and the polymer layer.