Semiconductor housing with symmetrically arranged power connections and method for its manufacture
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- INFINEON TECHNOLOGIES AG
- Filing Date
- 2018-07-25
- Publication Date
- 2026-07-30
AI Technical Summary
Existing semiconductor housings face challenges in achieving sufficient cooling, low impedance, and minimizing leakage inductances, particularly in high-current electrical circuits such as those found in motor vehicle inverters, which affect performance.
A semiconductor package with a double-sided cooling structure featuring symmetrically arranged power terminals and a specific manufacturing method that includes a lower carrier substrate with conductive layers, insulating layers, and spacers, along with encapsulation to reduce parasitic inductances.
The solution significantly reduces parasitic inductances by up to 5nH, enhancing the performance of electrical circuits by minimizing undesired overshooting and switching losses, especially with SiC power semiconductor chips.
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
TECHNICAL AREA
[0001] The present disclosure relates to a semiconductor package with a double-sided cooling structure and symmetrically arranged power terminals. The present disclosure further relates to a manufacturing process for a semiconductor package with a double-sided cooling structure. BACKGROUND
[0002] The ever-increasing demands on the performance of electrical circuits for high currents, such as those found in electric vehicle drives, necessitate the further development and improvement of semiconductor packages used in such circuits. These circuits can, for example, include inverters that convert battery voltage into alternating current to power an electric motor. Such an inverter can be implemented in a semiconductor package using a suitable circuit. For optimal inverter performance, it is crucial to achieve sufficient cooling, the lowest possible impedance, minimal stray inductance, and other factors within the semiconductor package. Improved semiconductor packages and / or improved manufacturing processes can further enhance the performance of such inverters.
[0003] The problem addressed by the invention is solved by the features of the independent claims. Advantageous embodiments and further developments of the invention are specified in the dependent claims. SUMMARY
[0004] Specific examples include a semiconductor package with a double-sided cooling structure, the semiconductor package comprising an upper electrically conductive element having an externally exposed metal surface, a lower support substrate having an upper electrically conductive layer, a lower electrically conductive layer with an externally exposed surface, and an electrical insulating layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, at least one power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer.which is arranged between the upper electrically conductive element and the power semiconductor chip and has a first, second and third power terminal arranged along a first side of the semiconductor package, wherein the second power terminal is arranged between the first and the third power terminal and wherein the first and third power terminals are configured to apply a first supply voltage and wherein the second power terminal is configured to apply a second supply voltage.
[0005] Specific examples relate to a method for manufacturing a semiconductor package with a double-sided cooling structure, the method comprising providing a lower support substrate having an upper electrically conductive layer, a lower electrically conductive layer, and an electrical insulating layer arranged between the upper and lower electrically conductive layers, attaching a first electrically conductive spacer to the upper electrically conductive layer of the lower support substrate, attaching at least one power semiconductor chip to the upper electrically conductive layer of the lower support substrate, attaching a second electrically conductive spacer to the power semiconductor chip, attaching an upper electrically conductive element to the spacers opposite the lower support substrate, and arranging a first,second and third power terminals on the upper electrically conductive layer of the lower support substrate along a first side of the semiconductor package, wherein the second power terminal is arranged between the first and the third power terminals, and wherein the first and the third power terminals are configured to apply a first supply voltage, and wherein the second power terminal is configured to apply a second supply voltage. List of characters
[0006] The accompanying drawings are examples and, together with the description, serve to explain the basic features of the disclosure. The elements of the drawings are not necessarily to scale with each other. Identical reference symbols may denote corresponding, similar, or identical parts. Fig. 1 consists of the Fig. 1A and Fig. 1B and shows in Fig. 1A A side view of a semiconductor package with a double-sided cooling structure. Fig. Figure 1B shows a side view of another semiconductor package with a double-sided cooling structure. Fig. Figure 2 shows a perspective view of a semiconductor package with a double-sided cooling structure, which further includes an encapsulation body. Fig. 3 consists of the Fig. 3A to Fig. 3D and shows in Fig. Figure 3A shows a perspective view of a lower support substrate of another semiconductor package. Fig. Figure 3B shows the upper cooling structure of the semiconductor package in perspective view. Fig. 3C the composite semiconductor package in perspective view and in Fig. 3D side view of the semiconductor package. Fig. 4 consists of the Fig. 4A and Fig. 4B and shows in Fig. 4A a lower support substrate of another semiconductor package. In Fig. Figure 4B shows the composite semiconductor package in perspective view. Fig. Figure 5 shows a flowchart of a process for manufacturing a semiconductor package. Fig. 6 consists of the Fig. 6A to Fig. 6C and shows another example of a semiconductor package. Fig. Figure 7 shows an example of an equivalent circuit diagram that is used for the semiconductor packages of the Fig. 1-4 and Fig. 6 may apply. DETAILED DESCRIPTION
[0007] In the present description, the terms "coupled", "electrically coupled" and / or "electrically connected" do not imply that the elements must be directly coupled; intervening elements may be provided between the "coupled" or "electrically coupled" elements, e.g. solder layers.
[0008] Fig. 1A shows a semiconductor package 100with a double-sided cooling structure according to the disclosure. Here, "double-sided cooling structure" means that the semiconductor package 100 an upper electrically conductive element 110 and a lower support substrate 120 features, each of which acts as a cooling structure for the semiconductor package 100 can have an effect. The semiconductor package 100 furthermore features a first electrically conductive spacer 130 , at least one power semiconductor chip 140 and a second electrically conductive spacer 150 up. The second electrically conductive spacer 150 is between the upper electrically conductive element 110 and the power semiconductor chip 140 arranged.
[0009] The lower support substrate 120 has an upper electrically conductive layer 121 , a lower electrically conductive layer 123 and one between the upper121 and lower 123 conductive layer electrical insulating layer 122 on. The lower support substrate 120 It could be, for example, a substrate of the type DCB (direct copper bond), DAB (direct aluminium bond), or AMB (active metal brazing).
[0010] According to one example, the semiconductor package 100 furthermore, they have an encapsulation body (not shown) which contains the spacers. 130 , 150 , which includes at least one power semiconductor chip 140 , the upper electrically conductive element 110 and the lower support substrate 120 encapsulated. In particular, a gap can be created between the upper electrically conductive element. 110 and the lower support substrate 120 be completely or partially filled by the encapsulation body.
[0011] For example, the encapsulation body can contain or consist of a potting compound or molding compound. The encapsulation body can be manufactured, for example, by compression molding. To manufacture the encapsulation body, for example, the still unencapsulated semiconductor package can be used. 100 The material is placed in a molding tool, a dielectric mass can be injected, and the dielectric mass can be cured to form the encapsulation body.
[0012] However, a metal surface 111 of the upper electrically conductive element 110 and a surface 124 the lower electrically conductive layer 123 in any case designed to be completely or at least partially exposed to the outside (i.e., the surfaces 111 , 124 represent the outer surfaces of the semiconductor package 100 (dar).
[0013] The electrically conductive spacers 130 ,150 They can be made of a metal or a metal alloy and can, for example, contain or consist of aluminum or copper. The first electrically conductive spacer 130 is connected to the upper electrically conductive element 110 and the lower support substrate 120 physically and electrically connected, e.g. by solder joints or by electrically conductive adhesive.
[0014] According to one example, it includes at least one power semiconductor chip. 140 SiC or consists of it. According to one example, it is at least a power semiconductor chip. 140 an IGBT (insulated-gate bipolar transistor) chip. According to one example, the semiconductor package contains 100 a half-bridge circuit is implemented. The half-bridge circuit can have a power connection for a positive supply voltage ( V DD ), a power connection for a negative supply voltage ( V SS ) and have a power connection designed as a phase.
[0015] The second electrically conductive spacer 150 can be electrically connected to an electrode (not shown) of the power semiconductor chip 140 and with the upper electrically conductive element 110 The electrodes must be connected, for example, by solder joints or electrically conductive adhesive. The electrode can be a power electrode or a control electrode of the power semiconductor chip. 140 be. The second electrically conductive spacer 150 can the power semiconductor chip 140 completely or partially cover.
[0016] For example, the semiconductor package can have external connections in the form of terminal fingers. At least some of these external connections can be designed to connect electrodes of the at least one power semiconductor chip. 140to connect electrically to the outside world. The external connections can be made with the upper electrically conductive element. 110 and / or with the upper electrically conductive layer 121 They must be electrically connected. The connection fingers can be part of a conductor frame. Individual external connections can be power connections, for example, connected to the respective power electrodes of the at least one power semiconductor chip. 140 They can be electrically connected. One or more of the external connections can be control connections, which are connected to a control electrode (e.g., a gate electrode) of the at least one power semiconductor chip. 140 are electrically connected. Some of the external connections may be measuring connections, which are designed, for example, to V DD , V SS , the voltage of the phase, a current flow, or a temperature in the semiconductor package 100 to eat.
[0017] The semiconductor package 100It features three power connectors located side by side along a first side of the semiconductor package. 100 are arranged. The two outer power terminals are designed to apply a first supply voltage, and the middle terminal, located between the two outer power terminals, is designed to apply a second supply voltage. For example, the first supply voltage V DD and the second supply voltage V SS According to another example, the first supply voltage V SS and the second supply voltage V DD .
[0018] Furthermore, the semiconductor package 100 It can also be expanded to include additional power connections on the first side, e.g., another one. V DD - or V SS -connection or to V DD - / V SS -connection pairs, so that the symmetry is maintained.
[0019] According to one example, the semiconductor package 100 An additional power connection is located on the second side of the semiconductor package, opposite the first side, and is configured as a phase connection. The control and / or measurement connections of the semiconductor package 100 They can also be arranged along the second side, e.g. to the left and right of the phase connection.
[0020] The symmetrical arrangement of power terminals for the first and second supply voltages described above can help to ensure that the semiconductor package 100 exhibits reduced parasitic inductances. In particular, it can be said that each pair of V DD and V SS a "loop" is formed, whereby the parasitic inductances of the opposing supply voltages cancel each other out or at least reduce each other within the respective loop. The phase terminal is located on the side of the semiconductor package opposite the other power terminals. 100 can also be used to reduce the inductance in the semiconductor package 100 These measures can contribute to the process within the semiconductor package. 100 A considerable reduction in parasitic inductances can be achieved, e.g., by approximately 5 nH. Such a reduction in parasitic inductances can significantly improve the performance of the semiconductor package. 100 realized electrical circuit. This is particularly relevant in the case where the at least one power semiconductor chip is used. 140In materials like SiC, which allow for fast switching, the tolerance for parasitic inductances is very low. These can lead to undesirable overshoot during switching and increased switching losses.
[0021] Fig. Figure 1B shows a semiconductor package 100_1, which, apart from the differences described below, is similar to the semiconductor package 100 the Fig. 1A can match. Regarding the semiconductor package 100 1 The upper electrically conductive element 110 an upper carrier substrate 160 with an electrically conductive upper layer 161 , a lower electrically conductive layer 163 and an electrical insulating layer arranged between the upper 161 and lower 163 electrically conductive layer 162 on. The upper electrically conductive layer corresponds to this. 161the exposed metal surface 111 .
[0022] The semiconductor package 100_1 can also have external connections 170 exhibit which, as in Fig. 1B shown, between the upper support substrate 160 and the lower support substrate 120 are arranged. According to an example, each of the external connections can be 170 with the lower electrically conductive layer 163 of the upper support substrate 160 or with the upper electrically conductive layer 121 of the lower support substrate 120 be electrically connected.
[0023] The lower electrically conductive layer 163 of the upper support substrate 160 and the upper electrically conductive layer 121 of the lower support substrate 120 are structured and can be, for example, chip islands, conductor tracks and / or attachment points for the electrically conductive spacers 130 ,150 exhibit.
[0024] Fig. Figure 2 shows a perspective view of a semiconductor package. 200 , which is related to the semiconductor packages 100 and 100 1 can be identical. The semiconductor package 200 has an encapsulation body 210 on, which the spacers 130 , 150 , the upper electrically conductive element 110 , the lower support substrate 120 and at least one power semiconductor chip 140 encapsulated. The surfaces 111 and the surface 124 (in Fig. 2 not visible) are located on the encapsulation body 210 on opposite sides of the semiconductor package 200 free.
[0025] The encapsulation body 210 The encapsulation body consists of, or incorporates, a suitable electrically insulating material, e.g., a plastic, a polymer, or a resin.210 It could be, for example, a molded body.
[0026] The surface 111 and / or the surface 124 They may have an electrically insulating coating and each may be designed for the attachment of a heat sink.
[0027] The semiconductor package 200 features external connections 220 , 230 on which are located on the side surfaces of the semiconductor package 200 are arranged so that the opposite sides are flush with the metal surface 111 and the surface 124 connect the external connections 220 can be designed as power connections and the external connections 230 They can be designed as control connections or measuring connections. For example, all power connections... 220 except for one power connection designed as a phase 240 on one side of the semiconductor package 200arranged and the power connection designed as a phase 240 and the control and measuring connections 230 on one of the second sides opposite the first. A third and a fourth side of the semiconductor package. 200 can be free of any connections. The external connections 220 , 230 and 240 can be parts of a common ladder frame.
[0028] Fig. Figure 3A shows a perspective view of a lower support substrate. 120 a semiconductor package 300 The semiconductor package 300 can be used with semiconductor packages 100 , 100_1 and 200 should be identical.
[0029] The upper electrically conductive layer 121 its lower support substrate 120 of the semiconductor package 300 is structured and can provide initial support areas 310 and a second support area 320 exhibit the first support areas310 can the second support area 320 on at least two sides 302 and 304 or on three sides 301 , 302 and 304 partially or completely surrounded. The first support areas 310 can be electrically connected to each other, e.g. via the upper support substrate 160 The first support areas 310 can also be a single, contiguous area 310 be. Apart from the initial support areas. 310 and the second support area 320 can the upper electrically conductive layer 121 other structured areas, e.g. areas 330 , 340 , 350 , 360 , 370 and 380 exhibit.
[0030] On the first support areas 310 Can the first power semiconductor chips 311 be arranged. One each on the underside of the first power semiconductor chips. 311The arranged power electrode, e.g. a drain electrode, can be electrically connected to the first carrier areas. 310 be connected, e.g. via a solder layer. The first support areas 310 are used to apply the initial supply voltage, e.g. V DD , designed and the first power semiconductor chips 311 Can high-side power semiconductor chips be housed in a semiconductor package? 300 The implemented half-bridge circuit. The first carrier regions 310 can with a first power connection 312 and a third power connection 313 be electrically connected.
[0031] The first support areas 310 can also be equipped with a measuring connection 314 be electrically connected, which is used for measuring the parameters at the first carrier areas. 310 applied voltage, e.g. V DD , is designed.
[0032] On the second support area 320can second power semiconductor chips 321 be arranged. One each on the underside of the second power semiconductor chip. 321 The arranged power electrode, e.g. a drain electrode, can be electrically connected to the second carrier area. 320 be connected, e.g. via a solder layer. The second support area 320 can be designed as a phase of the half-bridge circuit and the second power semiconductor chips 321 These can be low-side power semiconductor chips of the half-bridge circuit. The second carrier region 320 can be connected to a fourth power outlet 322 be electrically connected.
[0033] The second support area 320 can also be equipped with a measuring connection 323 be electrically connected, which is used for a measurement of the second carrier area 320 designed for the applied voltage, e.g., the phase.
[0034] The area 330can be a central area and it can be completely separated from the second support area 320 be surrounded. The area 330 can be used with control electrodes, e.g. gate electrodes, of the second power semiconductor chip 321 be electrically connected, e.g. by means of bond wires. The area 330 can also be accessed via the upper support substrate 160 with the area 370 be electrically connected. In that area 370 can a second control connection 371 to apply a control signal to the second power semiconductor chips 321 be arranged.
[0035] The areas 340 can along the second side 302 and along the fourth page 304 be arranged, e.g., outside the first support areas 310 The areas 340 can be used with control electrodes, e.g. gate electrodes, of the first power semiconductor chips 311be electrically connected, e.g. by means of bond wires. The areas 340 can also be accessed via the upper support substrate 160 with the area 360 be electrically connected. In that area 360 can a first control connection 361 to apply a control signal to the first power semiconductor chips 311 be arranged.
[0036] In the areas 350 A resistor, e.g. a resistor with a negative thermal coefficient (NTC), can be used (in Fig. 3A not shown). The areas 350 can be electrically connected to measuring terminals 351 be connected. The resistor and the measuring connections 351 can be designed to maintain a temperature within the semiconductor package 300 to measure, since the voltage drop across the NTC depends on the temperature.
[0037] Fig. Figure 3B shows a perspective view of an upper support substrate. 160of the semiconductor package 300 , whereby in Fig. 3B a perspective view of the underside of the upper support substrate 160 (see the arrow in Fig. 3D for the viewing direction) is shown.
[0038] The lower electrically conductive layer 163 of the upper support substrate 160 is structured and has a first area 3 10 open. The first area 3 10 can the first carrier areas 310 and / or the second support area 320 overlap at least partially if the upper support substrate 160 in the semiconductor package 300 above the lower support substrate 120 The first section 3_10 is designed for applying the second supply voltage, e.g., Vpp. The first section 3_10 can be configured to have a second (middle) power connection. 390 on the lower support substrate 120to be electrically connected, e.g. by means of an electrically conductive spacer 391 (thus, the second power connection is connected 390 the second supply voltage). The first area 3_10 can be connected to the second power semiconductor chips. 321 be electrically connected, e.g. by means of the second power semiconductor chips 321 arranged electrically conductive spacers 150 In particular, the first area 3 10 be electrically connected to a power electrode, e.g. a source electrode of the second power semiconductor chip.
[0039] The first area 3_10 can have a connection point 3_11 where the first area 3 10 electrically with the area 380 on the lower support substrate 120 is connected. In that area 380 can a measuring connection 381It must be arranged and electrically connected to it. The measuring connection 381 can be used to measure the voltage applied to the first area 3_10.
[0040] The lower electrically conductive layer 163 of the upper support substrate 160 exhibits second areas 3_20, which are associated with the first power semiconductor chips 311 can be electrically connected, e.g. by means of the first power semiconductor chips 311 arranged electrically conductive spacer 150 In particular, the second regions 3_20 can be electrically connected to a power electrode, e.g., a source electrode of the second power semiconductor chips. The second regions 3 20 are as a phase of the half-bridge circuit of the semiconductor package 300 trained.
[0041] The lower electrically conductive layer 163can have a further area 3_30 which is designed to connect with the first carrier areas 310 to be electrically connected, e.g. by means of electrically conductive spacers 130 The area 3_30 can be designed to form a first support area. 310 on the second page 302 and a first support area 310 on the fourth page 304 to connect each other electrically.
[0042] The lower electrically conductive layer 163 can another area 3 40 exhibiting the areas 330 and 370 on the lower support substrate 120 electrically connects them.
[0043] The lower electrically conductive layer 163 can another area 3 50 exhibiting the areas 340 and 360 on the lower support substrate 120electrically connects them.
[0044] Fig. 3C shows the semiconductor package 300 after the arrangement of the upper support substrate 160 from Fig. 3B above the lower support substrate 120 from Fig. 3A. For the sake of clarity, in Fig. 3C only the lower conductive layer 163 of the upper support substrate 160 shown, the upper electrically conductive layer 161 and the insulating layer 162 were omitted.
[0045] According to one example, the semiconductor package 300 an encapsulation body (cf. Fig. 2), which is in Fig. 3C is not shown for the sake of clarity.
[0046] Fig. 3D shows a side view of the semiconductor package. 300 along the direction of the arrow in Fig. 3C.
[0047] Fig. Figure 4A shows a perspective view of a lower support substrate. 120 a semiconductor package 400 The semiconductor package 400 can be used with semiconductor packages 100 , 100 1 and 200 be identical.
[0048] The semiconductor package 400 is the semiconductor package 300 similar and differs from this one mainly in the arrangement of the first, second and third areas 410 , 420 and 430 . In the first areas 410 are the first power semiconductor chips 411 arranged and connected to a first 412 and third 413 power connection. On the second area 420 are second power semiconductor chips 421 arranged and with a fourth power connection 422 connected. The first areas 410 They thus correspond to the first carrier areas. 310 in semiconductor packaging 300and the second area 420 corresponds to the second support area 320 .
[0049] The third areas 430 are electrically equipped with a second power connection 431 connected, which is located between the first 412 and the third 413 power connection.
[0050] In the first areas 410 can a first supply voltage, e.g. V DD , concerns and in the third areas 430 A negative supply voltage, e.g., Vpp, may be present. The second area 420 can be formed as a phase.
[0051] The first areas 410 and the third areas 430 can alternate along a first page 401 of the semiconductor package 400 be arranged, e.g., in the arrangement as shown in Fig. 4A is shown. The third areas 430 This can serve as a kind of shield for the first areas 410and vice versa. Such an alternating arrangement of areas where the first supply voltage can be applied and areas where the second supply voltage can be applied can help to reduce stray inductances in the semiconductor package. 400 to reduce.
[0052] lines 441 , 442 , 443 in the upper conductive layer 121 can at least partially be derived from the first, second and / or third areas 410 , 420 and 430 They must be surrounded and thereby shielded, especially electromagnetically shielded. The cables 441 , 442 and 443 These could be, for example, control lines, the control electrodes, e.g., gate electrodes, of the power semiconductor chips. 411 or 421 with control connections of the semiconductor package 400 connect.
[0053] Fig. 4B shows the semiconductor package400 after the arrangement of the upper support substrate 160 above the lower support substrate 120 from Fig. 4A. For the sake of clarity, in Fig. 4B only the lower conductive layer 163 of the upper support substrate 160 shown, the upper electrically conductive layer 161 and the insulating layer 162 were omitted.
[0054] The upper support substrate 160 of the semiconductor package 400 can a fourth area 450 , fifth areas 460 and a sixth area 470 exhibit. The fourth area 450 can be designed to cover the first areas 410 on the lower support substrate 120 to connect them electrically. The fifth areas 460 can each be used with the first power semiconductor chips 411 and with the second area 420be electrically connected. The fifth areas can be designed as a phase. The sixth area 470 can be used with the second power semiconductor chips 421 and with the third areas 430 be electrically connected. The sixth area 470 It may be designed to apply the second supply voltage.
[0055] Fig. Figure 5 shows a flowchart of a process 500 for manufacturing a semiconductor package with a double-sided cooling structure. According to the method 500 For example, the semiconductor packages 100 , 100_1 , 200 , 300 and 400 be manufactured.
[0056] The procedure 500 includes at 501The method involves providing a lower support substrate comprising an electrically conductive upper layer, an electrically conductive lower layer, and an electrically insulating layer arranged between the upper and lower conductive layers. 500 includes at 502 The process involves attaching a first electrically conductive spacer to the upper electrically conductive layer of the lower support substrate. 500 includes at 503 The process involves attaching at least one power semiconductor chip to the upper electrically conductive layer of the lower substrate. 500 includes at 504 Attaching a second electrically conductive spacer to the power semiconductor chip. The procedure 500 In the case of 505, this involves attaching an upper electrically conductive element to the spacers opposite the lower support substrate. The method 500In 506, this comprises arranging a first, second and third power terminal on the upper electrically conductive layer of the lower support substrate along a first side of the semiconductor package, wherein the second power terminal is arranged between the first and the third power terminal, and wherein the first and the third power terminal are configured to apply a first supply voltage, and wherein the second power terminal is configured to apply a second supply voltage.
[0057] The procedure 500 The procedure may further include the arrangement of the first, second, and third power connections involving the removal of the first, second, and third power connections from a conductor frame. 500 The method may also include electrically connecting the second power terminal to the upper electrically conductive element. 500may further comprise encapsulating the spacers, the at least one power semiconductor chip, the upper electrically conductive element and the lower support substrate in an encapsulation body.
[0058] The following refers to Fig. 6 Another example of a semiconductor package 600 shown. The semiconductor package 600 can the semiconductor packages 100 , 100_1 , 200 , 300 and 400 They will be similar and, compared to these, will only have the differences shown below. The semiconductor package 600 can be according to a manufacturing process such as the process 500 be manufactured.
[0059] Fig. Figure 6A shows a lower support substrate 601 of the semiconductor package 600 The lower support substrate 601 exhibits a first support area 610 with first power semiconductor chips and one next to the first carrier area610 arranged second support area 620 with second power semiconductor chips. The first carrier area 610 can be used, for example, to create V DD be designed and the second support area 620 It can, for example, be designed as a phase.
[0060] According to an example, a first power connection can 631 , a second power connection 632 and a third power connection 633 on one side of the lower support substrate 601 be arranged. The first and second power connections 631 , 632 can be electrically connected to the first carrier area 610 be connected and e.g. as V DD -connections must be designed. The third power connection 633 can be switched between the first and second power connection 631 , 632 be arranged and can be designed to be electrically connected to the first area 640of the upper support substrate 602 (cf.) Fig. 5B) to be connected. The second power connection can be, for example, as V SS -connection designed.
[0061] According to one example, a fourth power connection can 634 of the semiconductor package 600 with the second support area 620 be electrically connected and configured as a phase connection. The fourth power connection 634 can be placed on one of the second sides of the lower support substrate opposite the first side. 601 be arranged.
[0062] Fig. 6B shows the semiconductor package 600 after the application of the upper support substrate 602 above the lower support substrate 601 The upper support substrate exhibits the first area 640 and second areas 650 open. The first area 640 can be used to create V SS be trained and the second areas 650can be structured as a phase. The first area 640 is electrically connected to the third power connection 633 connected. The second areas 650 are each via a first electrically conductive spacer 661 with an upper power electrode (e.g. the source electrode) of the first power semiconductor chips and via a second electrically conductive spacer 662 with the second support area 620 tied together.
[0063] As in Fig. As can be seen from 6B, the first area overlaps. 640 of the upper support substrate 602 the first support area 610 of the lower support substrate 601 at least partially.
[0064] According to one example, the semiconductor package 600 furthermore, an encapsulation body that contains the upper and lower support substrate 601 , 602at least partially encapsulated. For the sake of clarity, such an encapsulation body is shown in Fig. 6B not shown. Furthermore, the semiconductor package 600 further structured areas on the lower and / or upper support substrate 601 , 602 e.g., control lines, and also other connections such as measuring or control connections. These are also not shown for the sake of clarity.
[0065] According to one example, the boundary between the first support area runs 610 and the second support area 620 not straight, but has an interlocking pattern. In Fig. 6C is a top view of the boundary between the first support area 610 and the second support area 620 shown according to an example that exhibits such an interlocking design. Such a progression of the support areas. 610 , 620can contribute to the first support area 610 optimal from the first area 640 of the upper support substrate 602 is overlapped.
[0066] Fig. Figure 7 shows an equivalent circuit diagram. 700 a semiconductor package such as the semiconductor package 100 , 100_1 , 200 , 300 , 400 and 600 The solid lines show the electrical conductors. For example, the dotted lines show the current flow from... V DD The dotted lines show the current flow from Vss to the phase, and the dashed lines show the current flow from Vss to the phase. According to another example, the dotted lines show the current flow from Vss to the phase, and the dashed lines show the current flow from Vss to the phase. V DD to the phase.
[0067] The points 701 can connect to the first and second power outlets 312 , 313 , 412 , 413 correspond to the point 702can the third power connection 390 , 431 correspond and the point 703 can the fourth power connection 322 , 422 correspond. The other points 704 can correspond to the control or measuring connections. The transistors 705 can be achieved through the first and second power semiconductor chips 311 , 321 , 411 , 421 be realized.
[0068] In Fig. 7 are in particular the parasitic inductances 706 the electrical conductor is shown. The one in Fig. 7. Easily recognizable symmetrical circuit structure of the semiconductor packages 100 , 100_1 , 200 , 300 , 400 and 600 can help to effectively reduce these inductances.
[0069] Although specific embodiments have been presented and described herein, it is obvious to the person skilled in the art that a multitude of alternative and / or equivalent implementations can replace the specific embodiments shown and described without departing from the scope of this disclosure. This application is intended to cover all adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this disclosure is limited only to the claims and their equivalents.
Claims
[1] Semiconductor package with double-sided cooling structure, comprising the semiconductor package: an upper electrically conductive element that has an externally exposed metal surface, a lower support substrate comprising an upper electrically conductive layer, a lower electrically conductive layer with an exposed surface, and an electrical insulating layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, at least one power semiconductor chip located between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer positioned between the upper electrically conductive element and the power semiconductor chip, and a first, second and third power terminal arranged along a first side of the semiconductor package, wherein the second power connection is arranged between the first and the third power connection, and wherein the first and third power terminals are designed to apply a first supply voltage and wherein the second power terminal is designed to apply a second supply voltage. [2] Semiconductor housing according to claim 1, wherein the upper electrically conductive element comprises an upper support substrate with an upper electrically conductive layer, a lower electrically conductive layer and an electrical insulating layer arranged between the upper and lower electrically conductive layers, wherein the upper electrically conductive layer corresponds to the externally exposed metal surface. [3] Semiconductor package according to claim 1 or 2, wherein the first supply voltage is positive and the second supply voltage is negative. [4] Semiconductor package according to any one of the preceding claims, further comprising: a phase terminal located on the second side opposite the first side of the semiconductor package. [5] Semiconductor housing according to one of the preceding claims, wherein the second power terminal is electrically connected to the upper electrically conductive element. [6] Semiconductor package according to one of the preceding claims, wherein the first and third power terminals are electrically connected to a first support area of the upper electrically conductive layer of the lower support substrate. [7] Semiconductor housing according to claims 4 and 6, wherein the first support area surrounds a second support area of the upper electrically conductive layer of the lower support substrate on at least two opposite sides, and wherein the phase terminal is electrically connected to the second support area. [8] Semiconductor housing according to one of the preceding claims, wherein a central region of the upper electrically conductive layer of the lower support substrate is electrically connected to a control electrode of the at least one power semiconductor chip, the upper electrically conductive element and a control terminal of the semiconductor housing. [9] Semiconductor package according to one of the preceding claims, wherein the at least one power semiconductor chip is a low-side power semiconductor chip of a half-bridge circuit and is electrically connected to the second power terminal. [10] Semiconductor housing according to claim 9, further comprising: at least one additional power semiconductor chip wherein at least one further power semiconductor chip is a high-side power semiconductor chip of the half-bridge circuit and is electrically connected to the first and third power terminals. [11] Semiconductor housing according to one of the preceding claims, wherein a first region of the upper electrically conductive element is electrically connected to the second power terminal. [12] Semiconductor housing according to claims 4 and 11, wherein a second region of the upper electrically conductive element is electrically connected to the phase terminal. [13] Semiconductor housing according to claims 6 and 11, wherein the first area at least partially covers the first support area. [14] Semiconductor housing according to one of the preceding claims, wherein the second power terminal is electrically connected to the upper electrically conductive element via the first spacer. [15] Semiconductor package according to any of the preceding claims, wherein the first, second and third power terminals are part of a conductor frame. [16] Semiconductor package according to any of the preceding claims, wherein the at least one power semiconductor chip comprises SiC. [17] Semiconductor housing according to any one of the preceding claims, further comprising: an encapsulation body that at least partially encapsulates the lower support substrate and the upper electrically conductive element, wherein the encapsulation body comprises a pressing compound. [18] Method for manufacturing a semiconductor package with a double-sided cooling structure, the method comprising: Providing a lower support substrate comprising an upper electrically conductive layer, a lower electrically conductive layer, and an electrical insulating layer arranged between the upper and lower electrically conductive layers. Attaching a first electrically conductive spacer to the upper electrically conductive layer of the lower support substrate, Attaching at least one power semiconductor chip to the upper electrically conductive layer of the lower substrate, Attaching a second electrically conductive spacer to the power semiconductor chip, Attaching an upper electrically conductive element to the spacers opposite the lower support substrate, and Arranging a first, second and third power terminal on the upper electrically conductive layer of the lower support substrate along a first side of the semiconductor package, wherein the second power connection is arranged between the first and the third power connection, and wherein the first and third power terminals are designed to apply a first supply voltage and wherein the second power terminal is designed to apply a second supply voltage. [19] Method according to claim 18, wherein the arrangement of the first, second and third power connection comprises removing the first, second and third power connection from a conductor frame. [20] Method according to claim 18 or 19, further comprising: Electrical connection of the second power terminal to the upper electrically conductive element. [21] Method according to any one of claims 18 to 20, further comprising: Encapsulation of the spacers, the at least one power semiconductor chip, the upper electrically conductive element and the lower support substrate in an encapsulation body. [22] Method according to claim 21, wherein the encapsulation comprises compression molding.