Semiconductor device structure with multiple gate terminals and methods for their formation

Abstract

Integrated circuit comprising a transistor, comprising: a semiconductor channel region (101, 201, 301, 401, 501, 601, 701, 801, 901, 1001, 1101, 1201, 1301, 1401, 1501, 1601) that includes a node which electrically connects three channel parts, Schottky contacts (124, 424, 524, 624, 1524, 1624) formed at each end of the semiconductor channel region (101, 201, 301, 401, 501, 601, 701, 801, 901, 1001, 1101, 1201, 1301, 1401, 1501, 1601), Outer gate contacts (221, 321, 433, 434, 533, 534, 633, 634, 733, 734, 833, 834, 933, 934, 1033, 1034, 1133, 1233) are arranged at each Schottky contact to control the conductivity of the Schottky barrier.