Optoelectronic component and method

Abstract

Optoelectronic component, comprising: - a semiconductor body (2, 2.1, 2.2) comprising a sequence of layers (2.1, 2.2, 3.3) with an active region provided for generating radiation; - a first dielectric layer (3.2) arranged on the layer sequence (2.1, 2.2) which has a plurality of first regions and a second region; - a first through-contact (3.2A) in each area from the multitude of first areas to contact a first side of the active region; - a second through-contact (3.5) in the second area to contact a second side of the active region; - a conductive layer (3.1) comprising a plurality of first regions and a second region surrounding the plurality of first regions and electrically insulated from the plurality of first regions, wherein the conductive layer (3.1) has a substantially planar surface and is arranged planarly on the plurality of first regions and the second region, such that each of the plurality of first regions of the conductive layer is in contact with the first via (3.2A) in the respective area of ​​the plurality of first regions and the second region of the conductive layer is in contact with the second via (3.5) of the first dielectric layer (3.2), wherein a conductive material (3.22) is recessed in the first via (3.2A) such that the conductive layer (3.1) extends partially into the via (3.2).

Description

TECHNICAL AREA

[0001] The invention relates to an optoelectronic component and a method for its manufacture. BACKGROUND

[0002] Optoelectronic components are used in a wide variety of lighting applications today. Customers and applications demand that such components be flexible with regard to their photometric properties. Optoelectronic components should be able to provide controllable photometric properties and adjustable illuminance, suitable, for example, for use in motor vehicles or household appliances. Therefore, there is a need for improved optoelectronic components and a method for their fabrication.

[0003] Semiconductor devices of various known types can be found in WO 2015 / 053 600 A1. Likewise, DE 10 2008 011 848 A1, DE 10 2012 112 302 A1 and DE 10 2012 217 533 A1 disclose optoelectronic devices of the type mentioned above.

[0004] An optoelectronic device according to one or more aspects comprises a semiconductor body having a sequence of layers with an active region provided for generating radiation. The device includes a first dielectric layer arranged on the sequence of layers, which has a plurality of first regions and a second region. A first via is provided in each region of the plurality of first regions for contacting a first side of the active region. Likewise, at least one second via is provided in the second region for contacting a second side of the active region. A conductive layer is arranged on the plurality of first regions, and the at least one second region with a substantially planar cap is a flat surface. The conductive layer comprises a plurality of first regions and a second region.The second region surrounds the multitude of first regions and is opposite the first.

[0005] A multitude of first regions are electrically insulated. Each of these first regions of the conductive layer is in contact with a corresponding first via in the respective region of the multitude of first regions. The at least one second region of the conductive layer is in contact with the at least one second via of the first dielectric layer.

[0006] According to the proposed principle, the conductive layer is formed as a single layer positioned above the dielectric layer. This approach reduces the surface topology of the conductive layer, which would otherwise be caused by the various processing steps of the respective vias. Consequently, the reduced topology significantly improves the properties for direct bonding of the device and considerably reduces the risk of delamination after the direct bonding process. Further problems associated with the through-silicon via (TSV) contacting the relevant sections in subsequent steps are prevented or reduced.

[0007] Another aspect concerns current distribution. A current distribution layer can be deposited on the active region and be in contact with the first via in each of the multiple first regions. The current distribution layer can comprise ITO (indium tin oxide) or another conductive material suitable for distributing charge carriers across the active region. To further improve current distribution, the first via in each of the multiple first regions in the first dielectric layer can have different shapes. It can be any type of closed shape, such as a rectangle, hexagon, rhombus, or polygon. Alternatively, the via can be circular. Multiple first vias can be arranged in a specific relationship to one another.

[0008] In this respect, the first via in each region can be filled with a conductive material. This material can differ from the material of the conductive layer. The conductive material in the first via in each region is recessed relative to the surface of the first dielectric layer. It does not completely fill the via. Thus, the conductive layer can partially extend into the via. This recess in the via prevents the formation of a protrusion when the conductive layer is deposited.

[0009] In some cases, the conductive material on its surface may be slightly recessed in an area above the second via. Thus, in some aspects, the optoelectronic device incorporates a filler material in areas of the conductive layer above the at least one second via, such that the conductive layer and the filler material form a flat and essentially level surface.

[0010] While the first via can touch the distribution layer and / or the first side of the active region, the second via can extend through the layer sequence containing the active region in the second region. To prevent a short circuit, it includes a dielectric layer on its sidewall.

[0011] To prevent a short circuit in the conductive layer, the conductive layer includes one or more recesses that electrically isolate the first regions from the second region. The insulating recesses extend from the first dielectric layer to the upper surface of the conductive layer and are filled with a dielectric and insulating material. Each insulating recess surrounds one of the first regions, such that contacts for the first via of the first dielectric layer are located within that region. The insulating recess can be of any suitable shape, including a round or polygonal shape such as rectangular or hexagonal, and the like.

[0012] In one aspect, the optoelectronic device can further comprise a second dielectric layer, which is arranged directly on top of the conductive layer. The second dielectric layer can include a plurality of first vias. Each of these first vias is in contact with a corresponding first region of the conductive layer such that each via is displaced with respect to a virtual extension of the first via in each of the plurality of first regions.

[0013] Likewise, the second dielectric layer can include at least one second via in the second dielectric layer that is in contact with the second region of the conductive layer, such that the second via is displaced with respect to a virtual extension of the second via in the second region.

[0014] Furthermore, the repositioning reduces the risk of delamination between the via in the second dielectric layer and the respective section of the conductive layer's surface. In other words, any remaining uneven surface sections, surface defects, or lattice shifts resulting from the processing of the via in the first dielectric layer, which are covered by the conductive layer but may extend further through it, do not affect bonding. This is largely achieved by the already flat and level surface and is further enhanced by the repositioning.

[0015] The proposed design allows for the segmentation of an optoelectronic device into a multitude of sections. Contact with each section is established via one of the first vias and at least one second via, which act as a common via. The segments of the optoelectronic device can therefore be individually powered.

[0016] In one aspect, the second dielectric layer of the optoelectronic device can comprise a core layer sandwiched between two dielectric layers. One of the dielectric layers, facing the conductive layer, acts as a bonding layer. The core layer can be a semiconductor or a conductive material. For example, the core layer can be silicon. Accordingly, the multiple first vias and the at least one second via are configured as silicon vias (TSVs). The second dielectric layer can be thick enough to provide the necessary stability for further processing of the optoelectronic device.

[0017] In one aspect, one or more solder beads can be arranged on each of the multiple first vias of the second dielectric layer and / or on the second via of the second dielectric layer. The one or more solder beads can extend at least partially onto the second dielectric layer. The solder beads can span one or more layers to ensure a rigid and tight connection to the respective via. Extending the solder beads beyond the via provides better accessibility and a larger contact area. Contact errors in the form of high local current densities due to mismatches when making a solder joint to another circuit are reduced.In one aspect, the TSV via, or more generally the plurality of first vias and the at least one second via in the second dielectric layer, can include a dialectical layer arranged on their respective sidewalls. Optionally, a conductive material can be deposited on the dielectric sidewall layer in the recess forming the via, with the conductive layer contacting the conductive layer. The remaining space of the plurality of first vias and the at least one second via in the second dielectric layer can be filled with a conductive material, for example, a metal, or with a doped semiconductor. In some aspects, the conductive material deposited on the dielectric sidewall of the via can be the same material as a layer of solder balls.

[0018] Another aspect of an optoelectronic device is the inclusion of a stress-reducing layer positioned between the conduction layer and the second dielectric layer. Such a layer serves to reduce lattice stresses or displacements that can occur when two different semiconductor materials are bonded together. Stress-reducing layers are also useful for compensating for differing coefficients of thermal expansion.

[0019] In another aspect, the optoelectronic device can further comprise a pattern on a surface of the semiconductor body opposite the first dielectric layer. Such a pattern can be arranged at least over a virtual extension from the plurality of first regions toward the surface of the semiconductor body, wherein the pattern preferably has a substantially flat surface. The pattern is arranged over the active zone and reduces the back-reflection of light into the semiconductor body. The pattern can comprise a dielectric layer deposited on a roughened surface of the semiconductor body.

[0020] To further improve light direction and reduce interference, the optoelectronic device can also include one or more structures on the surface of the semiconductor body and / or the patterned area. These structures are at least partially arranged over a virtual extension of the second region. Since second regions separate different segments of an optoelectronic device, the structures prevent interference between light transmitted from different segments. The structures can be made of different materials, such as silicon or metal. In one aspect, the structures are designed to function as support structures during several processing steps of the optoelectronic device.In some other aspects, the original substrate on which the semiconductor body is deposited during manufacturing may be structured.

[0021] Several other aspects concern a method for obtaining an optoelectronic device. The method comprises the following steps: Providing a semiconductor body that has a sequence of layers with an active region provided for generating radiation; Deposition of a first dielectric layer on the layer sequence, which has a plurality of first regions and a second region; Providing an initial contact point in each area from the multitude of initial areas to contacting an initial page of the active region; Providing a second through-contact in the second area to contact a second side of the active region; Deposition of a conductive layer having a substantially planar surface and arranged planarly on the plurality of first and second regions of the first dielectric layer, wherein the conductive layer comprises a plurality of first regions and a second region surrounding the plurality of first regions and electrically insulated from the plurality of first regions, such that each of the plurality of first regions of the conductive layer is in contact with the first via in the respective region of the plurality of first regions and the second region of the conductive layer is in contact with the second via of the first dielectric layer.

[0022] The proposed manufacturing process provides a conductive layer as a single, flat, and even layer positioned over the dielectric layers. In particular, surface irregularities such as unevenness and the like are reduced through various processing steps. The flat surface of the conductive layer facilitates subsequent processing, thereby reducing the risk of delamination. Contacting using TSV processes is simplified.

[0023] In one aspect of the process, providing an initial via in each region involves an etching step, i.e., etching the first contact recess in the first dielectric layer until the active region is reached. A conductive material is then deposited. Such a material can comprise a metal or a highly conductive material within the etched initial contact recess, leaving a depression between a top surface of the conductive material and a top surface of the first dielectric layer. Leaving a depression reduces the likelihood of a protrusion on the surface of a subsequently deposited layer. The material deposited in the initial via can be different from the conductive material.As a result of the depression left in the first via, the subsequent deposition of the conductive material will completely fill the first via.

[0024] Similarly, the second via is provided by etching a second recess in the second region, extending through the layer sequence containing the active region. A dielectric material is then deposited on the sidewalls of the etched recess to electrically insulate the different layers from the conductive material subsequently filled into the recess. The conductive material can be metal or the same as the material of the conductive layer.

[0025] In another aspect, a current distribution layer is deposited on the active region before the first dielectric layer is deposited. This current distribution layer is in contact with the first via of each of the numerous first regions.

[0026] The processing of the conductive layer can further include: depositing material that forms the conductive layer; etching an insulating recess into the conductive area to form a first region, thereby electrically isolating the first region from a surrounding second region of the conductive layer; and filling the insulating recess with a dielectric material. The insulating recess extends through the conductive layer. The insulating recess can have various shapes and surround an area of ​​conductive material that forms the first region. It is possible that the conductive layer over the second via is not perfectly flat. Therefore, additional material can be applied to fill the uneven areas so that the conductive layer and the filler material form a flat and essentially level surface.

[0027] In another aspect of the process, a second dielectric layer is placed directly on top of the conductive layer. A multitude of first vias are formed, each via being located above and in contact with a corresponding first region of the conductive layer. Each via is offset from the multitude of first regions by a virtual extension of the first via in each region. Therefore, the first via is not located above a via in either the first dielectric layer or the conductive layer.

[0028] For this purpose, a multitude of recesses are etched into the second dielectric layer down to the first region. Then, a dielectric layer is deposited on the sidewalls of the multitude of recesses; and the multitude of recesses is filled with a conductive material to form the multitude of first vias.

[0029] Similarly, at least one second via can be arranged in the second dielectric layer. Each second via is formed above and in contact with a corresponding second region of the conductive layer. Each second via is offset with respect to a virtual extension of the second via in the second regions.

[0030] In particular, in some aspects, at least one second recess can be etched into the second dielectric layer until the second region of the conductive layer is reached. This second recess is displaced relative to a virtual extension of the second via in the second region. A dielectric layer is then deposited on the sidewall of the second recess. A conductive material is filled into the second recess to form a second via in the second dielectric layer. Therefore, according to these aspects, the first and second vias through the second dielectric layer are displaced relative to their respective vias in the first dielectric layer.

[0031] According to one aspect, a layer to reduce mechanical stresses can be deposited between the conduction layer and the second dielectric layer. This stress-reducing layer minimizes any stresses due to differing lattice constants between the conduction layer and the second dielectric layer, thereby increasing the freedom in choosing a suitable material for the second dielectric layer.

[0032] Several other aspects concern the formation and deposition of the second dielectric layer. The second dielectric layer can be formed by at least one of the following steps, including the application of a body layer, the deposition of a dielectric bonding layer between the conductive layer and the body layer, and the deposition of a dielectric surface opposite the conductive layer. The body layer can act as a support layer, sufficiently thick to provide stability for subsequent processing or for lifting the optoelectronic device. Various materials can be used for the body layer. The dielectric layer on both sides can be used to electrically insulate the body layer from the conductive layer or other processing layers.

[0033] In another aspect, one or more solder beads are deposited on each of the multiple first vias. The one or more solder beads can also be deposited on at least one second via. They can extend at least partially over the second electrical layer. Extending the solder beads onto the second dielectric layer provides a larger area for creating a solder joint between a second circuit and the two electronic components. This reduces potential mismatch problems.

[0034] The first via in each of the many regions in the first dielectric layer can have different shapes. A closed shape surrounds a region of the first dielectric layer. Such a shape can be rectangular, rhombus-shaped, parallelogram-shaped, hexagonal, or any convex polygonal shape. The shape can be configured to provide suitable current introduction into a current distribution layer and into the respective active region. In particular, it is suitable for distributing the current over the entire area of ​​the active region. Likewise, the second vias to the first dielectric layer and to the active region can have similar shapes to introduce charge carriers into the semiconductor body and the active region.

[0035] Similarly, each of the insulating recesses in the conductive layer develops into a rectangular shape, a rhombus shape, a parallelogram, or any other convex polygonal shape. The shape of each insulating recess forms a closed enclosure that defines one of the first regions in the first dielectric layer and encloses the first via.

[0036] In another aspect, a surface of the semiconductor body can be structured relative to the first dielectric layer, at least over a virtual extension from the plurality of first regions towards the surface of the semiconductor body. This structuring provides improved decoupling of photons generated in the active region from the semiconductor body. The structuring can be achieved by forming a dielectric layer with a substantially flat surface on a roughened surface of the semiconductor body. In another aspect, one or more structures can be provided on the surface of the semiconductor body. These can be arranged over a virtual extension of the second region to prevent optical interference between adjacent first regions.One or more structures can support the segmentation of the optoelectronic device. These structures are made of silicon or another suitable material. The original substrate layer on which the semiconductor body is formed can potentially be used. The one or more structures can also be used to support the optoelectronic device during subsequent processing steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present application will now be explained in more detail with reference to the attached drawings, in which Fig. 1 illustrates some aspects of an embodiment of an optoelectronic device; Fig. 2 additional aspects of the proposed principle; Fig. 3 presents some further aspects of an embodiment of an optoelectronic device; Fig. 4 represents yet another embodiment of the proposed principle; the Fig. Figures 5A to 5G illustrate various manufacturing steps of an optoelectronic device according to one embodiment; Fig. 6 shows a detailed view of several layers of an optoelectronic device; Fig. 7. A top view illustrates some features of an embodiment of an optoelectronic device; Fig. 8 shows another top view, which represents an alternative embodiment; Fig. 9A represents parts of an embodiment of an optoelectronic device, the focus being on the light emission area; Fig. 9B represents parts of a further embodiment of an optoelectronic device, the focus being on the light emission area. DETAILED DESCRIPTION

[0038] Optoelectronic components are now often segmented into several separate lighting elements, each of which can be controlled individually. This segmentation allows for different lighting configurations, enabling a variety of lighting effects and flexibility in terms of color and light intensity. However, operating a lighting device separately requires powering each segment via its own individual contacts. A common contact (usually the n-terminal) can be used for each segment of the lighting device. Additional contacts (p-terminal contacts) then allow for the individual addressing of each segment.

[0039] The power supply to the individual segments can be provided via a so-called silicon via (SV) connection. These vias in a silicon substrate are used to establish contact with the respective terminals on an LED semiconductor 1, which contains the active region and the light-emitting region. Metallic solder is used to create a contact between the substrate (which, for example, comprises silicon) and the LED semiconductor 1, thus forming the optoelectronic device. The SV connection in the substrate can then be externally contacted to connect the optoelectronic device to the control or driver circuitry. However, soldering carries the risk of short circuits between individual segments and is therefore no longer commonly used. Instead, direct bonding methods are typically employed to connect the substrate to the LED semiconductor 1.However, direct bonding and subsequent processing of TSVs by etching the substrate can lead to delamination due to irregularities in the surface of the LED semiconductor 1. Larger areas of the LED semiconductor 1 with multiple segmentations can exacerbate the problem due to the increased surface topology during the various conventional processing steps of the LED semiconductor device 1. As a result, the bond contacts become destabilized, and TSV contacts may malfunction due to varying etch depths. Therefore, there are still opportunities to improve optoelectronic components.

[0040] The present application proposes the use of a single planar conductive layer over an isolated active region of the semiconductor body. The conductive layer can act as a contact to the n-doped layer of the active region as well as an (electrically isolated) contact to the p-doped region. The planar deposition over a relatively large area provides a current distribution that reduces the local high current density, thereby reducing the thermal load on the device.

[0041] The metal layer exhibits reflective properties, causing photons generated in the active region to be reflected back towards the light-emitting side of the device. Finally, the metal layer provides a substantially flat surface across all segments of the optoelectronic device, thus enabling subsequent etching and bonding processes.

[0042] Fig. Figure 1 illustrates some aspects of an embodiment according to the proposed principle. The embodiment shows a segment section of an LED semiconductor 1. Different segments are arranged side by side (not shown) and are processed in different manufacturing steps.

[0043] The LED semiconductor 1 is arranged on a substrate 1. Such a substrate can comprise sapphire, silicon, or any other suitable material on which a semiconductor body can be deposited and grown. For simplicity, the semiconductor body 2 shown herein comprises only a single layer. However, to compensate for lattice differences, mechanical stresses, or other loads between the substrate 1 and the semiconductor body 2, the semiconductor body 2 can have a layered structure that compensates for lattice differences between the substrate 1 and the body 2. The semiconductor body 2 can comprise a III-V semiconductor material such as GaN, GaAS, and the like. The semiconductor body 2 includes an active region, including an n-doped layer 2.1 on which a p-doped layer 2.2 is deposited. A pn ​​junction is formed between the two differently doped layers 2.1 and 2.2.The thickness of the doped region can vary and depends on various conditions. For simplicity, the semiconductor body 2 can be configured as an n-doped semiconductor. This can increase the conductivity of the material. A current distribution layer 3.3 is deposited on the p-doped layer 2.2. The current distribution layer 3.3 can have a thickness on the order of a few tens of nanometers and distributes charge carriers into the p-doped region 2.2.

[0044] A dielectric layer 3.2 with a thickness of up to 1 µm is deposited on the upper current distribution layer 3.3. The dielectric layer can comprise silicon oxide, aluminum oxide, titanium oxide, silicon nitride, or any combination thereof. Other material combinations may also be suitable, depending on the specific application. The various materials can be arranged as layered materials or as bulk layers. In the former case, for example, the deposition of titanium oxide and silicon oxide as a layered material can function as a Bragg reflector system, in which photons generated in the active region between the p-doped layer 2.2 and the n-doped layer 2.1 can be reflected towards the decoupling region (the surface of the body 2 adjacent to the support 1).

[0045] The first dielectric layer 3.2 is preferably grown with a planar and flat surface that extends over all (future) segments of the LED semiconductor 1. The first dielectric layer 3.2 comprises a plurality of first regions A, one of which is shown, and at least one second region A. Each region together with an adjacent region B corresponds to a segment of the LED semiconductor 1.

[0046] Each of the regions A includes a first via 3.2A extending from the upper surface of the first dielectric layer 3.2 towards the current distribution layer 3.3. The via comprises a conductive material 3.22, for example, a metal. The material 3.22 is deposited in the layer to a level just below the surface of the first dielectric layer 3.2, forming a small depression 3.27 as shown.

[0047] The second region B of the first dielectric layer 3.2, adjacent to region A and defined by the dotted line, also includes a via 3.5, as explained below. The via 3.5 extends from the top surface of the first dielectric layer 3.2 through the current distribution layer 3.3 and the pn junction into the semiconductor body 2. The sidewalls of the via 3.5 are covered with a dielectric layer 3.51, and the layer is filled with a conductive material 3.52. The dielectric layer 3.51 can be, for example, silicon oxide; the conductive material can be a metal. Thus, in such an arrangement, the first via 3.2A makes electrical contact with the p-doped layer of the optoelectronic device, while the via 3.5 is in contact with the n-doped region.To avoid short circuits between p-doped regions of different segments of the LED semiconductor 1, the via 3.5 can surround area A.

[0048] A planar metal layer 3.1 is formed on the surface of the first dielectric layer 3.2. As shown in Fig. As illustrated in Figure 1, the metal layer 3.1 extends partially into and completely fills the recesses of the first via 3.2A. The first metal layer 3.1 is also in contact with the conductive material 3.52 and the second via 3.5. During the deposition of the metal layer 3.1, one or more artificial and undesired depressions may remain above the second via 3.5. These are subsequently filled with filler material 3.9 to form a flat surface on the top of the metal layer 3.1.

[0049] For electrical separation, the metal layer 3.1 also includes an insulating recess filled with the electrical material 3.4. The insulating recess 3.4, filled with the dielectric material, forms an enclosed environment, thereby defining regions A and B by separating the metal layer material in contact with the first via 3.2A from the metal layer material in contact with the second via 3.5. In other words, the virtual extension of the recesses 3.4 into the dielectric material separates the two regions A and B. Fig. 1. As illustrated by the dotted line, this first dielectric layer 3.2 is divided into a region A and a region B. Regions A and B allow the segmentation of the optoelectronic device.

[0050] As a result, the conductive material layer 3.1 is in contact with both the n-doped and the p-doped segmented sections of the semiconductor body, maintaining a flat and uniform surface. Such a structure therefore facilitates simpler subsequent processing steps. In particular, direct bonding of the LED semiconductor 1 to a substrate or other device becomes possible with a significantly reduced risk of the uneven surface topology of the metal layer 3.1 causing delamination or faulty connections during the TSV process.

[0051] Fig. Figure 2 illustrates further aspects of the processing and the optoelectronic device according to the proposed principle.

[0052] As shown here, the optoelectronic component is turned upside down for further processing. The upper surface of the semiconductor body 2 of the LED semiconductor 1, which is located opposite the active region, is structured in such a way as to enable better photon transfer of photons generated in the active region of the semiconductor body 2.

[0053] For this purpose, the upper surface of the semiconductor body 2 is roughened or otherwise structured and subsequently oxidized to form a thin surface of the structured layer 3.28. The structure beneath the upper surface extends, as shown, entirely over region A of the first dielectric layer and partially through region B. Most photons are generated in this extension area during operation of the optoelectronic device. To guide transmitted light and to prevent optical interference between different segments of the LED semiconductor 1 and the optoelectronic device, further structures 5.1 are arranged on the surface of the dielectric structured layer 3.28. These structures can, for example, include a silicon layer or a metal mirror layer. In this respect, it might be useful to consider structure 5.1. To be used as an auxiliary support during the entire processing of the device. For example, the one in . Fig. One of the carriers shown is suitable for this purpose. Alternatively, the carrier can be removed during the processing of the optoelectronic device, and the additional layers 5.1 can be structured and arranged on the dielectric layer 3.28.

[0054] The flat and planar surface of the conductive layer 3.1 in its first and second regions enables bonding to a silicon substrate 4 using direct bonding techniques. The dielectric layer 4.1 of the substrate can be polished and has a roughness of less than 1 nm. Both the planar surfaces of the dielectric layer 4.1 and the conductive layer 3.1 are rigidly and directly bonded to each other, resulting in a large bonding area. This reduces the risk of unintentional delamination during subsequent processing steps or due to thermal stress during operation of the optoelectronic device. The silicon layer 4, with its greater thickness of several micrometers, for example in the range of 80 µm to 120 µm, provides stability for the LED semiconductor 1.

[0055] The first silicon substrate 4 comprises the first dielectric layer 4.1 and, on its opposite side, a second dielectric layer 4.2. Both dielectric layers are made of silicon oxide. Additionally, the silicon layer includes the vias 4.3A and 4.3, respectively. Each via extends from the surface of the electrical layer 4.2 through the silicon material of the substrate 4 to the dielectric layer 4.1, where it makes contact with the conductive layer 3.1 of the LED semiconductor 1. Each via comprises a sidewall having a dielectric material 4.31 deposited on it, and a conductive layer 4.32 extending from the respective sidewalls toward the metal layer surface. The dielectric layer 4.31 can, for example, comprise silicon oxide, while the conductive layer 4.32 can be made of silicon oxide.In this example, layer 32 consists of a metal compound, for example, TaCu or another copper-containing compound. The material of the conductive layer 4.32 is selected to provide good contact with the material of the conductive layer 3.1, thereby reducing the risk of delamination. The vias 4.3A and 4.3 are then filled with conductive material 4.35, e.g., a metal. Current supplied through the vias 4.3A and 4.3 is distributed over a larger area in the conductive layer 3.1, thus reducing the thermal load.

[0056] The via 4.3A is positioned so that it is in contact with the conductive layer 3.1, thus providing an electrical contact to the via 3.2A in the first region A. More specifically, the via 4.3A is positioned so that it is not directly above the via 3.2A in region A, but is slightly offset from it. In other words, the via 4.3A does not cross a virtual extension of the via 3.2A in the first dielectric layer towards the silicon substrate. This offset and the specific position of the via 4.3A and the via 3.2A further reduce the risk of the via detachment. Because the contact between the metal layer 3.1 and the material in the via 4.3A is offset relative to the via 3.2A, any detachment resulting from the growth process and caused by the via 3.2A is minimized.The roughness caused by 2A in the surface of the metal layer 3.1 does not affect the contact between the metal layer 3.1 and the via 4.3A. Furthermore, the relatively large area of ​​the material layer 3.1, which defines areas A and B, allows for slight misalignment during the direct bonding process without causing short circuits or other electrical contact problems.

[0057] Similarly, the via 4.3 above area B is located at a position that is offset relative to a virtual extension of the via 3.5. As in Fig. As illustrated in Figure 2, roughness or an uneven surface in the conductive layer 3.1, caused by the growth process during fabrication, does not affect the contact between the via 4.3 and the metal layer 3.1 in region B. Such a displacement of the via allows simultaneous contact of the p- and n-doped layers of the semiconductor body by the silicon substrate 4 and the metal layer 3.1.

[0058] A contact point is arranged on the surface of the dielectric layer 4.2. The contact point comprises the first metal protrusion 4.4, which is arranged over the respective vias, and a solder ball 4.5, which is arranged on the first metal protrusion 4.4. Both the solder ball and the metal protrusion are arranged over the via but may also extend partially over the dielectric layer 4.2. The first metal protrusion 4.4 is selected from a group of materials that provide a rigid connection to layer 4.2, thereby reducing delamination. It may be the same material as layer 4.32 in vias 4.3A and 4.3. This arrangement increases the size of the solder contacts to simplify downstream processing, thereby reducing misalignment problems.

[0059] Fig. Figure 3 illustrates an application of the optoelectronic device connected to a corresponding control circuit. The control circuit 4.8, indicated by semiconductor material, is in contact with the optoelectronic components via the solder balls 4.4, 4.5, and 4.6, respectively. For this purpose, the control circuit 4.8, which has one or more metallization layers and dielectric layers 4.7 on its surface, is positioned with its solder ball layers 4.6 opposite the respective contact sections on the surface of the dielectric layer 4.2 of the optoelectronic device. Both chips are then soldered together.

[0060] Fig. Figure 4 illustrates an alternative embodiment of an optoelectronic device. This embodiment takes into account the fact that the LED semiconductor 1, including its conductive layer 3.1, may have a different grid spacing or crystal structure compared to the dielectric layer 4.1 or the substrate 4. Direct bonding of the LED semiconductor 1 and the silicon substrate 4 can lead to mechanical grid stresses at the respective interface and into the LED semiconductor 1. Such mechanical stress can increase the risk of detachment or failure of the contacts at the vias 4.3 and 4.3A. To reduce the mechanical stress, an additional compensation layer 4.9 can be arranged between the metallization 3.1 and the silicon substrate 4.

[0061] The Fig. Figures 5A to 5G illustrate various processing steps of a section of an optoelectronic device according to the proposed principle. Although the processing of only a single segment is shown, the described manufacturing steps can be performed on larger areas to provide different segments of an LED semiconductor 1.

[0062] In Fig. In step 5A, a support layer 1 is provided on which a semiconductor material 2 is deposited. The support layer 1 can comprise silicon, sapphire, or any other suitable material. One or more compensation layers can be arranged to compensate for any possible lattice difference and mechanical stresses between the semiconductor body 2 and the support layer 1. The semiconductor body 2 can comprise an undoped material but is often n-doped to reduce its resistivity. The material can be a III-V semiconductor compound, for example, GaN, AlGaN, GaAs, AlGaAs, GaP, or any other suitable III-V semiconductor compound. The same technology and processing steps can also be used with a IV semiconductor or a II-VI material. The semiconductor material is physically deposited, chemically deposited, or provided in any other suitable manner.Typical deposition techniques for these and other processing steps include CVD, MOCVD, MBE, and the like. An n-doped layer 2.1 is deposited on the surface of the body 2. Then, a p-doped layer 2.2 is deposited. Both layers can be deposited using one of the techniques mentioned above. Alternatively, ion implantation techniques can be used. In one embodiment, the semiconductor body 2 is already n-doped, so only a p-doped layer needs to be deposited on its surface. In this case, the interface between the p-doped layer 2.2 and the n-doped layer 2.1 forms the depletion zone, where the charge carriers combine by emitting radiation.

[0063] A current distribution layer 3.3 is then placed on layer 2.2. The current distribution layer 3.3 can comprise ITO or any other suitable material with a relatively low resistivity. The first dielectric layer 3.2 is deposited on the current distribution layer 3.3. Such a dielectric layer can, for example, comprise silicon oxide, silicon nitride, or another suitable material. The thickness of the dielectric layer can vary between a few hundred nanometers and 1 µm.

[0064] During operation of the electronic device, photons are generated at the pn junction between layers 2.2 and 2.1, with the first dielectric layer 3.2 also functioning as a mirror or reflective layer that reflects the photons back towards the semiconductor body 2. To facilitate and improve reflection, the first dielectric layer 3.2 can also comprise a layer arrangement, for example, including titanium oxide as a Bragg reflector. In this respect, several very thin layers of titanium oxide and titanium nitride can be arranged as a layer (in Fig. 5A not shown). Fig. Figure 5B illustrates a subsequent processing step. A photoresist is deposited on the first dielectric layer 3.2 and illuminated. The photoresist is removed in the illuminated areas, thereby exposing the surface of the dielectric layer, which is then etched until the current distribution layer 3.3 is reached to form the first contact recesses 3.21. As shown in Fig. As shown in Figure 5C, the recessed areas are then filled with a conductive material 3.22, for example, metal or the like. The remaining unilluminated photoresist with the conductive material on it is removed, leaving the filled recesses. The material 3.22 is filled into the recess to near the top surface of the electrical layer 3.2. Alternatively, some of the material can be removed, for example, during the photoresist removal process. As a result, the recess 3.2A forms a via but still includes a small depression compared to the top surface of the dielectric via 3.2, as shown in Figure 5C. Fig. 5C illustrates this. Such a small depression has the advantage that, in subsequent steps, particularly during the deposition of a metallization layer, these areas do not cause any protrusions or raised areas on the upper surface of the metallization layer. In other words, the remaining depression in the via 3.2A prevents a protrusion on the upper surface of the metallization layer deposited thereon.

[0065] After the photoresist is removed, another layer of photoresist is deposited and illuminated. The illuminated areas are removed, and second recesses 3.51 are etched through the dielectric layer 3.2, the current distribution layer 3.3, and the pn junction into the semiconductor body 2. These steps can also be performed together with some of the preceding steps.

[0066] Fig. Figure 5D shows the processing step in which the sidewalls of the recesses 3.51 are insulated, i.e., a dielectric layer 3.51 is formed on the sidewalls. The dielectric layer 3.51 can include silicon oxide. This prevents a short circuit into the active region of the semiconductor body 2.

[0067] In Fig. In step 5E, the photoresist is removed to form the via 3.5, and the via 3.51 is filled with a conductive material, for example, a metal. The conductive material is also deposited on the surface of the first dielectric layer, which forms the conductive layer 3.1. As illustrated, the metallization layer 3.1 is now in contact with the p-doped layer 2.2 of the semiconductor body 2 via the via 3.2A and with the n-doped layer 2.1 of the semiconductor body 2 via the previously formed via 3.5.

[0068] In a subsequent processing step, which takes place in Fig. As shown in Figure 5F, regions A and B are defined to contact the respective p-doped and n-doped layers within the semiconductor body. For this purpose, a photoresist is deposited on the conductive layer 3.1 and illuminated. After removing the illuminated photoresist areas, the conductive region 3.1 is etched in these areas down to the first dielectric layer 3.2. The resulting recess forms a closed space surrounding a region, thus defining region A of the conductive layer 3.1 as well as region B. The recess is filled with a dielectric material 3.4 to electrically isolate region A of the conductive layer from region B. Among other things, the Fig. 5E and Fig. The processing steps carried out in step 5F can cause an uneven and rough surface. For example, the conductive material may not grow uniformly on the surface of the dielectric layer 3.2. Therefore, the conductive layer 3.1 and the dielectric material in the insulating recess 3.4 are polished and removed, providing a flat and even surface that extends across several different segments of the LED semiconductor 1.

[0069] The dielectric material 3.4 in the recesses of the conductive layer 3.1, which defines regions A and B, completely surrounds the material within region A and insulates it from region B. A multitude of such insulating recesses therefore forms a multitude of individual regions A in contact with the p-doped layer and a single region B in contact with the n-doped layer. Depending on the specific application, regions A and B can have different sizes and / or shapes.

[0070] Fig. Figure 6 illustrates an alternative embodiment of the first electrical layer 3.2 and the conductive layer 3.1. Both layers are implemented as layered structures. The conductive layer 3.1 comprises several different layers of metal compounds to provide good adhesion to the first dielectric layer, sufficient current distribution, and good contact on the top surface for direct bonding. Layer 3.11 comprises ITO, which exhibits good adhesion to the silicon oxide of the first dielectric layer. Layers 3.12 and 3.13 include a metal compound, for example, Al, Au, Cu, or Ag, to achieve sufficient current distribution. Titanium or a similar material can be used on the surface for direct bonding. Likewise, the first dielectric layer can comprise various individual layers.

[0071] While 3.35 can comprise silicon oxide, the layer structure 3.24 can function as a Bragg reflector using Al2O3, SiN, SiO2 or TiO2.

[0072] Fig. Figure 7 shows a top view of an optoelectronic device and, in particular, an LED semiconductor 1, to illustrate the segmentation of the various recesses filled with dielectric material. The “center” of Fig. Figure 7 includes the via 4.3A, which is in contact with the p-doped layer of the optoelectronic device. The via 4.3A is displaced relative to the via 3.2A, which is located in the first dielectric layer. The conductive layer 3.1 is connected to the p-doped portion of the pn junction through the first dielectric layer. Therefore, charge carriers flow through the via 4.3A and then through the conductive layer, distributing the current over the entire rectangular shape of the via 3.2A. Consequently, the current density is reduced by the relatively small via 4.3A, the conductive material 3.1, and the first via 3.2A to the p-doped semiconductor layer.

[0073] To prevent a short circuit between the different polarities, the conductive material 3.1 includes insulating recesses 3.4 surrounding the via 4.3A and the rectangular via 3.2A, thus forming region A of the conductive layer 3.1. The dielectric material of the insulating recesses 3.4 also insulates region A from region B in the conductive layer. Region B in the conductive layer connects the n-doped layer 2.1 of the LED semiconductor 1 to contact 4.3 via the via 3.5. As shown, contact 3.5 is also designed as a recess with a surrounding shape to achieve segmentation. The p-doped layer must be segmented in a similar manner to prevent current from flowing in the p-doped layer of one segment to the p-doped layer of another segment. This segmentation provides a multitude of vias 4.3A with respective segmented p-doped sections in the LED semiconductor 1. A single n-contact can be sufficient to connect all n-doped sections of the junction. Thus, for segmenting X of an optoelectronic device according to the proposed principle, X contacts for the p-region and a single contact for the n-region may be required.

[0074] The segmentation according to Fig. 7 can be different and adapted to the respective application needs and requirements of the optoelectronic component. Fig. Figure 8 shows another exemplary embodiment with differently shaped structures. The vias 4.3 and 4.3A are structured with rectangular shapes. Depending on the required current distribution, the first via 3.2A is structured with a hexagonal shape. As in the embodiment of Fig. 7 surrounds the first via 3.2A and the via 4.3A to improve current distribution. The via 4.3A is offset relative to the via 3.2A and does not overlap it, thus reducing the risk of the via detachment. The insulating recess 3.4 separates and segments the conductive layer 3.1.

[0075] The Fig. 9A and Fig. Figure 9B illustrates parts of an optoelectronic device according to some aspects of the present invention. The semiconductor body 2 is structured and roughened on the surface opposite a virtual extension of region A, i.e., the light emission region. Therefore, light generated by the recombination of electrons and holes in the pn junction adjacent to region A is coupled out of the semiconductor body 2 via the roughened surface. Adjacent to the roughened surface, the dielectric layer 3.28, which itself has a flat surface, is deposited. Direct or metal bonding is carried out to form the material 5.1 on the dielectric layer 3.28. Alternatively, and as shown, for example, in Fig.As shown in Figure 9B, the dielectric layer 3.28 can be deposited over the entire span and structured or roughened in the region relative to a virtual extension of region A. This can further improve the optical performance, as the difference in refractive index between the material and the air can be further reduced. Furthermore, the structuring process can be simplified because material 5.1 can act as a natural barrier. List of reference symbols 1 LED semiconductor 2 Semiconductor bodies 2.1 n-doped region 2.2 p-doped region 3.1 Conductive layer 3.2 First dielectric layer 3.2A First via 3.3 Power distribution layer 3.4 Insulating recess 3.5 Second via 3.8 Insulating recess 3.9 Filling material 3.21 First contact recess 3.22 Conductive material 3.28 Structuring 3.51 Dielectric layer 3.52 Conductive material 4 carriers 4.1 Dielectric layer 4.2 Dielectric layer 4.3 Through-hole plating 4.3A Through-hole plating 4.4 First metal survey 4.5 Solder ball 4.6 Solder ball 4.7 Dielectric Layers 4.8 Control circuit 4.31 Dielectric layer 4.32 Leading Layer 4.35 Conductive material 5.1 Structures

Claims

Optoelectronic device comprising: - a semiconductor body (2, 2.1, 2.2) having a sequence of layers (2.1, 2.2, 3.3) with an active region provided for generating radiation; - a first dielectric layer (3.2) arranged on the sequence of layers (2.1, 2.2) having a plurality of first regions and a second region; - a first via (3.2A) in each region of the plurality of first regions for contacting a first side of the active region; - a second via (3.5) in the second region for contacting a second side of the active region; - a conductive layer (3.1) comprising a plurality of first regions and a second region surrounding the plurality of first regions and electrically insulated from the plurality of first regions, wherein the conductive layer (3.1) has a substantially planar surface and is arranged in a planar fashion on the plurality of first regions and the second region, such that each of the plurality of first regions of the conductive layer is in contact with the first via (3.2A) in the respective region of the plurality of first regions and the second region of the conductive layer is in contact with the second via (3.5) of the first dielectric layer (3.2), wherein a conductive material (3.22) is recessed in the first via (3.2A) such that the conductive layer (3.1) extends partially into the via (3.2). Optoelectronic device according to claim 1, further comprising: - a second dielectric layer (4, 4.1, 4.2) which is arranged flat on the conductive layer (3.1) and comprises a plurality of third vias (4.3A), - wherein each via (4.3A) of the plurality of third vias (4.3A) is in contact with a corresponding first region of the conductive layer (3.1) such that each via (4.3A) is displaced with respect to a virtual extension of the first via (3.2A) in each region of the plurality of first regions. Optoelectronic device according to claim 2, further comprising: - a fourth via (4.3) in the second dielectric layer (4, 4.1, 4.2) which is in contact with the second region of the conductive layer (3.1) such that the fourth via (4.3) is displaced with respect to a virtual extension of the second via (3.5) in the second region. Optoelectronic component according to one of claims 2 to 3, wherein the second dielectric layer (4.1, 4) comprises at least one of the following: - a body layer (4); - a dielectric connecting layer (4.1) between the conductive layer and the body layer (4); - a dielectric surface layer (4.2) opposite the conductive layer. Optoelectronic component according to one of claims 2 to 4, further comprising one or more solder layer spheres (4.4, 4.5, 4.6) arranged on each of the plurality of first vias (4.3A) and / or on the second via (4.3) and extending at least partially onto the second dielectric layer (4, 4.1, 4.2). Optoelectronic component according to one of claims 2 to 5, wherein the plurality of third vias (4.3A) and the fourth via (4.3) in the second dielectric layer (4, 4.1, 4.2) comprise a dielectric layer (4.31) arranged on its side wall and optionally a conductive layer (4.32) on the dielectric layer (4.31), wherein the conductive layer (4.32) is in contact with the conductive layer (3.1). Optoelectronic component according to one of claims 1 to 6, wherein the conductive material (3.22) in the first via differs from the material of the conductive layer (3.1). Optoelectronic component according to any one of claims 1 to 7, wherein the first via (3.2A) in each region of the plurality of first regions and / or the second via (3.5) comprises at least one of: - a closed shape; - a rectangular shape; - a rhombus shape; - a parallelogram shape; - a hexagon or another convex polygon shape. Optoelectronic component according to one of claims 1 to 8, wherein the conductive layer (3.1) comprises a dielectric region (3.4) which electrically insulates the first regions and the second region and extends from the first dielectric layer (3.2) to the upper surface of the conductive layer (3.1). Optoelectronic component according to one of claims 1 to 9, wherein the second via (3.5) extends through the layer sequence (2.1, 2.2) with the active region in the second region and comprises a dielectric layer arranged on its side wall. Optoelectronic component according to one of claims 1 to 10, wherein the layer sequence (2.1, 2.2, 3.3) comprises a current distribution layer (3.3) which is in contact with the first via (3.2A) of each of the plurality of first regions. Optoelectronic component according to one of claims 1 to 11, comprising a layer (4.9) for reducing mechanical stresses, which is arranged between the conduction layer (3.1) and the second dielectric layer (4, 4.1, 4.2). Optoelectronic component according to one of claims 1 to 12, further comprising a structuring (3.28) on an emission surface of the semiconductor body (2), wherein the structuring (3.28) is arranged at least over a virtual extension from the plurality of first regions towards the surface of the semiconductor body (2), wherein the structuring preferably has a substantially flat surface. Optoelectronic device according to one of claims 1 to 13, further comprising one or more structures on the surface of the semiconductor body (2) and / or the structuring (3.28), which are preferably made of silicon and arranged over a virtual extension of the second region to prevent optical interference between adjacent first regions. Optoelectronic component according to one of claims 1 to 14, comprising a filler material (3,9) in areas of the conductive layer (3.1) above the second via (3.5), such that the conductive layer (3.1) forms a planar and substantially flat surface with the filler material. Method for obtaining an optoelectronic device, comprising: - providing a semiconductor body (2, 2.1, 2.2) having a sequence of layers (2.1, 2.2, 3.3) with an active region provided for generating radiation; - depositing a first dielectric layer (3.2) on the sequence of layers (2.1, 2.2) having a plurality of first regions and a second region; - providing a first via (3.2A) in each region of the plurality of first regions for contacting a first side of the active region; - providing a second via (3.5) in the second region for contacting a second side of the active region; - depositing a conductive layer (3.1) having a substantially planar surface and arranged flat on the plurality of first and second regions of the first dielectric layer, wherein the conductive layer comprises a plurality of first regions and a second region surrounding the plurality of first regions and electrically insulated from the plurality of first regions, such that each of the plurality of first regions of the conductive layer is in contact with the first via (3.2A) in the respective region of the plurality of first regions and the second region of the conductive layer is in contact with the second via (3.5) of the first dielectric layer (3.2); wherein providing a first via (3.2A) in each area comprises: - Etching the first contact recess in the first dielectric layer until the active region is reached; - Deposition of a conductive material, preferably comprising a metal, within the etched first contact recess, leaving a depression between an upper surface of the conductive material and an upper surface of the first dielectric layer. Method according to claim 16, wherein the conductive material (3.22) in the first via differs from the material of the conductive layer (3.1). Method according to one of claims 16 to 17, wherein the layer sequence (2.1, 2.2, 3.3) comprises a current distribution layer (3.3) which is in contact with the first via (3.2A) of each of the plurality of first regions. A method according to any one of claims 16 to 17, wherein the deposition of the conductive layer (3.1) comprises: - etching a recess into the conductive area to form a first region, thereby electrically isolating the first region from a surrounding second region of the conductive layer (3.1); - filling the recess with a dielectric material. A method according to any one of claims 16 to 19, wherein providing a second via (3.5) comprises: - etching a second recess in the second region extending through the layer sequence (2.1, 2.2) with the active region; - depositing a dielectric layer arranged on its side wall; - filling the second recess with a conductive material, preferably comprising a metal, to form the second via. Method according to claim 20, comprising: - filling with a material (3,9) in areas of the conductive layer (3.1) above the second via (3.5) such that the conductive layer (3.1) forms a flat and substantially planar surface with the filler material. Method according to any one of claims 16 to 20; further comprising: - depositing a second dielectric layer (4, 4.1, 4.2) arranged on the conductive layer (3.1); - depositing a plurality of third vias (4.3A), wherein each via (4.3A) of the plurality of third vias (4.3A) is in contact with a corresponding first region of the conductive layer (3.1) such that each via (4.3A) is displaced with respect to a virtual extension of the first via (3.2A) in each region of the plurality of first regions. Method according to claim 22, wherein the deposition of a second dielectric layer comprises: depositing a layer (4.9) for reducing mechanical stresses, which is arranged between the conduction layer (3.1) and the second dielectric layer (4, 4.1, 4.2). Method according to one of claims 22 to 23, wherein the deposition of a plurality of first vias comprises: - etching a plurality of recesses in the second dielectric layer up to the first region; - depositing a dielectric layer on the sidewalls of the plurality of recesses; - filling the plurality of recesses with a conductive material to form the plurality of third vias (4.3A). The method according to claims 22 to 24, further comprising: - etching at least one second recess in the second dielectric layer (4, 4.1, 4.2) to the second region of the conductive layer (3.1) such that at least one fourth via (4.3) is displaced in the second region with respect to a virtual extension of the second via (3.5); - depositing a dielectric layer (4.31) on its side wall; - filling the at least one second recess with a conductive material to form at least one fourth via (4.3) in the second dielectric layer (4, 4.1, 4.2). Method according to any one of claims 22 to 25, wherein the deposition of a second dielectric layer (4.1, 4) comprises at least one of the following: - deposition of a body layer (4); - deposition of a dielectric connecting layer (4.1) between the conductive layer and the body layer (4); - deposition of a dielectric surface layer (4.2) opposite the conductive layer. Method according to any one of claims 22 to 26, further comprising: - depositing one or more solder layer spheres (4.4, 4.5, 4.6) arranged on each of the plurality of third vias (4.3A) and / or on the fourth via (4.3) and extending at least partially onto the second dielectric layer (4, 4.1, 4.2). Method according to any one of claims 17 to 27, wherein the first via (3.2A) in each region of the plurality of first regions and / or the second via (3.5) comprises at least one of: - a closed shape; - a rectangular shape; - a rhombus shape; - a parallelogram shape; - a hexagon or another convex polygon shape. Method according to one of claims 16 to 28, wherein the layer sequence (2.1, 2.2, 3.3) comprises a current distribution layer (3.3) which is in contact with the first via (3.2A) of each of the plurality of first regions. Method according to any one of claims 16 to 29, further comprising: - structuring a surface of the semiconductor body (2) relative to the first dielectric layer (3.2) at least over a virtual extension from the plurality of first regions towards the surface of the semiconductor body (2); - depositing a dielectric layer having a rough or non-flat surface over the virtual extension from the plurality of first regions towards the surface of the semiconductor body (2). Method according to any one of claims 16 to 20, further comprising: - structuring a surface of the semiconductor body (2) relative to the first dielectric layer (3.2) at least via a virtual extension from the plurality of first regions towards the surface of the semiconductor body (2); - depositing a dielectric layer adjacent to a virtual extension from the plurality of first regions towards the surface of the semiconductor body, wherein the dielectric layer has a substantially flat surface. Method according to any one of claims 16 to 30, further comprising: - providing one or more structures on the surface of the semiconductor body (2), which are preferably made of silicon and arranged over a virtual extension of the second region to prevent optical interference between adjacent first regions.

Images