METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT AND A SEMICONDUCTOR COMPONENT

Abstract

A method of manufacturing a semiconductor device comprising the following steps: Producing a dummy gate structure (DG) over a channel region of a semiconductor layer (20,22); forming a source / drain epitaxial layer (60) on opposite sides of the dummy gate structure (DG); performing a planarization process on the source / drain epitaxial layer (60); Structuring the planarized source / drain epitaxial layer (60); Removing the dummy gate structure (DG) to create a gate gap (45); and Forming a metal gate structure in the gate gap (45), wherein the source / drain epitaxial layer (60) is formed to completely cover the dummy gate structure (DG).

Description

Background of the invention

[0001] Conventional complementary metal oxide semiconductor (CMOS) technology is often implemented to manufacture a large number of semiconductor devices, such as metal oxide semiconductor field-effect transistors (MOSFETs) and bipolar transistors (BJTs), at approximately the same level on a single integrated circuit (IC) chip. Modern IC chips have transistors arranged on multiple layers.

[0002] US 2014 / 0 154 846 A1 discloses a method for manufacturing a semiconductor device. A dummy gate structure is applied to a substrate with an SOI layer. A source / drain epitaxial layer is applied to the side of the dummy gate structure. After removing the dummy gate structure and inserting a replacement metal gate structure into the resulting empty space, an electrical layer is applied, and the resulting surface is planarized.

[0003] Furthermore, reference is made to publication KR 10 2012 0 047 032 A. Short description of the drawings

[0004] The present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale and are for illustrative purposes only. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 shows a sectional view of a FET semiconductor device according to an embodiment of the present invention. Fig. 2 shows a sectional view of a FET semiconductor device according to another embodiment of the present invention. Fig. 3 shows a sectional view of a FET semiconductor device according to another embodiment of the present invention. The Fig. 4A and Fig. 4B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 5A and Fig. 5B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 6A and Fig. 6B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 7A and Fig. 7B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 8A and Fig. 8B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 9A and Fig. 9B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 10A and Fig. 10B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 11A and Fig. 11B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 12A and Fig. 12B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 13A and Fig. 13B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 14A and Fig. 14B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 15A and Fig. 15B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. The Fig. 16A and Fig. 16B illustrate one of several stages of fabricating a FET semiconductor device according to an embodiment of the present invention. Fig. 17 shows a sectional view of a FET semiconductor device according to an embodiment of the present invention. Detailed description

[0005] It should be understood that the following description provides many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the specified range or values, but may depend on process conditions and / or desired device properties.Furthermore, the fabrication of a first element over or on a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Various elements may be drawn at different scales for convenience and clarity.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, the term "made of" can mean either "comprises" or "consists of."In the present invention, the phrase "an element selected from the group A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C) and does not mean an element of A, an element of B and an element of C unless otherwise specified.

[0007] In a transistor manufacturing process in the back end of line (BEOL), a source / drain epitaxial layer must be selectively grown. However, the method for selectively growing a source / drain epitaxial layer may not be suitable for a BEOL process due to limitations in the thermal budget, for example, lower than 450 °C. Introducing dopants into the source / drain epitaxial layer at high levels often results in selective epitaxial growth becoming non-selective. While HCl gas can help restore selectivity, it can also reduce doping efficiency and growth rate. For nm-scale structures, especially when using Ge or SiGe, a low thermal budget is required. However, selective epitaxial growth at a low temperature (<500 °C) for Si:P is generally problematic.While selective epitaxial growth at low temperatures (<500 °C) for Ge:P is possible, Ge:P is only selective for a high-density oxide. Selectivity is also a problem for nitride or PVD oxide. Furthermore, replacement gate (RPG) technology generally requires a contact opening mask to contact the source and drain (S / D) after the replacement gate process.

[0008] The present invention provides a new replacement gate (RPG) technology with one (1) less mask (no contact opening mask is required) and a non-selective source / drain (S / D) epitaxial process.

[0009] In the following embodiments, materials, configurations, dimensions, and / or processes of one embodiment may be used in another embodiment unless otherwise noted, and therefore, detailed explanation thereof may be omitted.

[0010] Fig. 1 shows a cross-sectional view of a FET semiconductor device according to an embodiment of the present invention. In some embodiments, a semiconductor device includes: a semiconductor layer 20 having a channel region, a source region, and a drain region formed over or as part of a semiconductor layer 10; a gate dielectric layer 82, such as a high-k dielectric material, disposed over the channel region of semiconductor layer 20; a metallic gate electrode layer 85 disposed over gate dielectric layer 82; first gate sidewall spacers 46 disposed on opposite side surfaces of gate electrode layer 85; and a source / drain epitaxial layer 60 disposed over the source and drain regions of semiconductor layer 20.In some embodiments, the semiconductor layer 20 is a crystalline semiconductor, such as Si, SiGe, Ge, or a III-V semiconductor.

[0011] In some embodiments, a height difference between a top portion of the epitaxial layer 60 and a top portion of the gate electrode layer 85 is less than 5 nm (±5 nm). In other embodiments, the height difference is less than 2 nm. In certain embodiments, the height difference is zero (both portions are flush with each other).

[0012] In some embodiments, the source / drain epitaxial layer 60 extends laterally beyond the source and drain regions of the semiconductor layer 20 and is disposed on a dielectric layer 30. In some embodiments, the dielectric layer 30 is a dielectric isolation layer, such as shallow trench isolation (STI). In some embodiments, the source / drain epitaxial layer 60 comprises SiP and / or SiCP. In other embodiments, the source / drain epitaxial layer 60 comprises SiGe and / or Ge. In some embodiments, a height difference between an uppermost portion of the first gate sidewall spacers 46 and the uppermost portion of the source / drain epitaxial layer 60 or the uppermost portion of the gate electrode layer 85 is less than 5 nm.In some embodiments, a height difference between a top portion of second gate sidewall spacers 48 and the top portion of source / drain epitaxial layer 60 or the top portion of gate electrode layer 85 is less than 5 nm. As shown in FIG. Fig. 1, a first ILD layer 50 (ILD: interlayer dielectric) is disposed on the gate structure side, and a second ILD layer 70 is disposed over the first ILD layer 50. A source / drain contact 80 is disposed over the source / drain epitaxial layer 60 and passes through the second ILD layer 70.

[0013] Fig. 2 shows a sectional view of a FET semiconductor device according to another embodiment of the present invention.

[0014] In some embodiments, a semiconductor device includes: a semiconductor layer 20 having a channel region, a source region, and a drain region formed over or as part of a semiconductor layer 10; a gate dielectric layer 82, such as a high-k dielectric material, disposed over the channel region of the semiconductor layer 20; a metallic gate electrode layer 85 disposed over the gate dielectric layer 82; first gate sidewall spacers 46 disposed on opposite side surfaces of the gate electrode layer 85; second gate sidewall spacers 48 disposed between the first gate sidewall spacers 46 and the gate electrode layer 85; and a source / drain epitaxial layer 60 disposed over the source and drain regions of the semiconductor layer 20.In some embodiments, the semiconductor layer 20 is a crystalline semiconductor, such as Si, SiGe, Ge, or a III-V semiconductor.

[0015] In some embodiments, a height difference between a top portion of the epitaxial layer 60 and a top portion of the gate electrode layer 85 is less than 5 nm (±5 nm). In other embodiments, the height difference is less than 2 nm. In certain embodiments, the height difference is zero (both portions are flush with each other). In some embodiments, a ratio H1 / H2 of a height H1 of the top portion of the epitaxial layer 60 to a height H2 of the top portion of the gate electrode layer 85, measured from the top surface of the semiconductor layer 20 or 22, is about 0.90 to 1.10, and in other embodiments, it is about 0.95 to 1.05.

[0016] In some embodiments, the source / drain epitaxial layer 60 extends laterally beyond the source and drain regions of the semiconductor layer 20 and is disposed on a dielectric layer 30. In some embodiments, the dielectric layer 30 is a dielectric isolation layer, such as shallow trench isolation (STI). In some embodiments, the source / drain epitaxial layer 60 comprises SiP and / or SiCP. In other embodiments, the source / drain epitaxial layer 60 comprises SiGe and / or Ge. In some embodiments, a height difference between an uppermost portion of the first gate sidewall spacers 46 and the uppermost portion of the source / drain epitaxial layer 60 or the uppermost portion of the gate electrode layer 85 is less than 5 nm.In some embodiments, a height difference between a top portion of the second gate sidewall spacers 48 and the top portion of the source / drain epitaxial layer 60 or the top portion of the gate electrode layer 85 is less than 5 nm. As shown in FIG. Fig. 2, a first ILD layer 50 (ILD: interlayer dielectric) is disposed on the gate structure side, and a second ILD layer 70 is disposed over the first ILD layer 50. A source / drain contact 80 is disposed over the source / drain epitaxial layer 60 and passes through the second ILD layer 70.

[0017] In this embodiment, the gate sidewall spacers include first gate sidewall spacers 46 and second gate sidewall spacers 48, which are arranged closer to the gate electrode 85 than the first gate sidewall spacers 46. A curved surface of the first gate sidewall spacers 46 faces the source / drain epitaxial layer 60, and a curved surface of the second gate sidewall spacers 48 faces the gate electrode layer 85. In some embodiments, the curved surface of the second gate sidewall spacers 48 is in contact with the gate dielectric layer 82.

[0018] In some embodiments, a portion of a dummy gate dielectric layer (in the Fig. 1 to 3) is disposed between the first gate sidewall spacers 46 and the semiconductor layer 20. In some embodiments, no portion of the dummy gate dielectric layer is disposed between the second gate sidewall spacers 48 and the semiconductor layer 20.

[0019] Fig. 3 shows a cross-sectional view of a FET semiconductor device according to another embodiment of the present invention. In this embodiment, a semiconductor layer 22 for the channel region and the source / drain regions is disposed on an insulating layer 32. In some embodiments, the insulating layer 32 is an insulating layer (e.g., a silicon oxide layer) of a silicon-on-insulator (SOI) wafer, and in other embodiments, the insulating layer 32 is an interlayer dielectric layer disposed over underlying devices, such as transistors. In some embodiments, the semiconductor layer 22 is a crystalline semiconductor, such as Si, SiGe, Ge, or a III-V semiconductor. In some embodiments, sidewalls 46' are formed on side surfaces of the semiconductor layer 22.

[0020] In some embodiments, a semiconductor device includes: a semiconductor layer 22 having a channel region, a source region, and a drain region formed over an insulating layer 35; a gate dielectric layer 82, such as a high-k dielectric material, disposed over the channel region of the semiconductor layer 22; a metallic gate electrode layer 85 disposed over the gate dielectric layer 82; first gate sidewall spacers 46 disposed on opposite side surfaces of the gate electrode layer 85; second gate sidewall spacers 48 disposed between the first gate sidewall spacers 46 and the gate electrode layer 85; and a source / drain epitaxial layer 60 disposed over the source and drain regions of the semiconductor layer 22.

[0021] In some embodiments, a height difference between a top portion of the epitaxial layer 60 and a top portion of the gate electrode layer 85 is less than 5 nm (±5 nm). In other embodiments, the height difference is less than 2 nm. In certain embodiments, the height difference is zero (both portions are flush with each other).

[0022] In some embodiments, the source / drain epitaxial layer 60 extends laterally beyond the source and drain regions of the semiconductor layer 22 and is disposed on an insulating layer 32. In some embodiments, the source / drain epitaxial layer 60 comprises SiP and / or SiCP. In other embodiments, the source / drain epitaxial layer 60 comprises SiGe and / or Ge. In some embodiments, a height difference between a top portion of the first gate sidewall spacers 46 and the top portion of the source / drain epitaxial layer 60 or the top portion of the gate electrode layer 85 is less than 5 nm. In some embodiments, a height difference between a top portion of the second gate sidewall spacers 48 and the top portion of the source / drain epitaxial layer 60 or the top portion of the gate electrode layer 85 is less than 5 nm. As in Fig. 1, a first ILD layer 50 is disposed on the gate structure side, and a second ILD layer 70 is disposed over the first ILD layer 50. A source / drain contact 80 is disposed over the source / drain epitaxial layer 60 and extends through the second ILD layer 70.

[0023] In this embodiment, the gate sidewall spacers include first gate sidewall spacers 46 and second gate sidewall spacers 48, which are arranged closer to the gate electrode 85 than the first gate sidewall spacers 46. A curved surface of the first gate sidewall spacers 46 faces the source / drain epitaxial layer 60, and a curved surface of the second gate sidewall spacers 48 faces the gate electrode layer 85. In some embodiments, the curved surface of the second gate sidewall spacers 48 is in contact with the gate dielectric layer 82.

[0024] In some embodiments, a portion of a dummy gate dielectric layer (in the Fig. 1 to 3) is disposed between the first gate sidewall spacers 46 and the semiconductor layer 22. In some embodiments, no portion of the dummy gate dielectric layer is disposed between the second gate sidewall spacers 48 and the semiconductor layer 22.

[0025] In some embodiments, the source / drain epitaxial layer 60 is disposed laterally beyond the source and drain regions of the semiconductor layer 22 and on top of the insulating layer 32.

[0026] Furthermore, in some embodiments, one or more dummy gate structures DG are arranged above the substrate 10. In some embodiments, the dummy gate DG has substantially the same structure as a gate structure for a functional transistor, and is arranged not on a semiconductor layer but on the insulating layer 35. No source / drain epitaxial layer is arranged on the sides of the dummy gate structure DG.

[0027] In some embodiments, the aforementioned height difference is not zero, and the source / drain epitaxial layer 60 is at least 0.5 nm higher or lower than the other features.

[0028] The Fig. 4A to 16B show various stages of fabricating a FET semiconductor device according to an embodiment of the present invention. It is clear that further steps may be performed before, during, and after the steps shown in the Fig. 4A to 16B, and some of the steps described below may be replaced or omitted in further embodiments of the method. The order of the steps / processes is interchangeable. Furthermore, in the present invention, a source and a drain are used interchangeably, and "a source / a drain" refers to a source and / or a drain. Fig. 4A to 16B, figures with the letter A are perspective views, and figures with the letter B are sectional views corresponding to a line A - A' of Fig. 4A.

[0029] As in the Fig. 4A and Fig. 4B, a substrate 10 is provided. In some embodiments, the substrate 10 is a silicon-on-insulator (SOI) substrate. In other embodiments, the substrate 10 includes a single-crystal semiconductor layer at least on its surface portion. The substrate 10 may be a single-crystal semiconductor material, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 10 is made of crystalline Si, SiGe, or Ge. The substrate 10, in some embodiments, may include one or more buffer layers (not shown) in its surface region. The buffer layers may serve to gradually change the lattice constant from that of the substrate to that of the source / drain regions.The buffer layers may be composed of epitaxially grown single-crystal semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a specific embodiment, the substrate 10 comprises silicon germanium (SiGe) buffer layers epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layers may increase from 30 atomic percent germanium for the bottom polymer layer to 70 atomic percent germanium for the top polymer layer.

[0030] As also in the Fig. 4A and Fig. 4B, an insulating layer 35 is disposed over the substrate 10, and a semiconductor layer 22 is disposed over the insulating layer 35. When an SOI substrate is used, the semiconductor layer 22 is a silicon layer, and the insulating layer 35 is the insulating layer of the SOI substrate. In some embodiments, the semiconductor layer 22 is formed by recrystallizing an amorphous semiconductor layer or a polycrystalline semiconductor layer formed on the insulating layer 35. In some embodiments, the semiconductor layer 22 is a crystalline semiconductor, such as Si, SiGe, Ge, or a III-V semiconductor. In some embodiments, the thickness of the semiconductor layer 22 is about 10 nm to about 10 μm.

[0031] As in the Fig. 5A and Fig. As shown in Figure 5B, the semiconductor layer 22 is patterned to form an active layer (channel and source / drain regions).

[0032] Then, dummy gate structures are fabricated for a gate replacement process, as shown in the Fig. 6A and Fig. 6B. In some embodiments, the dummy gate structures include a dummy gate dielectric layer (not shown), such as silicon oxide, and a dummy gate electrode layer 40. In some embodiments, the dummy gate electrode layer 40 is polycrystalline or amorphous SiGe or Ge. In certain embodiments, the dummy gate electrode layer 40 is amorphous or polycrystalline Ge. The dummy gate electrode layer 40 is formed by chemical vapor deposition (CVD) or another suitable layer formation technique. In some embodiments, CVD is performed at a temperature of 450°C or less. In some embodiments, the temperature is greater than 200°C.

[0033] Additionally, a hard mask layer 42 is formed over the dummy gate electrode layer 40. In some embodiments, the hard mask layer 42 is made of a silicon nitride-based material, such as silicon nitride, SiON, or SiCN. After its formation, the hard mask layer 42 is patterned using one or more lithographic and etching processes. Then, using the patterned hard mask layer 42 as an etch mask, the deposited dummy gate electrode layer 40 is patterned. In some embodiments, one or more dummy gate structures DG are formed to enclose the dummy gate structure for a functional transistor to suppress process variations and / or to improve the shape fidelity of the structure.

[0034] In some embodiments, the dummy gate electrode 40 for a functional transistor includes a gate portion disposed above the semiconductor layer 22 and a pad portion disposed above the insulating layer 35 for a gate contact. A distal end of the dummy gate electrode 40 is disposed on the insulating layer 35. The dummy gate structures DG are formed on a dielectric layer. In some embodiments, the thickness of the dummy gate electrode 40 is about 20 nm to about 500 nm, and in other embodiments, it is about 50 nm to about 200 nm. In some embodiments, the thickness of the hard mask layer 42 is about 20 nm to about 100 nm.

[0035] As in the Fig. 7A and Fig. 7B, first sidewall spacers 46 are then formed on side surfaces of the dummy gate electrode 40. A protective layer of an insulating material for the first sidewall spacers is conformally formed by CVD or other suitable methods. The protective layer is conformally deposited and thereby formed to have substantially uniform thicknesses on vertical surfaces, such as the sidewalls, on horizontal surfaces, and on the top surface of the dummy gate structure. In some embodiments, the protective layer is deposited to a thickness of about 2 nm to about 30 nm. In one embodiment, the insulating material of the protective layer is different from the materials of the dummy gate structure and is formed of a silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, or combinations thereof. In some embodiments, the protective layer is formed of silicon nitride.The sidewall spacers are fabricated by anisotropic etching on opposite side surfaces of the dummy gate structure. As also shown in the . Fig. 7A and Fig. As shown in Fig. 7B, the sidewalls 46' are formed on side surfaces of the semiconductor layer 22, and further, sidewall spacers are formed on the dummy gate structures DG.

[0036] As in the Fig. 8A and Fig. 8B, a source / drain epitaxial layer 60 is then formed. The source / drain epitaxial layer 60 comprises one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET, or SiGe and Ge for a p-channel FET. For the p-channel FET, boron (B) may also be used in the source / drain region. The source / drain epitaxial layer 60 is formed by epitaxial growth using CVD, ALD (atomic layer deposition), or MBE (molecular beam epitaxy) at a temperature of less than 500°C in some embodiments. In other embodiments, the temperature is from about 250°C to about 450°C, and in certain embodiments, it is from about 250°C to about 350°C. In some embodiments, the source / drain epitaxial layer 60 is non-selectively formed not only over the source / drain regions of the semiconductor layer 22, but also over the insulating layer 35.In some embodiments, prior to forming the source / drain epitaxial layer 60, the source / drain region of the semiconductor layer 22 is recessed, and the source / drain epitaxial layer 60 is formed over the recessed source / drain region. In some embodiments, the source / drain epitaxial layer 60 is formed such that its top surface is located above the dummy gate structure including the dummy gate electrode 40 and the hard mask layer 42. According to the invention, the source / drain epitaxial layer 60 is formed such that it completely covers the dummy gate structure.

[0037] As in the Fig. 9A and Fig. 9B, a planarization process, such as chemical mechanical polishing (CMP), is then performed to planarize the source / drain epitaxial layer 60. In some embodiments, the CMP process is performed to expose the hard mask layer 42.

[0038] As in the Fig. 10A and Fig. 10B, the planarized source / drain epitaxial layer 60 is then patterned using one or more lithographic and etch processes to substantially remain over the source / drain regions of the semiconductor layer 22.

[0039] In some embodiments, the source / drain epitaxial layer 60 includes a crystalline portion formed over the source / drain region of the semiconductor layer 22 and a non-crystalline portion formed over the insulating layer 35. In some embodiments, the non-crystalline portion of the planarized source / drain epitaxial layer 60 can be selectively removed with a wet and / or dry etch without using a lithographic process (no mask / resist pattern). In some embodiments, a mixture of hydrated ammonia and hydrogen peroxide (APM) is used as a wet etchant.

[0040] Then, a first ILD layer 50 (ILD: interlayer dielectric) is formed over the source / drain epitaxial layer 60 and the dummy gate structure, as shown in the Fig. 11A and Fig. 11B. The materials for the first ILD layer 50 may be compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, may also be used for the first ILD layer 50. After the first ILD layer 50 has been formed, a planarization process, such as CMP, is performed to expose the upper portions of the source / drain epitaxial layer 60 and the dummy gate electrode layer 40, as shown in FIGS. Fig. 12A and Fig. 12B. In some embodiments, the source / drain epitaxial layer 60 and / or the dummy gate electrode layer 40 function as a CMP stop layer. In some embodiments, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed prior to the formation of the first ILD layer 50.

[0041] Then, the dummy gate electrode layer 40 and the dummy gate dielectric layer are removed to form a gate gap 45, as shown in the Fig. 13A and Fig. 13B. The dummy gate structure may be removed by plasma dry etching and / or wet etching. In some embodiments, a mixture of hydrated ammonia and hydrogen peroxide (APM) is used as a wet etchant when the dummy gate electrode layer 40 is made of polycrystalline or amorphous Ge. In some embodiments, a tetramethylammonium hydroxide (TMAH) solution is used as a wet etchant when the dummy gate electrode layer 40 is made of polycrystalline amorphous Si. The dummy gate dielectric layer is also removed using a suitable wet or dry etch.

[0042] After the dummy gate structure has been removed, in some embodiments, second sidewall spacers 48 are optionally formed on the first gate sidewall spacers 46 in the gate gap 45, as shown in FIGS. Fig. 14A and Fig. 14B. The dielectric material for the second gate sidewall spacers 48 may be the same as or different from that for the first gate sidewall spacers 46. By forming the second gate sidewall spacers 48, the width of the gate gap 45 is reduced, and a gate length of a metal gate electrode to be formed later can also be reduced.

[0043] As in the Fig. 15A and Fig. 15B, a gate dielectric layer 82 and a gate electrode 85 are then formed in the gate gap 45. In some embodiments, the gate dielectric layer 82 comprises one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials are HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titania, hafnium oxide-alumina alloy (HfO2-Al2O3 alloy), other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interfacial layer formed by chemical oxidation between a channel layer and the dielectric material. The gate dielectric layer 82 may be formed by CVD, ALD, or other suitable method. In one embodiment, the gate dielectric layer 82 is formed using a highly conformal deposition process, such as ALD, to ensure a gate dielectric layer with a consistent thickness around each channel layer. The thickness of the gate dielectric layer 82, in one embodiment, is about 1 nm to about 10 nm.

[0044] The gate electrode layer 85 comprises one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal lines, other suitable materials, and / or combinations thereof. The gate electrode layer 85 may be formed by CVD, ALD, electroplating, or another suitable method. The metals for the gate dielectric layer 82 and the gate electrode layer 85 are also deposited over the top surface of the first ILD layer 50. The material for the gate electrode layer 85, which is formed over the first ILD layer 50, is then planarized, for example, by CMP, until the top surface of the first ILD layer 50 is exposed, as shown in FIGS. Fig. 16A and Fig. 16B. In some embodiments, after planarization, the metal gate electrode layer is recessed, and a capping insulating layer (not shown) is formed over the recessed gate electrode layer. The capping insulating layer comprises one or more layers of a silicon nitride-based material, such as silicon nitride. The capping insulating layer may be formed by depositing an insulating material followed by a planarization process.

[0045] In certain embodiments of the present invention, one or more work function adjustment layers (not shown) are sandwiched between the gate dielectric layer 82 and the gate electrode layer 85. The work function adjustment layers are composed of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For an n-channel FET, one or more elements or compounds from the group consisting of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for a p-channel FET, one or more elements or compounds from the group consisting of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer.The work function adjustment layer can be fabricated by ALD, PVD, CVD, electron beam evaporation, or any other suitable process. Furthermore, the work function adjustment layer can be fabricated separately for the n-channel FET and the p-channel FET, which may use different metal layers.

[0046] In addition, a second ILD layer 70 is formed over the first ILD layer 50 (see Fig. 1 to 3), and conductive contacts 80 penetrating through the second ILD layer 70 or the second and first ILD layers are formed to contact the gate electrode 85 and the source / drain epitaxial layer 60. Contact openings are created in the first ILD layer 50 and / or the second ILD layer 70. One or more layers of conductive materials are formed in and over the contact openings, and then a planarization process, such as a CMP process, is performed to form the conductive contacts 80. In some embodiments, the conductive contacts 80 include a cap layer and a body layer. The cap layer is a barrier layer and / or an adhesive layer (adhesion layer). In some embodiments, a Ti layer is formed on the source / drain epitaxial layer, and a TiN or TaN layer is formed on the Ti layer as the cap layer.The body layer comprises one or more layers of Co, Ni, W, Ti, Ta, Cu and Al or another suitable material.

[0047] It is clear that the FET undergoes further CMOS processes to produce various structural elements, such as contacts / vias, metallic interconnect layers, dielectric layers, passivation layers, and the like.

[0048] Fig. 17 shows a sectional view of a semiconductor device according to an embodiment of the present invention. As in Fig. As shown in Figure 17, a bottom-layer device 100 is fabricated over a substrate. The bottom-layer device 100 includes one or more fin field-effect transistors (FinFETs), gate-all-around FETs (GAA-FETs), planar FETs, vertical FETs, or other electronic components. Fig.17 also shows an upper-layer device 200 disposed over the lower-layer device 100. In some embodiments, one or more ILD layers, metal interconnect layers, and / or vias are disposed between the lower-layer device 100 and the upper-layer device 200. In some embodiments, the upper-layer device 200 includes one or more FETs fabricated with the above embodiments of the present invention.

[0049] In the above embodiments, it is possible to fabricate a source / drain structure without increasing the number of lithographic processes, or even to eliminate one of the lithographic processes in a gate replacement process. Furthermore, it is possible to reduce a gate length in the gate replacement process. Furthermore, a large source / drain epitaxial layer can be obtained, which can also increase the contact area. Furthermore, since the source / drain epitaxial layer can be formed using a low-temperature process, the aforementioned processes may be suitable for a BEOL process.

[0050] It should be understood that not all advantages have necessarily been discussed here, no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide other advantages.

[0051] According to one aspect of the present invention, in a method for manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer; a source / drain epitaxial layer is formed; a planarization process is performed on the source / drain epitaxial layer; the planarized source / drain epitaxial layer is patterned; the dummy gate structure is removed to create a gate gap; and a metal gate structure is formed in the gate gap. In one or more of the above or following embodiments, first gate sidewall spacers are formed on opposite side surfaces of the dummy gate structure before the source / drain epitaxial layer is formed.In one or more of the above or following embodiments, second gate sidewall spacers are formed on the first gate sidewall spacers in the gate gap. In one or more of the above or following embodiments, the dummy gate structure comprises a dummy gate electrode layer made of polycrystalline or amorphous SiGe or Ge. In one or more of the above or following embodiments, the source / drain epitaxial layer is formed such that a top surface of the source / drain epitaxial layer is located above the dummy gate structure. According to the claim, the source / drain epitaxial layer is formed such that it completely covers the dummy gate structure. In one or more of the above or following embodiments, the source / drain epitaxial layer is formed at a temperature of 250°C to 450°C.In one or more of the above or following embodiments, a first interlayer dielectric (ILD) layer is formed over the planarized source / drain epitaxial layer and the dummy gate structure, and a planarization process is performed on the first ILD layer such that top surfaces of the planarized source / drain epitaxial layer and the dummy gate structure are exposed. In one or more of the above or following embodiments, a second ILD layer is formed over the metal gate structure, and a source / drain contact is formed. In one or more of the above or following embodiments, the semiconductor device is formed over a silicon-on-insulator (SOI) substrate, and the semiconductor layer is a silicon layer of the SOI substrate.

[0052] According to one aspect of the present invention, in a method for manufacturing a semiconductor device, a semiconductor layer is formed on a dielectric layer disposed over a substrate; a dummy gate structure is formed over a channel region of the semiconductor layer; a source / drain epitaxial layer is formed; a planarization process is performed on the source / drain epitaxial layer; the planarized source / drain epitaxial layer is patterned; the dummy gate structure is removed to create a gate gap; and a metal gate structure is formed in the gate gap. In one or more of the above or following embodiments, first gate sidewall spacers are formed on opposite side surfaces of the dummy gate structure before the source / drain epitaxial layer is formed.In one or more of the above or following embodiments, second gate sidewall spacers are formed on the first gate sidewall spacers in the gate gap. In one or more of the above or following embodiments, the dummy gate structure comprises a dummy gate electrode layer made of polycrystalline or amorphous SiGe or Ge. In one or more of the above or following embodiments, the source / drain epitaxial layer is formed such that a top surface of the source / drain epitaxial layer is located above the dummy gate structure. According to the claim, the source / drain epitaxial layer is formed such that it completely covers the dummy gate structure. In one or more of the above or following embodiments, the source / drain epitaxial layer is formed at a temperature of 250°C to 450°C.In one or more of the above or following embodiments, a first interlayer dielectric (ILD) layer is formed over the planarized source / drain epitaxial layer and the dummy gate structure, and a planarization process is performed on the first ILD layer such that top surfaces of the planarized source / drain epitaxial layer and the dummy gate structure are exposed. In one or more of the above or following embodiments, a field-effect transistor (FET) is formed over the substrate, and a dielectric layer is formed to cover the FET.

[0053] According to one aspect of the present invention, in a method for manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, and a source / drain epitaxial layer is formed. The source / drain epitaxial layer has a crystalline portion formed over a source / drain region of the semiconductor layer and a non-crystalline portion formed over a dielectric layer. A planarization process is performed on the source / drain epitaxial layer; the non-crystalline portion of the planarized source / drain epitaxial layer is selectively removed; the dummy gate structure is removed to create a gate gap; and a metal gate structure is formed in the gate gap. In one or more of the above or following embodiments, the source / drain epitaxial layer comprises SiP.In one or more of the above or following embodiments, first gate sidewall spacers are formed on opposite side surfaces of the dummy gate structure before the source / drain epitaxial layer is formed. In one or more of the above or following embodiments, second gate sidewall spacers are formed on the first gate sidewall spacers in the gate gap. In one or more of the above or following embodiments, the dummy gate structure includes a dummy gate electrode layer made of polycrystalline or amorphous SiGe or Ge. In one or more of the above or following embodiments, the source / drain epitaxial layer is formed such that a top surface of the source / drain epitaxial layer is located above the dummy gate structure.According to the claim, the source / drain epitaxial layer is formed to completely cover the dummy gate structure. In one or more of the above or following embodiments, the source / drain epitaxial layer is formed at a temperature of 250°C to 450°C. In one or more of the above or following embodiments, a first interlayer dielectric (ILD) layer is formed over the planarized source / drain epitaxial layer and the dummy gate structure, and a planarization process is performed on the first ILD layer such that top surfaces of the planarized source / drain epitaxial layer and the dummy gate structure are exposed. In one or more of the above or following embodiments, a field-effect transistor (FET) is formed over the substrate, and a dielectric layer is formed to cover the FET.In one or more of the above or following embodiments, the source / drain region of the semiconductor layer is recessed before the source / drain epitaxial layer is formed.

[0054] According to one aspect of the present invention, a semiconductor device comprises: a channel formed as a portion of a semiconductor layer disposed on a dielectric layer; a gate dielectric layer disposed over the channel; a gate electrode layer disposed over the gate dielectric layer; gate sidewall spacers disposed on opposite side surfaces of the gate electrode layer; and a source and a drain, each comprising an epitaxial layer. A height difference between an uppermost portion of the epitaxial layer and an uppermost portion of the gate electrode layer is less than 5 nm. In one or more of the above or following embodiments, the height difference is zero.In one or more of the preceding or subsequent embodiments, the source / drain epitaxial layer extends laterally beyond a source / drain region of the semiconductor layer and is disposed on a dielectric layer. In one or more of the preceding or subsequent embodiments, the dielectric layer is a capping insulating layer. In one or more of the preceding or subsequent embodiments, the source / drain epitaxial layer comprises SiP and / or SiCP. In one or more of the preceding or subsequent embodiments, a height difference between an uppermost portion of the gate sidewall spacers and the uppermost portion of the epitaxial layer or the uppermost portion of the gate electrode layer is less than 5 nm.In one or more of the preceding or subsequent embodiments, the gate sidewall spacers comprise first gate sidewall spacers and second gate sidewall spacers, and a curved surface of the first gate sidewall spacers is in contact with the source / drain epitaxial layer, and a curved surface of the second gate sidewall spacers is in contact with the gate dielectric layer. In one or more of the preceding or subsequent embodiments, one or more dummy gate structures are arranged on the dielectric layer. In one or more of the preceding or subsequent embodiments, a height difference between an uppermost part of the one or more dummy gate structures and the uppermost part of the source / drain epitaxial layer or the uppermost part of the gate electrode layer is less than 5 nm.In one or more of the above or following embodiments, a field effect transistor is covered by the dielectric layer.

[0055] According to one aspect of the present invention, a semiconductor device comprises: an electronic device disposed on a substrate; one or more dielectric layers disposed over the electronic device; and thin-film transistors disposed on a topmost layer of the one or more dielectric layers. The thin-film transistors each comprise: a channel fabricated as part of a semiconductor layer disposed on a dielectric layer; a gate dielectric layer disposed over the channel; a gate electrode layer disposed over the gate dielectric layer; sidewall spacers disposed on opposite side surfaces of the gate electrode layer; and a source and a drain, each comprising an epitaxial layer.A ratio H1 / H2 of a height H1 of an uppermost part of the epitaxial layer to a height H2 of an uppermost part of the gate electrode layer, measured from a top surface of the semiconductor layer, is approximately 0.90 to 1.10. In one or more of the above or following embodiments, a height difference between the uppermost part of the epitaxial layer and the uppermost part of the gate electrode layer is less than 5 nm. In one or more of the above or following embodiments, the electronic device is a transistor. In one or more of the above or following embodiments, the transistor is a field-effect transistor or a gate-all-around transistor. In one or more of the above or following embodiments, the height difference is zero.In one or more of the preceding or subsequent embodiments, the source / drain epitaxial layer extends laterally beyond a source / drain region of the semiconductor layer and is disposed on a dielectric layer. In one or more of the preceding or subsequent embodiments, the dielectric layer is a capping insulating layer. In one or more of the preceding or subsequent embodiments, the source / drain epitaxial layer comprises SiP and / or SiCP. In one or more of the preceding or subsequent embodiments, a height difference between an uppermost portion of the gate sidewall spacers and the uppermost portion of the epitaxial layer or the uppermost portion of the gate electrode layer is less than 5 nm.In one or more of the preceding or subsequent embodiments, the gate sidewall spacers comprise first gate sidewall spacers and second gate sidewall spacers, and a curved surface of the first gate sidewall spacers is in contact with the source / drain epitaxial layer, and a curved surface of the second gate sidewall spacers is in contact with the gate dielectric layer. In one or more of the preceding or subsequent embodiments, one or more dummy gate structures are arranged on the dielectric layer. In one or more of the preceding or subsequent embodiments, a height difference between an uppermost part of the one or more dummy gate structures and the uppermost part of the source / drain epitaxial layer or the uppermost part of the gate electrode layer is less than 5 nm.

[0056] According to one aspect of the present invention, a semiconductor device comprises: a channel made of a semiconductor material; a gate dielectric layer disposed over the channel; a gate electrode layer disposed over the gate dielectric layer; gate sidewall spacers disposed on opposite side surfaces of the gate electrode layer; and a source and a drain, each comprising an epitaxial layer. A height difference between an uppermost part of the epitaxial layer and an uppermost part of the gate electrode layer is less than 5 nm. In one or more of the above or following embodiments, the height difference is zero. In one or more of the above or following embodiments, the source / drain epitaxial layer is disposed laterally beyond a source / drain region of the semiconductor layer and on a dielectric layer.In one or more of the above or following embodiments, the dielectric layer is a top insulating layer (STI). In one or more of the above or following embodiments, the source / drain epitaxial layer comprises SiP and / or SiCP. In one or more of the above or following embodiments, a height difference between an uppermost part of the gate sidewall spacers and the uppermost part of the epitaxial layer or the uppermost part of the gate electrode layer is less than 5 nm. In one or more of the above or following embodiments, the gate sidewall spacers comprise first gate sidewall spacers and second gate sidewall spacers, and a curved surface of the first gate sidewall spacers is in contact with the source / drain epitaxial layer, and a curved surface of the second gate sidewall spacers is in contact with the gate dielectric layer.In one or more of the above or following embodiments, one or more dummy gate structures are arranged on the dielectric layer. In one or more of the above or following embodiments, a height difference between an uppermost part of the one or more dummy gate structures and the uppermost part of the source / drain epitaxial layer or the uppermost part of the gate electrode layer is less than 5 nm.

[0057] Features of various embodiments or examples have been described above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can readily use the present invention as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

[1] A method of manufacturing a semiconductor device comprising the following steps: Producing a dummy gate structure (DG) over a channel region of a semiconductor layer (20,22); forming a source / drain epitaxial layer (60) on opposite sides of the dummy gate structure (DG); performing a planarization process on the source / drain epitaxial layer (60); Structuring the planarized source / drain epitaxial layer (60); Removing the dummy gate structure (DG) to create a gate gap (45); and Forming a metal gate structure in the gate gap (45), wherein the source / drain epitaxial layer (60) is formed to completely cover the dummy gate structure (DG). [2] The method of claim 1, further comprising forming first gate sidewall spacers (46) on opposite side surfaces of the dummy gate structure (DG) prior to forming the source / drain epitaxial layer (60). [3] The method of claim 2, further comprising, after forming the gate gap, forming second gate sidewall spacers (48) on the first gate sidewall spacers (46) in the gate gap (45). [4] Method according to one of the preceding claims, wherein the dummy gate structure (DG) comprises a dummy gate electrode layer (40) consisting of polycrystalline or amorphous SiGe or Ge. [5] Method according to one of the preceding claims, wherein the source / drain epitaxial layer (60) is formed such that a top surface of the source / drain epitaxial layer (60) is located above the dummy gate structure (DG). [6] The method of claim 1, wherein the source / drain epitaxial layer (60) is formed at a temperature of 250°C to 450°C. [7] A method according to any one of the preceding claims, further comprising: forming a first interlayer dielectric (ILD) layer (50) over the planarized source / drain epitaxial layer (60) and the dummy gate structure (DG); and Performing a planarization process on the first ILD layer (50) such that top surfaces of the planarized source / drain epitaxial layer (60) and the dummy gate structure (DG) are exposed. [8] The method of claim 7, further comprising: forming a second ILD layer (70) over the metal gate structure; and Making a source / drain contact (80). [9] Method according to one of the preceding claims, wherein the semiconductor device is fabricated over a silicon-on-insulator (SOI) substrate (10), and the semiconductor layer (22) is a silicon layer of the SOI substrate. [10] A method of manufacturing a semiconductor device comprising the following steps: Producing a semiconductor layer (22) on a dielectric layer (32, 35) arranged over a substrate (10); Producing a dummy gate structure (DG) over a channel region of the semiconductor layer (20); forming a source / drain epitaxial layer (60) on opposite sides of the dummy gate structure (DG); performing a planarization process on the source / drain epitaxial layer (60); Structuring the planarized source / drain epitaxial layer (60); Removing the dummy gate structure (DG) to create a gate gap (45); and Forming a metal gate structure in the gate gap (45), wherein the source / drain epitaxial layer (60) is formed to completely cover the dummy gate structure (45). [11] The method of claim 10, further comprising forming first gate sidewall spacers (46) on opposite side surfaces of the dummy gate structure (DG) prior to forming the source / drain epitaxial layer (60). [12] The method of claim 11, further comprising forming second gate sidewall spacers (48) on the first gate sidewall spacers (46) in the gate gap (45). [13] Method according to one of claims 10 to 12, wherein the dummy gate structure (DG) comprises a dummy gate electrode layer (40) consisting of polycrystalline or amorphous SiGe or Ge. [14] The method according to any one of claims 10 to 13, wherein the source / drain epitaxial layer (60) is formed such that a top surface of the source / drain epitaxial layer (60) is located above the dummy gate structure (DG). [15] The method of any one of claims 10 to 14, wherein the source / drain epitaxial layer (60) is formed at a temperature of 250°C to 450°C. [16] A method according to any one of claims 10 to 15, further comprising: forming a first interlayer dielectric (ILD) layer (50) over the planarized source / drain epitaxial layer (60) and the dummy gate structure (DG); and Performing a planarization process on the first ILD layer (50) such that top surfaces of the planarized source / drain epitaxial layer (60) and the dummy gate structure (DG) are exposed. [17] A method according to any one of claims 10 to 16, further comprising: fabricating a field-effect transistor (FET) over the substrate; and Fabricate the dielectric layer so that it covers the field-effect transistor. [18] Semiconductor device comprising: a channel formed as part of a semiconductor layer (20) disposed on a dielectric layer; a gate dielectric layer (82) disposed over the channel; a gate electrode layer (85) disposed over the gate dielectric layer (82); Gate sidewall spacers (46, 48) disposed on opposite side surfaces of the gate electrode layer (85); and a source and a drain, each having an epitaxial layer (60), wherein a height difference between an uppermost part of the epitaxial layer (60) and an uppermost part of the gate electrode layer (85) is less than 5 nm; wherein the source / drain epitaxial layer (60) is arranged laterally beyond a source / drain region of the semiconductor layer (20) and at a distance from the gate sidewall spacers (46, 48) on a dielectric insulation layer (30).

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