Multiplying delay control loops with compensation for realignment errors

Abstract

Multiplying delay control loop (MDLL) (10) with realignment error compensation, wherein the MDLL (10) comprises: a multiplexed oscillator (1) configured to generate an oscillator signal (OSC); a control circuit (3) configured to selectively inject a reference clock signal (CLKREF) into the multiplexed oscillator (1) to provide phase realignment; and an integrating and subtracting circuit (4) configured to compensate for a realignment error of the multiplexed oscillator (1) based on a determination of a difference between a first integral of the oscillator signal (OSC) and a second integral of the oscillator signal (OSC).

Description

Territory of Revelation

[0001] Embodiments of the invention relate to electronic systems and in particular to multiplying delay locked loops (MDLLs). BACKGROUND

[0002] A wide variety of electronic systems operate based on the timing of clock signals. Examples of electronic circuits that operate based on clock signal timing include, but are not limited to, analog-to-digital converters, digital-to-analog converters, wired or optical data communication links, and / or high-frequency front ends. SUMMARY OF THE REVELATION

[0003] This document describes MDLLs with realignment error compensation. An MDLL can include an oscillator that generates an output clock signal to control the timing of a downstream circuit, and a multiplexer used to periodically feed a reference clock signal into the oscillator to provide phase realignment. The MDLLs described here feature realignment error compensation resulting from the periodic injection of the reference clock signal. By compensating for the realignment error, output clock signals with higher spectral purity are produced, leading to improved performance, reduced costs, and / or enhanced design flexibility of the downstream circuitry.

[0004] In one aspect, an MDLL with realignment error compensation is created. The MDLL features a multiplexed oscillator configured to generate an oscillator signal, a control circuit configured to selectively inject a reference clock signal into the multiplexed oscillator to provide phase realignment, and an integrating and subtracting circuit configured to compensate for a realignment error of the multiplexed oscillator based on determining a difference between a first integral of the oscillator signal and a second integral of the oscillator signal.

[0005] In another aspect, an electronic system is created. The electronic system comprises a multi-function digital unit (MDLL) configured to generate an output clock signal based on a timing input from a reference clock signal, and a downstream circuit whose timing is controlled by the MDLL's output clock signal. The MDLL includes a multiplexed oscillator configured to generate an oscillator signal, and the multiplexed oscillator includes a multiplexer configured to receive the reference clock signal and the oscillator signal. The MDLL further includes an integrator and subtractor circuit configured to compensate for a realignment error of the multiplexed oscillator based on a difference between a first integral and a second integral of the oscillator signal.

[0006] In another aspect, a method for compensating for a realignment error in an MDLL is created. The method involves generating an oscillator signal using a multiplexed oscillator, which includes periodically injecting a reference clock signal into the multiplexed oscillator to provide phase realignment. The method further includes determining a first integral of the oscillator signal, determining a second integral of the oscillator signal, and compensating for a realignment error of the multiplexed oscillator based on the difference between the first and second integrals. List of characters Fig. Figure 1A is a schematic diagram of an embodiment of a multiplying delay control loop (MDLL) with compensation for a realignment error. Fig. 1B is an example of a timing diagram for the MDLL of Fig. 1A. Fig. 1C is another example of a timing diagram for the MDLL from Fig. 1A. Fig. Figure 2 is a schematic diagram of another embodiment of an MDLL with compensation for a realignment error. Fig. Figure 3A is a schematic diagram of an embodiment of an integrating and subtracting circuit for an MDLL. Fig. 3B is an example of a timing diagram for the integrating and subtracting circuit of Fig. 3A. Fig. Figure 4A is a schematic diagram of another embodiment of an integrating and subtracting circuit for an MDLL. Fig. 4B is an example of a timing diagram for the integrating and subtracting circuit of Fig. 4A. Fig. Figure 5 is a schematic diagram of another embodiment of an integrating and subtracting circuit for an MDLL. Fig. Figure 6 is a schematic diagram of another embodiment of an MDLL with compensation for a realignment error. Fig. Figure 7A is a schematic diagram of an embodiment of a phase-frequency detector and charge pump (PFD / CP) with calibration for a realignment error. Fig. Figure 7B is a schematic diagram of another embodiment of a PFD / CP with a calibration for a realignment error. Fig. 7C is an example of a time diagram for the PFD / CPs of Fig. 7A and Fig. 7B. Fig. 8A is an example of measuring the output clock power versus frequency for an MDLL without calibration for a realignment error. Fig. 8B is an example of measurements of output clock power versus frequency for an MDLL with a calibration for a realignment error. Fig. Figure 9A is a schematic diagram of an embodiment of a frequency synthesis system. Fig. Figure 9B is a schematic diagram of an embodiment of a digital / analog data conversion system. Fig. Figure 9C is a schematic diagram of an embodiment of an analog / digital data conversion system. Fig. Figure 9D is a schematic diagram of an embodiment of a high-frequency front-end system. DETAILED DESCRIPTION OF EXECUTION FORMS

[0007] The following detailed description of embodiments provides various descriptions of specific embodiments of the invention. This description refers to the drawings, in which the same reference numerals may denote identical or functionally similar elements. It is understood that elements shown in the figures are not necessarily drawn to scale. Furthermore, it is understood that certain embodiments may have more elements than shown in a drawing and / or may include a subset of the elements shown in a drawing. Additionally, some embodiments may include any suitable combination of features from two or more drawings.

[0008] The performance of electronic systems that operate based on the timing of clock signals is influenced by the accuracy and / or precision of the clock signals used to control the timing. For example, the performance of such electronic systems can be improved by controlling the timing using clock signals with low phase noise and high spectral purity.

[0009] A multiplying delay loop (MDLL) is a type of electronic circuit used to generate a clock signal for timing control. An MDLL can exhibit lower phase noise than a phase-locked loop (PLL) because an MDLL accumulates less phase noise. For example, certain MDLLs have a 1 / f noise profile, while PLLs have a 1 / f 2 -may exhibit a noise profile.

[0010] MDLLs can be used in a wide variety of applications. In one example, an MDLL generates a clock signal to control a time-controlled circuit, such as an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a wired or optical communication link, and / or a radio frequency (RF) front end. In another example, the MDLL is used to change the input reference frequency for a fractional-synthesizer, helping to avoid boundary noise at low frequency offsets of the fractional-synthesizer. Although several exemplary applications of MDLLs have been described, they can be used for a multitude of purposes in a wide range of electronic systems.

[0011] An MDLL can include a ring oscillator and a multiplexer used to periodically inject a high-quality reference clock signal into the ring oscillator to provide phase realignment. Using a high-quality reference clock signal to provide phase realignment results in low phase noise. However, such realignment of the ring oscillator can introduce realignment errors that occur with the reference rate. For example, the ring oscillator outputs a clock signal where, once every M cycles, the clock signal is slightly longer or shorter than in other cycles due to a realignment error. The Mth cycle represents the reference injection cycle, and the time difference between the Mth cycle and the cycles in which the reference clock signal is not injected represents the realignment error of the MDLL.

[0012] If correction and / or calibration of the realignment disturbances is lacking, the realignment disturbances degrade the spectral purity of the MDLL's output clock signal, which can affect the performance of electronic circuits that operate based on the timing of the MDLL's output clock signal.

[0013] In certain implementations herein, an MDLL includes a control circuit, a multiplexed oscillator, and an integrator-subtractor circuit, such as a switching resistor-capacitor integrator (switching RC integrator). The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrator-subtractor circuit receives an oscillator signal from the multiplexed oscillator and tunes an oscillation frequency of the multiplexed oscillator based on the difference between the integration of the oscillator signal over the injected period and the integration of the oscillator signal over the natural period.

[0014] Integrating and subtracting in this manner eliminates the need for a phase-frequency detector and charge pump (PFD / CP), thereby reducing the power consumption, area, and / or complexity of the MDLL. Furthermore, the integration and subtraction circuitry reduces or eliminates realignment error without requiring additional calibration. Instead, realignment is achieved with the accuracy of the integration and subtraction operation itself.

[0015] In certain implementations, the integrator and subtractor circuit is a switching RC integrator that calculates an integral over the input cycle and an integral over the natural cycle, and uses the difference in the integrals to tune the frequency of the multiplexed oscillator. The switching RC integrator can be fully differential and include a differential amplifier that uses auto-zeroing and / or chopping to reduce input offset and thereby improve the accuracy of the integrator and subtractor operations.

[0016] Thus, the switching RC integrator can be operated to determine the difference between an integral of a pulse of the injection period and an integral of a pulse of the natural period (also called the non-injection period). The resulting difference in the integrals is used in negative feedback to tune the frequency of the multiplexed oscillator. In the latched state, the difference is essentially zero, which corresponds to a frequency-locked state with essentially no realignment error.

[0017] Fig. 1A is a schematic diagram of an embodiment of an MDLL. 10 with compensation for a realignment error. The MDLL 10 features a multiplexed oscillator 1 , a divider 2 , a control circuit 3 and an integrating and subtracting circuit 4 on.

[0018] In the illustrated embodiment, the MDLL receives 10 a reference clock signal CLKREF and generates an output clock signal CLK OUT In the locked state, the output clock signal has a frequency CLK. OUT a positive integer M that is greater than a frequency of the reference clock signal CLK REF Thus, the MDLL 10 operated to multiply the frequency of the reference clock signal CLKREF.

[0019] As it is in Fig. As shown in 1A, the output clock signal CLK OUT in this embodiment to the divider circuit 2 delivered. The divider circuit 2 The output clock signal CLK is divided OUT , to generate a split clock signal DIV, which serves as input to the control circuit 3 It serves a purpose. In certain implementations, the divider circuit works 2 with a divisor of M that can be selected (for example, by digital control of the MDLL)10 ).

[0020] The control circuit 3 It generates a clock selection signal SEL, a first enable signal EN1, and a second enable signal EN2 based on a timing specification of the split clock signal CLK. The clock selection signal SEL is used to control the multiplexed oscillator. 1 to control the reference clock signal CLKREF selectively in the multiplexed oscillator 1 to feed in. The multiplexed oscillator 1 It operates with an injection period when the reference clock signal CLKREF is injected, and with a natural or non-injection period when the reference clock signal CLKREF is not injected. In certain implementations, the selection signal SEL is triggered once every M cycles of the output clock signal CLK. OUT activated.

[0021] The integrating and subtracting circuit 4 receives an oscillator signal (OSC) from the multiplexed oscillator 1and generates a tuning signal TUNE for tuning an oscillation frequency (for example, the non-feed period) of the multiplexed oscillator 1 The oscillator signal OSC can be any suitable signal from the multiplexed oscillator. 1 This is what a feedback clock signal for a multiplexer of the multiplexed oscillator is. 1 includes, but is not limited to. The integrating and subtracting circuit 4 controls the tuning signal TUNE based on a comparison of the feed period of the multiplexed oscillator. 1 with the natural period of the multiplexed oscillator 1 .

[0022] For example, the integrating and subtracting circuit 4 to be operated to adjust the frequency of the multiplexed oscillator 1to reconcile based on a difference between an integration performed during the injection period and an integration performed during the natural period. As stated in Fig. As shown in 1A, the integrating and subtracting circuit receives 4 in this embodiment the first release signal EN1 and the second release signal EN2 from the control circuit 3 In certain implementations, the first release signal EN1 activated once every M cycles when the reference clock signal CLK REF is fed in, and the second release signal EN2 one cycle after the activation of the first release signal EN1 is activated.

[0023] In the illustrated embodiment, the first enable signal controls EN1 the integration via the feed-in period and the second release signal EN2 Integration over the natural period. In certain implementations, the integrals are taken during successive cycles of the oscillator signal OSC.

[0024] For example, the control circuit 3 the first release signal EN1 activate during a feed-in period, so that the integrating and subtracting circuit 4 An integral of the oscillator signal OSC is determined over at least part of the injection period. Additionally, the control circuit can determine the second enable signal. EN2 activate during a natural period, so that the integrating and subtracting circuit 4 An integral of the oscillator signal is determined over at least a portion of the natural period. The integrating and subtracting circuit 4It determines a difference between the integrals and uses the result to control the tuning signal TUNE, thereby providing negative feedback to control the frequency of the multiplexed oscillator. 1 is delivered. In the locked state, the difference is essentially zero, which corresponds to a state with frequency locking and essentially no realignment error.

[0025] Fig. 1B is an example of a timing diagram for the MDLL 10 from Fig. 1A. The timing diagram shows a diagram of the first release signal. EN1 over time, a diagram of the second release signal EN2 over time and a diagram of the oscillator signal OSC over time.

[0026] With renewed reference to Fig. 1A powers the control circuit 3 periodically the reference clock signal CLK REF using the clock selection signal SEL in the multiplexed oscillator1 one. For example, the control circuit 3 to be operated to generate the reference clock signal CLK REF once every M cycles of the output clock signal CLK OUT to feed in, where M is an integer greater than 1. If the MDLL 10 If it is not locked, the output clock signal CLK OUT (as well as the oscillator signal OSC) may be slightly longer or shorter during feed-in cycles compared to non-feed-in cycles due to a realignment error.

[0027] As it is in Fig. The version shown in 1B differs because the MDLL 10Before a latch has been reached, the pulse width of the oscillator signal OSC is determined based on whether a particular pulse is assigned to a feed cycle in which the reference clock signal CLKREF is fed in, or to a natural cycle in which the reference clock signal CLKREF is not fed in. In this example, M is equal to three, so the reference feed occurs once every three cycles. Fig. 1B was annotated to represent an injected impulse. 7 , which is a feed period of the multiplexed oscillator 1 is assigned, and a natural impulse 8 , which is a natural period of the multiplexed oscillator 1 is assigned to represent.

[0028] The difference in pulse width between the injected pulse 7 and the natural impulse 8 represents the realignment error of the MDLL 10 dar.

[0029] The integrating and subtracting circuit 4 is operated to adjust the frequency of the multiplexed oscillator 1 based on a difference between an integration over the injection period (for example, an integral of the injected impulse) 7 ) and an integration over the natural period (for example, an integral of the natural momentum) 8 ) to tune, and uses the result to control the tuning signal TU-NE. Thus, the integrating and subtracting circuit provides 4 negative feedback to adjust the frequency of the multiplexed oscillator 1 to control. In the locked state, the difference is essentially zero, which corresponds to a state with frequency locking and essentially no realignment error.

[0030] Fig. 1C is another example of a timing diagram for the MDLL 10 from Fig. 1A. The timing diagram includes a graph of the oscillator signal OSC over time, a graph of the reference clock signal CLKREF over time, a graph of the clock selection signal SEL over time, and a graph of the first enable signal. EN1 over time, a diagram of the second release signal EN2 over time and a graph of the TUNE tuning signal over time.

[0031] The timing diagram has been annotated to represent a time difference Δt between a rising edge of the oscillator signal OSC and a corresponding rising edge of the reference clock signal CLKREF. The timing diagram has been further annotated to represent the length of different periods of the oscillator signal OSC relative to a desired oscillator period T. OSC to show.

[0032] Fig. 2 is a schematic diagram of another embodiment of an MDLL 20with compensation for a realignment error. The MDLL 20 features a multiplexed ring oscillator 11 , a divider 2 , a control circuit 3 and an integrating and subtracting circuit 4 on.

[0033] The MDLL 20 from Fig. 2 is the MDLL 10 from Fig. 1A similar, except that the MDLL 20 from Fig. 2 represents a specific implementation of a multiplexed oscillator. In particular, the MDLL 20 the multiplexed ring oscillator 11 on, which has a multiplexer 12 , an inverter 13 , a tunable delay circuit 14 and a feedback buffer 15 exhibits. Although in Fig. 2. An implementation of a multiplexed oscillator is represented. An MDLL may contain a multiplexed oscillator implemented in a variety of ways, including but not limited to the use of another implementation of a multiplexer and / or oscillator.

[0034] As it is in Fig. As shown in 2, the multiplexer receives 12 The clock selection signal SEL controls a selection between the reference clock signal CLKREF and a ring oscillator signal ROSC. When the ring oscillator signal ROSC is selected, the signal is driven by the inverter. 13 , the tunable delay circuit 14 and the feedback buffer 15 The formed ring is not interrupted, and thus the multiplexed ring oscillator oscillates. 11 with a natural period. However, if the reference clock signal CLKREF is selected, the ring is interrupted and the multiplexed ring oscillator is used. 11It operates with an injection period that corresponds to the reference clock signal CLK. REF is assigned.

[0035] In the illustrated embodiment, the integrating and subtracting circuit receives 4 the ring oscillator signal ROSC, which is used in the integrating and subtracting circuit 4 processed to generate a TUNE signal for controlling a delay of the tunable delay circuit 14 and thus the natural period of the multiplexed ring oscillator 11 to generate. Although the integrating and subtracting circuit 4 In this embodiment, if integration and subtraction are performed on the ring oscillator signal ROSC, the integrating and subtracting circuit can 4 process any suitable clock signal, such as another clock signal along the ring.

[0036] Thus, the integrating and subtracting circuit delivers 4In this example, frequency tuning is based on the difference between an integral over the feed-in period and an integral over the natural period or non-feed-in period. By providing frequency tuning in this way, the integrating and subtracting circuit compensates for 4 a realignment error of the multiplexed ring oscillator 11 , including a realignment error resulting from non-idealities of the multiplexer 12 results.

[0037] Fig. Figure 3A is a schematic diagram of an embodiment of an integrating and subtracting circuit. 40 for an MDLL. The integrating and subtracting circuit 40 This illustrates an example of a suitable circuit for providing integration and subtraction in an MDLL, implemented according to the teachings herein. Although Fig. 3A represents an embodiment of an integrating and subtracting circuit, the teachings herein are applicable to MDLLs which have integrating and subtracting circuits implemented in a variety of ways.

[0038] The integrating and subtracting circuit 40 features a first integration switch 21 , a second integration switch 22 , a first deintegration switch 23 , a second de-integration switch 24 , a first upward current source 31 and a second upward current source 32 , a first downward current source 33 , a second downward current source 34 , a capacitor 35 , a first AND gate 37 and a second AND gate 38 on.

[0039] As it is in Fig. As shown in 3A, a voltage across the capacitor is used. 35as a tuning voltage Vtune for controlling the oscillation frequency of an oscillator in an MDLL. For example, the tuning voltage Vtune can be used to control the delay of a controllable delay element in a ring oscillator of the MDLL. The capacitor 35 is from the first upward current source 31 charged when the first integration switch 21 is closed, and from the second upward current source 32 charged when the second integration switch 22 is closed. In addition, the capacitor 35 through the first downward current source 33 discharged when the first de-integration switch 23 is closed, and through the second downward current source 34 discharge when the second de-integration switch 24 is closed.

[0040] In the illustrated embodiment, a digital logic circuit arrangement is used to integrate or de-integrate the capacitor. 35 to control. For example, the first AND gate opens or closes. 37 the first integration switch 21 and opens or closes the first de-integration switch 23 based on an AND operation of the first release signal EN1 and the ring oscillator signal ROSC. Additionally, the second AND gate opens or closes. 38 the second integration switch 22 and opens or closes the second integration switch 24 based on an AND operation of the second release signal EN2 and the ring oscillator signal ROSC.

[0041] Fig. 3B is an example of a timing diagram for the integrating and subtracting circuit. 40 from Fig. 3A. The timing diagram shows a diagram of the first enable signal. EN1 over time, a diagram of the second release signal EN2 over time, a graph of the ring oscillator signal ROSC over time and a graph of the tuning voltage Vtune over time.

[0042] As it is in Fig. As shown in Figure 3B, one period of the ring oscillator signal ROSC changes based on whether a given cycle is an injection period Ti, which is associated with the reference injection, or a natural period Tn in which no reference clock signal is injected. In the example shown, the reference clock signal CLKREF is injected once every three cycles.

[0043] The integrating and subtracting circuit 40 The tuning voltage Vtune is controlled based on a difference between an integral of the ring oscillator signal ROSC during the injection period Ti and an integral of the ring oscillator signal ROSC during the natural period Tn.

[0044] In this embodiment, the integrating and subtracting circuit loads 40 the capacitor 35 during a first section 41 the injection period Ti (which in this example corresponds to a high value of ROSC) and discharges the capacitor 35 during a second section 42 The injection period Ti (which in this example corresponds to a low value of ROSC) discharges the capacitor. 35 during a first section 43 the natural period Tn (which in this example corresponds to a high value of ROSC) and charges the capacitor 35 during a second section 44 the natural period Tn (which in this example corresponds to a low value of ROSC).

[0045] By charging and discharging the capacitor 35 In this way the capacitor stores 35a charge quantity that corresponds to a difference between an integral of the ring oscillator signal ROSC during the injection period Ti and an integral of the ring oscillator signal ROSC during the natural period Tn.

[0046] Fig. Figure 4A is a schematic diagram of another embodiment of an integrating and subtracting circuit. 80 for an MDLL. The integrating and subtracting circuit 80 This illustrates another example of a suitable circuit for providing integration and subtraction in an MDLL, implemented according to the teachings herein. In this embodiment, the integrating and subtracting circuit is 80 It is implemented as a switching RC integrator. However, integrating and subtracting circuits can be implemented in many different ways.

[0047] The integrating and subtracting circuit 80 features a differential amplifier 60, a first integration control switch 61 , a second integration control switch 62 , a third integration control switch 63 , a fourth integration control switch 64 , a first integration capacitor 65 , a second integration capacitor 66 , a first output resistance 67 , a second output resistor 68 , a first power source 69 , a second power source 70 , a first AND gate 71 and a second AND gate 72 on.

[0048] In the illustrated embodiment, the first integrating capacitor 65 between a first input and a first output of the differential amplifier 60 electrically connected and the second integration capacitor 66 between a second input and a second output of the differential amplifier 60electrically connected. Furthermore, the output resistance is 67 between the first output of the differential amplifier 60 and electrically connected to a non-inverted tuning voltage Vtune_p and the second output resistance 68 between the second output of the differential amplifier 60 and electrically connected to an inverted tuning voltage Vtune_n. The first integration control switch 61 is between the first power source 69 and the first input of the differential amplifier 60 electrically connected and the second integration control switch 62 is between the second power source 70 and the first input of the differential amplifier 60 electrically connected. In addition, the third integration control switch is 63 between the first power source 69 and a second input of the differential amplifier 60electrically connected and the fourth integration control switch 64 is between the second power source 70 and the second input of the differential amplifier 60 electrically connected.

[0049] A differential tuning voltage, which corresponds to a difference between the non-inverted tuning voltage Vtune_p and the inverted tuning voltage Vtune_n, serves as a tuning voltage to control an oscillation frequency of an oscillator of an MDLL.

[0050] In the illustrated embodiment, a digital logic circuit arrangement is used to control each of the switches. 61 - 64 to open or close. For example, the first AND gate opens or closes. 71 the first integration control switch 61 and the fourth integration control switch 64 based on an AND operation of the first release signal EN1 and the ring oscillator signal ROSC. Additionally, the second AND gate opens or closes. 72 the second integration control switch 62 and the third integration control switch 63 based on an AND operation of the second release signal EN2 and the ring oscillator signal ROSC.

[0051] As it is in Fig. 4A is shown, the first power source provides 69 an integration current I INT and the second power source 70 takes the integration current I INT up. The first power source 69 and the second power source 70 are used to control the desired charging or discharging of the integration capacitors 65 - 66 to provide. In certain implementations, the integration stream I INT controllable, thereby providing a mechanism for selecting a desired size of the integration current I INT to provide.

[0052] Fig. 4B is an example of a timing diagram for the integrating and subtracting circuit of Fig. 4A. The timing diagram shows a diagram of the first enable signal. EN1 over time, a diagram of the second release signal EN2 over time, a diagram of the ring oscillator signal ROSC over time and a diagram of the differential tuning voltage Vtune over time.

[0053] The integrating and subtracting circuit 80The differential tuning voltage Vtune is controlled based on the difference between an integral of the ring oscillator signal ROSC during an injection period Ti and an integral of the ring oscillator signal ROSC during a natural period Tn. In this embodiment, the integral during the injection period Ti and the integral during the natural period Tn are taken while the ring oscillator signal ROSC is at a high value. However, other implementations are possible, such as integrating and subtracting circuits that calculate integrals at a low value, a high value, or a combination thereof.

[0054] Fig. Figure 5 is a schematic diagram of another embodiment of an integrating and subtracting circuit. 100 for an MDLL. In this embodiment, the integrating and subtracting circuit 100It is implemented as a switching RC integrator. However, integrating and subtracting circuits can be implemented in many different ways.

[0055] The integrating and subtracting circuit 100 from Fig. 5 is the integrating and subtracting circuit 80 from Fig. 4A similar, except that the integrating and subtracting circuit 100 furthermore, a first automatic zeroing switch 81 , a second auto-zeroing switch 82 , a third auto-zero adjustment switch 83 , a fourth auto-zeroing switch 84 , a fifth auto-zeroing switch 85 , a sixth auto-zero adjustment switch 86 , a seventh auto-zero adjustment switch 87 , an eighth auto-zero adjustment switch 88 , a first auto-zeroing capacitor 89 , a second auto-zeroing capacitor 90 and a holding capacitor 91The illustrated embodiment also features a first current source resistance. 97 and a second current source resistor 98 on, which is an implementation of the first power source 69 or the second power source 70 from Fig. 4A corresponds.

[0056] By including the switches 81 - 88 and the capacitors 89 - 90 An automatic zero adjustment of the differential amplifier will be performed. 60 Provided for removing the input offset during an auto-zeroing cycle. Specifically, the switches open. 87 - 88 then, when the auto-zero adjustment signal AZ is activated to control the outputs of the differential amplifier 60 to disconnect from the differential tuning voltage, and the switches 85 -86 open to allow charge integration at the integrating capacitors 65 - 66to prevent this. Furthermore, the switches close. 81 - 84 , so that the differential amplifier 60 the capacitors 89 - 90 controls to store a voltage corresponding to an input offset of the differential amplifier 60 This corresponds to, for example, the switches control 81 - 82 one end of the capacitors 89 - 90 to a common-mode voltage V CM , while the differential amplifier 60 the voltages at the other end of the capacitors 89 - 90 based on the input offset of the differential amplifier 60 controls. After the auto-zero adjustment cycle, the charge on the capacitors is compensated. 89 - 90 The input offset of the differential amplifier is stored.

[0057] By compensating for the input offset voltage of the differential amplifier 60can determine the accuracy of an integration and subtraction operation of the switching RC integrator 100 can be improved. Although an example of automatic zero adjustment is shown, the input offset of a differential amplifier can be corrected in many ways, including, but not limited to, the use of a wide variety of automatic zero adjustment and / or chopping circuits. Thus, any suitable input offset compensation circuit can be used.

[0058] The differential amplifier 60 It can be calibrated at a variety of times to compensate for input offset voltage. For example, an auto-zero calibration cycle can be performed at startup and / or during operation. For example, the switches 87 - 88 and the holding capacitor 91This is included to keep the differential tuning voltage essentially constant during an auto-zeroing cycle, thus keeping the controlled ring oscillator in normal operation during auto-zeroing. In certain implementations, input offset compensation occurs periodically during MDLL operation, for example, once every 100 or more cycles of the multiplexed oscillator.

[0059] In the illustrated embodiment, the integrating and subtracting circuit has 100 the first current source resistance 97 to supply the integration current I INT and the second current source resistance 98 to record the integration current I INT , which allows the charging and discharging of the integration capacitors 65 - 66is controlled. Although an example of a circuit arrangement for generating integration currents is shown, integration currents for a switching RC integrator can be generated in many different ways.

[0060] In certain implementations, the resistance of the first current source resistance 97 and / or the resistance of the second current source 98 controllable (e.g., programmable and / or tunable), thus providing a mechanism for changing the loop bandwidth of the MDLL. For example, the resistance can control the magnitude of the integration current I. INT and thus a rate at which the integration capacitors 65 - 66 The charging or discharging process can be controlled. Therefore, changing the resistors can be used to control the loop bandwidth.

[0061] In the embodiments discussed above, an integrating and subtracting circuit tunes the oscillation frequency of a multiplexed oscillator of an MDLL. Implementing the MDLL in this way eliminates the need for a phase-frequency detector and charge pump (PFD / CP), thereby reducing the power consumption, area, and / or complexity of the MDLL.

[0062] In other embodiments, an MDLL includes a PFD / CP for frequency tuning and an integrating and subtracting circuit that generates a calibration signal to correct a realignment error. In these embodiments, the oscillation frequency of the multiplexed oscillator is controlled by a PFD / CP, while the integrating and subtracting circuit generates a calibration signal for the PFD / CP to reduce or eliminate the realignment error.

[0063] Fig. 6 is a schematic diagram of another embodiment of an MDLL 210 with compensation for a realignment error. The MDLL 210 features a multiplexed ring oscillator 11 , a divider 2 , a control circuit 3 , an integrating and subtracting circuit 4 , a PFD / CP 201 and a loop filter 202 on.

[0064] The MDLL 210 from Fig. 6 is the MDLL 20 from Fig. 2 similar, except that the MDLL 210 further the PFD / CP 201 for controlling the TUNE signal and a loop filter 202 for filtering the TUNE signal to provide loop stability. Additionally, the integrating and subtracting circuit generates 4 a calibration signal CAL for the PFD / CP 201 In contrast to the MDLL 20 from Fig. 2 generates the integration and subtraction circuit 4 from Fig. 6 is therefore not the tuning signal TUNE, but rather the calibration signal CAL.

[0065] As it is in Fig. As shown in 6, the PFD / CP receives 201 the reference clock signal CLK REF The ring oscillator signal ROSC, the clock selection signal SEL, and the calibration signal CAL are also included. Additionally, the PFD / CP provides... 201 The tuning signal TUNE is off. If the clock selection signal SEL is activated, the PFD / CP adjusts. 201 The value of the tuning signal TUNE is determined by comparing the timing of the reference clock signal CLKREF with the timing of the ring oscillator signal ROSC. The PFD / CP 201 It can perform phase and / or frequency comparisons.

[0066] The PFD / CP 201 used to align the PFD / CP 201 entered reference clock signal CLKREF to the one in the PFD / CP 201The input ring oscillator signal ROSC. However, unknown delays, such as those resulting from conductor routing or traces and / or manufacturing variations, can lead to a phase difference between the inputs to the multiplexer. 12 This can lead to a realignment error if no compensation is made.

[0067] The integrating and subtracting circuit 4 It generates a calibration signal CAL that reduces or eliminates the realignment error. In certain implementations, the calibration signal CAL provides a phase shift that adjusts the phases of the inputs to the multiplexer. 12 aligned, thus providing phase alignment to the inputs into the multiplexer and not to the inputs into the PFD / CP.

[0068] For example, the calibration signal CAL can introduce a fixed amount of charge into the loop filter. 202control while the MDLL 210 is locked in place. Frequency locking results in an essentially constant value of the tuning signal TU-NE, but the phase of the multiplexed ring oscillator 11 The signal is offset to compensate for the applied charge. Thus, the calibration signal CAL is used to control a phase shift to ensure alignment with the inputs to the multiplexer and not with the inputs to the PFD / CP.

[0069] In the illustrated embodiment, the integrating and subtracting circuit generates 4 the calibration signal CAL is based on determining a difference between an integral of the output clock signal. CLK OUT over an input period and an integral of the output clock signal CLK OUT over a natural period or non-feed-in period. Although an implementation is shown where the integrating and subtracting circuit 4 the output clock signalCLK OUT Integrated, an integrating and subtracting circuit can provide integration for other clock signals.

[0070] Fig. 7A and Fig. Figure 7B shows examples of PFDs / CPs calibrated using an integrating and subtracting circuit. The PFD / CP of Fig. 7A or the PFD / CP from Fig. 7B can be placed in an MDLL such as the MDLL 210 from Fig. 6. Although two examples are shown, an integrating and subtracting circuit can calibrate a PFD / CP for realignment errors in a variety of ways.

[0071] Fig. 7A is a schematic diagram of an embodiment of a PFD / CP with a calibration for a realignment error. The PFD / CP has a PFD 251 up, a CP 252 and a controllable power source 254 and is depicted as having a loop capacitor 255 is coupled. A current I Cinto the loop capacitor 255 is shown. Although the loop capacitor 255 While an MDLL represents an implementation of a loop filter, it may contain a loop filter that is implemented in a different way.

[0072] As it is in Fig. As shown in 7A, the PFD compares 251 The reference clock signal CLKREF and the ring oscillator signal ROSC when the clock selection signal SEL is enabled. The PFD 251 generates an upward signal UP to control the CP 252 , to the loop capacitor 255 to load, and a downward signal DN to control the CP 252 , to the loop capacitor 255 to unload. For example, the CP 252 have an upward current source that is selectively activated by the upward signal UP, and a downward current source that is selectively activated by the downward signal DN.

[0073] In the illustrated embodiment, the calibration signal CAL controls a leakage current quantity. I bleed , which is due to the controllable power source 254 to the loop capacitor 255 is supplied. The electricity I bleed the controllable power source 254 controls a static phase shift between the reference clock signal CLK REF and the ring oscillator signal ROSC.

[0074] Fig. 7B is a schematic diagram of another embodiment of a PFD / CP with calibration for a realignment error. The PFD / CP has a PFD 261 and a CP 252 on and is equipped with a loop capacitor 255 shown coupled. A current I C into the loop capacitor 255 is shown.

[0075] The PFD 261 has a first detection element 271 (a D flip-flop in this example), a second detection element 272(a D flip-flop in this example), a NAND gate 273 , a first controllable delay element 275 and a second controllable delay element 276 In this example, the D flip-flops each have a data input (D), a data output (Q), a clock input, and a logic-inverted reset (rb). To make the figure clearer, details on enabling the PFD are shown below. 261 using the clock selection signal SEL in Fig. 7B omitted.

[0076] The calibration signal CAL serves to establish a first delay t1, which is determined by the first controllable delay element. 275 is supplied, and a second delay t2, which is provided by the second controllable delay element 276 It is delivered, to be controlled separately. By controlling a delay when resetting the first detection element. 271 relative to a delay in resetting the second detection element272 A static phase shift between the reference clock signal CLKREF and the ring oscillator signal ROSC can be controlled.

[0077] Fig. 7C is an example of a time diagram for the PFD / CPs of Fig. 7A and Fig. 7B. The timing diagram shows a graph of the reference clock signal CLKREF over time, a graph of the ring oscillator signal ROSC over time, and a graph of the current I. C from Fig. 7A over time and a diagram of the current I C from Fig. 7B over time.

[0078] As it is in Fig. As shown in 7C, the current represents I bleed A phase shift is introduced between the reference clock signal CLKREF and the ring oscillator signal ROSC. The magnitude of the phase shift is determined based on the current value. I bleed and a charge pump current icp from the CP 252 controlled. If the MDLL 210 from Fig. 6 with the PFD / CP from Fig. 7A is implemented and controls the integrating and subtracting circuit. 4 a value of the calibration signal CAL to provide a phase shift that adjusts the inputs to the multiplexer 12 The phase shift also preferably controls the duty cycle of a feed-in period so that it is essentially the same as the duty cycle of a non-feed-in period.

[0079] With further reference to Fig. 7C can additionally or alternatively base the phase shift on a difference between the first delay t1 and the second delay t2 of the embodiment of Fig. 7B is controlled. The magnitude of the phase shift is determined based on the difference between the first delay t1 and the second delay t2, and on a charge pump current icp from the CP. 252 controlled. If the MDLL 210 from Fig. 6 with the PFD / CP from Fig. 7B is implemented, controls the integrating and subtracting circuit. 4 a difference between the first delay t1 and the second delay t2 to allow the inputs to enter the multiplexer 12 to align them with each other and to essentially adapt the work cycle of the feed-in period to the work cycle of the non-feed-in period.

[0080] Fig. 8A is an example of measuring the output clock power versus frequency for an MDLL without calibration for a realignment error.

[0081] Fig. 8B is an example of measurements of output clock power versus frequency for an MDLL with calibration for a realignment error.

[0082] As by comparing Fig. 8A and Fig. As shown in Figure 8B, the inclusion of a calibration for a realignment error leads to a reduction in the power of realignment disturbances and to an improved spectral purity of the output clock signal of the MDLL.

[0083] Fig. 9A-9D are examples of electronic systems that may incorporate an MDLL with realignment error compensation as described herein. Such electronic systems are affected by the accuracy and / or precision of the clock signal used to control timing, and thus reducing or eliminating realignment errors can improve system performance. Furthermore, reducing realignment error may provide additional benefits, such as improved design flexibility and / or lower design costs. Although various examples of electronic systems are described below, realignment error compensation MDLLs can be used to control the timing of a wide variety of downstream circuitry.

[0084] Fig. Figure 9A is a schematic diagram of an embodiment of a frequency synthesis system. 410The frequency synthesis system 410 has a clock buffer 400 , an MDLL 401 , a divider 402 (in this example, division by the integer R) and a frequency synthesizer 403 on. The MDLL 401 is implemented according to one or more of the features described here.

[0085] In the illustrated embodiment, the MDLL serves 401 to provide a frequency of a reference clock signal for the frequency synthesizer 403 to control. Including the MDLL 401 This helps to eliminate borderline interference at low frequency offsets of the fractional synthesizer. 403 to avoid this, thereby increasing the flexibility of the frequency synthesizer and achieving high performance across a wide range of operating parameters and / or application scenarios.

[0086] Without including the MDLL 401 can the frequency synthesizer 403suffer from major disturbances that fall within the loop bandwidth of the frequency synthesizer when the frequency synthesizer 403 works with small fractional ratios. In contrast, the inclusion of the MDLL offers 401 Flexibility in setting the operating frequency of the frequency synthesizer's PFD 403 away from frequencies that are assigned integer limit disturbances resulting from the voltage-controlled oscillator (VCO) and / or the output frequency of the frequency synthesizer.

[0087] Fig. Figure 9B is a schematic diagram of an embodiment of a digital / analog data conversion system. 420 The digital-to-analog data conversion system 420 exhibits an MDLL 401 and a DAC 413 on. The DAC 413 receives a digital input signal D IN and generates an analog output signal OUT. Additionally, the timing of conversion operations of the DAC is specified. 413through the output clock signal CLK OUT from the MDLL 401 controlled. The MDLL 401 is implemented according to one or more features herein and thus the output clock signal exhibits CLK OUT a small realignment error to improve the performance of the DAC 413 to improve.

[0088] Fig. Figure 9C is a schematic diagram of an embodiment of an analog-to-digital data conversion system. 430 The analog-to-digital data conversion system 430 exhibits an MDLL 401 and an ADC 423 on. The ADC 423 It receives an analog input signal IN and generates a digital output signal D. OUT The time frame for the ADC's implementation operations 423 is determined by the output clock signal CLK OUT from the MDLL 401 controlled. By implementing the analog-to-digital data conversion system. 430Using an MDLL with low reorientation error can result in better ADC operation. 423 This can be achieved. For example, the timing of data conversion operations can be controlled more precisely, leading to a performance improvement both when using a single ADC and when using multiple ADCs to digitize signals assigned to parallel paths.

[0089] Fig. Figure 9D is a schematic diagram of an embodiment of a high-frequency front-end system. 440 The high-frequency front-end system 440 exhibits an MDLL 401 , an upward converter mixer 431 , a power amplifier (PA) 433 , a step-down mixer 432 , a low-noise amplifier (LNA) 434 , an antenna access component 435 (for example, a switch, a duplexer and / or a circulator) and an antenna 436 on.

[0090] As it is in Fig. As shown in 9D, the MDLL serves this purpose. 401 as a local oscillator for generating clock signals for frequency-up and frequency-down conversion operations. In certain implementations, a polyphase filter or other suitable quadrature clock generation circuit can be used to process the MDLL's output clock signal to generate a pair of clock signals with a quadrature phase relationship, enabling transmit and / or receive paths to operate using quadrature signaling. By implementing the MDLL 401 According to the teachings herein, data with higher spectral purity can be sent and / or received, which in turn allows communication with higher bandwidth, over greater distances and / or through radio environments with more noise. Applications

[0091] Devices employing the schemes described above can be implemented in various electronic devices. Examples of electronic devices include, but are not limited to, consumer electronics products, consumer electronics product components, electronic test equipment, communication infrastructure, and so on. For instance, an MDLL with realignment error compensation can be used in a wide range of analog, mixed-signal, and RF systems, including, but not limited to, data converters, chip-to-chip communication systems, clock and data recovery systems, base stations, mobile devices (such as smartphones or handsets), laptop computers, tablets, and wearable electronics. A wide range of consumer electronics products may also incorporate an MDLL with realignment error compensation for IoT applications in the Internet of Things (IoT applications).For example, an MDLL containing realignment error compensation may be found in an automobile, camcorder, camera, digital camera, portable memory chip, washing machine, dryer, washer-dryer, copier, fax machine, scanner, multifunctional peripheral device, or a variety of other consumer electronics products. Furthermore, electronic devices may include unfinished products, including those for industrial, medical, and automotive applications. Conclusion

[0092] The foregoing description may refer to elements or features that are “connected” or “coupled” to one another. As used herein, “connected,” unless expressly stated otherwise, means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically. Likewise, “coupled,” unless expressly stated otherwise, means that one element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically. Thus, although the various circuits shown in the figures represent exemplary arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the circuits shown is not adversely affected).

[0093] Although this invention has been described with respect to certain embodiments, other embodiments, which are apparent to the ordinary person skilled in the art, including embodiments that do not offer all the features and advantages set forth herein, are also within the scope of this invention. Furthermore, the various embodiments described above can be combined to create further embodiments. Moreover, certain features shown in connection with one embodiment can also be incorporated into other embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

[0094] According to one aspect, multiplying delay control loops (MDLLs) with realignment error compensation are created. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrator-subtractor circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injection period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrator-subtractor circuit receives an oscillator signal from the multiplexed oscillator and tunes the oscillation frequency of the multiplexed oscillator based on the difference between the integration of the oscillator signal over the injection period and the integration of the oscillator signal over the natural period.

Claims

[1] Multiplying delay control loop (MDLL) with compensation for realignment errors, wherein the MDLL has the following: a multiplexed oscillator designed to generate an oscillator signal; a control circuit designed to selectively inject a reference clock signal into the multiplexed oscillator to provide phase realignment; and an integrating and subtracting circuit designed to compensate for a realignment error of the multiplexed oscillator based on a determination of a difference between a first integral of the oscillator signal and a second integral of the oscillator signal. [2] MDLL according to claim 1, wherein the integrating and subtracting circuit is configured to determine the first integral when the control circuit feeds the reference clock signal into the multiplexed oscillator, and to determine the second integral when the control circuit does not feed the reference clock signal into the multiplexed oscillator. [3] MDLL according to any of the preceding claims, wherein the integrating and subtracting circuit comprises a switching resistor-capacitor integrator (RC integrator). [4] MDLL according to claim 3, wherein the switching RC integrator has a differential amplifier configured to generate a differential signal representing the difference between the first integral and the second integral, wherein the switching RC integrator has an input offset compensation circuit configured to compensate for an input offset of the differential amplifier. [5] MDLL according to one of the preceding claims, wherein the multiplexed oscillator has a controllable delay element, wherein the integrating and subtracting circuit is configured to control a delay of the controllable delay element. [6] MDLL according to any of the preceding claims, wherein the multiplexed oscillator has a controllable delay element, wherein the MDLL further comprises a phase-frequency detector and a charge pump designed to control a delay of the controllable delay element based on a comparison of a timing specification of the multiplexed oscillator with a timing specification of the reference clock signal. [7] MDLL according to claim 6, wherein the integrating and subtracting circuit is configured to calibrate the phase-frequency detector and the charge pump based on the difference. [8] MDLL according to claim 7, further comprising a loop filter coupled to an output of the phase frequency detector and charge pump, wherein the integrating and subtracting circuit is operable to calibrate a leakage current quantity into the loop filter. [9] MDLL according to claim 7 or 8, wherein the phase-frequency detector and the charge pump comprise a first detection element and a second detection element designed to compare the timing of the multiplexed oscillator with the timing of the reference clock signal, wherein the integrating and subtracting circuit is operable to calibrate a delay in resetting the first detection element relative to a delay in resetting the second detection element. [10] Electronic system comprising the following: a multiplying delay control loop (MDLL) configured to generate an output clock signal based on a timing specification of a reference clock signal, wherein the MDLL comprises the following: a multiplexed oscillator configured to generate an oscillator signal, wherein the multiplexed oscillator includes a multiplexer configured to receive the reference clock signal and the oscillator signal; and an integrating and subtracting circuit designed to compensate for a realignment error of the multiplexed oscillator based on a difference between a first integral of the oscillator signal and a second integral of the oscillator signal; and a downstream circuit with a time specification that is controlled by the output clock signal of the MDLL. [11] Electronic system according to claim 10, wherein the integrating and subtracting circuit is configured to determine the first integral when the multiplexer selects the reference clock signal and to determine the second integral when the multiplexer selects the oscillator signal. [12] Electronic system according to claim 10 or 11, wherein the integrating and subtracting circuit comprises a switching RC integrator. [13] Electronic system according to claim 12, wherein the switching RC integrator has a differential amplifier configured to generate a differential signal representing the difference between the first integral and the second integral, wherein the switching RC integrator has an input offset compensation circuit configured to compensate for an input offset of the differential amplifier. [14] Electronic system according to one of claims 10 to 13, wherein the multiplexed oscillator has a controllable delay element, wherein the integrating and subtracting circuit is configured to control a delay of the controllable delay element. [15] Electronic system according to any one of claims 10 to 14, further comprising a control circuit configured to control the selection of the multiplexer based on a time specification of the output clock signal. [16] Electronic system according to any one of claims 10 to 15, wherein the downstream circuit comprises a frequency synthesizer, wherein the output clock signal of the MDLL is configured to control an input reference frequency for the frequency synthesizer. [17] Electronic system according to one of claims 10 to 16, wherein the downstream circuit comprises a data conversion circuit with a time specification of data conversion operations controlled by the output clock signal of the MDLL. [18] Method for compensating a realignment error in a multiplying delay control loop (MDLL), wherein the method comprises: Generating an oscillator signal using a multiplexed oscillator, including periodically injecting a reference clock signal into the multiplexed oscillator to provide phase reorientation; Determining a first integral of the oscillator signal; Determining a second integral of the oscillator signal; and Compensating for a realignment error of the multiplexed oscillator based on a difference between the first integral and the second integral. [19] Method according to claim 18, wherein determining the first integral includes integrating the oscillator signal while the reference clock signal is being injected, and wherein determining the second integral includes integrating the oscillator signal while the reference clock signal is not being injected. [20] Method according to claim 18 or 19, further comprising controlling an adjustable delay of the multiplexed oscillator based on the difference between the first integral and the second integral.

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