Circuit arrangement, method for operating a circuit arrangement, microcontrol and communication interface

Abstract

Circuit arrangement (100) comprising: a reference clock circuit (102) configured to provide a reference clock signal (REFCLK); an oscillator (104) controlled by a trim value and configured to generate an output clock signal (CLK); a counter (106) configured to count a number (Nmeas) of clock cycles of the output clock signal (CLK); and at least one processor (108) configured to set a time span based on the reference clock signal (REFCLK), repeating for successive time spans: determining a number (Nmeas) of clock cycles of the output clock signal (CLK) using the counter, determining a ratio between a target number (N) of clock cycles of the output clock signal (CLK) and the determined number (Nmeas) of clock cycles of the output clock signal (CLK), and applying a time-span averaged fractional value of a least significant bit of the trim value by switching back and forth.depending on the ratio of the least significant bit between a high value (LSBH) and a low value (LSBL), wherein the switching divides the time interval into a high phase, which lasts a first integer number of clock cycles during which the least significant bit has the high value (LSBH), and a low phase, which lasts a difference between the target number (N) of clock cycles of the output clock signal (CLK) and the first integer number during which the least significant bit has the low value; and wherein the circuit arrangement (100) further comprises a register configured to store the high value (LSBH), the first integer, and the low value (LSBL).

Description

Technical field Different embodiments generally relate to a circuit arrangement, a method for operating a circuit arrangement, a microcontroller, and a communication interface. background Software-implemented frequency control loops (FLLs), also known as software frequency control loops (SW-FLLs), use timers to measure the frequency of a clock of interest (hereinafter referred to as CLK) relative to a (fixed) low-frequency reference clock or signal. When calculating the actual frequency of the CLK, the software (SW) may update trim bits of an oscillator that generates the CLK. Therefore, the accuracy of the CLK frequency after correction depends on the step size of the least significant bit (LSB) of the oscillator. Thus, even if the comparison and calculation yields an accurate value for the CLK frequency (e.g., accurate to approximately 100 ppb (parts per billion) or less, depending on a comparison timescale), the SW would not be accurate for a fraction of an LSB. Current implementations of FLLs in software typically ensure a frequency accuracy of approximately 1000 ppm (0.1%). DE 103 08 643 A1 discloses a phase control arrangement in which, in addition to a frequency divider arranged in a feedback branch of a phase-locked loop (PLL), a further frequency counter is provided which is designed to be readable and is also connected to the oscillator output. The US 2011 / 0 261 871 A1 reveals a fully digital frequency synthesizer architecture based on a digitally controlled oscillator that is tuned in response to a digital tuning word. DE 60 2004 005 218 T2 discloses a phase detector for detecting a phase difference between a data clock and a reference clock using a data signal. Summary A circuit arrangement according to claims 1 and 9, a microcontroller according to claim 7, a communication interface according to claim 8, and a method for operating a circuit arrangement according to claims 11 and 17 are provided. Further embodiments are described in the dependent claims. A circuit arrangement is provided. The circuit arrangement can include a reference clock circuit configured to provide a reference clock signal, an oscillator controlled by a trim value and configured to generate an output clock signal, a counter configured to count a number of clock cycles of the output clock signal, and at least one processor configured to set a time interval based on the reference clock signal and, for successive time intervals, to: determine a number of clock cycles of the output clock signal using the counter, determine a ratio between a target number of clock cycles of the output clock signal and the determined number of clock cycles of the output clock signal, and apply a time-interval-averaged fractional value of a least significant bit of the trim value by toggling back and forth, depending on the ratio.of the least significant bit between a high value and a low value. Brief description of the drawings In the drawings, the same reference numerals refer generally to the same parts throughout the different views. The drawings are not necessarily to scale; rather, the illustration of the principles of the invention is generally emphasized. The following description describes various embodiments of the invention with reference to the following drawings, which show: Fig. 1 a schematic diagram of a circuit arrangement according to various embodiments; Figs. 2A and 2B each show a schematic visualization of a dithering technique as used in a method for operating a circuit according to various embodiments; Fig. 3 a flowchart of a method for operating a circuit arrangement according to various embodiments; Fig.Figure 4 shows a schematic diagram of a circuit arrangement in accordance with various embodiments; Figure 5 shows a flowchart of a method for operating a circuit arrangement in accordance with various embodiments; and Figure 6 shows a flowchart of a method for operating a circuit arrangement in accordance with various embodiments. Description The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be practiced. The word "exemplary" is used here to mean "serving as an example, instance, or representation." Any embodiment or design described herein as "exemplary" is not necessarily to be interpreted as preferred or advantageous over other embodiments or designs. Various aspects of the disclosure are provided for devices, and various aspects of the disclosure are provided for methods. It is to be understood that the basic properties of the devices also apply to the methods, and vice versa. Therefore, for the sake of brevity, duplicate descriptions of such properties may have been omitted. In various embodiments, the limitation described above, particularly the low clock frequency accuracy, can be overcome for a frequency control loop. The technique described below can improve the FLL accuracy to the range of parts per billion (ppb). To achieve high frequency accuracy, the value(s) of the least significant bit (LSB) applied to an oscillator for fine-tuning its frequency to a target frequency can be visualized as fractions of LSB values. This fraction can be achieved by switching between two or more fine-trim bits, depending on a calculated CLK frequency value. This method can also be referred to as "dithering." Dithering can be easily implemented in software and enables fast execution in real-time applications. In other words, fractions of LSB values ​​can be implemented using software methods in various embodiments. Implementing fractions of LSB values ​​in FLLs (or phase-locked loops (PLLs, see below)) can increase frequency accuracy. By incorporating a (hardware, e.g. silicon) phase detector, the technique, which is explained in detail below, can be extended to software phase control loops in various embodiments. In various embodiments, the precise clocks provided can help support multiple communication interfaces, even when a system-on-a-chip (SoC) is in a low-power state. In various implementations, the dithering concept can provide a way to achieve accurate clocks even in very low-power states. This concept can thus help support communication interfaces even in very low-power states. Furthermore, this concept can help minimize the power required by an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), or, more generally, a system operating in a low-power mode, by eliminating the need to provide a crystal clock or other accurate clock source in low-power modes. Fig. 1 shows a schematic diagram of a circuit arrangement 100 in accordance with various embodiments. Fig. 2A and Fig. 2B show schematic visualizations 200a and 200b, respectively, of a dithering technique as used in a method for operating a circuit in accordance with various embodiments. Fig. 3 shows a flowchart 300 of a method for operating a circuit arrangement in accordance with various embodiments. As shown in Fig. 1, the circuit arrangement 100, which can implement a FLL, can include semiconductor (e.g., silicon) hardware (represented by the white boxes and the dashed boxes) and corresponding software (indicated by the light gray boxes). The circuit arrangement 100 can include a reference clock circuit 102, an oscillator 104 controlled by a trim value, a counter 106, and a processor 108. In various embodiments, the software can be installed as hard-coded firmware. In other embodiments, the software can be installed via a (standard) programming interface. The reference clock circuit 102 can be configured to provide a reference clock signal REFCLK, which can have a precise reference clock frequency. The reference clock signal REFCLK can be provided to the processor 108. Typically, the reference clock signal REFCLK can be generated by an external crystal oscillator. Depending on the platform, the clock frequency accuracy can be as low as 100 ppb (parts per billion). The reference clock signal REFCLK can commonly be subdivided down to a low frequency to improve the measurement resolution of an output clock signal CLK (i.e., with a CLK frequency), which can be provided by the oscillator 104. Oscillator 104 can be configured to generate an output clock signal CLK. This output clock signal CLK can be provided to counter 106. Oscillator (OSC) 104 can be configured so that its frequency is controlled by coarse and fine trim register bits. Oscillator 104 can also support dynamic updates of its coarse and fine trim register bits. The registers can be accessed by software. In other words, oscillator 104 can be configured so that its frequency is controlled by software. Counter 106 can be a low-power timer ("timer") that can be configured to operate on the CLK provided by the oscillator. Counter 106 can also be started / stopped via a software-accessible register. The counter value of counter 106 can be dynamically updated on a read-only register. Counter 106 can be configured to count a number of Nmeas of clock cycles of the output clock signal CLK. A time period for counting can be provided by processor 108, which can send both a start and a stop signal indicating the start and end of the time period, respectively. The at least one processor 108 can be configured to set the time span based on the reference clock signal REFCLK and to repeat the following for successive time spans: determining the number Nmeas of clock cycles of the output clock signal CLK using the counter 106, determining a ratio between a target number N of clock cycles of the output clock signal and the determined number Nmeas of clock cycles of the output clock signal CLK, and applying a time-span averaged fractional value of a least significant bit of the trim value by switching back and forth, depending on the ratio, of the least significant bit between a high value LSBH and a low value LSBL. The at least one Processor 108 can be configured, by being equipped with software for performing the functions, to perform its functions described above and possibly other functions. At least one processor 108 can be part of a standby controller or processing core that can always be active, i.e., even in the lowest-power operating mode supported by the circuit 100, which can be, for example, part of an application-specific integrated circuit (ASIC), a microcontroller (µC), or a corresponding system or communication interface. The FLL can primarily operate on this standby controller or processing core. As shown in Fig. 1, at least one processor 108 can contain software (also called a trigger source) for triggering the determination (e.g., counting) of the number of clock cycles Nmeas of the output clock signal CLK (indicated by the "Trigger" box; the triggering itself is indicated by the "Start / Stop" arrow). The trigger source can be controlled by software running on the processor 108 of the standby control. For example, the trigger source can be implemented as dual-buffer FLOTS within a semiconductor (e.g., silicon) register, thereby providing software with low-latency start / stop triggers for the counter 106 (also referred to as the timer). Cyclically refreshed mirroring of the read-only register for the timer count value can also be supported. The reference clock REFCLK, provided by the reference clock circuit 102 for the processor 108, can be used as an input parameter for software that can be configured to calculate the time interval, for example, as an integer multiple k of the duration TREF of the reference clock signal REFCLK. In other words, the time interval can have a length of TREF × k. This is visualized in Fig. 2A and Fig. 2B, where the time interval is labeled "Comparison Time (TREF * k)". In various embodiments, the time interval can be as long as possible with respect to an application for which the controlled clock CLK is provided (the integer k can be as high as possible). The longer the time interval (i.e., the higher k), the more accurate the frequency of the CLK signal can be. However, this only applies to the time average, where the time over which the frequency is averaged corresponds to the time interval. Thus, the time interval TREF × k can be determined, for example, by...B. by the processor 108, that it is short enough so that a negative impact on the application caused by an excessively slow update of the frequency of the clock signal CLK can be avoided. The processor 108 can also include software for determining (e.g., calculating) the ratio between the target number of clock cycles N of the output clock signal and the determined number of clock cycles Nmeas of the output clock signal CLK. The target number of clock cycles N and the determined number of clock cycles Nmeas of the output clock signal CLK can be provided to the processor 108 as input parameters for the software by the counter 106. In Figures 2A and 2B, the difference between the target number of clock cycles N of the output clock signal CLK and the measured number of clock cycles Nmeas of the output clock signal CLK is denoted as E. The processor 108 can also include software for controlling the oscillator 104, in other words, for providing several control parameters—the trim value—for the oscillator 104. The control parameters can be calculated by the software to apply a time-averaged fractional value of a least significant bit of the trim value by toggling the least significant bit between a high value LSBH and a low value LSBL, depending on the ratio between the target number of clock cycles N of the output clock signal and the specified number of clock cycles Nmeas of the output clock signal CLK. The toggling in this context can be understood as at least one toggling from the low value LSBL to the high value LSBH of the least significant bit, or vice versa.The fractional value averaged over the time period can correspond to the trim value that the oscillator 104 needs to be trimmed to the target number of clock cycles N (which corresponds to a target frequency). As shown in Fig. 2A and Fig. 2B, switching the least significant bit back and forth between a high value LSBH and a low value LSBL can divide the time interval into a high phase, which lasts for a first integer number N1 of clock cycles of the output clock signal CLK, during which the least significant bit has the high value LSBH, and a low phase, which lasts for a difference N-N1 between the target number N of clock cycles of the output clock signal CLK and the first integer number N1, during which the least significant bit has the low value LSBL. This allows the oscillator 104 to be controlled to have a first (e.g., higher) frequency during the high phase and a second (e.g., lower) frequency during the low phase.Averaged over the time interval TREF× k, the frequency can have a fractional value between the frequencies corresponding to the low value LSBL and the high value LSBH of the least significant bit, and this fractional value of the frequency can be much closer to the target frequency than either of the frequencies corresponding to the low value LSBL and the high value LSBH of the least significant bit. Trim parameters, calculated by the processor 108 and provided to the oscillator 104 for trimming the oscillator to the predefined target number of clock cycles N, can include or consist of the low value of the least significant bit LSBL, the high value of the least significant bit LSBH, and the first integer N1. In various embodiments, the high phase can be a single continuous phase, and / or the low phase can be a single continuous phase. In other words, switching back and forth between the high phase and the low phase can only occur during the time interval. In various embodiments, each time interval can be started in the same phase (e.g., the high phase or the low phase), so that further switching back and forth can be applied at one end of the time interval or at the beginning of a subsequent time interval. This is shown, for example, in Fig. 2A, where a fine-trim value TREF× k (“reference time”) is switched to LSBH at the beginning of each time interval. In various embodiments, for example, in a case where at least one of N1 and (N-N1) is even-numbered, the high phase can be formed by several non-continuous phase segments, and / or the low phase can be formed by several non-continuous phase segments. In other words, more than one switching operation can be performed during the time interval. In the case where both N1 and (N-N1) are even-numbered, both the high phase and the low phase can be divided into two or more non-continuous phase segments. In various embodiments, as shown for example in Fig. 2A, continuous time spans TREF× k can be separated by time intervals Tc, during which the trim parameters can be calculated. After the end of the calculation time interval Tc, which coincides with the beginning of the time span in which the fine-trim value is set to LSBH at the beginning of each time span TREF× k, the fine-trim value can be set to a starting value (LSBH in Fig. 2A) and switched to the other fine-trim value later during the time span, e.g., after N1 cycles, as shown in Fig. 2A. In various embodiments, successive time intervals TREF× k can follow each other directly without an intervening computation time interval Tc. This can occur, for example, if no recalculation of the trim parameters is performed for several consecutive time intervals TREF× k. The recalculation can be deliberately omitted, for example, after an initial calibration process (the calibration process is explained in more detail in the context of Fig. 3). Another requirement that can be enforced for deliberately omitting the recalculation of the trim parameters is that the time since the last calculation, also known as an inner loop time (ILT), can be below a predefined limit. An inner loop time limit can be, for example, in a range of approximately 10 ms to approximately 1000 ms, e.g., from approximately 50 ms to approximately 500 ms, e.g., approximately 100 ms. During this time, the reference clock may not be required, so the reference clock circuit 102 can be switched off, or at least the reference clock REFCLK cannot be requested.This means that at least one processor 108 can be configured to turn off the reference clock REFCLK after several time intervals TREF× k, and can be configured to turn the reference clock REFCLK back on after a predetermined elapsed time, e.g. the inner loop time ILT. The processor 108 can also be configured to enforce regular recalibrations, for example after a predefined elapsed time of the frequency control loop running, for example after between about 10 and 100 inner loops, e.g. after between about 100 ms (for an ILT of 10 ms and 10 inner loops) and about 100 s (for an ILT of 1 s and 100 inner loops). Energy can be saved by omitting the recalculation of the trim parameters. Instead of recalculating the trim values ​​(the low value LSBL, the high value LSBH, and the first integer N1), they can be retrieved from the register where they are stored and updated after each calculation. In other words, at least one processor 108 can be configured, in a case where no reference clock signal REFCLK is provided, to control the oscillator 104 using the high value LSBH, the first integer N1, and the low value LSBL as stored in the register. In various embodiments, recalculation can also be omitted in cases where the reference clock REFCLK is not provided, for example, due to a fault in the reference clock circuit 102. In this case, the trim parameters can be retrieved from the register as long as necessary until the functionality of the reference clock circuit 102 is restored. However, a warning message can be generated, for example, if the time during which the reference clock REFCLK is not provided exceeds a predefined limit, e.g., several seconds or longer. Another example of achieving directly continuous time intervals involves performing the calculation of the trim parameters resulting from a previous time interval during the current time interval and, for example, upon completion of the calculation process or at a suitable later time during the TREF× k time interval, performing the back-and-forth switching. An example of this is shown in Fig. 2B. The dithering concept is visualized in Fig. 2A and Fig. 2B (with reference to Fig. 1). The software (“trigger”) can trigger the start of counter 106 (“timer”) to begin counting the number of CLK clock cycles within the time interval corresponding to k reference clock cycles REFCLK. Since a REFCLK period is known and fixed, the software (“processor computation” 108) can estimate the target number N of CLK cycles to obtain a target (average) frequency for CLK. The value of N can be given by During the time interval TREF×k (also referred to as the "reference time" or "reference cycle"), the software may be able to measure (e.g., count) the number Nmeas of CLK clock cycles based on the count values ​​of counter 106 ("timer"). If the mean frequency of CLK is not equal to the target frequency, this may result in an error E in the number of CLK cycles, as shown in Figures 2A and 2B. The relationship between N, E, and Nmeas can be given as It is noted that E can be either positive or negative. During the first few comparison cycles, the software can adjust the integer fine-trim value until the measured error, E, translates into a fine-trim value of a fraction of the LSB. In other words, the integer fine-trim value can be adjusted until, using LSBL, Nmeas is less than the target number of cycles N, and, using LSBH, Nmeas is greater than N, or vice versa. The software can then calculate the LSBH, LSBL, and N1 values ​​so that the required (time-averaged) fraction of the fine-trim (or LSB) value is LSBavist, where N1 is the first integer. In various embodiments, cycle counting to implement fine-trim changes from LSBH to LSBL or vice versa can be performed by having the software directly read the count values ​​determined by counter 106. A software latency for applying these changes is typically on the order of a few microseconds (this may depend on the standby control machine clock cycles). The impact of an error introduced due to such latency can be minimized by maximizing the k-value for a given application, e.g., as described above. In its flowchart 300, Fig. 3 shows a method for operating a circuit arrangement, for example the circuit arrangement 100, in accordance with various embodiments. Various processes can be carried out as described above in the context of Fig. 1, Fig. 2A and Fig. 2B. However, some specific aspects are further explained in the context of Fig. 3. After a start of an execution of the procedure (330), the reference clock REFCLK can be requested (see 332), for example, by processor 108. Furthermore, an LSB step can be calibrated: A key factor in calculating the required LSB value to achieve the target frequency (or the target number of counts N) can be the actual LSB step size (i.e., a number of cycles per LSB step size) for a given (e.g., hardware) part under operating conditions. The LSB step size can be calculated by subtracting the difference between Nmeas with LSBL+1 and Nmeas with LSB. Therefore, it may require at least two comparison cycles to determine the actual step size, and this process is called calibration. Simultaneously (also at 332), an outside loop time OLT, which can be used to track the approximate time at which the LSB step size calibration needs to be recalculated, can be initialized (set to zero). An FLL / dithering-based comparison (e.g., as described above) can be performed (see 334) until an error E is below a predetermined allowable error, minE (in other words, until |E| < minE, see 336). Upon starting the FLL frequency control loop, the inner-loop time ILT, which can be used to track the approximate time at which the dithering values ​​(LSBH, LSBL, N1) should be recalculated, can be initialized (see 334). In various embodiments, the dithering values ​​(LSBH, LSBL, N1), once calculated, can be applied periodically (338, 340, 344) until a recalculation of new FLL dithering values ​​is necessary (when the inner loop time ILT exceeds a predetermined limit). Typically, it may be necessary to update the dithering values ​​(LSBH, LSBL, N1) approximately every 100 ms (which may depend on the application, the hardware used, etc.). Similarly, recalibration of the LSB step size (see 246) may be required approximately every few seconds due to changes in operating conditions (temperature, voltage, etc.). Fig. 5 shows a flowchart 500 of a method for operating a circuit arrangement in accordance with various embodiments. The procedure may include providing a reference clock signal (in 510), setting a time interval based on the reference clock signal (in 520), generating an output clock signal (in 530), and repeating the following for successive time intervals: counting a number of clock cycles during the time interval, determining a ratio between a target number of clock cycles of the output clock signal and the counted number of clock cycles of the output clock signal, and applying a time-interval averaged fractional value of a least significant bit of the trim value by switching back and forth, depending on the ratio of the least significant bit between a high value and a low value (in 540). Fig. 4 shows a schematic diagram of a circuit arrangement 400 in accordance with various embodiments. The circuit arrangement 400 may be similar to the circuit arrangement 100, and many of the hardware and software components and their respective functions may be identical or similar to those of the circuit arrangement 100. For the sake of brevity, repeated descriptions are kept to a minimum, and mainly differences from the circuit arrangement 100 are presented. While the frequency control loop using the dithering concept, as implemented, for example, by circuit arrangement 100 and the method described in the context of Fig. 3 and Fig. 5, can correct frequency errors in a given time period, a phase-locked loop (PLL)-based implementation can be configured to track a phase (and thus a frequency) with respect to a reference clock REFCLK. Fig. 4 shows a circuit arrangement 400 implementing such a phase-locked loop, and Fig. 6 shows a flowchart 600 of a corresponding method. The circuit arrangement 400 can include a reference clock circuit 102 configured to provide a reference clock signal REFCLK, an oscillator 104 controlled by a trim value and configured to generate an output clock signal CLK, a counter 106 configured to count a number of clock cycles Nmeas of the output clock signal CLK, at least one processor 108 configured to set a time interval based on the reference clock signal REFCLK, and a phase determination circuit 442 configured to determine a phase relationship between the reference clock signal REFCLK and the output clock signal CLK and to provide the phase relationship information to the at least one processor 108, wherein the at least one processor 108 can further be configured to repeat the following for successive time intervals: determining the number Nmeas of clock cycles of the output clock signal using the counter 108,Determining a ratio between a target number N of clock cycles of the output clock signal CLK and the determined number Nmeas of clock cycles of the output clock signal CLK, and applying a time-averaged fractional value of a least significant bit of the trim value by switching back and forth, depending on the ratio and phase relationship information, of the least significant bit between a high value LSBH and a low value LSBL. The circuit 400 may further include a divider 440, e.g. a hardware divider, which may be configured to divide the reference clock signal REFCLK so that the reference clock signal REFCLK can be provided both to the processor 108 (to be used as a basis for setting the time span) and to the phase determination circuit 442 (as a basis for determining the phase). As an extension to the frequency control loop, after reaching or approaching the phase-lock condition using the FLL circuit, the phase difference between the output clock signal CLK and the REFCLK provided by the divider 440 can be converted into digital phase information by a hardware (e.g., semiconductor, silicon) block (e.g., circuit) called a phase-frequency detector (PFD). The digital phase information can be low-pass filtered and, together with N and Nmeas information, calculated to arrive at the dithering values ​​(LSBH, LSBL, and N1). Fig. 6 shows a flowchart 600 of a method for operating a circuit arrangement in accordance with various embodiments. The procedure may include providing a reference clock signal (in 610), setting a time interval based on the reference clock signal (in 620), generating an output clock signal (in 630), and repeating the following for successive time intervals: counting a number of clock cycles of the output clock signal during the time interval, determining a phase relationship between the reference clock signal and the output clock signal, determining a ratio between a target number of clock cycles of the output clock signal and the determined number of clock cycles of the output clock signal, and applying a time-interval averaged fractional value of the least significant bit of the trim value by switching back and forth, depending on the ratio and phase relationship information, of the least significant bit between a high value and a low value (in 640). Several examples are presented below: Example 1 is a circuit arrangement. The circuit arrangement can include a reference clock circuit configured to provide a reference clock signal, an oscillator controlled by a trim value and configured to generate an output clock signal, a counter configured to count a number of clock cycles of the output clock signal, and at least one processor configured to set a time interval based on the reference clock signal and, for successive time intervals, to: determine a number of clock cycles of the output clock signal using the counter, determine a ratio between a target number of clock cycles of the output clock signal and the determined number of clock cycles of the output clock signal, and apply a time-interval-averaged partial value of a least significant bit of the trim value by toggling back and forth, depending on the ratio.of the least significant bit between a high value and a low value. In Example 2, the subject of Example 1 can optionally include the switching back and forth dividing the time span into a high phase, which lasts a first integer number of clock cycles during which the least significant bit has the high value, and a low phase, which lasts a difference between the target number of clock cycles of the output clock signal and the first integer number during which the least significant bit has the low value. In Example 3, the subject of Example 2 can optionally include that the high phase is a single continuous phase and / or the low phase is a single continuous phase. In Example 4, the subject of Example 2 may optionally include the fact that the high phase is formed by several non-continuous phase segments and / or that the low phase is formed by several non-continuous phase segments. In Example 5, the subject of one of Examples 2 to 4 can optionally contain a register configured to store the high value, the first integer count, and the low value. In Example 6, the subject of Example 5 may optionally include that at least one processor is further configured, in a case where no reference clock signal is provided, to control the oscillator using the high value, first integer and low value as stored in the register. In Example 7, the subject of Example 6 may optionally include the fact that the reference signal is not provided due to at least one processor configured to turn off the reference clock after several time intervals. In Example 8, the subject of Example 7 can optionally include that at least one processor is configured to reactivate the reference clock after a predetermined elapsed time. In Example 9, the subject of Example 8 can optionally include that the predetermined elapsed time is in a range between 10 ms and 1 second. In Example 10, the subject of one of the preceding examples may optionally include that the target number of clock cycles of the output clock signal, the time-averaged fractional value LSBav, the high value LSBH, the low value LSBL, and the first integer are related by LSBav = (LSBH × N1)+LSBL × (N-N1)) / N. Example 11 is a microcontroller. The microcontroller can contain the circuit arrangement of any of the preceding examples. Example 12 is a communication interface. The communication interface can contain the circuit arrangement of any of the preceding examples. Example 13 is a circuit arrangement. The circuit arrangement may include a reference clock circuit configured to provide a reference clock signal, an oscillator controlled by a trim value and configured to generate an output clock signal, a counter configured to count a number of clock cycles of the output clock signal, at least one processor configured to set a time interval based on the reference clock signal, and a phase determination circuit configured to determine a phase relationship between the reference clock signal and the output clock signal and to provide the phase relationship information to the at least one processor, wherein the at least one processor is further configured to repeat the following for successive time intervals: determining a number of clock cycles of the output clock signal using the counter,Determining a ratio between a target number of clock cycles of the output clock signal and the specified number of clock cycles of the output clock signal, and applying a time-averaged fractional value of a least significant bit of the trim value by switching back and forth between a high value and a low value, depending on the ratio and phase relationship information of the least significant bit. In Example 14, the subject of Example 13 may optionally include that the phase detector is a phase-frequency detector. In Example 15, the subject of Example 13 or 14 may optionally include the fact that the controller is further configured to low-pass filter the phase information. Example 16 is a method for operating a circuit arrangement. The method may include providing a reference clock signal, setting a time interval based on the reference clock signal, generating an output clock signal, and repeating the following for successive time intervals: counting a number of clock cycles during the time interval, determining a ratio between a target number of output clock cycles and the counted number of output clock cycles, and applying a time-interval-averaged fractional value of a least significant bit of the trim value by toggling back and forth, depending on the ratio of the least significant bit between a high value and a low value. In Example 17, the subject of Example 16 may optionally include the switching back and forth dividing the time span into a high phase, which lasts a first integer number of clock cycles during which the least significant bit has the high value, and a low phase, which lasts a difference between the target number of clock cycles of the output clock signal and the first integer number during which the least significant bit has the low value. In Example 18, the subject of Example 17 may optionally include that the high phase is a single continuous phase and / or that the low phase is a single continuous phase. In Example 19, the subject of Example 18 may optionally include the fact that the high phase is formed by several non-continuous phase segments and / or that the low phase is formed by several non-continuous phase segments. In Example 20, the object of one of Examples 17 to 19 may optionally also contain storage of the high value, the first integer, and the low value. In Example 21, the subject of Example 20 may optionally include, in a case where the reference clock signal is not provided, controlling the oscillator using the stored high value, first integer, and low value(s). In Example 22, the subject of Example 20 or 21 may optionally also include switching off the reference clock after several time intervals before controlling the oscillator using the stored high value, first integer and low value(s). In Example 23, the subject of Example 22 can optionally also include the reactivation of the reference clock after a predetermined elapsed time. In Example 24, the subject of Example 20 may optionally include that the predetermined elapsed time is in a range between 10 ms and 1 s. In Example 25, the subject of one of Examples 16 to 24 may optionally include that the target number of clock cycles of the output clock signal, the time-averaged fractional value LSBav, the high value LSBH, the low value LSBL and the first integer N1 are related by LSBav = (LSBH × N1)+LSBL × (N-N1)) / N Example 26 is a method for operating a circuit arrangement. The method may include providing a reference clock signal, setting a time interval based on the reference clock signal, generating an output clock signal, and repeating the following for successive time intervals: counting a number of clock cycles of the output clock signal during the time interval, determining a phase relationship between the reference clock signal and the output clock signal, determining a ratio between a target number of clock cycles of the output clock signal and the determined number of clock cycles of the output clock signal, and applying a time-interval-averaged fractional value of the least significant bit of the trim value by toggling, depending on the ratio and phase relationship information, the least significant bit between a high value and a low value. Although the invention has been shown and described in particular with reference to specific embodiments, it is understood by those skilled in the art that various changes to its form and details can be made without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus defined by the appended claims, and all modifications that fall within the meaning and equivalence of the claims,

Claims

Circuit arrangement (100) comprising: a reference clock circuit (102) configured to provide a reference clock signal (REFCLK); an oscillator (104) controlled by a trim value and configured to generate an output clock signal (CLK); a counter (106) configured to count a number (Nmeas) of clock cycles of the output clock signal (CLK); and at least one processor (108) configured to set a time span based on the reference clock signal (REFCLK), repeating for successive time spans: determining a number (Nmeas) of clock cycles of the output clock signal (CLK) using the counter, determining a ratio between a target number (N) of clock cycles of the output clock signal (CLK) and the determined number (Nmeas) of clock cycles of the output clock signal (CLK), and applying a time-span averaged fractional value of a least significant bit of the trim value by switching back and forth.depending on the ratio of the least significant bit between a high value (LSBH) and a low value (LSBL), wherein the switching divides the time interval into a high phase, which lasts a first integer number of clock cycles during which the least significant bit has the high value (LSBH), and a low phase, which lasts a difference between the target number (N) of clock cycles of the output clock signal (CLK) and the first integer number during which the least significant bit has the low value; and wherein the circuit arrangement (100) further comprises a register configured to store the high value (LSBH), the first integer, and the low value (LSBL). Circuit arrangement (100) according to claim 1, wherein the high phase is a single continuous phase and / or the low phase is a single continuous phase. Circuit arrangement (100) according to claim 1 or 2, wherein the at least one processor (108) is further configured to control the oscillator (104) in a case where no reference clock signal (REFCLK) is provided, using the high value (LSBH), first integer and low value (LSBL) as stored in the register. Circuit arrangement (100) according to claim 3, wherein the at least one processor (108) configured to switch off the reference clock after several time intervals causes the reference signal to be unavailable. Circuit arrangement (100) according to claim 4, wherein the at least one processor (108) is configured to reactivate the reference clock after a predetermined elapsed time. Circuit arrangement (100) according to one of the preceding claims, wherein the target number (N) of clock cycles of the output clock signal (CLK), the time-averaged fractional value LSBav, the high value LSBH, the low value LSBL and the first integer N1 are related as: LSBav = ( LSBH × N1 ) + LSBL × ( N − N1 ) ) / N Microcontroller comprising: the circuit arrangement (100) according to any of the preceding claims. Communication interface comprising: the circuit arrangement (100) according to any of the preceding claims. Circuit arrangement (400) comprising: a reference clock circuit (102) configured to provide a reference clock signal (REFCLK); an oscillator (104) controlled by a trim value and configured to generate an output clock signal (CLK); a counter configured to count a number (Nmeas) of clock cycles of the output clock signal (CLK); at least one processor (108) configured to set a time interval based on the reference clock signal (REFCLK); and a phase determination circuit (442) configured to determine a phase relationship between the reference clock signal (REFCLK) and the output clock signal (CLK) and to provide the phase relationship information to the at least one processor (108);wherein the at least one processor (108) is further configured to repeat the following for successive time intervals: determining a number (Nmeas) of clock cycles of the output clock signal (CLK) using the counter, determining a ratio between a target number (N) of clock cycles of the output clock signal (CLK) and the determined number of clock cycles of the output clock signal (CLK), and applying a time-interval averaged fractional value of a least significant bit of the trim value by switching back and forth, depending on the ratio and phase relationship information, of the least significant bit between a high value (LSBH) and a low value (LSBL);wherein the switching back and forth divides the time interval into a high phase, which lasts a first integer number of clock cycles during which the least significant bit has the high value (LSBH), and a low phase, which lasts a difference between the target number (N) of clock cycles of the output clock signal (CLK) and the first integer number during which the least significant bit has the low value (LSBL); and wherein the circuit arrangement (400) further comprises a register configured to store the high value (LSBH), the first integer, and the low value (LSBL). Circuit arrangement (400) according to claim 9, wherein the phase detector is a phase-frequency detector. Method for operating a circuit arrangement comprising: providing a reference clock signal (510); setting a time interval based on the reference clock signal (520); generating an output clock signal (530); and repeating for successive time intervals: counting a number of clock cycles during the time interval;Determining a ratio between a target number of clock cycles of the output clock signal and the counted number of clock cycles of the output clock signal, and applying a time-averaged fractional value of a least significant bit of the trim value by switching back and forth, depending on the ratio of the least significant bit between a high value and a low value (540), wherein the switching back and forth divides the time span into a high phase, which lasts a first integer number of clock cycles during which the least significant bit has the high value, and a low phase, which lasts a difference between the target number of clock cycles of the output clock signal and the first integer number during which the least significant bit has the low value; furthermore comprising storing the high value, the first integer, and the low value in a register. Method according to claim 11, wherein the high phase is a single continuous phase and / or the low phase is a single continuous phase. The method of claim 11 or 12, further comprising: in a case where the reference clock signal is not provided, controlling the oscillator using the stored high value, first integer and low value(s). Method according to one of claims 11 to 13, further comprising: switching off the reference clock after several time intervals before controlling the oscillator using the stored high value, first integer and low value. The method of claim 14, further comprising: reactivating the reference clock after a predetermined elapsed time. A method according to any one of claims 11 to 15, wherein the target number of clock cycles of the output clock signal, the fractional value LSBav averaged over the time span, the high value LSBH, the low value LSBL and the first integer N1 are related as: LSBav = ( LSBH × N1 ) + LSBL × ( N − N1 ) ) / N A method for operating a circuit arrangement comprising: providing a reference clock signal (610); setting a time interval based on the reference clock signal (620); generating an output clock signal (630); and repeating for successive time intervals: counting a number of clock cycles of the output clock signal during the time interval; determining a phase relationship between the reference clock signal and the output clock signal; and determining a ratio between a target number of clock cycles of the output clock signal and the determined number of clock cycles of the output clock signal; and applying a time-interval-averaged fractional value of a least significant bit of the trim value by switching back and forth, depending on the ratio and phase relationship information, of the least significant bit between a high value and a low value (640);wherein the switching back and forth divides the time span into a high phase, which lasts a first integer number of clock cycles during which the least significant bit has the high value, and a low phase, which lasts a difference between the target number of clock cycles of the output clock signal and the first integer number during which the least significant bit has the low value; furthermore comprising storing the high value, the first integer and the low value in a register.

Images