Synchronizing the update of day counters using time stamp exchange via a control level

Abstract

Method comprising: Distributing a clock signal from a time control card (109, 110, 209, 403, 503, 607, 707, 708, 905) to a first line card and to a second line card via a backplane; Performing a timestamp exchange (709) between the first line card and the second line card using a control plane (701) coupled to the first and second line cards; and Synchronizing a second daytime counter on the second line card with a first daytime counter on the first line card based on the timestamp exchange (709) and the clock signal, wherein the synchronization is performed without using a 1 pulse per second (PPS) signal.

Description

BACKGROUND Area of ​​the invention

[0001] This invention relates to time control synchronization using a control plane for exchanging timestamps. Description of the state of the art

[0002] Currently, 1 pulse per second (PPS) signals generated by different disks in a distributed system must be synchronized so that they occur almost simultaneously across the entire system. Because these 1 PPS signals are simultaneous, separate communication paths are required for each source of these 1 PPS signals. This presents two problems: (1) multiple dedicated communication paths are needed, and (2) the lengths of these paths to and from the central timing board are not identical, adding an uncompensated delay and causing misalignment. Control and coordination of these systems is performed over yet another shared communication channel, adding even more uncertainty. Reducing this uncertainty would improve system timing synchronization. BRIEF SUMMARY OF THE FORMATIONS OF THE INVENTION

[0003] To achieve accuracy for Time of Day (ToD) distribution to master line maps, existing resources are used to update ToD counters.

[0004] Accordingly, in one embodiment, a method involves distributing a clock signal from a time control card to a first line card and to a second line card via a backplane. A second timestamp exchange is performed between the first and second line cards using a control plane coupled to both. A second daily time counter on the second line card is synchronized with the first daily time counter on the first line card based on the timestamp exchange and the clock signal, without requiring a 1 pulse per second signal.

[0005] In another embodiment, a device includes a first line card with a first daily time counter and a second line card with a second daily time counter. A time control card is configured to provide a clock signal to the first and second line cards via a backplane. A control plane couples the first and second line cards via the backplane. The first and second line cards are configured to perform a timestamp exchange, and the second line card is configured to synchronize the second daily time counter with the first daily time counter based on the timestamp exchange and a local clock frequency coupled to the clock signal distributed by the time control card.

[0006] In another embodiment, a method includes a slave line card that synchronizes timing with a grand master. A timing card synchronizes a system clock signal with the timing of the slave line card. The timing card distributes the system clock signal via a backplane to a plurality of line cards, including master line cards and the slave line card. The slave line card and one of the master line cards perform a timestamp exchange, and the master line card synchronizes the update of a second daytime counter in the master line card with a first daytime counter in the slave line card, based on the timestamp exchange and a local clock in the master line card coupled to the system clock signal. List of characters

[0007] The present invention and its numerous objectives, features and advantages, which are apparent to the person skilled in the art, can be better understood with reference to the accompanying drawings. Fig. Figure 1 shows an architecture for distributing Time-of-Day (ToD) from the Grandmaster 101 to the slave wiring card 103 . Fig. Figure 2 illustrates an embodiment in which delays between the master time control card and the line cards are determined using existing backplane communication paths. Fig. Figure 3 illustrates an embodiment in which a synchronous Ethernet path is used to determine track delay between the master timing control card and the slave line card. Fig. Figure 4 illustrates an embodiment in which delays between the master time control card and the master line cards are determined using existing backplane communication paths. Fig. Figure 5 illustrates an embodiment in which the delay between the master time control card and a master line card is determined using a synchronous Ethernet path. Fig. Figure 6 illustrates the limitation of asymmetry by using bidirectional buffers, so that the feedback path is identical to the transmission path. Fig. Figure 7 illustrates an embodiment in which a control plane is used to exchange timestamps. Fig. Figure 8 illustrates wasted bandwidth in a conventional use of the 1 PPS signal line. Fig. Figure 9 illustrates an embodiment in which a time information source provides the 1 PPS signals to the line cards and also carries information between the primary time control source and the line cards. Fig. Figure 10 illustrates a 1-second time information bus frame that is divided into multiple time windows. Fig. Figure 11 illustrates an example time window in a frame of the time information bus. Fig. Figure 12 illustrates the primary system clock loop and the PTP master clock loop.

[0008] The use of the same reference symbols in different drawings indicates similar or identical objects. DETAILED DESCRIPTION

[0009] Fig. Figure 1 shows an architecture for distributing time-of-day (ToD). 102 from the Grandmaster 101 to the slave wiring card 103The Slave line card ToD is used with the Grandmaster ToD. 104 Synchronization occurs through the exchange of timestamps according to the IEEE 1588 protocol. This exchange takes place at 105 shown. Each of the timestamps t1 - t4 represents the departure time ( t1 , t3 ) or the reception time ( t2 , t4 The timestamp exchange allows determination of the one-way delay (OWD) and the error offset, as in 107 shown. The slave unit shares information with the master time control card. 109 The system in Fig. 1 includes backup time control card 110 The slave line card 10 The master time control card delivers 109 a SyncE signal (signal line) 111Timestamps are exchanged between the slave line card and the master time control card to synchronize the master time control card clock signal with the timing of the slave line card, which in turn has been synchronized with the grandmaster. The master time control card provides a system clock (SysClk). 115 to the slave line card. The SysClk clocks the time stamper in the line card. A servo loop sets a controllable oscillator (such as a digitally controlled oscillator; DCO) in the master timing card to synchronize the SysClk in both frequency and phase with the timing of the slave line card. The master timing card also provides a 1 pulse per second (PPS) signal. 117ato the slave line card, which is synchronized with the Grandmaster's Time-of-Day (ToD) rollover via phase adjustment. The various ToD counters contain the same value and turnover at the same time based on the 1 PPS signal. The servo loop ensures that the slave line card and the Master Time Control card are synchronized. The Master Time Control card 109 also supplies the master line cards 121 with the SysClk 116 and the 1 PPS signal 118 Without a feedback mechanism, such as the servo loop used to synchronize the slave line card and the timing cards, the ToD distribution to the master line cards can be affected by, for example, track differences, path length differences, driver differences, voltage differences, and / or temperature differences between the timing card and the different master line cards. 121lacking the desired precision. Therefore, other circuit boards (master circuit boards) are used. 121 ), although the grandmaster receives the most accurate clock signal in the network and the master timing card and slave line card are synchronized, given the open loop distribution of the 1 PPS signal by the master timing card without compensation for different track delays between master line cards 121 and the master time card 109 and other differences between the line cards are not synchronized.

[0010] The embodiments described herein describe approaches for distributing the Time-of-Day (ToD) and the 1 PPS signal to master line cards in an IEEE 1588Central Timing Architecture. These methods address challenges such as (a) ToD and 1 PPS signal alignment across all line cards <1ns (+ / -500ps), (b) backboard track lengths need to be aligned or compensated, (c) backboard driver / receiver delay uncertainty needs to be considered in the timing budget, and (d) line card PLL I / O delay also needs to be considered in the budget.

[0011] Currently, aligning the ToD and 1PPS signals is a manual, cumbersome process in an open-loop control system. The approaches presented in this disclosure provide more accurate measurement and adjustment techniques in a closed-loop control system. Some embodiments utilize existing hardware and / or software infrastructure to distribute the ToD and 1PPS signals with <1 ns alignment accuracy across all line cards.

[0012] Fig. Figure 2 illustrates an embodiment in which delays between the master time control card and the line cards can be determined using existing backboard communication paths between the time control card and the line cards. Fig. Figure 2 shows the slave line diagram. 203 and the master time card 209 In the embodiment in Fig. 2. A synchronous packet-based communication network exists, such as synchronous Ethernet (SyncE) and IEEE 1588, between the master time control card. 209 and the slave line card 203 In Fig. 2 includes the connection between the time control card 209 and the slave line card 203 Tx SyncE 221 and Rx SyncE 223 To determine the track delay, one approach measures the round-trip time for a signal from the timing control card. 209 to the slave line card 203was sent, and return to the time control map via path 231 Thus, it sends in Fig. 2 the master time card 209 a signal, such as a pulse, via the 1 PPS signal line 225 and the slave line card 203 The signal is routed via the Rx SyncE path. 223 back again. The line card can be configured to switch to a test mode to feed back the received pulse and allow the trace delay to be determined. The trace delay to the slave line card 203 is considered half the round-trip time for the impulse from the timing card 209 The output is assumed to be accurate. The measured track delays can be taken into account on the line map to provide higher accuracy in the 1 PPS signal.

[0013] Fig. Figure 3 illustrates an embodiment in which the time control card transmits the SyncE signal line. 221used to send the test signal, and SyncE receive signal line 223 used to receive the feedback signal from the slave line card 203 to receive. The track delay to the line map can be expressed as half the round-trip time over the path. 233 for the impulse that comes from the time control card 209 Assume it is issued.

[0014] Fig. 4 and Fig. Figure 5 illustrates that the identical approach can be used for all master circuit boards on the backboard, not just the slave circuit board. Fig. Figure 4 shows how the 1 PPS signal line is used for the transmit path, and the Rx SyncE path is used for the return path to eliminate trace delays between the master line card. 401 and the time control card 403 using path 431 to eat. Fig. Figure 5 shows how the Tx SyncE signal line is used for the transmit path and the Rx SyncE for the return path. 531 is used to determine the track delays between the master line card 501 and the time control card 503 to measure the track delays between the additional master line cards. 409 and 509 , which in Fig. 4 and Fig. 5 will be shown, and the time control card will be measured in the same way.

[0015] An assumption that is relevant to the in Fig. 2, Fig. 3, Fig. 4 and Fig. The difference made in the five illustrated embodiments is that the forward and return paths are symmetrical. A lack of symmetry in the forward and return paths can lead to errors in the trace delay compensation performed by the line cards based on round-trip measurements. Referring to Fig. 6 is one way to limit asymmetry, the use of bidirectional buffers. 601 and 603 for the 1 PPS signal line (or the Tx SyncE signal line), so that the feedback path is identical to the transmit path. In a test mode, the test pulse that is sent to the slave line card 605 is received through the bidirectional buffer 603 to the time control card 607 returned.

[0016] This allows round-trip delay through existing backboard communication paths to be measured for each line card at startup and other suitable times, and compensation can be performed based on these round-trip measurements. This improves the alignment of ToD and 1 PPS using both manual and open-loop processes.

[0017] Fig. Figure 7 illustrates another embodiment to achieve higher accuracy for ToD distribution to master circuit boards. In one embodiment, the system works 700 as a Telecom Boundary Clock (TBC) at the edge of a larger system, but the teachings of the implementation of Fig. 7 can be used in multiple environments. The embodiment of Fig. 7 includes a control plane used for exchanging timestamps. Physically, the control plane can be a backboard communication path, and the circuit boards are physically connected to the control plane via wiring or other electrical / optical connections to the bottom board. As in Fig. As illustrated in Figure 7, the control plane may further include circuitry, such as field-programmable gate arrays (FPGAs) and processors, to perform necessary functions, such as switching and transparent clocking, as described in more detail herein. The intelligence required by the control plane may be located directly on the backplane or on a printed circuit board that is plugged into or wired to the backplane. The control plane may, for example, utilize various high-speed communication protocols according to the system requirements. In some embodiments, the control plane is a network-based Ethernet. In other embodiments, instead of a backplane, the various components in the system may be integrated circuits coupled to a mainboard, and the control plane may provide communication between the various components via the mainboard.

[0018] system 700It also includes a slave line card. 703 , Master line cards 705 and master time card 707 and a backup time control card 708 If the slave line card 703 If it fails, the system switches to using one of the master line cards. 705 than the slave card. This is possible because there are inputs and outputs at the control level for each line card. Thus, infrastructure for sharing timestamps between all line cards and the time control card is in place. 707 available. Although in Fig. Not shown in Figure 7, in embodiments the time control card is also coupled to the control plane. The use of the control plane, which is available to all line cards in the system, allows the control plane to use timestamps to align all of the ToD counters in the master line cards. In one embodiment, the slave line card synchronizes703 their ToD counter (ToD A ) with the Grandmaster (GM). This can be done in a way that is appropriate for the person responsible for the in Fig. The system described in the illustration is similar. 1 The PPS signal is normally used to synchronize the 1-second rollover of the ToD counter. However, the control plane allows the system to synchronize day-of-day counters by exchanging timestamps, as in... 709 shown.

[0019] Assuming the slave line card 703 is with the Grandmaster (in Fig. (7 not shown) synchronized and the master time control card 707 This is in turn linked to the timing of the slave line card by using a clock signal at Rx SyncE. 712 synchronized. The network processor 710(also referred to herein as a host processor) in the slave line card (or another control processor) controls the 1588 timestamp exchange with the grandmaster. The phase-locked loop (PLL) 716 generates the system clock signal 711 , which is synchronized with the timing of the slave line card.

[0020] The time control card distributes a system clock signal. 711 through the backboard 715 (or mainboard) to all of the line cards, including slave line card 703 and the master line maps 705 The circuit boards are connected to the system clock. 711 through their PLLs 718 Frequency-coupled. Each of the master line cards 705 Includes a ToD counter that requires synchronization. One of the master line cards. 705 includes, for example, a ToD counter. B The slave line card 703 initiates a timestamp exchange709 via the control level with one of the master line cards 705 , to the death A -Counter and ToD B -counters to synchronize, but with the advantage that master and slave synchronize at the same frequency using the existing backboard frequency distribution of the system clock. 711 work. Based on the timestamp exchange, the one-way delay ( ( t 2 − t 1 ) + ( t 4 − t 3 ) 2 ) and error offset ( ( t 2 − t 1 ) − ( t 4 − t 3 ) 2 ) (see 107 in Fig. 1) used to measure the ToD counter T O D A and T O D B to synchronize. Thus, the signal used to update the T is based on O D B -counter is used, on the timestamp exchange and uses the system clock 711 , which is synchronized with the slave line card. That 1A PPS signal is not required. The ToD counters throughout the system are synchronized in the same way. Note that once a master line card is aligned through a timestamp exchange, that master line card can be used to align other line cards. That is, there is no need for the slave line card to perform all timestamp exchange operations. Thus, in one embodiment, one of the master line cards synchronizes. 705 The ToD counter is updated in another of the master line cards using a timestamp exchange. In some embodiments, systems can choose for all timestamp exchange operations to be initiated by a single entity, such as the slave line card, but this is not necessary.

[0021] There are minor packet delay variations in the system because the timestamp exchange is localized. Although this is no longer necessary for aligning the ToD counters, the 1 PPS signal indicating the ToD counter rollover can also be adjusted using this approach (timestamp exchange) if there is a desire to distribute the 1 PPS signal. Thus, the alignment of distributed 1 PPS signals can be improved by using timestamp exchange. Any kind of static asymmetry can be calibrated out. Additionally, the control plane should be 1588-aware.This means that the physical layer (PHYs) used in the control plane to exchange timestamps must not add its own delay to the timestamp messages and must instead use transparent clocking to pass the timestamp without adding delay by taking latency into account through the PHY circuitry, either by adjusting the timestamp to account for the latency or by sending an additional message indicating the latency.

[0022] In addition to the need for 1588-level awareness, the timestamp must be of high resolution to achieve the desired accuracy for the time-of-death (ToD). A timestamp with nanosecond resolution or higher would, for example, be considered high resolution in this context. Such resolution is available in high-performance timing integrated circuits. Network processors (NPs), FPGAs, and PHYs on the line and timing boards can be used to provide high-resolution timestamps. One advantage of the embodiment in Fig. 7 is that existing infrastructure at the tax level can be used to achieve higher ToD accuracy.

[0023] 1. PPS signals generated by different disks in a distributed system must be synchronized so that they occur almost simultaneously across the entire system. To achieve this degree of synchronization, and again referring to Fig. 1, sends the time control card 109 In conventional systems, simultaneous 1 PPS signals are sent to each line card. Because these 1 PPS signals are transmitted simultaneously, separate communication paths from the time control card to the line cards are required for each of these 1 PPS signals, as is the case for 1 PPS signals. 117a , 117b and 117c in Fig. Figure 1 shows two problems: (1) multiple dedicated communication paths and (2) the lengths of these paths to and from the master time control card. 110 are not identical, which adds an uncompensated delay and causes misalignments. As the number of circuit boards increases, so does the number of tracks on the backplane. The control and coordination of these systems is performed via yet another common communication channel (see control plane). 701 in Fig. 7), which adds even more uncertainty. To address such problems, embodiments herein utilize a common bus that time-interleaves 1 PPS signals in such a way that the delays introduced by time-interleaving the data can be precisely eliminated. Furthermore, the same common bus can be used to also transmit control and coordination data, thus avoiding the use of a separate system. The common bus provides a single track on the backboard that connects all of the line cards, as opposed to separate tracks for each of the line cards.

[0024] Fig. Figure 8 illustrates the use of the 1 PPS signal line in conventional systems. Over the 1-second interval, the 1 PPS signal line contains a 0.1 µs pulse. 801 . During the rest of the time (greater than 99.99%), at 803As specified, the signal line remains unused. Additionally, the time control card, which sends the 1 PPS signals, and the master line cards, which receive the 1 PPS signals, are configured in a star configuration with the time control card in the center and the master line cards connected to the time control card via separate 1 PPS signal lines.

[0025] With reference to Fig. 9. Implementations address the shortcomings of dedicating one PPS connection to each master line card in a star configuration using a time information bus. 901one in which the 1 second between ascending edges of the 1 PPS signal on the PPS signal line is divided into multiple time windows. The time information bus can, for example, be divided into frames that have 64 time windows for a time information bus supporting a system with 32 line cards. Of course, other embodiments can use a different number of time windows and support a different number of line cards. In the embodiment of Fig. 9, generates the time control card 905 the system clock (SysClk) 902 and distributes it to all line cards. Each of the line cards receives the system clock signal in a phase-locked loop (PLL). 906 and maintains phase and frequency coupling with the system clock. The microcontroller unit (MCU), which is also involved in 906As shown, it provides control functionality for the PLL, including setting the phase and / or frequency of the local clock signal. 931 , which is from the PLL 906 is generated based on timestamp exchange processes. The host processor 926 implements the messaging and protocol stack assigned to 1588 and communicates with the timestamp logic in logic block 928 The local clock 931 , clocks, based on system clock 902 , the ToD counter 908 in each line card. The system clock is synchronized with the 1 PPS signal. In embodiments, a second timing control card (not shown) provides redundancy. With a 125 MHz system clock and 64 time windows, each time window corresponds to 1,953,125 cycles of the system clock, or approximately 15.6 ms. Instead of being distributed in a star configuration, the time information bus 901A passive bidirectional bus (one track on the backboard running to each line card) allows each card connected to the bus to send data to or receive from it. This approach minimizes the number of tracks on the backboard, making it straightforward to expand the bus to include more line cards compared to a star configuration. Additionally, the physical path is the same for both receive and transmit directions, providing symmetry, which can be beneficial when considering path length differences.

[0026] Fig. Figure 10 illustrates a 1-second time information bus frame 1001, which is divided into several time windows. Fig. Figure 10 shows 64 numbered time slots (0, 1, 2, ..., 63). Some of the time slots are assigned for transmission by the primary timing source to the line cards, and other time slots are assigned for transmission from the line cards to the primary timing source. In one embodiment, the primary timing source uses precisely these time slots to transmit the 1 PPS timing signals. The primary timing source provides the primary timing reference for the system and could be one of the line cards, for example, the slave line card. 903 or the time control card 905The odd-numbered time windows are used by the line cards to send a pulse back to the primary time control source, for example, in a test mode, and / or to send back other control and / or timestamp (TS) information. Using even-numbered time windows for transmissions to the line cards and odd-numbered time windows for transmissions from the line cards eliminates contention on the time information bus. In other embodiments, the roles of the even and odd-numbered time windows are reversed. If the slave line card is the primary time control source, the time control card communicates on the time information bus like any of the line cards. Time window 0 or 1 can be encoded with identifying information at a predetermined position within the time window for other cards to identify the time window and keep the time information bus aligned. Alternatively,Time windows can contain one or more other time window-identifying information at a predetermined location. Line cards utilize the bus based on a unique identifier, such as their line card number on the bus (0, 1, 2, 3, ...). Thus, for example, line card 1 receives PPS signals at the window number equal to (line card number × 2) and transmits the time window number equal to ((line card number × 2) + 1) on the time information bus. In this way, line card 1 receives PPS signals at even time windows and transmits information at odd time windows. Other embodiments use different approaches to assign time windows and line cards based on the line card number.

[0027] When the system starts, the time control card works 905as the primary timing source. At a specific time, one of the line cards becomes a Precision Time Protocol (PTP) slave, and in embodiments, the PTP slave line card takes over. 903 the role as the primary timing control source. In the embodiment of Fig. 9. The PTP slave is communicatively coupled to the Grandmaster (GM) through the physical layer (PHY). This change in role as the primary time control source is communicated via communications on the time control information bus or via the control plane (see Fig. 7) coordinated. Fig. 9 also shows a communication channel 935 from the line map 907 to a downstream external device, which could be, for example, a fiber optic connection.

[0028] Fig. Figure 11 illustrates an example time frame 1100 At the beginning of the time window, the primary timing source sends the 0.1 µs 1 PPS signal as a pulse. 1101Protective tapes 1103 and 1105 They extend for 1 ms from the beginning and end of the time window and leave approximately 1000 bits for transmitting other information during the time window to the line card from the primary timing source. Each of the line cards 907One of the 64 windows is assigned to receive the 1 PPS signal. Thus, in an embodiment with 32 line cards, a 1 PPS signal is transmitted 32 times during each second, one for each line card. The timing of the 1 PPS signal is known because it is known to occur with a specific offset of the system clock from the beginning of the frame. Assuming the 1 PPS signal occurs at the beginning of a time window, with a 125 MHz system clock, the offset is (N × 1,953,125) system clock cycles from the beginning of the frame, where N is the number of time windows in the frame. For other positions for the 1 PPS signal within the time window, the offset is increased based on the specific position within the time window.

[0029] The time windows can also be used as dedicated data channels for sending timestamp (TS) data. t1 , t2 , t2 and t4 serve. The timestamp logic is used in 910in the line maps 903 and 907 and 919 in the time control card 905 As shown, due to the time windows, certain timestamp information is already known. For example, it can be assumed that the 1 PPS signal from the primary timing source (or another signal at a known position within the time window) serves as the first timestamp. The timestamp itself is known in advance by the primary timing source based on the time window number for the timing pulse. t2 The timestamp indicates the time at which the 1 PPS signal is received from the circuit board and can, for example, have a range of ±1 µs to account for the worst-case scenario of backboard movement. An 11-bit timestamp in timestamp logic. 910 provides 1 nanosecond accuracy, while a 15-bit timestamp 100 It delivers picosecond resolution. t3The timestamp represents the local time at which the message was sent to the primary time control source and is known in advance by the time slot number (since each line card was assigned a unique time slot number) and assuming that the timestamp was sent at a known point within that time slot. t4 The timestamp represents the time at which the t3 A message was received from the primary timing source. Again, a range of ±1 µs should include the worst-case scenario of backboard movement. An 11-bit timestamp provides an accuracy of 1 nanosecond, while a 15-bit timestamp offers a resolution of 100 Provides picoseconds. The length of the timestamp depends on the accuracy requirements of the specific implementation. The one-way delay ( ( t 2 − t 1 ) + ( t 4 − t 3 ) 2 ) and error offset ( ( t 2 − t 1 ) − ( t 4 − t 3 ) 2 ) (see 107 in Fig. 1) can be used to determine the appropriate compensation to be used to account for delays between the primary time control source and the line card.

[0030] Trace delays between the primary timing source and the line cards can also be determined in a test mode by having the primary timing source send a pulse that the line card returns via the time information bus. The symmetry of the bus makes calculating the delay a simple division by two, which can be used to accurately compensate for the delay on the back board between the primary timing source and each of the line cards.

[0031] While the embodiment of the in Fig. In the 11 shown time windows, a 1 PPS signal is placed in one time window. In other embodiments, all of the 1 PPS signals occur in the first millisecond of the frame. Thus, each master line card receives the 1 PPS signal at a predefined time within the first millisecond of the frame. The remainder of the 1-second frame can be used for sending data / control in assigned time windows based on the unique line card identification, e.g., (0, 1, 2, 3, ...). Other embodiments group the 1 PPS signals at other predetermined times within the frame, allowing the remainder of the frame to be used for data / control information. In still other embodiments, the Fig. The 1 PPS signal shown in Figure 11 is fed to all of the line cards simultaneously. This means that at a predetermined time within the frame, for example, the beginning of the first time window, the line cards listen for a transmission of the 1 PPS signal, and the remainder of the frame is available for message exchange between the line cards and the primary time control source. The rest of the frame can be divided into time windows for transmissions to and from the respective line cards according to their line card ID.

[0032] In one embodiment, time window 0 belongs to the primary time control source, and when functioning as the primary time control source, the time control card takes over the time window of the primary time control source. However, the assignment of the primary time control source need not be static, and whichever card is the primary time control source can take over the first time window.

[0033] Current implementations feature a separate system for incorporating 1 PPS information into distributed systems from satellite timing signals, such as GPS (United States), Galileo (Europe), BeiDou (China), and other types of Global Navigation Satellite System (GNSS) technology. By timestamping the received satellite 1 PPS signal, a single approach can be used to interface an IEEE 1588 System 900 with other networked IEEE 1588 systems and GNSS signals.

[0034] The system's "source" for 1 PPS / ToD moves to where the primary time signal enters the system. The primary time signal can enter the system from the line card, which has the primary Precision Time Protocol (PTP) role (i.e., the PTP slave). In embodiments, when the system is in GPS (or another satellite system) operation, initial startup, or idle mode, the time control card provides the system time control source. The time control card has a GPS unit that can be used as a backup in case the PTP slave fails. Moving the system's source to where the primary time signal enters the system helps reduce the degradation of time control information, as it is processed by more cards.

[0035] Implementations in GPS operation use a timestamper, which significantly simplifies system operation. Using the timestamper retains the PTP timestamp concept used for the PTP slave, but switches to using timestamps based on the GPS 1 PSS signal. Operation is similar to the configuration for PTP one-way time synchronization. That is, with a GPS signal, there is no communication back to the GPS system. Once the GPS information is timestamped, the system treats the GPS information as a primary time control source. Thus, it receives, again with reference to Fig. 9. Timestamp logic 919 in time control card 905 a satellite 1 PPS signal 921 The PLL 925 in the time control card 905 is synchronized with the 1 PPS signal and the 1 PPS signal, which is transmitted via the time information bus 901The signal transmitted is synchronized with the Satellite 1 PPS signal. This establishes the system's ToD (Time of Death). 900 synchronized with the satellite 1 PPS signal.

[0036] Switching between PTP and GPS can be smoother (since the same control loop is used) if timestamps are used to align all line cards in the system via a dedicated time information bus, as this eliminates any concerns about buffer delays from a shared communication resource. Similar to PTP, timestamp data is exchanged between the primary timestamper, for example, the time control card. 905 , and the distributed time stamps, for example the line cards 907 , exchanged. The data is exchanged via time information bus. 901 exchanged. Note that the time stamper in the circuit boards and the time control board are located in field-programmable gate arrays (FPGAs). 928or other types of integrated circuits and in embodiments the time stamper has the ability to time stamp internal signals or external signals received by the integrated circuit, as required to implement the 1588 time stamp exchange.

[0037] When the primary timing source is moved, for example, from the slave line card coupled to the Grandmaster to the timing card coupled to receive a GPS signal, the current primary timing source (the slave line card) enters holdover mode. In holdover mode, the phase and frequency of the 1 PPS signal are maintained at their current phase and frequency. Additionally, the timing card enters a holdover mode for the system clock (SysClk), which is distributed via the backboard to the line cards and synchronized with the 1 PPS / ToD signal used in the system. Thus, the system clock is maintained at its current phase and frequency. The new primary timing source (the timing card) 905The system does the same with the phase clamping of its 1 PPS signal, i.e., it adjusts the phase of the 1 PPS signal so that it matches the new primary time control source. Remember that the system was locked, so the system clock frequency is very close to what it should be, as is the 1 PPS signal. In one embodiment, communication regarding the change to the primary time control source occurs via the time information bus. Thus, the current or future time control source sends a message over the time information bus requesting the change, which is acknowledged by the message receiver. Additional messages required to carry out the change are exchanged over the time information bus. For example, the new primary time control source (the time control card) communicates... 905 ) with the PTP slave line card 903, that starting, for example at the next frame, the new primary time control source (the time control map) 905 ) will deliver the 1 PPS signal. After the nominal locking, the time control card exits. 905 The holdover. New timestamps are exchanged with all line cards because the path lengths between the new primary time control source and the line cards differ from the path lengths between the previous primary time control source and the line cards. Note that path asymmetries (to and from) to the line cards are zero because the time information bus is used for bidirectional communication. The timestamp measures the outgoing pulse as well as the incoming pulses at the pin. The only sensitivity is to variability in the path between the integrated circuit pin and the timestamp within the integrated circuit.

[0038] Fig.Figure 12 illustrates the system clock (SysClk) primary loop 1201 and the PTP master timing loop 1203 The SysClk primary timing loop 1201 locks the system clock (SysClk) 902 to the timing of the PTP slave and thus the Grandmaster (GM), assuming that the PTP slave acts as the primary timing source. The PTP master timing loop 1203 This allows PTP masters to adjust their timing based on timestamp exchanges via the time information bus. Thus, assuming the PTP slave... 903 which delivers 1 PPS signals via the time information bus, which deliver 1 PPS signals based on, for example, timestamp exchange processes via the time information bus 901 will be aligned.

[0039] The time information bus can thus be used to provide both the 1 PPS signal and bidirectional communication between the primary time control source and the other cards (e.g., line cards or time control cards) in the system. The time information bus can be used to exchange timestamps between the primary time control source and the other cards in the system. The time information bus can also be used when the primary time control source changes, for example, from the time control card based on a satellite 1 PPS signal to the PTP slave line card coupled to the grandmaster, or vice versa.

[0040] The terms "first," "second," "third," etc., as used in the claims, serve, unless the context clearly indicates otherwise, to distinguish between different objects in the claims and do not otherwise specify or imply any order in time or space. For example, "a first time window" or "a second time window" does not mean or imply that the first time window occurs before the second time window or at a specific point in a frame.

[0041] Thus, various aspects relating to the use of a backplate and timestamp exchange processes for updating daily time counters have been described. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. Other variations and modifications of the embodiments disclosed herein may be made on the basis of the description set forth herein without departing from the scope of the invention as set forth in the following claims.

Claims

[1] Procedure, encompassing: Distributing a clock signal from a timing control card to a first line card and to a second line card via a backplane; Performing a timestamp exchange between the first line card and the second line card using a control plane coupled to the first and second line cards; and Synchronizing a second daily time counter on the second line card with a first daily time counter on the first line card based on the timestamp exchange and the clock signal. [2] Method according to claim 1, wherein timestamps exchanged in the timestamp exchange have a resolution of at least 1 nanosecond. [3] Method according to one of claims 1 to 2, wherein the first line card and second line card have local clock signals which are frequency-bound to the clock signal. [4] Method according to any of the preceding claims, wherein the control level uses transparent timing. [5] Method according to any of the preceding claims, wherein synchronization is achieved without using a 1 pulse per second (PPS) signal. [6] Method according to any one of claims 1 to 4, further comprising: Distributing individual 1 pulse per second (PPS) signals from the time control card to a multitude of master line cards and aligning the individual 1 PPS signals in the master line cards using respective timestamps exchanged via the control plane. [7] Method according to any of the preceding claims, further comprising setting one-way delay and error offset based on the timestamp exchange to synchronize the second day time counter with the first day time counter. [8] Method according to any of the foregoing claims, further comprising: Sending the clock signal via a backplate to a third line card; After the second daily time counter has been synchronized with the first daily time counter, perform a second timestamp exchange between the second line card and the third line card; and Synchronizing a third daily time counter in the third line card with the second daily time counter based on the second timestamp exchange. [9] Method according to any one of claims 1 to 7, further comprising: Sending the clock signal via a backplate to a third line card; Perform a second timestamp exchange between the first line card and the third line card and Synchronizing a third daily time counter in the third line card with the first daily time counter based on the second timestamp exchange. [10] Device comprising: a first line map with a first daily time counter; a second line card with a second daily time counter; a timing control card configured to provide a clock signal to the first and second line cards; a control level that communicatively links the first and second line cards; the first and second line cards are configured to perform a timestamp exchange; and where the second line card is configured to synchronize the second daily time counter with the first daily time counter based on the timestamp exchange. [11] Device according to claim 10, wherein timestamps associated with the timestamp exchange have a resolution of at least 1 ns. [12] Device according to one of claims 10 to 11, wherein the control plane uses transparent timing. [13] Device according to one of claims 10 to 12, wherein the timing card is further configured to distribute 1 pulse per second (PPS) signals to the first and second line cards. [14] Device according to claim 13, wherein the first and second line card are configured to align the 1 PPS signals based on timestamps. [15] Device according to any one of claims 10 to 14, wherein one-way delay and error offset are produced based on the timestamp exchange and are used to synchronize the second day time counter with the first day time counter. [16] Device according to any one of claims 10 to 15, further comprising: a third circuit board, which is coupled to receive the clock signal via the backboard; and a third daily time counter in the third line card; wherein the third line card is configured to synchronize the third day time counter with the first day time counter based on a timestamp exchange with the first line card and a different local clock signal frequency coupled to the clock signal. [17] Device according to any one of claims 10 to 15, further comprising: a third circuit board, which is coupled to receive the clock signal via the backboard; and a third daily time counter in the third line card with the first daily time counter; wherein the third line card is configured to synchronize the third day time counter with the second day time counter based on a timestamp exchange with the second line card and based on another local clock signal in the third line card that is coupled to the clock signal. [18] Procedures, including: a slave line card that synchronizes timing with a grandmaster; a timing control card that synchronizes a system clock signal with the timing of the slave line card; wherein the timing card distributes the system clock signal to a variety of line cards, including master line cards and the slave line card; The slave line card and one of the master line cards perform a timestamp exchange; and The update of a second daily time counter in one of the master line cards is synchronized with a first daily time counter in the slave line card based on the timestamp exchange. [19] The method of claim 18, further comprising: that one of the master line cards performs a second timestamp exchange with a second of the master line cards; and The second of the master line cards updates a third daily time counter in the second of the master line cards, synchronized with the second daily time counter based on the second timestamp exchange. [20] The method of claim 18, further comprising: that the slave line card and another of the master line cards perform a second timestamp exchange; and The other of the master line cards synchronizes the update of a third daily time counter in the other of the master line cards with the first daily time counter in the slave line card based on the second timestamp exchange.

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