PHOTOLITHOGRAPHING METHOD AND DEVICE

Abstract

Extreme ultraviolet lithography (EUVL) process comprising: providing at least two phase-shift mask regions with an identical structure; forming a resist layer (520) over a substrate (510); determining an optimal exposure dose of the resist layer (520);and forming a latent image on the same first region of the resist layer (520) by a multiple exposure process, wherein the multiple exposure process comprises several exposure processes, and each of the multiple exposure processes uses a different phase-shift mask region of the at least two phase-shift mask regions having the same structure, wherein a first exposure process of the multiple exposure processes comprises exposing the first region of the resist layer (520) with a first exposure dose using a first phase-shift mask region of the at least two phase-shift mask regions, wherein a second exposure process of the multiple exposure processes comprises exposing the first region of the resist layer (520) with a second exposure dose using a second phase-shift mask region of the at least two phase-shift mask regions;and exposure of a second area of ​​the resist layer (520) with the second exposure dose using the first phase-shift mask area.;

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over preliminary US patent application No. 62 / 719 ,313, submitted on August 17, 2018, the entire disclosure of which is hereby incorporated by reference into the present text. BACKGROUND

[0002] The integrated semiconductor (IC) industry has experienced rapid growth. Technological advances in IC materials and design have led to generations of ICs, each featuring smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be formed by a manufacturing process) has decreased. This process of downscaling generally delivers benefits by increasing production efficiency and reducing manufacturing costs. However, such downscaling has also increased the complexity of IC processing and manufacturing, and similar advancements in IC processing and manufacturing are necessary to realize these improvements.For example, higher-resolution lithography processes, such as extreme ultraviolet (EUV) lithography, are implemented to meet size requirements approaching the critical dimensional tolerances of 7 nm technology nodes and below. ELTV lithography uses a reflective mask (also called a reticle) to transfer the structure of a layer of an integrated circuit device to a wafer. A reflective mask typically contains a multilayer reflective coating (a stack of multilayer mirrors) arranged on a substrate. Any defects, including microscopic defects, in the substrate, the multilayer reflective coatings, or the absorbers can undesirably affect the printability of the reflective mask structure. Such defects are often difficult to inspect and, even if detected, difficult to repair.Accordingly, while existing ELTV masks and methods for manufacturing EUV masks have generally been sufficient for their intended purposes, they are not entirely satisfactory in every respect. List of characters

[0003] The present disclosure is best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale and are for illustrative purposes only. The dimensions of the various structural elements may, in fact, be enlarged or reduced as necessary for the clarity of this discussion. Fig. Figure 1 is a diagrammatic cross-sectional view of an EUV mask at a manufacturing stage, constructed according to an embodiment of the disclosure. Fig. Figure 2 is a diagrammatic cross-sectional view of the EUV mask (partially) of Fig. 1, which is constructed according to an embodiment of the disclosure. Fig. Figure 3 is a diagrammatic cross-sectional view of the EUV mask (partially) of Fig. 1 according to one embodiment of the disclosure. Fig. Figure 4 is a diagrammatic cross-sectional view of the EUV mask (partially) of Fig. 1d according to embodiments of the disclosure. Fig. Figure 5 is a graphical top view of an EUV mask according to embodiments of the disclosure. Fig. Figure 6 is a flowchart of a method for forming a structured resist layer according to embodiments of the present disclosure. Fig. Figure 7 is a diagrammatic cross-sectional view of a resist layer during a stage of a method for manufacturing a semiconductor device according to embodiments of the disclosure. Fig. 8A, Fig. 8B, Fig. 8C, Fig. 8D and Fig. Figure 8F are diagrammatic cross-sectional views of a resist layer during various stages of the fabrication of a semiconductor device according to embodiments of the disclosure. Fig. Figure 8E is a top view of a phase shift mask according to one embodiment of the disclosure. Fig. Figure 9 shows a photolithography device according to an embodiment of the disclosure. Fig. 10A and Fig. Figure 10B shows an embodiment of a control unit for a photolithography device according to an embodiment of the disclosure. Fig. Figure 11 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 12 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 13 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 14 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 15 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 16 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 17 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 18 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 19 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 20 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 21 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 22 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 23 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 24 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 25 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 26 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 27 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 28 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 29 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 30 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 31 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 32 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 33 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 34 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 35 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 36 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 37 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 38 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 39 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 40 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 41 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 42 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 43 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 44 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 45 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 46 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 47 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 48 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 49 shows one of several sequential operations in a method for exposing a semiconductor substrate according to an embodiment of the present disclosure. Fig. Figure 50 shows a comparison between a single exposure and 4 exposures using 4 different masks on the same region of a semiconductor wafer according to embodiments of the disclosure. DETAILED DESCRIPTION

[0004] It is understood that the following disclosure provides many different embodiments or examples for implementing various features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values ​​but may depend on the process conditions and / or desired properties of the device.Furthermore, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements may not be in direct contact. Various features may be arbitrarily drawn to different scales for the sake of simplicity and clarity.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly. Additionally, the term "made of" can mean either "comprises" or "consists of."

[0006] The following description refers to an EUV photomask or an EUV phase-shifting mask (PSM) and a mask fabrication process. The terms "photomask" and "mask" are used interchangeably. The mask fabrication process comprises two operations: a mask blank fabrication process and a mask structuring process. During the mask blank fabrication process, a mask blank is formed by depositing suitable layers (for example, a reflective multilayer) onto a suitable substrate. The mask blank is then structured during the mask structuring process to create a design for a layer of an integrated circuit (IC). The structured mask is then used to transfer circuit structures (for example, the design of a layer of an IC) onto a semiconductor wafer.The structures on the mask can be transferred repeatedly to multiple wafers using various lithography processes. Different masks can be used (for example, a set of...). 15 until 30 Masks are used to build a complete integrated circuit (IC). Generally, different masks are manufactured for use in various lithography processes. Types of masks include binary intensity masks (BIMs) and phase shift masks (PSMs).

[0007] Fig. 1 and Fig. 2 are cross-sectional views of a photomask 40 at various manufacturing stages, which is constructed according to embodiments of the present disclosure. The mask 40 and the process for their manufacture are discussed together with reference to the Fig. 3 and Fig. Figure 4 and other figures are described. In the following embodiments, the mask 40a phase shift mask (PSM).

[0008] As in Fig. The mask can be seen in step 1. 40 at this stage an ELTV mask blank, which is a substrate 110 contains a material consisting of a low thermal expansion material (LTEM). The LTEM material may contain TiO2-doped SiO2 or other low thermal expansion materials known to those skilled in the art. The LTEM substrate 110 It serves to minimize image distortions due to mask heating. In the present embodiment, the LTEM substrate contains 110 Materials with a low defect rate and a smooth surface. Additionally, a conductive layer can be used. 105 on the back of the LTEM substrate 110 They are arranged to enable electrostatic clamping. In one embodiment, the conductive layer contains 105Chromium nitride (CrN), although other compositions are also possible.

[0009] A reflective multilayer (multilayer, ML ) 120 is placed above the LTEM substrate 110 separated on the front side. The ML 120This is also referred to as a first reflective layer to avoid confusion when another reflective layer is added later. According to Fresnel's equations, light reflection occurs when light travels across the interface between two materials with different refractive indices. The reflected light is stronger when the difference in refractive indices is greater. To increase the reflected light, the number of interfaces can be increased by depositing a multilayer of alternating materials and constructively interfering with light reflected from different interfaces by selecting an appropriate thickness for each layer within the multilayer. However, the absorption of the materials used for the multilayer limits the maximum reflectivity that can be achieved. Die ML 120contains multiple film pairs, such as molybdenum-silicon (Mo / Si) film pairs (for example, a layer of molybdenum above or below a layer of silicon in each film pair). Alternatively, the ML 120 Molybdenum-beryllium (Mo / Be) film pairs, or any material that strongly reflects at EUV wavelengths, can be used for the ML 120 can be used. The thickness of each layer of the ML 120 depends on the EUV wavelength and the angle of incidence. The thickness of the ML 120 is adjusted to ensure maximum constructive interference of the ELTV light reflected at each interface and minimal absorption of the EUV light by the ML 120 can be achieved. ML 120In some embodiments, it is selected to have a high reflectivity for a selected radiation wavelength. In some embodiments, the number of film pairs is in the range of 20 until 80 However, any number of film pairs is possible. In one embodiment, the ML 120 Forty pairs of Mo / Si layers. Each Mo / Si film pair has a thickness of approximately 7 nm, with a total thickness of 280 nm. In this case, an ELTV reflectance of approximately 70% is achieved.

[0010] In some embodiments, a buffer layer is used. 130 above the ML 120 designed for one or more functions. In one embodiment, the buffer layer acts 130 as an etch stop layer in a structuring process or in other operations, such as repair or cleaning. In another embodiment, the buffer layer serves 130preventing oxidation of the ML 120 The buffer layer 130 It can contain one or more films to achieve the intended functions. In the present embodiment, the buffer layer has 130 different etching characteristics than a second reflective layer 150 , which will be described later. In one embodiment, the buffer layer contains 130 Ruthenium (Ru). Continuing the example, the buffer layer contains 130 a Ru film with a thickness in the range of approximately 2 to 5 nm. In other embodiments, the buffer layer contains 130 Ru compounds such as RuB and RuSi, chromium (Cr), Cr oxide, or Cr nitride. In some embodiments, a low-temperature deposition process is used to form the buffer layer. 130 used to create an interdiffusion of ML 120 to prevent.

[0011] In one embodiment, the mask contains40 the second reflective layer 150 , which are above the first reflective layer 120 is formed. In the embodiment where the buffer layer 130 If present, the second reflective layer will be 150 above the buffer layer 130 trained, as in Fig. 1 illustrates. The second reflective layer 150The system is to be structured according to an IC layout. The second reflective layer is designed to generate a 180° phase shift of the reflection coefficient (with respect to the region where the second reflective layer is removed after structuring), thus enabling the realization of a phase-shift mask for the EUVL. Here, the relative reflection coefficient of a first region with respect to a second region is defined as the ratio of the amplitudes (complex numbers, including phase information) – assessed at the same vertical height from a common mask surface – of light reflected from the first region and the second region with the same incident light.

[0012] If the reflection coefficient is -1 ("1" means no attenuation and "-" means 180° phase shift), then the mask 40An alternating phase-shift mask (Alt-PSM) is used, in which there is no oth-order diffraction if the IC layout's conduction-to-space area ratio is 1:1, and the highest interframe contrast can be achieved. However, if the required thickness of the second reflective layer is too large, a mask shadowing effect occurs, which in turn degrades the interframe contrast. Therefore, the design of the second reflective layer must be a compromise between the reflection coefficient and the thickness. The highest interframe contrast is achieved in some embodiments because oth-order diffraction is removed by a pupil filter.However, if the reflection coefficient is too close to -1, the amplitude of the o-th diffraction order is too close to 0, and the exposure dose loss due to the removal of the o-th diffraction order is minimized, thus maximizing the throughput of the exposure tool. Furthermore, if the required thickness of the second reflective layer to achieve a 180° phase shift is smaller, light scattering due to mask topography is reduced, and the throughput of the exposure tool is further increased due to the enhanced strength of the ±1st diffraction order. In the EUV wavelength range, every material is highly absorptive. It is difficult to achieve a reflection coefficient close to -1 using a single material for the second reflective layer. In EUVL, a multilayer system of alternating materials is used to achieve high reflectivity. Reflectivity is defined as the absolute value.2 defined by the reflection coefficient.

[0013] For an EUVL using an imaging wavelength of 13.5 nm, Si and Mo are used, as outlined above, because they provide the highest integrated reflectivity over the spectral range around 13.5 nm. An ML design consists of Si / Mo pairs with approximately 4 nm Si to approximately 3 nm Mo in each pair. If this ML design is used for the second reflective layer... 150 When used to implement a phase shift mask, each Si / Mo pair contributes a phase shift of approximately 12°. Therefore, to achieve a 180° phase shift, 15 Si / Mo pairs with a total thickness of approximately 105 nm are required, in which case the masking effect should be pronounced. Since the refractive index and extinction coefficient of Si at the EUV wavelength are close 1 or 0While Si contributes little to the phase shift (with respect to light propagating in air), almost all of the phase shift is due to the presence of Mo. Si's role is to generate multiple Si / Mo interfaces where light reflection occurs. Thus, the total thickness of Mo should be close to 44 nm, regardless of the design used for the second reflective layer. In one embodiment of the ML design, the phase difference of light reflected by adjacent Si / Mo pairs is 360° (the minimum value, as only integer multiples of 360° provide high reflectivity). In such a case, each 3 nm Mo layer is accompanied by a 4 nm Si layer, resulting in a large film stack height.However, if the phase difference of light reflected by adjacent Si / Mo pairs is 720°, it is not necessary to incorporate so many Si layers, and the total thickness required to generate a 180° phase shift for the second reflecting layer can be reduced.

[0014] In the first embodiment, the second reflective layer contains 150 a single molybdenum (Mo) layer 151 with a thickness of approximately 44 nm, as in Fig. Figure 2 illustrates this. As explained earlier in this text, this should be the thinnest design for the second reflective layer if Mo is used. In this embodiment, the reflection coefficient is approximately -0.7757, and the reflectance is approximately 0.6017.

[0015] In a second embodiment, the second reflective layer contains 150 several films, as in Fig. Figure 3 (a cross-sectional view) illustrates this. More precisely, the second reflective layer contains... 150 five Mo films 152 , 154 , 156 , 158 and 160 as well as five Si films 162 , 164 , 166 , 168 and 170 , which are configured such that two adjacent Mo films hold a Si film between them and two adjacent Si films hold a Mo film between them. In the present embodiment, the Mo film has 152 a thickness of approximately 1 nm; the Mo films 154 , 156 , 156 and 158 have a uniform thickness of approximately 10.1 nm; the Si film 162 has a thickness of approximately 4 nm; the Si films 164 , 166 and 168 have a uniform thickness of approximately 4.3 nm; and the uppermost Si film 170 has a thickness of approximately 2.6 nm. The second reflective layer 150Furthermore, another buffer layer can be added. 172 containing substances that are located on the uppermost silicon film 160 is deposited. In this embodiment, the reflection coefficient is approximately -0.8665, and the reflectance is approximately 0.7508. In this embodiment, the total thickness of the second reflective layer is 150 approximately 63.4 nm, which is much smaller than 105 nm. Compared to the first embodiment (single Mo layer), the total thickness of the second reflective layer is about 19.4 nm greater, and the reflectivity is about 55.7% higher.

[0016] In either the first or the second embodiment, each thickness lies within 20% of its respective nominal value. Or, put another way: Each thickness lies within a range of 80% to 120% of its respective nominal value. The buffer layer 172 resembles the buffer layer 130 For example, the buffer layer contains 172a Ru film. In some embodiments, the buffer layer contains 172 a Ru film with a thickness in the range of approximately 2 to 5 nm. In other embodiments, the buffer layer contains 172 Ru compounds, such as ruthenium boron (RuB) and ruthenium silicon (RuSi), chromium (Cr), Cr oxide or Cr nitride.

[0017] We return to Fig. 1 back. One or more of the layers 105 , 120 , 130 and 150 (such as 151 in Fig. 2 or Fig. 152-170 in Fig. 3) can be formed by various processes, including a physical vapor deposition (PVD) process, such as evaporation and direct current magnetron sputtering; a plating process, such as electrodeless plating or electroplating; a chemical vapor deposition (CVD) process, such as atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or high-density plasma CVD (HDP CVD); atomic layer deposition (ALD); ion beam deposition; spin deposition; metal-organic decomposition (MOD); and / or other processes known to those skilled in the art. MOD is a deposition technique using a liquid-based process in a non-vacuum environment. In MOD, a metal-organic precursor dissolved in a solvent is spin-deposited onto a substrate, and the solvent evaporates.A vacuum ultraviolet (VUV) source is used to convert the organometallic precursors into their individual metal elements.

[0018] As in Fig. As can be seen in 4, in one embodiment the second reflective layer 150 structured to form a two-state mask. The second reflective layer 150 is structured to create a state 210 and a condition 220 to form a structured resist layer through a mask structuring process. The mask structuring process may include resist coating (e.g., spin coating), soft firing, mask alignment, exposure, post-exposure firing, development, rinsing, drying (e.g., hard firing), other suitable processes, and / or combinations thereof to form a structured resist layer. Electron, ion, or photon beam direct writing can be used for the exposure step in the mask structuring process.

[0019] In the structuring process of the previous section, an etching process is subsequently used to create sections of the second reflective layer. 150 to remove the structured resist layer as an etching mask. The etching process may include dry (plasma) etching, wet etching, and / or other etching methods. For the condition 210 The second reflective layer is removed. For the condition 220 The second reflective layer remains intact.

[0020] We'll stick with it. Fig. 4. The ELTV mask 40 now contains two states 210 and 220 The reflection coefficients of state 210 and condition 220 are r1 or r2. The two states are configured such that the absolute value of r2is essentially equal to or close to the absolute value of ri. In this embodiment, the reflected ELTV light from a region with the state 210 and the reflected EUV light from a region with the condition 220 a 180° phase difference.

[0021] Fig. 5 is a top view of the mask 40 , which is constructed according to an embodiment of the disclosure. Removing the o-th order diffraction (in the frequency domain) leads to spatial frequency doubling (in real space). Consequently, a halving of the spatial frequency on the mask occurs. 40necessary to obtain the desired IC structures on the target. This can be achieved by a mask with three states, i.e., three different reflection coefficients, and by assigning different states to adjacent principal polygons (for IC structures) and the background (i.e., the region without principal polygons). There are already two states, i.e., the states 210 and 220 In the present embodiment, a third state for the background is created by implementing sub-resolution helper polygons in the background and assigning the same state (for example, the state) to all sub-resolution helper polygons. 220) is assigned. Note that the background is defined as the regions without main polygons, and the field is defined as the regions without main polygons and auxiliary polygons. The field and the sub-resolution auxiliary polygons together define the background. The field is then assigned to another state (for example, the state 210 ) linked, which is different from the one assigned to the auxiliary polygons. The sub-resolution auxiliary polygons cannot be printed during a lithographic exposure process. At least one edge of the sub-resolution auxiliary polygon is shorter than λ / NA, where λ is a wavelength of a radiation source and NA is a numerical aperture of a projection optics box (POB). Because the sub-resolution auxiliary polygons are not printable, the background together has an effective reflection coefficient that differs from those of the first and second states ( 210 and 220). Consequently, the effective reflection coefficient of the background is the area-weighted average of the reflection coefficients of different regions (the sub-resolution auxiliary polygons and the field) in the background.

[0022] Thus, as in Fig. 5 illustrates the mask 40 3 Different states. The adjacent main polygons 310 and 320 different states (such as state 210 or 220 ). assigned. In the background, the field is 330 and the sub-resolution helper polygons 340 different states (such as state 210 or 220 ) assigned, thereby generating the background with the third mask state, which differs from the first and second mask states ( 210 and 220 ) differs. Since the sub-resolution auxiliary polygons 340Since they are not printable, the background has an effective reflection coefficient that differs from those of the first and second states, but is due to the structure density of the sub-resolution auxiliary polygons. 340 Voting is possible in the background.

[0023] During a lithographic exposure process, the mask 40 by near-on-axis illumination (ONI) with partial coherence σ of less than 0.3 to produce diffracted and non-diffracted lights, removing most of the non-diffracted lights and collecting and directing the diffracted lights and the non-removed non-diffracted lights through the POB to illuminate a target.

[0024] In the present embodiment, the mask 40A phase shift mask, such as an alternating phase shift mask (AltPSM) for an EUV lithography process. The mask 40 It contains several main polygons (for IC structures) and auxiliary polygons. Adjacent main polygons are assigned different states. For example, different main polygons 310 and 320 the condition 210 or 220The sub-resolution auxiliary polygons are not mapped onto the target (such as a wafer) during the ELTV lithography process. However, they do modify the (effective) reflectance coefficient of the background. In the present embodiment, the background structure density is essentially uniform. The background structure density is defined as the total area of ​​auxiliary polygons in a unit area. The (effective) reflectance coefficient of the background can be adjusted by varying the background structure density. Primary and auxiliary polygons are created by structuring the second reflective layer. 150 trained.

[0025] Furthermore, in some embodiments, the reflected ELTV light has been altered by the state 210 and the reflected ELTV light from the state 220a 180° phase difference. In this case, the amplitude of the o-th diffraction order (proportional to the area-weighted reflection coefficients of different regions, including the principal polygons, auxiliary polygons, and the field) on the mask can be 40 ) can be zero by adjusting the structure density. For example, if r2=r1 and the structure density is 50%, then the amplitude of the o-th diffraction order is 0 Therefore, the exposure dose loss is minimized by removing the o-th diffraction order, and the throughput of the exposure tool is maximized.

[0026] The second reflective layer 150 determines the reflection coefficient of the state 220 relative to that of the state 210 In one embodiment, which leads to Fig. 2, the (relative) reflection coefficient is approximately -0.7757. In an embodiment that leads to Fig. For 3, the (relative) reflection coefficient is approximately -0.8665. Here, the "-" sign represents a 180° phase difference.

[0027] The different embodiments of the disclosure realize various advantages. If the mask 40 Using an alternating phase-shift mask improves quality, contrast, and resolution. 40 Compared to other alternating phase-shift masks, this one is not affected by structural imbalance problems. Since the amplitude A is essentially close to 1 (0.776 in the embodiment that leads to Fig. 2 belongs, and 0.867 in the embodiment which is to Fig. 3), in one embodiment the total radiation energy loss is substantially low, about 40% or less. Accordingly, the exposure time of the lithography exposure process is reduced, and the throughput is increased. In various embodiments, the thickness of the structured layer (the second reflective layer) is 150 ) the mask 40 The wavelength is reduced to below 90 nm, and the shadowing effect during the exposure process is reduced or eliminated. This is achieved because no absorption layer is used, or a less attenuating material is used to create a structured layer. 150 To form a mask, the loss of radiation energy is reduced. In other embodiments, the mask 40 in Fig. 5 designed so that the sub-resolution helper polygons 340 in the first state 210 are and the field 330 in the second state 220 is.

[0028] Fig. Figure 6 is a flowchart of a method for forming a structured resist layer according to embodiments of the present disclosure. The method 400 begins with surgery S410 , where a resist layer forms over a substrate. During surgery S420 an optimal exposure dose ( E OP A given resist layer subjected to a given lithographic process has a specific threshold exposure dose (ETH), which is the minimum exposure dose required to reliably change the behavior of an exposed portion of the resist layer compared to an unexposed portion (when structures on the mask are large compared to the wavelength of the radiation source used). For example, if the resist layer contains a positive-tone resist material, the exposed portions of the resist layer will become soluble beyond the threshold exposure dose, such that the exposed portions of the resist layer are removed during a development process, and the developed resist layer contains the structure.In another embodiment, where the resist layer contains a negative-tone resist material, the exposed portions of the resist layer become insoluble beyond the threshold exposure dose, such that the unexposed portions of the resist layer are removed during a development process, and the developed resist layer contains the structure. However, in reality, a variety of different effects can cause the threshold dose to be insufficient. For example, the effect of diffraction, which reduces the contrast of the intermediate image, becomes apparent when the size of structures on the mask is close to or smaller than the wavelength of the radiation source used. In another embodiment, a firing process after exposure exhibits effects such as acid diffusion in a chemically enhanced resist, acid annihilation by a quenching agent, and so on.To correct this, in some embodiments an optimal exposure dose is determined based on an exposure dose for a previously specified test structure in order to achieve a previously specified target dimension on a wafer under a corresponding single exposure process. During operation... S430 A structure is formed in the resist layer by performing a multiple exposure process. In some embodiments, the multiple exposure process is performed using extreme ultraviolet radiation (EUV), and the radiation for each exposure process has approximately the same wavelength. In the multiple exposure process of operation S430Each exposure process uses an exposure dose that is lower than the optimal exposure dose, and the total exposure dose (ET) of the multiple exposure process is approximately equal to the optimal exposure dose (or in other words: E1). <E OP , E2 <E OP , ..., E N <E OP and E T =E1+E2+E3+ ... +E N ≈ EOP , where N is a total number of exposure processes performed). In some embodiments, the total exposure dose ( E T ) the multiple exposure processes within a range of approximately 90% to approximately 110% of the optimal exposure dose ( E OP ).

[0029] During each exposure process, the resist layer is brought into contact with the same structure, such as an identical integrated circuit structure. In one embodiment, each exposure process uses a different section of a single phase-shift mask to expose the resist layer, with each section of the mask having the same structure. In another embodiment, each exposure process uses a different phase-shift mask to expose the resist layer, with each mask having the same structure. The single phase-shift mask and the different phase-shift masks can contain defects (such as bump defects, pit defects, other types of defects, or combinations thereof) and phase defect regions. The formation of the structure in the resist layer further includes a development process in which a developer solution is applied to the exposed resist layer.In some embodiments, the resist layer is also subjected to a firing process before and / or after exposure. Additional steps may be performed before, during, and after the process. 400 can be applied, and some of the described steps can be replaced, omitted, or postponed to allow for additional embodiments of the process. 400 to obtain. The following discussion illustrates various embodiments of a resist layer obtained according to the method. 400 from Fig. 6. structured.

[0030] Fig. 7-8D and Fig. Figure 8F shows various diagrammatic cross-sectional views of a resist layer during different stages of the process. 400 from Fig. 6. Fig. 7-8D and Fig. Sections 8F have been simplified for the sake of clarity in order to better understand the inventive concepts of the present disclosure. Fig. 7 will be a semiconductor substrate 510 , such as a wafer 510 , provided. In some embodiments, the substrate 510 Any starting material on which processing is carried out to form layers of material to create various structural elements of an integrated circuit (IC) device. In the embodiment shown, the wafer contains 510 Silicon (i.e., a silicon wafer). Alternatively or additionally, the wafer contains 510 another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In a further embodiment, the semiconductor substrate is 510a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 510 It can alternatively be described as a material layer, or the semiconductor substrate. 510 It may contain a material layer on which a resist layer is formed. In one embodiment, the material layer is a metal layer, a semiconductor layer, or a dielectric layer. In another embodiment, the material layer is a hard mask layer, such as a silicon oxide layer or a silicon nitride layer.

[0031] A resist layer 520 is over the wafer 510 for example, deposited using a centrifugal casting technique. The resist layer 520 It is also referred to as a photoresist layer, light-sensitive layer, imaging layer, structuring layer, or radiation-sensitive layer. A rinsing process, such as rinsing with deionized (DI) water, can be performed on the wafer.510 be executed before the resist layer 520 is deposited. The resist layer 520 It can be subjected to a firing process, such as a soft firing process (also referred to as a post-firing firing process). In the embodiment shown, the resist layer contains 520 Positive tone resist material. Alternatively, the resist layer contains 520 Negative tone resist material. The resist layer 520 It has any suitable thickness, such as a thickness from about 10 nm to about 1,000 nm.

[0032] In the Fig. 8A-8F will be the resist layer 520 structured to form a structured resist layer 520A to form. Structuring the resist layer 520 This involves performing more than one exposure process, as in Fig. 8A-8D are shown, with each exposure process using an exposure dose that is lower than the optimal exposure dose. E OP for a corresponding single exposure process. In the illustrated embodiment, a first exposure process is used. 530 ( Fig. 8A), a second exposure process 540 ( Fig. 8B), a third exposure process 550 ( Fig. 8C) and a fourth exposure process 560 ( Fig. 8D) each a different phase shift mask or different regions of a single phase shift mask having the same circuit structure, for selectively illuminating the resist layer 520 with an initial exposure dose ( E1 ), a second exposure dose ( E2 ), a third exposure dose ( E3 ) or a fourth exposure dose ( E4 ) of radiation, resulting in a latent image structure 532D in the resist layer 520 is formed. The first exposure dose ( E1 ), the second exposure dose ( E2), the third exposure dose ( E3 ) and the fourth exposure dose ( E4 ) are each less than the optimal exposure dose ( E OP Furthermore, in the present embodiment, a total exposure dose ( E T ) the first exposure dose ( E1 ), the second exposure dose ( E2 ), the third exposure dose ( E3 ) and the fourth exposure dose ( E4 ) approximately equal to the optimal exposure dose ( E OP ) (or in other words: E T =E1+E2+E3+E4=E OP ), so that the latent image structure 532 after the fourth exposure process 560 can be developed. In some embodiments, the total exposure dose ( E T ) the multiple exposure processes within a range of approximately 90% to approximately 110% of the optimal exposure dose ( E OP ).

[0033] In the embodiment shown, the first exposure process illuminates 530 , the second exposure process 540 , the third exposure process 550 and the fourth exposure process 560 the resist layer 520 with radiation whose wavelength is less than about 100 nm, such as radiation in an extreme ultraviolet (EUV) range, an X-ray range, a deep ultraviolet range, a vacuum ultraviolet range, or combinations thereof. In one embodiment, the radiation is EUV radiation with a wavelength of about 13.5 nm. Alternatively, in some embodiments, the radiation has a wavelength range greater than about 100 nm. For example, a radiation source may be a light source such as a krypton fluoride (KrF) excimer laser with a wavelength of 248 nm, an argon fluoride (ArF) excimer laser with a wavelength of 193 nm, a fluorine dimer ( F2The light source can be an excimer laser with a wavelength of 157 nm, or other light sources. In some embodiments, only two exposure processes are needed, or more than four exposure processes can be required to develop a latent image structure in the resist layer. 520 form.

[0034] The phase shift masks, which are created in the first exposure process 530 , in the second exposure process 540 , in the third exposure process 550 and in the fourth exposure process 560 They are used and contain a structure, such as an integrated circuit structure according to a design layout, which is used during each of the exposure processes. 530 , 540 , 550 and 560 to the resist layer 520 is transferred. In one embodiment, the phase shift mask is a reflective mask. In one example, various phase shift masks (mask) are used. 1 , mask 2 , mask3 , mask 4 ), which have the same integrated circuit structure, in the first exposure process 530 , in the second exposure process 540 , in the third exposure process 550 and in the fourth exposure process 560 used. In some embodiments, mask 1 , mask 2 , mask 3 and mask 4 different areas of a single phase shift mask, as in Fig. 8E shown.

[0035] As in Fig. 8A can be seen, projecting the first exposure process 530 Radiation of the first exposure dose ( E1 ) on the phase shift mask ( PSM ) MASK 1 , and some of the radiation is absorbed by the resist layer 520 reflected, thereby the structure of the PSM mask 1 to the resist layer 520 is transferred to the latent image structure 532 to form the latent image sections532A contains. In some embodiments, where the resist layer 520 If a positive tone resist material is present, the latent image sections will be 532A partially soluble. Then, as in Fig. 8B can be seen, projected by the second exposure process. 540 Radiation of the second exposure dose ( E2 ) on the PSM mask 2 , and some of the radiation is absorbed by the resist layer 520 reflected, thereby the structure of the PSM mask 2 to the resist layer 520 is transferred to determine the solubility of the latent image structure. 532 , more precisely, the latent image sections 532A , to increase. The latent image structure 532 It therefore contains the latent image sections. 532B , which are more soluble than the latent image sections 532A The solubility of the latent image sections is increased due to the additional exposure dose applied in the second exposure process. 540is supplied. As in Fig. To see 8C, the third exposure process is projected. 550 Radiation of the third exposure dose ( E3 ) on the PSM mask 3 , and some of the radiation is absorbed by the resist layer 520 reflected, thereby the structure of the PSM mask 3 to the resist layer 520 is transferred to determine the solubility of the latent image structure. 532 , more precisely, the latent image sections 532B , to increase further. The latent image structure 532 It therefore contains the latent image sections. 532C , which are more soluble than the latent image sections 532B As in Fig. To see 8D, the fourth exposure process is projected. 560 Radiation of the fourth exposure dose ( E4 ) on the PSM mask 4 , and some of the radiation is absorbed by the resist layer 520 reflected, thereby the structure of the PSM mask 4 to the resist layer520 is transferred to determine the solubility of the latent image structure. 532 , more precisely, the latent image sections 532C , to increase further. The latent image structure 532 It therefore contains the latent image sections. 532D , which are more soluble than the latent image sections 532C Because the total exposure dose of the first exposure dose ( E1 ), the second exposure dose ( E2 ), the third exposure dose ( E3 ) and the fourth exposure dose ( E4 ) approximately equal to the optimal exposure dose ( E OP ) is (within a range of approximately 90% to approximately 110% of the optimal exposure dose), the latent image sections are 532D soluble, so that the latent image structure 532 can be developed.

[0036] The multiple exposure process described above is fully compatible with the actions performed by a scanner when the entire wafer is exposed by stepwise movement and sweeping. The impact on wafer throughput resulting from the multiple exposure process can be minimized according to embodiments of the disclosure. The phase-shift mask (PSM) allows the use of a reduced exposure dose. That is, although multiple exposures are used, each exposure dose is lower than that which would be required without a PSM, thereby increasing wafer throughput. Therefore, embodiments of the disclosure enable a synergy of increased wafer throughput and a reduced reject rate due to mask defects.In addition to reducing the effects of randomly distributed mask defects, embodiments of the disclosure can also effectively reduce the effects of other random errors, such as conductor edge roughness and registration errors of mask structures.

[0037] The use of a multiple exposure process to create the latent image structure 532 in the resist layer 520 , where each exposure process exposes the resist layer 520 Bringing a similar structure into contact with an exposure dose lower than the optimal exposure dose reduces the effects of defects or defect regions in the masks used during the multiple exposure process. For example, in the embodiment shown, the masks or mask areas exposed during the first exposure process 530 , of the second exposure process 540 , of the third exposure process550 and the fourth exposure process 560 Defects or defect regions are used. In the example where different phase shift masks are used, the MASK contains 1 , MASK 2 , MASK 3 and MASK 4 a phase defect region. Or, in the embodiment where different sections of the MASK are used, one or more of the different sections contain a phase defect region. Because the exposure dose applied to the MASK 1 , MASK 2 , MASK 3 and MASK 4 or if the different sections of the phase shift mask are projected, and the exposure dose is lower than the optimal exposure dose, the effects of such phase defect regions in the mask will be reduced. 1 , MASK 2 , MASK 3 and MASK 4or significantly reduced in the various sections of the phase-shift mask. Since such defects or defect regions are randomly distributed across the different masks or mask areas, no single defect or defect region receives the full exposure dose. More precisely, the intermediate frame intensity affected by each individual defect or defect region is reduced, thereby decreasing the printability of such a defect or defect region.

[0038] Different embodiments can have different advantages, and no specific advantage is required for every embodiment. In one embodiment, the exposure dose for each exposure is approximately equal to the optimal exposure dose ( E OP ), divided by N, where N is a total number of exposures. Accordingly, in the present embodiment, the first exposure dose ( E1) the second exposure dose ( E2 ), the third exposure dose ( E3 ) and the fourth exposure dose ( E4 ) essentially equal to a quarter of the optimal exposure dose ( E OP Alternatively, the first exposure dose ( E1 ), the second exposure dose ( E2 ), the third exposure dose ( E3 ) and the fourth exposure dose ( E4 ) approximately equal to the varying fractions of the optimal exposure dose ( E OP The exposure dose of each of the multiple EUV exposure processes can be adjusted according to the defect printability. Thus, if a defect on a mask or in a mask region is easier to print, the exposure dose for the mask or mask region is reduced. In some embodiments, a total exposure dose ( E T ) of the multiple exposure doses within 90% to 110% of the optimal exposure dose ( E OP ).

[0039] After the resist layer 520 Once it has received full exposure, the resist layer can 520 They undergo a firing process after exposure (post-exposure bake, PEB). As in Fig. To see 8F, a development process will take place. 570 on the resist layer 520 executed, thereby creating the structured resist layer 520A arises. During the development process 570 A development solution will be applied to the resist layer. 520 applied. In one embodiment, the developing solution is a basic solution, such as tetramethylammonium hydroxide (TMAH). Depending on the characteristics of the resist layer. 520Any concentration of TMAH developer solution can be used, such as approximately 2.38% TMAH developer solution. Depending on the resist material, the developer solution removes exposed or unexposed sections of the resist layer. 520 For example, the resist layer contains 520 in the present embodiment a positive tone resist material, so that the development process 570 the exposed sections of the resist layer 520 (the latent image structure 522 ) removed (dissolves), thereby removing the unexposed sections of the resist layer 520 above the wafer 510 remain. Alternatively, if the resist layer 520 The negative tone resist material is removed during the development process. 570 the unexposed sections of the resist layer 520 (dissolves them), thereby exposing the exposed sections of the resist layer 520 above the wafer 510residues remain. In some embodiments, a rinsing process, such as rinsing with deionized (DI) water, is performed. In some embodiments, the rinsing process removes residue particles.

[0040] The structured resist layer 520A contains openings 572 , the sections of the underlying wafer 510 Expose. Subsequent processing may involve removing sections of the exposed wafer. 510 Etching can be used to obtain the metal. Alternatively, metal deposition, ion implantation, or other processes can be applied over or onto the wafer. 510 to be executed. The structured resist layer 520A It can then be removed (or peeled off) by any suitable process. For example, the structured resist layer can be 520A They can be removed with a fluid (or peeling solution). In some cases, where the exposed sections of the wafer 510When subjected to an ion bombardment or plasma treatment process, the fluid attracts the ion-bombarded, structured resist layer. 520A and / or the plasma-treated, structured resist layer 520A off. After the structured resist layer 520A Once the removed material has been removed, subsequent processing can proceed to complete the fabrication of an integrated circuit device. In some embodiments, additional structuring, etching, deposition, and other processes can be performed to form additional structural elements of the integrated circuit device.

[0041] A photolithography device 900 According to one embodiment of the disclosure, in Fig. Figure 9 illustrates a semiconductor substrate. 510 , onto which a photoresist layer 520 The coating is processed in the photolithography device. 900The semiconductor substrate coated with the photoresist is exposed to radiation. It is moved through a wafer table. 910 supported. A photomask 40 is through a mask table 905 supported. In some embodiments, the photomask 40 and the photoresist layer separated by a distance Di. The wafer table 910 In some embodiments, it is configured to move laterally L or vertically V relative to a photomask 40 to move. The lateral movement L involves movement along the X-axis or the Y-axis (inward). The vertical movement V occurs along the Z-axis. In some embodiments, the wafer table 910 vertically relative to the photomask 40 moved, thereby increasing the distance between the photomask 40 and the photoresist layer 520 is changed. Thus, in some embodiments, the distance between the photomask increases or decreases.40 and the photoresist layer 520 relative to the original distance Di. In some embodiments, the wafer table is configured to tilt around the X-axis or the Y-axis.

[0042] In some embodiments, the radiation is extreme ultraviolet radiation, and the photomask 40 is a reflective ELTV phase-shift photomask. In some embodiments, the extreme ultraviolet radiation is emitted from an EUV radiation source. 915 generated. The EUV radiation source 915 generates EUV radiation 534 , which are based on the photomask 40 is directed and by the reflective photomask 40 is reflected further. The reflected EUV radiation 536 Contains structural information according to the structure in the photomask 40 The reflected EUV radiation 536 , which carries the structural information, exposes the photoresist layer520 in a structured manner, thereby creating a latent structure in the photoresist layer 520 The structure is formed according to the photomask structure. A structure is formed in the structured, exposed photoresist layer by developing the exposed photoresist layer using a suitable developer. The photoresist is either a positive-tone or a negative-tone resist. In some embodiments, the structure in the photoresist is extended into an underlying layer using a suitable etching operation. The etching operation can be a wet or dry etching operation. After the structure has formed in the underlying layer, the remaining photoresist is removed by a suitable photoresist peeling or plasma ashing process.

[0043] The EUV lithography device 900 uses the EUV radiation source 915to generate ELTV light, such as ELTV light with a wavelength in the range between approximately 1 nm and approximately 100 nm. In a specific example, the EUV radiation source generates 915 an ELTV light with a wavelength centered at approximately 13.5 nm. In the present embodiment, the EUV radiation source uses 915 a mechanism of laser-produced plasma (LPP) to generate EUV radiation.

[0044] The EUV radiation source 915It contains a target droplet generator and an LPP collector. In some embodiments, the target droplets are made of tin (Sn), lithium (Li), or an alloy of Sn and Li. In some embodiments, the target droplets have a diameter ranging from about 10 micrometers (µm) to about 100 µm. For example, in one embodiment, the target droplets are tin droplets with a diameter of about 10 µm to about 100 µm. In other embodiments, the target droplets are tin droplets with a diameter of about 25 µm to about 50 µm. In some embodiments, the target droplets are fed through the nozzle of the target droplet generator. The target droplets are then heated by a laser that pulses synchronously with the ejection of target droplets through the nozzle.In some embodiments, a laser pre-pulse heats the target droplets as they move through the excitation zone, transforming them into low-density target plumes. These plumes are then heated by a main laser pulse, creating a high-temperature plasma. The plasma emits EUV radiation, which is collected and focused by a collector for the lithography exposure process.

[0045] In some embodiments, the laser contains a carbon dioxide (CO2) or neodymium-doped yttrium aluminum garnet (Nd:YAG) laser source with a wavelength in the infrared region of the electromagnetic spectrum. In some embodiments, the laser has a wavelength of 9.4 µm or 10.6 µm.

[0046] In some embodiments, additional optics are provided between the EUV radiation source as needed. 915 and the photomask 40 or between the photomask 40and the photoresist layer 520 , to determine the size of the structure on the photoresist layer 520to further reduce or focus EUV radiation. For the purposes of this text, the term "optics" shall be understood in a broad sense, so that it includes, for example (but is not necessarily limited to), one or more components that reflect and / or transmit and / or work with incident light, and includes, but is not limited to, one or more lenses, windows, filters, wedges, prisms, gratings, gratings, transmission fibers, etalons, diffusers, homogenizers, detectors and other instrument components, apertures, axicons and mirrors, including multilayer mirrors, mirrors with near-perpendicular incidence, mirrors with grazing incidence, mirror reflectors, diffuse reflectors, and combinations thereof.Furthermore, unless otherwise specified, the term "optics" as used in this text shall not be limited to components that operate exclusively or advantageously within one or more specific wavelength ranges, such as the EUV output light wavelength, the irradiation laser wavelength, a wavelength suitable for metrology, or any other special wavelength.

[0047] In some embodiments, the movement of the wafer table 910 and the generation of the exposure radiation is controlled by a control unit. Fig. 10A and Fig. Figure 10B illustrates a control unit 920 according to some embodiments of the present disclosure. In some of the embodiments, the control unit 920 A computer system that includes computer hardware and computer programs. Fig. Figure 10A is a schematic view of a computer system that controls radiation generation and wafer table movement. All or some of the processes, procedures, and / or operations of the preceding embodiments can be implemented using computer hardware and computer programs running on it. The operations include wafer table movement, exchanging one phase-shift mask for another, sequence of exposure triggers, exposure dose, EUV radiation generation (including the Sn droplet generation rate), and laser pulse timing. In some embodiments, the computer system is combined with a computer. 925 equipped with an optical disc read-only storage device (for example, CD-ROM or DVD-ROM) drive 945 and a magnetic disk drive 950 , a keyboard 930 , a mouse 935 and a monitor 940 contains.

[0048] Fig. 10B is a diagram showing an internal configuration of some embodiments of the control unit. 920 shows. In Fig. 10B is the computer 925 - in addition to the optical disc drive 945 and the magnetic disk drive 950 - with one or more processors 960 , such as a microprocessing unit (MPU) 960 , a ROM 965 , in which a program such as a boot program is stored, a random access memory (RAM) 970 , the one with the MPU 960 is connected and in which a command of an application program is temporarily stored and a temporary memory area exists, a hard drive 975 , on which an application program, a system program and data are stored, and a bus 990 , who is undergoing the MPU 960 , the ROM 965and similar devices are connected, equipped. It should be noted that the computer 925 may include a network card (not shown) to provide a connection to a LAN.

[0049] The program that controls the control unit 920 caused to execute the functions of the sequence of exposure triggers, exposure dose and wafer table movement of the preceding embodiments, can be on an optical disk 980 or a magnetic disk 985 , which go into the optical disc drive 945 or the magnetic disk drive 950 be inserted, saved and added to the hard drive 975 can be transferred. Alternatively, the program can be transferred to the computer via a network (not shown). 925 transferred and stored on the hard drive 975 The program will be stored. At the time of execution, the program will be loaded into RAM. 970 The program can be run from the optical disc.980 or the magnetic disk 985 or be loaded directly from a network. The program does not necessarily need to contain, for example, an operating system (OS) or a third-party program to access the computer. 925 to cause the functions of the photomask data generation and fusion device from the preceding embodiments to be executed. The program only needs to contain one instruction section to call a suitable function (module) in a controlled mode and obtain the desired results.

[0050] Fig. Figure 11 is a flowchart illustrating an extreme ultraviolet lithography process. 1 illustrated according to one embodiment of the present disclosure. In operation S1110 A phase-shift mask is provided that has at least two mask regions with the same circuit structure. A resist layer is used in operation.S1120 formed over a substrate. An optimal exposure dose of Eop is determined during surgery. S1130 for the photoresist layer 520 determined. In operation S1140 The resist layer is irradiated with extreme ultraviolet radiation using a phase-shift mask to expose the same area of ​​the resist layer multiple times through the two mask regions. For example, if the same structure is exposed four times using four different masks or mask regions, each dose is equal to Eop / 4. Extreme ultraviolet irradiation of the resist layer involves multiple exposure processes, and each of these processes uses an exposure dose of extreme ultraviolet radiation that is lower than the optimal exposure dose.

[0051] In some embodiments, at least one of the two mask regions of the phase-shift mask contains a defect. In some embodiments, the optimal exposure dose is based on the exposure for a structure on one of the at least two mask regions to achieve a target dimension under a corresponding single exposure process. In some embodiments, the total exposure dose is the optimal exposure dose for the photoresist layer. 520 In some embodiments, the optimal exposure dose is determined beforehand and stored in a memory. The optimal exposure doses can be determined and stored for different wafer sizes, photoresist compositions, and photoresist layer thicknesses. In some embodiments, the stored optimal exposure dose is transferred to the control unit before the exposure operations. 900 fed in.

[0052] In some embodiments, the exposure is a coating exposure, and the semiconductor substrate 510 During the coating exposure operation, it is moved in such a way that the coating radiation creates the desired structure in the photoresist layer. 520 exposed. Moving the semiconductor substrate 510 relative to the photomask 40 Moving the wafer table between exposure operations is involved. 910 , which supports the semiconductor wafer, closer to, or further away from, the photomask 40 , for example - for example in a vertical direction, or moving (stepping) the wafer table 910 in a lateral direction - from a die on the semiconductor substrate 510 to another die. During the stepping operation, the wafer table 910The mask is moved (stepped) incrementally so that the same section is positioned over a different die in a subsequent exposure operation than in a previous exposure operation. The first section and the second section of the photoresist layer 520 In some embodiments, they are exposed simultaneously during the exposure operation.

[0053] Then, in some embodiments, the semiconductor substrate 510 relative to the photomask 40 moved, and the first section of the photoresist layer 520 is exposed to a third exposure dose of extreme ultraviolet radiation using a third mask area, the second section of the photoresist layer. 520 is exposed with the third exposure dose of extreme ultraviolet radiation using the second mask area, and a third section of the photoresist layer 520The third exposure dose is applied using the first mask area. In some embodiments, the first, second, and third sections of the photoresist layer are exposed. 520 During the exposure operation, the two parts were essentially exposed simultaneously.

[0054] In some embodiments, the semiconductor substrate 510 then relative to the photomask 40 moved, and the first section of the photoresist layer 520 is exposed with a fourth exposure dose of extreme ultraviolet radiation using a fourth mask area, the second section of the photoresist layer. 520 is exposed with the fourth exposure dose of extreme ultraviolet radiation using the third mask area, a third section of the photoresist layer. 520is exposed with the fourth exposure dose using the second mask area, and a fourth section of the photoresist layer 520 The fourth exposure dose of extreme ultraviolet radiation is applied using the first mask area. The first, second, third, and fourth sections of the photoresist layer. 520 In some embodiments, they are exposed essentially simultaneously during the exposure operation.

[0055] In some embodiments, the first mask region, the second mask region, the third mask region, and the fourth mask region each have the same circuit or chip structure. Thus, the same structural images are present in the first section of the photoresist layer. 520 layered on top of each other.

[0056] In some embodiments, the first, second, third, and fourth exposure doses are different. In some embodiments, the first and third exposure doses are the same, and the second and fourth exposure doses are the same. In some embodiments, the first and third exposure doses are different from the second and fourth exposure doses. In some embodiments, each of the first, second, third, and fourth exposure doses is less than the target exposure dose. In some embodiments, the sum of all exposure doses received by each section of the photoresist layer is substantially equal to the optimal exposure dose.In some embodiments, each of the first, second, third and fourth exposure doses is approximately one quarter of the optimal total exposure dose.

[0057] In some embodiments, the method includes performing additional exposure steps (triggers) such that each section of the photoresist layer 520 the same number of times it is exposed.

[0058] Fig. Figure 12 is a flowchart illustrating an extreme ultraviolet lithography process. 1200 illustrated according to one embodiment of the present disclosure. In operation S1210 Two phase-shift masks with identical circuit structures are provided. A resist layer is used in operation. S1220 formed over a substrate. An optimal exposure dose is determined during surgery. S1230 for the photoresist layer 520 determined. In operation S1240The resist layer is irradiated with extreme ultraviolet radiation using two phase-shift masks to expose the same area of ​​the resist layer multiple times through the two phase-shift masks. This irradiation of the resist layer with extreme ultraviolet radiation involves multiple exposure processes, and each of these processes uses an exposure dose of extreme ultraviolet radiation that is lower than the optimal exposure dose.

[0059] In some embodiments, at least one of the two phase-shift masks contains a defect. In some embodiments, the optimal exposure dose is based on the exposure for a structure on one of the at least two phase-shift masks to achieve a target dimension under a corresponding single exposure process. In some embodiments, the total exposure dose is the optimal exposure dose for the photoresist layer. 520 In some embodiments, the optimal exposure dose is determined beforehand and stored in a memory. The optimal exposure doses can be determined and stored for different wafer sizes, photoresist compositions, and photoresist layer thicknesses. In some embodiments, the stored optimal exposure dose is transferred to the control unit before the exposure operations. 900 fed in.

[0060] In some embodiments, the exposure is a scanning exposure, and the semiconductor substrate 510 During the scanning exposure operation, the device is moved in such a way that the scanning radiation projects the desired structure into the photoresist layer. 520 exposed. Moving the semiconductor substrate 510 relative to the masks 40 Moving the wafer table between exposure operations is involved. 910 , which supports the semiconductor wafer, closer to, or further away from, the photomask 40 , for example - for example in a vertical direction, or moving (stepping) the wafer table 910 in a lateral direction - from a die on the semiconductor substrate 510 to another die. During the stepping operation, the wafer table 910The mask is moved (stepped) in such a way that in a subsequent exposure operation, one mask is positioned over a different die than in a previous exposure operation. The first section and the second section of the photoresist layer. 520 In some embodiments, they are exposed simultaneously during the exposure operation.

[0061] Then, in some embodiments, the semiconductor substrate 510 relative to the masks 40 moved, and the first section of the photoresist layer 520 The second section of the photoresist layer is exposed to a third exposure dose of extreme ultraviolet radiation using a third phase-shift mask. 520 is exposed with the third exposure dose of extreme ultraviolet radiation using the second phase-shift mask, and a third section of the photoresist layer 520The third exposure dose is applied using the first phase-shift mask. In some embodiments, the first, second, and third sections of the photoresist layer are exposed. 520 During each exposure operation, the exposure is essentially simultaneous.

[0062] In some embodiments, the semiconductor substrate 510 then relative to the masks 40 moved, and the first section of the photoresist layer 520 The second section of the photoresist layer is exposed to a fourth exposure dose of extreme ultraviolet radiation using a fourth phase-shift mask. 520 is exposed with the fourth exposure dose of extreme ultraviolet radiation using the third phase-shift mask, a third section of the photoresist layer. 520is exposed with the fourth exposure dose using the second phase-shift mask, and a fourth section of the photoresist layer 520 The fourth exposure dose of extreme ultraviolet radiation is used to expose the sample to the first phase-shift mask. The first, second, third, and fourth sections of the photoresist layer are then exposed. 520 In some embodiments, they are exposed essentially simultaneously during the exposure operation.

[0063] In some embodiments, the first, second, third, and fourth phase-shift masks each have the same circuit or chip structure. Thus, the same structural images are present in the first section of the photoresist layer. 520 layered on top of each other.

[0064] In some embodiments, the first, second, third, and fourth exposure doses are different. In some embodiments, the first and third exposure doses are the same, and the second and fourth exposure doses are the same. In some embodiments, the first and third exposure doses are different from the second and fourth exposure doses. In some embodiments, each of the first, second, third, and fourth exposure doses is less than the target exposure dose. In some embodiments, the sum of all exposure doses received by each section of the photoresist layer is substantially equal to the optimal exposure dose.In some embodiments, each of the first, second, third and fourth exposure doses is approximately one quarter of the optimal total exposure dose.

[0065] In some embodiments, the method includes performing additional exposure steps (triggers) such that each section of the photoresist layer 520 the same number of times it is exposed.

[0066] Fig. Figure 13 is a flowchart illustrating an extreme ultraviolet lithography process. 1300 illustrated according to one embodiment of the present disclosure. In operation S1310 At least two phase-shift mask regions with the same structure are provided. A resist layer is used in operation. S1320 formed over a substrate. An optimal exposure dose is determined during surgery. S1330 for the resist layer 520The optimal exposure dose is determined based on an exposure dose for a previously specified structure on one of at least two phase-shift mask regions to achieve a target dimension under a corresponding single exposure process. In operation S1140 A latent image is formed in the resist layer using the two phase-shift mask regions. Forming the latent image involves performing at least two exposures on the same region of the resist layer. Each of the at least two exposures uses an exposure dose that is lower than the optimal exposure dose. The sum of the exposure doses of each of the at least two exposures is approximately equal to the optimal exposure dose.

[0067] In some embodiments, performing at least two exposures involves each of the at least two exposure processes projecting the same structure of the at least two phase-shift mask regions onto the same region of the resist layer. In some embodiments, the at least two phase-shift mask regions are derived from a single phase-shift mask. In some embodiments, the at least two phase-shift mask regions are derived from at least two phase-shift masks. In some embodiments, the exposure doses of each of the at least two exposures are substantially the same. In some embodiments, the exposure doses of each of the at least two exposures are different. In some embodiments, the method involves performing additional exposure steps (triggers) such that each section of the photoresist layer 520the same number of times it is exposed.

[0068] Fig. Figure 14 is a flowchart illustrating an extreme ultraviolet lithography process. 1400 illustrated according to one embodiment of the present disclosure. In operation S1410 A first phase shift mask area is provided. A second phase shift mask area with the same structure as the first phase shift mask area is created in operation. S1420 A resist layer is provided in operation. S1430 formed over a substrate. An optimal exposure dose is determined during surgery. S1440 for the resist layer 520The same area of ​​the resist layer is exposed using the first phase-shift mask area with a first exposure dose and using the second phase-shift mask area with a second exposure dose. Both the first and second exposure doses are lower than the optimal exposure dose.

[0069] In some embodiments, the first phase shift mask area and the second phase shift mask area are derived from a single phase shift mask. 40 In some embodiments, the first phase shift mask region and the second phase shift mask region are derived from two phase shift masks. 40In some embodiments, at least one of the first phase-shift mask region and one of the second phase-shift mask region has a defect. In some embodiments, the first exposure dose is different from the second exposure dose. In some embodiments, the first exposure dose is the same as the second exposure dose. In some embodiments, the same area of ​​the resist layer is used. 520 The photoresist layer is exposed with four exposure doses. In some embodiments, the sum of all exposure doses used to expose the same area of ​​the resist layer is essentially equal to the optimal exposure dose. In some embodiments, the method includes performing additional exposure steps (triggers) such that each section of the photoresist layer is exposed 520 the same number of times it is exposed.

[0070] To improve the exposure resolution in an EUVL operation, multiple exposures of the photoresist-coated wafer are performed using one or more phase-shift masks. For example, in some embodiments, each die on the photoresist-coated wafer is exposed four times with the same structure on one or more phase-shift masks.

[0071] In some embodiments, the phase-shift mask contains the same structure at four adjacent locations on the mask, and when the wafer is moved relative to the exposure beam, each die is exposed four times with the same structure. To prevent overexposure of a given die, the exposure dose of each exposure is one-quarter of the desired total exposure dose. The reduced exposure dose for each exposure is achieved in some embodiments by moving the wafer table faster for each exposure. For example, the wafer table can be moved at four times the normal speed during the coating exposure, so that each die is exposed for only one-quarter of the total exposure time for each exposure. The present disclosure is not limited to four exposures of each die, and the multiple number of exposures can also be two, three, five, or more.In some embodiments, multiple exposures through different sections of a single phase-shift mask or multiple phase-shift masks with the same structure smooth out any defects that may be present at a given location of the one or more phase-shift masks.

[0072] Fig. 15-49 show a method for exposing a photoresist-coated semiconductor wafer 510 according to one embodiment of the present disclosure. As in Fig. As shown in Figure 15, a die in the lower left is first exposed to radiation with a radiation dose of less than the optimal dose using a reflective phase-shift mask.

[0073] The photomask 40 is then relative to the wafer 510 in Fig. The die was moved upwards by 16, and three dies were exposed with a radiation dose lower than the optimal dose. Thus, the originally exposed die (the die at the bottom left) was exposed twice. The two dies above the first die were each exposed once.

[0074] The photomask 40 The diagram shows six structural regions that have the same structure, so that up to six dies can be exposed at once. However, the present disclosure is not limited to masks that have the same structure six times, and in some embodiments the mask contains two, three, four, five or more than six of the same structure, whereby two, three, four, five or more dies can be imaged on the wafer simultaneously.

[0075] In Fig. 17 will be the photomask 40 relative to the wafer 510 moved upwards, and the wafer 510The exposure is performed using an exposure dose that is lower than the optimal exposure dose. As explained in the present text, moving the mask 40 relative to the wafer 510 in some embodiments by moving the wafer table 910 accomplished.

[0076] As in Fig. 18 shown, the mask 40 relative to the wafer 510 The die was moved upwards, and an exposure was performed using an exposure dose lower than the optimal dose. The two uppermost dies were exposed once, and the four lower dies were exposed twice.

[0077] As in Fig. As shown in 19, the mask 40 relative to the wafer 510The dies are moved upwards, and the two upper dies in the bottom left are exposed a second time with an exposure dose lower than the optimal dose. Thus, each die in the leftmost column of dies has been exposed twice.

[0078] The mask 40 is then relative to the wafer 510 in Fig. 20 moved to the right, and four dies are exposed, resulting in the two top dies in the first column being exposed three times and the two top dies in the second column being exposed once with exposure doses lower than the optimal exposure dose.

[0079] In Fig. The mask will be worn in 21 40 relative to the wafer 510 moved downwards, and the wafer 510The samples were exposed using EUV radiation. Thus, the two uppermost dies in the first column were exposed four times, and the two uppermost dies in the second column were exposed twice. The third dies from the top in the first and second columns were exposed three times and once, respectively.

[0080] As in Fig. 22 shown, the mask 40 relative to the wafer 510 The image is moved downwards, and an exposure with a dose lower than the optimal dose is performed. The third image from the top of the first column was exposed four times, the third image from the top of the second column was exposed twice, the second and third images from the bottom of the first column were exposed three times, and the second and third images from the bottom of the second column were exposed once.

[0081] The mask 40 is then relative to the wafer 510 in Fig. The dies were moved downwards by 23, and the three bottom dies in the first and second columns were exposed with a dose lower than the optimal dose. Thus, the second and third dies from the bottom in the first column were exposed four times. The second and third dies from the bottom in the second column were exposed twice. The bottom die in the first column was exposed three times, and the bottom die in the second column was exposed once.

[0082] In Fig. The mask will be 24 40 relative to the wafer 510 moved downwards, and the wafer 510The die is exposed with an exposure dose that is lower than the optimal exposure dose. After this step, all dies in the first column have been exposed four times, and all dies in the second column have been exposed twice. In embodiments where each exposure is approximately one-quarter of the total exposure dose, each die in the first column is now fully exposed.

[0083] As in Fig. 25 shown, the mask 40 relative to the wafer 510 The slider is moved to the right, and an exposure lower than the optimal exposure dose is performed. The lower die in the second column was now exposed three times, and the lower die in the third column was exposed once.

[0084] The mask 40 is then relative to the wafer 510 in Fig. The dies were moved upwards by 26, and six dies were exposed with less than the optimal exposure dose. Thus, the second and third dies from the bottom of the second column were exposed three times, once above and twice below the target focus, and the second and third dies from the bottom of the third column were exposed once. The bottom dies of the second and third columns were exposed four times and twice, respectively.

[0085] In Fig. The mask will be 27 40 relative to the wafer 510 moved upwards, and the wafer 510The exposure was performed using a dose lower than the optimal dose. Thus, the second and third dies from the bottom of the second column were exposed four times, and the third die from the top of the second column was exposed three times. The second and third dies from the bottom of the third column were exposed twice, and the third die from the top of the third column was exposed once.

[0086] As in Fig. 28 shows the mask 40 relative to the wafer 510 The exposure is moved upwards, and an exposure lower than the optimal exposure dose is performed. The two uppermost dies in the second column are exposed a third time, and the third die from the top of the second column has now been exposed four times. The two uppermost dies in the third column have been exposed once, and the third die from the top of the third column has been exposed twice.

[0087] The mask 40is then relative to the wafer 510 in Fig. The process moved upwards from column 29, and the two uppermost dies in the second and third columns were exposed with a lower exposure dose than the optimal dose. Thus, the two uppermost dies in the second column were exposed four times, and the two uppermost dies in the third column were exposed twice.

[0088] In Fig. The mask will turn 30. 40 relative to the wafer 510 moved to the right, and the wafer 510 The dies are exposed with a dose lower than the optimal dose. Therefore, the two top dies in the third column and the two top dies in the fourth column were exposed three times and once, respectively.

[0089] As in Fig. 31 shows the mask 40 then relative to the wafer 510The die was moved downwards, and an exposure lower than the optimal exposure dose was performed. The two uppermost dies in the third and fourth columns were exposed four times and twice, respectively. The third die from the top of the third column was exposed three times, and the third die from the top of the fourth column was exposed once.

[0090] As in Fig. 32 shown, the mask 40 relative to the wafer 510 The dies were moved downwards, and six dies were exposed with an exposure dose lower than the optimal dose. Thus, the third dies from the top of the third and fourth columns were exposed four times and twice, respectively. The second and third dies from the bottom of the third column were exposed three times. The second and third dies from the bottom of the fourth column were exposed once.

[0091] The mask 40 is then relative to the wafer 510 in Fig. The dies were moved downwards by 33, and six dies were exposed with an exposure dose lower than the optimal exposure dose. Thus, the second and third dies from the bottom of the third column were exposed four times. The second and third dies from the bottom of the fourth column were exposed twice. The bottom dies of the third and fourth columns were exposed three times and once, respectively.

[0092] In Fig. The mask will be 34 40 relative to the wafer 510 moved downwards, and the wafer 510 The exposure dose is less than optimal. Therefore, the lower dies in the third and fourth columns were exposed four times and twice, respectively.

[0093] As in Fig. 35 shown, the mask 40 relative to the wafer 510The camera is moved to the right, and an exposure lower than the optimal exposure dose is performed. The lower dies of the fourth and fifth columns were then exposed three times and once, respectively.

[0094] The mask 40 is then relative to the wafer 510 in Fig. The process moved upwards from column 36, and the six lower dies in the fourth and fifth columns were exposed with a dose lower than the optimal dose. Thus, the second and third dies from the bottom of the fourth column were exposed three times. The second and third dies from the bottom of the fifth column were exposed once. The bottom die in the fourth column was exposed four times, and the bottom die in the fifth column was exposed twice.

[0095] In Fig. The mask will be 37 40 relative to the wafer 510 moved upwards, and the wafer 510The exposure was performed using a dose lower than the optimal dose. The second and third dies from the bottom of the fourth column were exposed four times, and the second and third dies from the bottom of the fifth column were exposed twice. The third die from the top of the fourth column was exposed three times, and the third die from the top of the fifth column was exposed once.

[0096] As in Fig. 38 shows the mask 40 relative to the wafer 510 The exposure was moved upwards, and an exposure lower than the optimal exposure dose was performed. The two uppermost dies in the fourth column were now exposed three times, and the two uppermost dies in the fifth column were exposed once. The third die from the top of the fourth column was exposed four times, and the third die from the top of the fifth column was exposed twice.

[0097] In Fig. The mask will be 39 40 relative to the wafer 510 The dies were moved upwards, and four of them were exposed with an exposure dose lower than the optimal dose. The two topmost dies of the fourth column were exposed four times, and the two topmost dies of the fifth column were exposed twice.

[0098] As in Fig. 40 shown, the mask 40 relative to the wafer 510 The image is moved to the right, and an exposure lower than the optimal exposure dose is performed. The two topmost dies in the fifth column are exposed a third time, and the two topmost dies in the fifth column were exposed once.

[0099] The mask 40 is then relative to the wafer 510 in Fig. The exposure meter moved downwards on column 41, and the six dies in the upper right corner of the fifth and sixth columns were exposed with less than the optimal exposure dose. Thus, the two uppermost dies in the fourth column were exposed four times, and the two uppermost dies in the sixth column were exposed twice. The third die from the top of the fifth column was exposed three times, and the third die from the top of the sixth column was exposed once.

[0100] In Fig. The mask will be 42 40 relative to the wafer 510 moved downwards to the right, and the wafer 510 The images were exposed with less than the optimal exposure dose. Therefore, the second and third dies from the bottom of the fifth column and the second and third dies from the bottom of the column were exposed three times and once, respectively. The third die from the top of the fifth column and the third die from the top of the sixth column were exposed four times and twice, respectively.

[0101] As in Fig. 43 shows the mask 40 then relative to the wafer 510 The dies were moved downwards, and an exposure lower than the optimal exposure dose was performed. The second and third dies from the bottom of the fifth and sixth columns were exposed four times and twice, respectively. The lower dies of the fifth and sixth columns were exposed three times and once, respectively.

[0102] As in Fig. 44 shows the mask 40 relative to the wafer 510 The die was moved downwards, and an exposure with a dose lower than the optimal dose was performed. The two lower dies in the fifth and sixth columns were then exposed four times and twice, respectively.

[0103] The mask 40 is then relative to the wafer 510 in Fig. The position was moved 45 degrees to the right, and the lower die in the sixth column was exposed with less than the optimal exposure dose. Thus, the lower die of the sixth column was exposed three times.

[0104] In Fig. The mask will be 46 40 relative to the wafer 510 The dies were moved upwards, and four of them were exposed with less than the optimal exposure dose. The bottom die in the sixth column was now exposed four times, and the second and third dies from the bottom of the sixth column were exposed three times.

[0105] As in Fig. 47 shows the mask 40 relative to the wafer 510 The image was moved upwards, and an exposure with a dose lower than the optimal dose was performed. The second and third images from the bottom of the sixth column were exposed four times, and the third image from the top of the sixth column was exposed once.

[0106] The mask 40 is then relative to the wafer 510 in Fig. The exposure was moved upwards by 48, and an exposure lower than the optimal exposure dose was performed. The two top dies in the sixth column were now exposed three times, and the third die from the top of the sixth column was exposed four times.

[0107] In Fig. 49 will be the mask 40 relative to the wafer 510 moved upwards, and the wafer 510 The dies were exposed with less than the optimal exposure dose. The two uppermost dies of the sixth column were exposed four times; thus, all dies in the 6×6 arrangement were exposed four times.

[0108] The 6×6 arrangement of dies on the semiconductor wafer 510 or the 2×3 arrangement of dies in a phase shift mask of the Fig. Figures 15-49 are examples of the disclosure, and the present disclosure is not limited to a wafer with 36 dies or a mask with 6 identical die structures. In some embodiments, fewer than 36 dies or more than 36 dies are exposed. In the embodiment of Fig. The mask was worn from 15-49 40 relative to the wafer 510 moved or stepped (moved step by step) in the following cycle: Stepping from one die to an adjacent die, then stepping two more dies, followed by stepping to an adjacent die, and alternating between a one-die step and a two-die step.

[0109] In some embodiments, the phase-shift mask has a 2×2 arrangement of dies, each die having the same structure. When a phase-shift mask with a 2×2 arrangement of dies is used, the mask is stitched one die at a time between exposures.

[0110] As in Fig. As shown in Figure 50, methods according to the disclosed embodiments enable an unexpected reduction in defects. For example, CD variations are drastically reduced, particularly at the ends of the distribution, corresponding to structural elements near the edge of printability, as shown in the histograms. A single exposure process produced 120 failures at a critical dimension of 22 ±5 nm, while a quadruple exposure process reduced the number of failures to 12 in some embodiments, as shown in the region between the vertical bars in Figure 50. Fig. Figure 50 is shown. The region bounded by the vertical bars lies below 17 nm (the lower acceptance limit of the critical dimension).

[0111] In some embodiments, a method for inspecting a phase-shift mask is provided. The method involves inspecting a phase-shift mask containing several identical circuit structures. The phase-shift mask is inspected. If a defect is found at a specific location in one of the circuit structures and is not found at the same locations in other identical circuit structures on the phase-shift mask, then the mask passes the inspection. If a defect is found in a mask structure, in some embodiments it is not resolved in the illustrated photoresist.

[0112] In some embodiments, a phase-shift mask is provided that includes several identical circuit structures. One of these identical circuit structures has a defect at a specific location. The other identical circuit structures do not have the same defect at the same location. In some embodiments, the phase-shift mask is acceptable for use in a photolithography process because the defect on only one of the identical circuit structures is not resolved in the imaged photoresist exposed using the mask containing the defect.

[0113] It is desirable to improve the resolution of EUVL operations to increase the production yield of semiconductor devices. In some cases, structural defects in a mask or particle contamination on a mask surface cause defects in a photoresist layer structure when the photomask containing the defect or contamination is used to form the structure in the photoresist layer. To improve the exposure resolution in an EUVL operation and avoid defective structures due to particles or mask defects, multiple exposures of the photoresist-coated wafer are performed. For example, in some embodiments, each die on the photoresist-coated wafer is exposed four times with the same structure using a different section of the mask.In some embodiments, the exposure mask contains the same structure at four adjacent locations on the mask, and when the wafer is moved relative to the exposure beam, each die is exposed four times with the same structure. To prevent overexposure of a given die, the exposure dose of each exposure is one-quarter of the desired total exposure dose. The reduced exposure dose for each exposure is achieved in some embodiments by performing a faster sweep with the exposure beam for each exposure. Thus, the photoresist-coated wafer is exposed for a shorter time during each sweep exposure. For example, the sweep beam can be moved relative to the photoresist layer at four times the normal speed, so that each die is exposed for one-quarter of the total exposure time in each sweep.In some embodiments, the reduced exposure dose is achieved by moving the wafer stage faster during each coating exposure. It is unlikely that a defect in, or particle contamination on, one structure would be found at the same location in another structure of the mask. Because each exposure is below the desired total exposure, isolated defects or particles on one section of the mask are not imaged in the photoresist layer. According to embodiments of the disclosure, the cumulative exposure doses of multiple exposures using different sections of the mask with the same circuit or chip structure reproduce the structure in the photoresist without imaging the isolated defects or particles.

[0114] Although performing multiple exposures at different depths of field can increase the time required to expose all dies on the wafer, the semiconductor device fabrication process is overall more efficient due to the reduced number of defects and the higher device production yield enabled by embodiments of the disclosure. Multiple exposures of the same section of a photoresist layer through different sections of a phase-shifting mask having the same circuit structure prevent defects or contaminant particles formed on a single mask structure from affecting the structure formed in the photoresist layer using the mask with the defect or particle contamination.Performing the methods of the present disclosure enables an improved Image Log Slope (ILS), which is a measure of the steepness of an image when transitioning from light to dark, and an improved Mask Error Enhancement Factor (MEEF), which is the ratio of the change in resist structure element width to the change in mask structure element width.

[0115] One embodiment of the disclosure is an extreme ultraviolet lithography (EUVL) process comprising the provision of at least two phase-shift mask regions with identical structure and the formation of a resist layer over a substrate. An optimal exposure dose of the resist layer is determined. A latent image is formed on the same region of the resist layer by a multiple exposure process. The multiple exposure process comprises several exposure processes, and each of the multiple exposure processes uses a phase-shift mask region that is different from the at least two phase-shift mask regions having identical structure. In one embodiment, at least one of the at least two phase-shift mask regions contains a defect. In another embodiment, the at least two phase-shift mask regions originate from a single phase-shift mask.In one embodiment, the at least two phase-shift mask regions are derived from at least two phase-shift masks. In another embodiment, the optimal exposure dose is based on an exposure dose for a structure on one of the at least two phase-shift mask regions to achieve a target dimension under a corresponding single exposure process. In another embodiment, the exposure dose of each of the multiple exposure processes is less than the optimal exposure dose. In another embodiment, the exposure doses of each of the multiple exposure processes are equal. In another embodiment, the exposure doses of each of the multiple exposure processes are different. In another embodiment, the sum of the exposure doses of the multiple exposure processes lies within a range of 90% to 110% of the optimal exposure dose.In one embodiment, forming a latent image on the same area of ​​the resist layer involves performing four exposure processes, each of which uses a different phase-shift mask area having the same structure.

[0116] Another embodiment of the disclosure is an extreme ultraviolet lithography (EUVL) process comprising the provision of at least two phase-shift masks with identical circuitry and the formation of a resist layer over a substrate. An optimal exposure dose of the resist layer is determined, and the resist layer is irradiated with extreme ultraviolet radiation using the at least two phase-shift masks to expose an identical area of ​​the resist layer multiple times using each of the at least two phase-shift masks. The irradiation of the resist layer with extreme ultraviolet radiation comprises multiple exposure processes, and each of the multiple exposure processes uses an exposure dose of extreme ultraviolet radiation that is lower than the optimal exposure dose. In one embodiment, at least one of the at least two phase-shift masks contains a defect.In one embodiment, the optimal exposure dose is based on an exposure dose for a structure on one of the at least two phase-shift masks to achieve a target dimension under a corresponding single exposure process. In another embodiment, the sum of the exposure doses of the individual exposure processes lies within a range of 90% to 110% of the optimal exposure dose. In another embodiment, the exposure doses of the individual exposure processes are different from each other. In yet another embodiment, the exposure doses of the individual exposure processes are the same. In yet another embodiment, the exposure of each region of the resist layer is an accumulation of four exposures, each using a different mask region with the same circuit structure.

[0117] Another embodiment of the disclosure is an extreme ultraviolet lithography (EUVL) process comprising the provision of at least two phase-shift mask regions with an identical structure, and at least one of the at least two phase-shift mask regions contains a defect. A resist layer is formed over a substrate. An optimal exposure dose is determined based on an exposure dose for a previously specified structure on one of the at least two phase-shift mask regions to achieve a target dimension under a corresponding single exposure process. A latent image is formed in the resist layer using the at least two phase-shift mask regions.Forming a latent image comprises the following: performing at least two exposures on the same area of ​​the resist layer, each of the at least two exposures using an exposure dose lower than the optimal exposure dose, and the sum of the exposure doses of the at least two exposures being within 90% to 110% of the optimal exposure dose. In one embodiment, performing at least two exposures comprises projecting the same structure of the at least two phase-shift mask regions onto the same area of ​​the resist layer. In one embodiment, the at least two phase-shift mask regions are derived from a single phase-shift mask. In another embodiment, the at least two phase-shift mask regions are derived from at least two phase-shift masks. In one embodiment, the exposure doses of each of the at least two exposures are equal.In one embodiment, the exposure doses for each of the at least two exposures are different from each other.

[0118] Another embodiment of the disclosure is a method comprising: providing a first phase-shift mask region and providing a second phase-shift mask region with the same structure as the first phase-shift mask region. A resist layer is formed over a substrate, and an optimal exposure dose is determined for the resist layer. The same region of the resist layer is exposed using at least the first phase-shift mask region with a first exposure dose and the second phase-shift mask region with a second exposure dose. The first exposure dose and the second exposure dose are both lower than the optimal exposure dose. In one embodiment, the first phase-shift mask region and the second phase-shift mask region are derived from a single phase-shift mask.In one embodiment, the first phase-shift mask region and the second phase-shift mask region are derived from two phase-shift masks. In another embodiment, at least one of the first phase-shift mask regions and the second phase-shift mask region has a defect. In another embodiment, the first exposure dose is different from the second exposure dose. In yet another embodiment, the first exposure dose is equal to the second exposure dose. In yet another embodiment, the sum of all exposure doses for the same region of the resist layer lies within 90% to 110% of the optimal exposure dose.

[0119] Another embodiment of the disclosure is a photolithography device comprising a radiation source and a phase-shift mask, the latter comprising a first mask region and a second mask region, both having the same structure. A mask table is configured to support the phase-shift mask, and a wafer table is configured to support a wafer.A control unit is configured to: determine an optimal exposure dose for a resist layer coated onto the wafer; control the exposure of a first section of the resist layer to a first exposure dose using the first mask region of the phase-shift mask; control the movement of the wafer relative to the phase-shift mask; and control the exposure of the first section of the resist layer to a second exposure dose using the second mask region of the phase-shift mask and the exposure of a second section of the resist layer to the second exposure dose using the first mask region of the phase-shift mask. In one embodiment, the phase-shift mask is a reflective mask. In one embodiment, the radiation source is an extreme ultraviolet radiation source.In one embodiment, the phase-shift mask includes a third mask region and a fourth mask region, both of which have the same structure as those in the first mask region or the second mask region. In another embodiment, the control unit is further configured to: control exposure of the first section of the resist layer to a third exposure dose using a third mask region of the phase-shift mask, exposure of the second section of the resist layer to the third exposure dose using the second mask region of the phase-shift mask, and exposure of a third section of the resist layer to the third exposure dose using the first mask region of the phase-shift mask, wherein the third mask region has the same structure as those in the first mask region or the second mask region.In one embodiment, the control unit is further configured to: control an exposure of the first section of the resist layer to a fourth exposure dose using a fourth mask area of ​​the phase-shift mask, an exposure of the second section of the resist layer to the fourth exposure dose using the third mask area of ​​the phase-shift mask, an exposure of the third section of the resist layer to the fourth exposure dose using the second mask area of ​​the phase-shift mask, and an exposure of a fourth section of the resist layer to the fourth exposure dose using the first mask area of ​​the phase-shift mask, wherein the fourth mask area has the same structure as that in the first mask area or the second mask area or the third mask area.In one embodiment, the control unit is further configured to control additional exposures such that each section of the resist layer is exposed through an equal number of different mask areas. In one embodiment, the wafer table is configured for lateral movement during coating exposure operations and stepping from one die to another. In another embodiment, the wafer table is further configured to move in a vertical direction and to rotate about a horizontal axis.

[0120] Another embodiment of the disclosure is a photolithography device comprising a radiation source and a first phase-shift mask and a second phase-shift mask, both having the same structure. A mask stage is configured to support the first phase-shift mask, and a wafer stage is configured to support a wafer. A control unit is configured to: determine an optimal exposure dose for a resist layer coated on the wafer; control the exposure of a portion of the resist layer to a first exposure dose using the first phase-shift mask; control the exchange of the first phase-shift mask for the second phase-shift mask on the mask stage; and control the exposure of the portion of the resist layer to a second exposure dose using the second phase-shift mask.In one embodiment, both the first and second phase-shift masks are reflective masks. In one embodiment, the radiation source is an extreme ultraviolet radiation source. In one embodiment, the wafer table is configured for lateral movement during coating exposure operations and stepping from one die to another. In one embodiment, the control unit is further configured to control the movement of the wafer table. In one embodiment, the photolithographic device includes a third phase-shift mask, wherein the third phase-shift mask has the same circuit structure as the first and second phase-shift masks.In one embodiment, the photolithographic device includes a fourth phase-shift mask, wherein the fourth phase-shift mask has the same circuit structure as the first, second, and third phase-shift masks. In another embodiment, the control unit is further configured to: control the exposure of the first section of the photoresist layer to a third exposure dose of radiation using a third phase-shift mask; control the exposure of the second section of the photoresist layer to the third exposure dose of radiation using the second phase-shift mask; and control the exposure of a third section of the photoresist layer to the third exposure dose using the first phase-shift mask, wherein the third phase-shift mask has the same circuit structure as the first and second phase-shift masks.In one embodiment, the control unit is further configured to: control an exposure of the first section of the photoresist layer to a fourth exposure dose of radiation using a fourth phase-shift mask, an exposure of the second section of the photoresist layer to the fourth exposure dose of radiation using the third phase-shift mask, an exposure of the third section of the photoresist layer to the fourth exposure dose of radiation using the second phase-shift mask, and an exposure of a fourth section of the photoresist layer to the fourth exposure dose of radiation using the first phase-shift mask, wherein the fourth phase-shift mask has the same circuit structure as the first, second, and third phase-shift masks.In one embodiment, the control unit is further configured to control additional exposure steps such that each section of the photoresist layer is exposed an equal number of times. In another embodiment, the wafer table is further configured to move in a vertical direction and to rotate about a horizontal axis.

[0121] The above outlines features of various embodiments or examples so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments or examples presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure.

Claims

[1] Extreme ultraviolet lithography (EUVL) process, which includes: Provide at least two phase shift mask regions with an identical structure; Formation of a resist layer over a substrate; Determining an optimal exposure dose for the resist layer; and Formation of a latent image on the same area of ​​the resist layer through a multiple exposure process, wherein the multiple exposure process contains multiple exposure processes, and each of the multiple exposure processes uses a phase-shift mask area that is different from the at least two phase-shift mask areas that have the same structure. [2] EUVL method according to claim 1, wherein at least one of the at least two phase-shift mask regions contains a defect. [3] EUVL method according to claim 1, wherein the at least two phase shift mask regions are derived from a single phase shift mask. [4] EUVL method according to claim 1, wherein the at least two phase shift mask regions are derived from at least two phase shift masks. [5] EUVL method according to one of the preceding claims, wherein the optimal exposure dose is based on an exposure dose for a structure on one of the at least two phase-shift mask regions to achieve a target dimension under a corresponding single exposure process. [6] EUVL method according to one of the preceding claims, wherein the exposure dose of each of the multiple exposure processes is less than the optimal exposure dose. [7] EUVL method according to one of the preceding claims, wherein the exposure doses of the individual exposure processes are the same. [8] EUVL method according to any one of the preceding claims 1 to 6, wherein the exposure doses of the individual exposure processes are different from each other. [9] EUVL method according to one of the preceding claims, wherein the sum of the exposure doses of the multiple exposure processes is within a range of 90% to 110% of the optimal exposure dose. [10] EUVL method according to one of the preceding claims, wherein forming a latent image on the same area of ​​the resist layer includes performing four exposure processes, each of which uses a different phase-shift mask area having the same structure. [11] Photolithography apparatus comprising the following: a radiation source; a phase shift mask containing a first mask region and a second mask region, both of which have the same structure; a mask table configured to support the phase shift mask; a wafer table configured to support a wafer; and a control unit the control unit is configured for the following: Determining an optimal exposure dose for a resist layer coated onto the wafer; Controlling the exposure of a first section of the resist layer to a first exposure dose using the first mask region of the phase-shift mask; Controlling the movement of the wafer relative to the phase shift mask; and Controlling an exposure of the first section of the resist layer to a second exposure dose using the second mask area of ​​the phase shift mask, and an exposure of a second section of the resist layer to the second exposure dose using the first mask area of ​​the phase shift mask. [12] Photolithography apparatus according to claim 11, wherein the phase-shift mask is a reflective mask. [13] Photolithography apparatus according to claim 11 or 12, wherein the radiation source is an extreme ultraviolet radiation source. [14] Photolithography apparatus according to any one of the preceding claims 11 to 13, wherein the phase-shift mask includes a third mask area and a fourth mask area, both of which have the same structure as the first mask area or the second mask area. [15] Photolithography apparatus according to any one of the preceding claims 11 to 14, wherein the control unit is further configured to: control an exposure of the first section of the resist layer to a third exposure dose using a third mask area of ​​the phase-shift mask, an exposure of the second section of the resist layer to the third exposure dose using the second mask area of ​​the phase-shift mask, and an exposure of a third section of the resist layer to the third exposure dose using the first mask area of ​​the phase-shift mask, wherein the third mask area has the same structure as that in the first mask area or the second mask area. [16] Photolithography apparatus according to claim 15, wherein the control unit is further configured to: control an exposure of the first section of the resist layer to a fourth exposure dose using a fourth mask area of ​​the phase-shift mask, an exposure of the second section of the resist layer to the fourth exposure dose using the third mask area of ​​the phase-shift mask, an exposure of the third section of the resist layer to the fourth exposure dose using the second mask area of ​​the phase-shift mask, and an exposure of a fourth section of the resist layer to the fourth exposure dose using the first mask area of ​​the phase-shift mask, wherein the fourth mask area has the same structure as that in the first mask area or the second mask area or the third mask area. [17] Photolithography apparatus according to claim 16, wherein the control unit is further configured to control additional exposures such that each section of the resist layer is exposed through an equal number of different mask areas. [18] Photolithography apparatus comprising the following: a radiation source; a first phase shift mask and a second phase shift mask, both of which have the same structure; a mask table configured to support the first phase shift mask; a wafer table configured to support a wafer; and a control unit the control unit is configured for the following: Determining an optimal exposure dose for a resist layer coated onto the wafer; Controlling the exposure of a section of the resist layer to a first exposure dose using the first phase-shift mask; Controlling the exchange of the first phase shift mask for the second phase shift mask on the mask table; and Controlling an exposure of a section of the resist layer to a second exposure dose using the second phase shift mask. [19] Photolithography apparatus according to claim 18, wherein both the first phase-shift mask and the second phase-shift mask are reflective masks. [20] Photolithography apparatus according to claim 18 or 19, wherein the radiation source is an extreme ultraviolet radiation source.