Methods using the formation of epitaxial source / drain structures

Abstract

A semiconductor fabrication method comprising: providing a semiconductor structure (100) comprising: a substrate (102); bottom, second, third and fourth fins (106) over the substrate (102); forming an epitaxial n-type source / drain “S / D” structural element (130) on the first and second fins (106); and forming an epitaxial p-type S / D structural element (140) on the third and fourth fins (106); and performing a selective etching process on the semiconductor structure to remove upper sections of the epitaxial n-type S / D structural element (130) and the epitaxial p-type S / D structural element (140) such that more of the epitaxial n-type S / D structural element (130) is removed than of the epitaxial p-type S / D structural element (140), wherein the selective etching process comprises several cycles, each cycle comprising: performing a first dry etching process on the semiconductor structure (100) using a first etching gas;Performing a second dry etching process on the semiconductor structure (100) using a second etching gas different from the first etching gas; and performing a wet cleaning process to remove a polymer layer formed in the first dry etching process.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US patent application with serial number entitled “Optimized Epitaxial Structure and Method for Resistance and Capacitance Reduction”, filed on August 31, 2018, the entire disclosure of which is hereby incorporated by reference into the present text. BACKGROUND

[0002] The integrated semiconductor (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to generations of ICs, each featuring smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be formed using a manufacturing process) has decreased. This process of downscaling generally delivers benefits by increasing production efficiency and reducing manufacturing costs.Such downward scaling has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to realize these advances.

[0003] For example, when a source / drain (S / D) structure is formed for a FinFET, part of the S / D structure is grown epitaxially within the S / D region of the FinFET. Multiple epitaxial S / D structures on different fins can fuse during their growth to form a fused S / D structure. In this way, a single contact element can be formed on the fused S / D structure to control the sources / drains of multiple fins. While the fused S / D structure is a useful IC structure, its shape profile is often difficult to control. Although existing S / D formation processes are generally adequate for their intended purposes, they have not proven entirely satisfactory in every respect (for example, in realizing different shape profiles for n-type and p-type FinFETs). List of characters

[0004] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1 is a flowchart of a method for forming a semiconductor device according to various aspects of the present disclosure. Fig. Figure 2A illustrates a three-dimensional view of a section of a semiconductor device at an intermediate stage of manufacturing according to some embodiments. Fig. 2B, Fig. 3A and Fig. 4 are cross-sectional views of a section of the semiconductor device in Fig. 2A along the line “ A-A “according to some embodiments, at intermediate stages of manufacturing according to one embodiment of the method in Fig. 1. Fig. 2C and Fig. Figure 3B shows cross-sectional views of a section of the semiconductor device in Fig. 2A along the line “ B-B “according to some embodiments, at intermediate stages of manufacturing according to one embodiment of the method in Fig. 1. Fig. 5 and Fig. Figure 7 illustrates enlarged views of a section of the semiconductor device in Fig. 2A along the line “ A-A “(with an additional fused epitaxial S / D structural element) according to some embodiments at intermediate stages of manufacturing according to an embodiment of the method in Fig. 1. Fig. Figures 6A-6E illustrate a partial view of the semiconductor device in Fig. 5, which undergoes a void formation process. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0006] Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed. Moreover, the formation of a structural element on, in conjunction with, and / or coupled to another structural element in the following present disclosure may include embodiments in which the structural elements are in direct contact, and may also include embodiments in which further structural elements may be formed that lie between the structural elements, so that the structural elements may not be in direct contact.Furthermore, spatially relative terms, such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "under", "upwards", "downwards", "above", "below", etc., and their derivatives (e.g., "in a horizontal direction", "downwards", "upwards", etc.), are used to simplify the present disclosure with regard to the relationship of one structural element to another. These spatially relative terms are intended to cover different orientations of the component containing the structural elements. Moreover, when a number or range of numbers is described by "about", "approximately", and the like, the term is also intended to include numbers that lie within a meaningful range containing the stated number, such as within ±10% of the stated number or other values, as would be understood by a person skilled in the art.For example, the term "approximately 5 nm" covers the dimension range from 4.5 nm to 5.5 nm.

[0007] Since multiple epitaxial S / D structural elements fuse during their growth, it is sometimes difficult to precisely control the height of the fused S / D structural element (referred to as "fusion height" or simply "fusion height") during the fabrication of semiconductor transistor devices. MH “ (“merge height”)). Since an S / D contact structure element sits above the fused S / D structure element, the MH can have a capacitance ( C) between the S / D contact structure element and a nearby metal gate structure. Furthermore, when etching contact holes for depositing S / D contact structure elements, it can be difficult to optimize the contact hole profile for both n-type and p-type FinFETs simultaneously. Depending on whether a fused S / D structure element is intended for an n-type or a p-type FinFET, its ideal contact hole profile differs. For example, for an n-type FinFET, a deeper contact recess on the fused S / D structure element can increase contact resistance ( R ) between the contact structure element and the fused S / D structure element. For a p-type FinFET, however, a deeper contact recess can undesirably increase the contact resistance.

[0008] The present disclosure provides methods for forming epitaxial structures that have optimized shape profiles for resistance and capacitance reduction. According to some embodiments, a fused S / D structural element with an increased merge height (Merge Height, MH ) are formed. The increased fusion height reduces the overlap area of ​​the S / D structural element and a nearby metal gate, and therefore reduces a capacity ( C) in between. The increased fusion height is achieved through several techniques. As a first example, prior to forming a fused S / D structural element, the two underlying fins are partially etched to provide space for epitaxial growth of the S / D structural element. During this partial etching process, maintaining a larger remaining fin sidewall height increases the fusion height. The fin sidewall height, and thus the increased fusion height, can be within a range of approximately 3–15 nanometers greater than in conventional manufacturing processes, or about 0.1–0.5 times the fin center-to-center distance. As a second example, the epitaxial growth conditions of the S / D structural element can be specifically tailored to delay the fusion of separate S / D structural elements onto fins. Details of the embodiments are described below in conjunction with the figures.

[0009] Fig. Figure 1 illustrates a flowchart of a process 10 to form a semiconductor device 100 (hereinafter referred to as “Device 100”) according to some embodiments of the present disclosure. The method 10 This is merely an example and is not intended to limit the present disclosure beyond what is expressly set forth in the claims. Additional operations may be performed before, during, and after the process. 10 The procedure can be performed, and some of the described operations can be replaced, omitted, or postponed to obtain additional embodiments of the method. 10 is described below in conjunction with other figures showing various three-dimensional and cross-sectional views of the device. 100 during intermediate steps of the process 10 illustrate. In particular, illustrate Fig. 2A a three-dimensional view of the device100 ; Fig. 2B, Fig. 3A and Fig. 4 illustrate cross-sectional views of the device 100 along the line AA , as in Fig. 2A shown; Fig. 2C and Fig. 3B illustrates cross-sectional views of the device 100 along line BB, as in Fig. 2A shown; Fig. 5 and Fig. Figure 7 illustrates enlarged views of the device. 100 along the line AA , but with an additional fused epitaxial S / D structural element; Fig. Figures 6A-6D illustrate a partial view of Fig. 5, which undergoes a void formation process.

[0010] The device 100 can be an intermediate device used during the processing of an integrated circuit ( IC ) or a section thereof, which may include: static random access memory ( SRAM ) and / or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (pFETs), n-type FETs (nFETs), fin-like FETs (FinFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. This disclosure is not limited to a specific number of devices or device regions or to specific device configurations. For example, the device 100 Although illustrated as a three-dimensional FET device (for example, a FinFET or a Gate-All-Around (GAA)-FET), the present disclosure can also provide embodiments for fabricating planar FET devices.

[0011] We turn to the Fig. 1 and Fig. 2A- Fig. 2C to. The procedure 10 during surgery 12 a starting device 100 ready (or receives one) that has one or more semiconductor fins 106 (sometimes referred to simply as "fins") which are from a substrate 102 protrude and are separated by an isolation structure 104 are separated. A dummy gate stack 107 is above the substrate 102 arranged and cuts the fins 106 The device 100 May contain other components, such as gate spacers (not included), which are attached to the side walls of the dummy gate stack. 107 are arranged, various layers of hard mask that are placed above the dummy gate stack. 107 are arranged (which will be discussed in detail below), barrier layers, other suitable layers, or combinations thereof.

[0012] The substrate 102The substrate may comprise an elemental semiconductor (consisting of a single element), such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; or an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. 102 It can be a single-layer material with a uniform composition. Alternatively, the substrate can be... 102 They contain multiple layers of material with similar or different compositions suitable for manufacturing IC devices. For example, the substrate could be... 102It could be a silicon-on-insulator (SOI) substrate, which has a silicon layer formed on a silicon oxide layer. In another example, the substrate could be 102 containing a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof.

[0013] In some embodiments, where the substrate 102 FETs contain various doped regions, such as source / drain regions, in or on the substrate. 102 The doped regions can be arranged as follows: depending on the design requirements, they can be doped with p-type dopants, such as phosphorus or arsenic, and / or n-type dopants, such as boron or BF₂. The doped regions can be placed directly on the substrate. 102, in a p-well structure, in an n-well structure, in a dual-well structure, or using an elevated structure. Doped regions can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0014] A semiconductor fin 106 It can be suitable to provide an n-type FET or a p-type FET. In some embodiments, the semiconductor fins can 106 In the form illustrated in this text, they may be suitable for providing FinFETs of a similar type, i.e., both n-type or both p-type. Alternatively, they may be suitable for providing FinFETs of opposite types, i.e., one n-type and one p-type. This configuration is for illustrative purposes only and is not intended to be restrictive. The semiconductor fins 106They can be manufactured using suitable processes, including photolithography and etching. The photolithography process can include: forming a photoresist layer (resist) over the substrate. 102 The process involves contacting the resist with a structure, performing firing processes after contacting, and developing the resist to form a masking element (not shown) that contains the resist. The masking element is then used to create recesses in the substrate. 102 to etch, thereby removing the semiconductor fins 106 on the substrate 102 remain. The etching process can be dry etching, wet etching, reactive ion etching ( RIE ), and / or other suitable processes.

[0015] Numerous other embodiments of methods for forming semiconductor fins 106 They may be suitable. For example, semiconductor fins 106They can be structured using dual or multiple structuring processes. Generally, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, center-to-center spacing smaller than that achievable through a single, direct photolithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and structured by a photolithography process. Spacers are formed along the structured sacrificial layer by a self-aligning process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, can then be used to structure the fins. In some embodiments, the fins have 106 after their formation a height (in Fig. 2C as F_H (designated) between approximately 50 and approximately 90 nm. Such a fin height is important for the performance of the device and the DC / AC balance.

[0016] Each of the Finns 106 contains a canal region 106b and two S / D regions 106a, which comprise the canal region 106b between them. The S / D regions 106a are used for this purpose as the source and drains of a FET to serve while the canal region 106b , which are located under the gate stack 107 located, is used to serve as a channel connecting the source and the drain. In some embodiments, the method can 10 the formation of weakly endowed S / D ( LDD )-Structural elements in the S / D regions 106a the Finns 106 contain.

[0017] The isolation structures 104 silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass ( can be used) FSG ), a dielectric material with a low k-value, and / or other suitable materials. The insulation structures 104 They may contain shallow trench insulation (STI) structural elements. In one embodiment, the insulation structures are 104 formed by the formation of semiconductor fins 106 Trenches in the substrate 102 The trenches can be etched. They can then be filled with an insulating material described above via a deposition process, followed by a chemical-mechanical planarization (CMP) process. Other insulating structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, can also be used as the insulating structures. 104 can be implemented. Alternatively, the isolation structures can be used. 104They contain a multilayer structure, which, for example, has one or more lining layers made of thermal oxide. The insulation structures 104 can be separated by any suitable method, such as chemical evaporation ( CVD ), flowable CVD ( FCVD ), Spin-on-Glass ( SOG ), other suitable methods, or combinations thereof. The isolation structures 104 can be formed by placing a dielectric layer as a spacer layer over the semiconductor fins 106 is deposited and then the dielectric layer is left out, such that a top surface of the insulating structures is formed. 104 under one top side of the semiconductor fins 106 lies.

[0018] In some embodiments, the dummy gate stack serves 107 as a placeholder for the subsequent formation of a high-k metal gate structure (High-k Metal Gate, HKMG ; where “with a high k-value” means a dielectric constant greater than that of silicon dioxide, which is approximately 3,9 is). The dummy gate stack 107 can form an oxide layer 108 including those above the canal region 106b is arranged. The oxide layer 108 can be formed by any suitable process that may involve deposition and etching. The oxide layer 108 It can include silicon dioxide or an oxide with a high k-value (having a dielectric constant greater than that of silicon dioxide), such as Hf oxide, Ta oxide, Ti oxide, Zr oxide, Al oxide, or a combination thereof. The oxide layer 108 can be formed to a thickness of a few angstroms to a few tens of angstroms.

[0019] The dummy gate stack 107 can a dummy gate electrode 110 Included. In some embodiments, the dummy gate electrode contains 110Polysilicon. In the illustrated embodiment, as in Fig. As can be seen in 2C, the dummy gate stack also contains a hard mask layer. 112 , which are above the dummy gate electrode 110 is arranged, and / or a hard mask layer 114 , which are above the hard mask layer 112 is arranged. Side wall spacers 113 are attached to the side walls of the dummy gate 110 trained. As will be discussed in detail below, sections of the dummy gate stack are used. 107 during a gate replacement process by the HKMG replaced after other components (for example, the epitaxial S / D structural elements) 250 ) the device 100 were manufactured. The hard mask layers 112 and 114 Each layer can contain any suitable dielectric material, such as a semiconductor oxide and / or a semiconductor nitride. In one example, the hard mask layer contains... 112Silicon carbonitride, and the hard mask layer 114 Contains silicon oxide. Various material layers of the dummy gate stack. 107 can be formed by any suitable process, such as CVD, PVD, ALD, chemical oxidation, other suitable processes, or combinations thereof.

[0020] As in the Fig. 1 and Fig. Seeing 3A-3B shortens the procedure 10 during surgery 14 Sections of the S / D regions 106a , for example by removing upper sections of the fins 106 , while their lower sections in the S / D regions 106a to be preserved. In many embodiments, the process removes 10 partially by a suitable etching process, such as a dry etching process, a wet etching process, or an RIE process. In some embodiments, the process removes 100 selectively the semiconductor fins 106without etching or significant etching of other components, such as the dummy gate stack 107 The etching process can occur during surgery. 14 Implement a dry etching process using an etchant, such as a bromine-containing gas (e.g., HBr and / or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, or combinations thereof. The extent to which the semiconductor fins 106 The amount of residue removed can be controlled by adjusting conditions such as pressure, temperature, and duration of the etching process. In some embodiments, the etching process uses an etchant that HBr and contains CF4, under a pressure between about 5 and about 30 millitorr and at a temperature between about 30 and about 60 degrees Celsius. In some embodiments, the etching takes about 5 to about 10 seconds. In some embodiments, as in Fig. As shown in 3B, the etching process during surgery removes 14 upper sections of the fins 106 , such that a remaining height of the fins 106 (in Fig. 3B (designated as FSW_H, where FSW stands for fin sidewall) between approximately 30% and approximately 40% of the original height of the fins 106 (i.e., F_H). As described below, maintaining such a relatively high remaining fin sidewall height supports increasing the fusion height of a fused epitaxial S / D structural element.

[0021] After shortening the S / D regions 106a The process continues 10 to form epitaxial S / D structural elements on the shortened S / D regions 106a forward. Fig. Figure 4 illustrates a simplified view focusing on two epitaxial S / D structural elements. 120A and 120B concentrated on two Finns 106are grown and ultimately become a fused epitaxial S / D structural element 120 merge. As in the Fig. 1 and Fig. As seen in section 4, the process breeds 10 during surgery 16 the epitaxial S / D structural elements 120A and 120B on two S / D regions 106a , which are on the same side of the dummy gate stack 107 The epitaxial S / D structural elements are located. 120A and 120B They initially grow separately on their respective fins and eventually fuse together at a certain height (known as a fusion height or MH designated), to form the fused epitaxial S / D structural element 120 to form.

[0022] The present disclosure allows the fused epitaxial S / D structural element 120, to achieve an optimized shape profile for resistance and capacitance reduction. In some embodiments, the fused S / D structural element can 120 by controlling the growth conditions and by increasing the remaining fin height ( FSW_H ) exhibit an increased fusion height (MH) of approximately 3 to 15 nm, which is, for example, approximately 2 to 10 nm higher than that of fused epitaxial S / D structural elements formed using other technologies. Such an increased fusion height reduces the overlap area of ​​the fused S / D structural element. 220 and a nearby metal gate (which serves as a replacement for the dummy gate stack). 116 to be trained), and therefore reduces a capacity (C) in between.

[0023] The increased fusion height of the fused epitaxial S / D structural element 120This can be achieved through several techniques. For example (as above with reference to operation). 14 (described) are performed before the formation of the fused S / D structural element. 120 the two underlying fins 106 Partial etching is performed to provide space for epitaxial growth of the S / D structural element. During this partial etching process, maintaining a larger remaining fin sidewall height (for example, approximately 30% to approximately 40% of the fin height) increases the fusion height of the fused epitaxial S / D structural element. 120 .

[0024] In another example, the epitaxial growth conditions of the S / D structural element can be adapted so that the fusion of separate S / D structural elements 120A and 120B on the Finns 106 is delayed. In one embodiment, the fused epitaxial S / D structural element has 120multiple layers of semiconductor materials, including a first layer ( L1 ), a second layer ( L2 - 1 ) and a third layer ( L2 - 2 Changing the educational conditions of these social strata can lead to a controllable MH lead to. In some embodiments, the first epitaxial layer L1 on the upper and side wall surfaces of the S / D regions 106a deposited. Furthermore, the second epitaxial layer forms. L2 - 1 around the first epitaxial layer L1 around. In the Fig. In the embodiment shown in Figure 4, the first epitaxial layers fuse. L1 the epitaxial S / D structural elements 120A and 120B No, but the second epitaxial layers L2 - 1 the epitaxial S / D structural elements 120A and 120B fuse laterally (i.e., touch each other). To create the structure as in Fig. 4 shown to form, the operation awaits 16 , until the first epitaxial layers L2 - 1 fuse laterally before the third epitaxial layer L2 - 2 is bred. It should be noted that - depending on the lateral distance (along the "x" direction) between the two fins 106 and the control of epitaxial growth - the first and second epitaxial layers, 120 and 122 , can be trained in such a way that they have different fusion profiles.

[0025] In various embodiments, the different epitaxial layers can comprise the same or different semiconductor materials, such as silicon, germanium, silicon-germanium, one or more III-V materials, a composite semiconductor, or an alloy semiconductor. In one embodiment, the fins comprise 106Silicon, and the epitaxial layers comprise silicon-germanium. The epitaxial growth process can be an LPCVD process with a silicon-based precursor, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process. For example, a silicon crystal with LPCVD They can be grown using silane (SiH4) and dichlorosilane (DCS) gases. The controllable MH may depend on a ratio between silane (SiH4) and dichlorosilane (DCS) gases, which are used to... L2-1 to form. In some embodiments, the controllable MH no less than about 55% of the height of the Finns 106 ( F_H ).

[0026] In some embodiments, the fused epitaxial S / D structural element contains 120 : a first layer of semiconductor material ( L1), which are located on the lower sections of the first and second fins 106 is grown, a second layer of semiconductor material ( L2-1 ), which is based on the L1 is grown, and a third layer of semiconductor material ( L2-2 ), which is based on the L2-1 is cultivated. In one embodiment, the L1 on the first fin 106 and the L1 not on the second fin, while the L2 -1 on the first fin and the L2-1 on the second fin at a controllable fusion height. The controllable MH depends on a ratio between silane (SiH4) and dichlorosilane (DCS) gases, which are used to control the L2-1 to form. The ratio between silane (SiH4) and dichlorosilane ( DCS The ratio of )-gases can be approximately 1:15 to approximately 1:50 in some embodiments. In one embodiment, the controllable MH is not less than approximately 55% of the height of the first and second fins. In one embodiment, the L2 -2 exhibits a substantially conformal thickness across the first and second fins.

[0027] After the formation of the fused epitaxial S / D structural element 120 The process continues 10 to create a recess thereon in preparation for forming an S / D contact on the fused epitaxial S / D structural element 120 Forward. As described above, the ideal contact hole profile of a fused S / D structural element differs depending on whether it is intended for an n-type FinFET or a p-type FinFET. For example, for an n-type FinFET, a deeper contact recess on the fused S / D structural element can result in a contact resistance ( R) between the contact structure element and the fused S / D structure element. For a p-type FinFET, however, a deeper contact recess can undesirably increase the contact resistance. The present disclosure allows optimized recess profiles for an n-type FinFET or a p-type FinFET, as described below. To demonstrate two different profiles for an n-type FinFET or a p-type FinFET, the following is illustrated. Fig. 5 a cross-sectional view of two fused epitaxial S / D structural elements, including a fused epitaxial n-type structural element 130 and a fused epitaxial p-type structural element 140 , which the fused epitaxial structural element 120 similar, unless otherwise noted.

[0028] As in the Fig. 1 and Fig. Seeing 5 saves the process 10 during surgery 18the fused epitaxial S / D structural elements 130 and 140 to form recessed grooves within it. According to some embodiments, each recess profile is optimized to reduce the contact resistance between a contact structure element and the epitaxial S / D structure element. Depending on whether the epitaxial S / D structure element is intended for an n-type FinFET or a p-type FinFET, different recess profiles are achieved. As in Fig. Figure 5 shows the fused epitaxial n-type structural element. 130 a relatively deep contact recess 132 reached. The recess 132 is deep enough to ensure that the entire lower silicon nitride (SiN) that is on the fused epitaxial n-type structural element 130 The recess is removed because any remaining silicon nitride can increase contact resistance. 132is not so deep that the fused epitaxial n-type structural element 130 would be etched through. For the fused epitaxial p-type structural element 140 A relatively shallow contact recess will be created. 142 This is achieved so that an S / D contact can directly touch a region of the S / D that has a higher Ge and / or B concentration. The recess 132 can a depth 132a within a range of approximately 15-20 nanometers. The recess 142 can a depth 142a within a range of approximately 5-10 nanometers. In some examples, the amount of material removed by the NFET device can be 1.5-2.5 times the amount of material removed by the PFET device using the selective etching process described in this text.

[0029] As in the Fig. 6A-6E can be seen during surgery 18the difference in the depths of the recesses 132 and 142 This can be achieved by specifically adjusting the etching conditions to realize different etch rates of S / D structural elements. In one embodiment, the fused epitaxial n-type structural element contains 130 Silicon doped with phosphorus, but not silicon-germanium, and the fused epitaxial p-type structural element 140 It contains silicon germanium. A selective etching procedure can be performed on the semiconductor structure to expose upper sections of the epitaxial S / D structural elements. 130 and 140 to remove where the removed section of the epitaxial n-type S / D structural element 130 thicker (for example, 1.5 to 2.5 times thicker at corresponding points on the epitaxial S / D structural elements) than the remote section of the epitaxial p-type S / D structural element 140 . Fig. Figure 6A illustrates the epitaxial n-type S / D structural element 130 and the fused epitaxial p-type structural element 140 , before the selective etching process is applied.

[0030] In the illustrated embodiment, the selective etching procedure comprises several cycles, each cycle including the execution of a first dry etching process on the semiconductor structure using the gas mixture, as described in the Fig. 6B-6D shown. As in Fig. Figure 6B shows the top surfaces of the fused epitaxial S / D structural elements. 130 and 140 brought into contact with an etching gas. In some embodiments, the etching gas is a gas mixture containing fluoromethane (CH3F), hydrogen ( H2) and carbonyl sulfide (COS). As an example of ratios between gas components, approximately 1 part fluoromethane (CH3F), approximately 10 to approximately 20 parts hydrogen (H2), and approximately 0.5 to approximately 1.5 parts carbonyl sulfide (COS) may be present. The gas mixture reacts with silicon germanium in the epitaxial p-type S / D structural element in the first dry etching process, forming a polymer layer containing germanium sulfide (GeS or GeS2). The first dry etching process removes a first thickness of the epitaxial n-type S / D structural element and a second thickness of the epitaxial p-type S / D structural element. Due to the presence of the polymer layer on the epitaxial p-type S / D structural element, the second thickness (which may be close to 0) is smaller (for example, about 1 nm smaller) than the first thickness. As in Fig. As shown in 6B, the first dry etching process also forms carbon fluoride (C x F y) as a byproduct on both the epitaxial n-type S / D structural element and the epitaxial p-type S / D structural element. In one embodiment, the thickness of the carbon fluoride layer before flushness is a maximum of 5 nm. Thus, as in Fig. As shown in Figure 6C, each cycle of the selective etching procedure also includes performing a second dry etching process on the semiconductor structure using a gas containing diazene (N₂H₂) to remove the carbon fluoride formed in the first dry etching process. In one embodiment, the thickness of the germanium sulfide (GeS or GeS₂) layer after etching is at most about 1 nm. After the several cycles of the selective etching procedure, as shown in Figure 6C, the semiconductor structure is further reduced by approximately 1 nm. Fig. The epitaxial n-type S / D structural element was shown in 6D. 130 more strongly etched than the fused epitaxial p-type structural element 140 As in Fig. As shown in Figure 6E, a wet cleaning process can be performed to remove the epitaxial p-type S / D structural element GeS / GeS2 that was formed in the first dry etching process of each cycle.

[0031] In one embodiment, the multiple cycles of the selective etching process are performed at temperatures between 20 and 60 degrees Celsius and pressures between 10 and 30 millitorr. In one embodiment, during each cycle of the selective etching process, the removed first thickness of the epitaxial n-type S / D structural element is at least 1 nm thicker than the removed second thickness of the epitaxial p-type S / D structural element. In one embodiment, the removed section of the epitaxial n-type S / D structural element has approximately 1.5 to approximately 2.5 times the thickness of the removed section of the epitaxial p-type S / D structural element.

[0032] In one embodiment, forming the recessed trench includes 132 (or 142) The following: Etching the fused S / D structural element to form an intermediate trench; depositing a silicon nitride (for example, Si3N4) spacer structural element in and over the intermediate trench; removing a lower section of the silicon nitride spacer structural element using anisotropic etching while retaining sidewall sections of the silicon nitride spacer structural element; and further etching the fused S / D structural element in the intermediate trench, creating the recessed trench.

[0033] We return to Fig. 5 back. The procedure 10 Silicidalization or germano-silicidalization can also occur on the surfaces of the epitaxial S / D structural elements. 130 and 140 form. For example, silicidation, such as nickel silicide or titanium silicide, can be formed by: deposition of a metal layer over the epitaxial S / D structural elements. 130and 140 , healing of the metal layer, such that the metal layer bonds with silicon in the epitaxial S / D structural elements 130 and 140 reacts to form the metal silicification, and the unreacted metal layer is subsequently removed. In an alternative embodiment, the process forms 10 no silicification, and the process 10 Silicidization occurs after etching of contact holes, as described below.

[0034] We turn to Fig. 7 to. The procedure 10 forms during surgery 20 S / D contacts 134 and 144 over the epitaxial S / D structural elements 130 or 140 As in Fig. As shown in 7, the recess trench 132 on the epitaxial S / D structural element 130 is deeper than the recess trench 142 on the epitaxial S / D structural element 140- one underside of the S / D contact 134 lower than one underside of the second S / D contact 144 The S / D contact 134 can a depth 134a within the S / D structural element 130 within a range of approximately 15-20 nanometers. The S / D contact 144 can a depth 144a within the S / D structural element 140 within a range of approximately 5-10 nanometers. Each S / D contact can contain one or more conductive layers and can be formed using any suitable process, such as ALD, CVD, PVD, plating, and / or other suitable processes. In some embodiments, each S / D contact contains a seed metal layer and a filler metal layer. In various embodiments, the seed metal layer contains cobalt (Co), tungsten ( W), ruthenium (Ru), nickel (Ni), other suitable metals, or combinations thereof. The filler metal layer may contain copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof.

[0035] We turn to Fig. 1 to. The procedure 100 can occur during surgery 22 Additional processing steps can be performed. For example, additional vertical interconnection elements, such as vias, horizontal interconnection elements, such as conductors, and / or multilayer interconnection elements, such as metal layers and interlayer dielectrics, can be placed over the device. 100The various interconnecting structural elements can implement different conductive materials, including copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), titanium (Ti), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), gold (Au), manganese (Mn), zirconium (Zr), ruthenium (Ru), their respective alloys, metal silicides, other suitable materials, or combinations thereof. The metal silicides can include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable metal silicides, or combinations thereof.

[0036] Without intending any limitation, one or more embodiments of the present disclosure can realize many benefits for a semiconductor device and its formation. The present disclosure provides methods for forming a fused epitaxial S / D structural element with an optimized profile. Embodiments of the present disclosure include the formation of a fused epitaxial S / D structural element with controllable fusion height and recess depth. Accordingly, the disclosed epitaxial S / D structural element reduces its contact resistance with overlying S / D contacts and its capacitance with nearby metal gate structures.

[0037] According to an example, a semiconductor fabrication process includes providing a semiconductor structure comprising a substrate and first, second, third, and fourth fins above the substrate. The process further includes: forming an epitaxial n-type source / drain (S / D) structure on the first and second fins, forming an epitaxial p-type S / D structure on the third and fourth fins, and performing a selective etching process on the semiconductor structure to remove upper portions of the epitaxial n-type S / D and p-type S / D structures, such that more of the epitaxial n-type S / D structure is removed than of the epitaxial p-type S / D structure.

[0038] According to an example, a method includes the following: providing a semiconductor structure having a substrate and first and second fins above the substrate; removing upper sections of the first and second fins while retaining lower sections of the first and second fins; growing first and second epitaxial source / drain (S / D) structural elements on the lower sections of the first and second fins such that the first and second epitaxial S / D structural elements fuse, creating a fused S / D structural element with a controllable fusion height; forming a recessed trench in the fused S / D structural element; and filling, into the recessed trench, an S / D contact that is in electrical contact with the fused S / D structural element.

[0039] According to an example, a semiconductor device comprises: a substrate, first, second, third and fourth fins projecting from the substrate, an epitaxial n-type source / drain (S / D) structural element arranged on the first and second fins, a first S / D contact arranged on the epitaxial n-type S / D structural element, an epitaxial p-type S / D structural element arranged on the third and fourth fins, and a second S / D contact arranged on the epitaxial p-type S / D structural element, wherein a bottom surface of the first S / D contact is lower than a bottom surface of the second S / D contact.

[0040] The above has outlined features of various embodiments, enabling the person skilled in the art to better understand the following disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure.

Claims

[1] Semiconductor manufacturing process comprising: Providing a semiconductor structure that features the following: a substrate; and first, second, third and fourth fins above the substrate; Formation of an epitaxial n-type source / drain (S / D) structural element on the first and second fins; and Formation of an epitaxial p-type S / D structural element on the third and fourth fins; and Performing a selective etching process on the semiconductor structure to remove upper sections of the epitaxial n-type S / D structural element and the epitaxial p-type S / D structural element, such that more of the epitaxial n-type S / D structural element is removed than of the epitaxial p-type S / D structural element. [2] The method of claim 1, wherein the selective etching process comprises several cycles, each cycle comprising: Performing a first dry etching process on the semiconductor structure using a first etching gas; Performing a second dry etching process on the semiconductor structure using a second etching gas that is different from the first etching gas; and Performing a wet cleaning process to remove a polymer layer that formed in the initial dry etching process. [3] Method according to claim 2, wherein the first etching gas is a gas mixture containing fluoromethane (CH3F), hydrogen (H2) and carbonyl sulfide (COS), wherein the gas mixture reacts with silicon germanium in the epitaxial p-type S / D structural element in the first dry etching process, forming the polymer layer containing silicon sulfide. [4] Method according to claim 2 or 3, wherein the first dry etching process removes a first thickness of the epitaxial n-type S / D structural element, wherein the first dry etching process removes a second thickness of the epitaxial p-type S / D structural element, which is less than the first thickness, due to the presence of the polymer layer on the epitaxial p-type S / D structural element, and wherein the first dry etching process also removes carbon fluoride (C x F y ) as a by-product on both the epitaxial n-type S / D structural element and the epitaxial p-type S / D structural element. [5] Method according to any one of claims 2 to 4, wherein the second etching gas contains diazene (N2H2) configured to remove the carbon fluoride formed in the first dry etching process. [6] Method according to any one of claims 2 to 5, wherein the wet cleaning process removes the epitaxial p-type S / D structural element silicon sulfide that was formed in the first dry etching process of each cycle. [7] Method according to any one of claims 2 to 6, wherein the multiple cycles of the selective etching process are carried out at temperatures between 20-60 degrees Celsius and pressures between 10-30 millitorr. [8] Method according to any one of claims 2 to 7, wherein, during each cycle of the selective etching procedure, the first thickness of the epitaxial n-type S / D structural element is at least 1 nm thicker than the second thickness of the epitaxial p-type S / D structural element. [9] Method according to any of the preceding claims, wherein the remote section of the epitaxial n-type S / D structural element has approximately 1.5 to approximately 2.5 times the thickness of the remote section of the epitaxial p-type S / D structural element. [10] Method according to any of the preceding claims, wherein the epitaxial n-type S / D structural element is configured to contain silicon doped with phosphorus but not silicon germanium, and wherein the epitaxial p-type S / D structural element is configured to contain silicon germanium. [11] Procedure comprising the following: Providing a semiconductor structure that includes a substrate and first and second fins above the substrate; Removing the upper sections of the first and second fins while retaining the lower sections of the first and second fins; Cultivating first and second epitaxial source / drain (S / D) structural elements on the lower sections of the first and second fins, such that the first and second epitaxial S / D structural elements fuse, resulting in a fused S / D structural element with a controllable fusion height; Forming a recessed trench in the fused S / D structural element; and Filling the recessed trench of an S / D contact that is in electrical contact with the fused S / D structural element. [12] Method according to claim 11, wherein the height of the remaining lower sections of the first and second fins is between about 30 and about 40% of the height of the first and second fins. [13] Method according to claim 11 or 12, wherein the fused S / D structural element comprises: a first layer of semiconductor material (L1) that is grown on the lower sections of the first and second fins; a second layer of semiconductor material (L2-1) grown on top of L1; and a third layer of semiconductor material (L2-2) that is grown on top of L2-1. [14] Method according to claim 13, wherein the L1 on the first fin and the L1 on the second fin do not fuse, wherein the L2-1 on the first fin and the L2-1 on the second fin fuse at the controllable fusion height. [15] Method according to any one of claims 11 to 14, wherein the controllable fusion height depends on a ratio between silane (SiH4) and dichlorosilane (DCS) gases used to form the L2-1. [16] Method according to any one of claims 11 to 15, wherein the controllable fusion height is located at a position that is at least about 55% of the height of the first and second fins. [17] Method according to any one of claims 13 to 16, wherein the L2-2 has a substantially conformal thickness over the first and second fins. [18] Method according to any one of claims 11 to 17, wherein forming the recessed trench comprises: Etching of the fused S / D structural element to form an intermediate trench; Deposition of a silicon nitride spacer structural element in and above the intermediate trench; Removal of a lower section of the silicon nitride spacer structural element using anisotropic etching while retaining sidewall sections of the silicon nitride spacer structural element; and Further etching of the fused S / D structural element in the intermediate trench, creating the recessed trench. [19] Semiconductor device comprising the following: a substrate; first, second, third and fourth fins that protrude from the substrate; an epitaxial n-type source / drain (S / D) structural element located on the first and second fins; a first S / D contact located on the epitaxial n-type S / D structural element; an epitaxial p-type S / D structural element located on the third and fourth fins; and a second S / D contact located on the epitaxial p-type S / D structural element, where one underside of the first S / D contact is lower than one underside of the second S / D contact. [20] Semiconductor device according to claim 19, wherein the epitaxial n-type S / D structural element is configured to contain silicon doped with phosphorus but not silicon germanium, and wherein the epitaxial p-type S / D structural element is configured to contain silicon germanium.