Electronic circuit capable of selectively compensating crosstalk noise and intersymbol interference

Abstract

Electronic circuit comprising: a first driver for outputting a driven first signal by driving a first signal from signals received in parallel; a first selection circuit for selecting one signal from the first signal and a second signal from the signals; and a first compensator circuit for generating a first compensation signal for compensating the driven first signal in response to the one signal selected by the first selection circuit, wherein, when the first selection circuit selects the first signal, the first compensator circuit generates the first compensation signal to compensate for intersymbol interference of the selected first signal, and wherein, when the first selection circuit selects the second signal, the first compensator circuit generates the first compensation signal to compensate for crosstalk noise of the driven first signal caused by a driven second signal driven from the second signal.

Description

Technical field

[0001] The present inventive concept relates to an electronic circuit and, in particular, to configurations and operations of an electronic circuit for transmitting a data signal. Description of the state of the art

[0002] Generally, an electronic device performs specific functions depending on the operations of various electronic circuits included in the electronic device. The electronic device and the electronic circuit may operate independently of each other, or they may operate while communicating with another electronic device or another electronic circuit.

[0003] As the amount of data exchanged between electronic devices increases, an electronic circuit (e.g., a communication circuit) capable of transmitting and receiving signals at high speed is used. Electronic devices are connected by a communication channel, and signals transmitted and received between the electronic devices are transmitted through the communication channel. When multiple communication channels are used, signals can be transmitted and received in parallel through the multiple communication channels. Therefore, communication performance can be further increased.

[0004] However, noise can occur due to various physical factors. For example, a signal transmitted through one communication channel may be distorted due to a physical characteristic of the communication channel, resulting in an undesirable waveform. Furthermore, the signal may be distorted due to interference from another communication channel. When this happens, the quality of signals transmitted at high speeds may be reduced, leading to communication errors.

[0005] From the documents US 6 480 021 B2, US 8 588 331 B2, US 2005 / 0 268 149 A1 and US 2012 / 0 207 196 A1, circuits and methods for reducing transmission interference caused by crosstalk of signals between several lines are known. Summary

[0006] In exemplary embodiments of the present inventive concept, an electronic circuit comprises: a first driver for outputting a driven first signal by driving a first signal from signals received in parallel; a first selection circuit for selecting the first signal or a second signal from the signals received in parallel;and a first compensator circuit for generating a first compensation signal for compensating the driven first signal in response to the first signal or the second signal selected by the first selection circuit, wherein, when the first selection circuit selects the first signal, the first compensator circuit generates the first compensation signal to compensate for intersymbol interference of the driven first signal, and wherein, when the first selection circuit selects the second signal, the first compensator circuit generates the first compensation signal to compensate for crosstalk noise of the driven first signal caused by a driven second signal driven from the second signal.;

[0007] In exemplary embodiments of the present inventive concept, an electronic circuit for transmitting an output signal comprises: a driver for receiving a first signal and outputting a driven first signal; and a compensator circuit for receiving a selected first or second signal received in parallel with the first signal and outputting a first compensation signal to compensate for intersymbol interference of the driven first signal in response to the first signal, or for outputting a second compensation signal to compensate for crosstalk noise of the driven first signal in response to the second signal.

[0008] In exemplary embodiments of the present inventive concept, an electronic circuit comprises: a driver for driving a first signal from signals received in parallel; a selection circuit for selecting the first signal or a second signal from the signals received in parallel; and a compensator circuit for compensating for a first noise occurring in the driven first signal in response to the first signal selected by the selection circuit or for compensating for a second noise of the driven first signal caused with respect to the second signal in response to the second signal selected by the selection circuit.

[0009] In exemplary embodiments of the present inventive concept, an electronic circuit comprises: a driver for driving a first signal and outputting a driven first signal; a selection circuit for selecting the first signal or a second signal received in parallel with the first signal;and compensator circuits for generating first compensation signals for compensating for intersymbol interference of the driven first signal based on the first signal, or second compensation signals for compensating for crosstalk noise of the driven first signal caused by a driven second signal driven from the second signal based on the second signal, according to a selection of the selection circuit, wherein waveforms of the first compensation signals or the second compensation signals change when an influence of the intersymbol interference or the crosstalk noise of the driven first signal changes.;

[0010] In exemplary embodiments of the present inventive concept, an electronic circuit comprises: a driver for driving a first signal and outputting a driven first signal; respective selection circuits for selecting the first signal or a second signal received in parallel with the first signal; and compensator circuits respectively connected to the selection circuits and each generating a first compensation signal for compensating for intersymbol interference of the driven first signal based on the first signal or generating a second compensation signal for compensating for crosstalk noise of the driven first signal caused by a driven second signal driven from the second signal based on the second signal, according to a selection of one of the selection circuits connected to the compensator circuit.

[0011] In exemplary embodiments of the present inventive concept, an electronic circuit comprises: a driver for receiving a first signal and outputting a driven first signal; a selection circuit for receiving the first signal and a second signal and selecting one of the first signal and the second signal; and a compensator circuit for generating a compensation signal for compensating the driven first signal in response to the first signal or the second signal selected by the first selection circuit, wherein, when the selection circuit selects the first signal, the compensator circuit generates the compensation signal to compensate for a first distortion affecting the driven first signal, and wherein, when the selection circuit selects the second signal, the compensator circuit generates the compensation signal to compensate for a second distortion affecting the driven first signal. Short description of the drawings

[0012] The above and other features of the present inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings. Fig. 1 is a block diagram illustrating a configuration of an electronic system including an electronic circuit according to exemplary embodiments of the present inventive concept. Fig. 2 is a block diagram showing a connection between transmitting circuits and receiving circuits of Fig. 1 represents. Fig. 3 is a scheme for describing crosstalk noise occurring between communication channels from Fig. 2 occurs. Fig. 4 and Fig. 5 are graphs describing long-distance crosstalk noise occurring between communication channels from Fig. 3 occurs. Fig. 6 is a graph describing how far-end crosstalk noise from Fig. 5 is compensated. Fig. 7 is a graph describing characteristics of communication channels from Fig. 2. Fig. 8 and Fig. 9 are diagrams describing intersymbol interference for a signal transmitted through a communication channel of Fig. 3 is transferred. Fig. 10 is a graph describing how intersymbol interference from Fig. 9 is compensated. Fig. 11 is a block diagram showing a configuration of an electronic circuit used in an electronic system of Fig. 1 is included. Fig. 12 is a flowchart for describing an operation of an electronic circuit of Fig. 11. Fig. 13 is a block diagram illustrating a configuration associated with an electronic circuit of Fig. 11 is associated. Fig. 14 is a diagram describing how compensation for far-end crosstalk noise or intersymbol interference is performed in an electronic circuit of Fig. 11 is carried out. Fig. 15, Fig. 16 and Fig. 17 are block diagrams illustrating a configuration associated with an electronic circuit of Fig. 11 is associated. Fig. 18 is a block diagram for describing an operation of an electronic circuit of Fig. 17. Fig. 19 is a block diagram illustrating a configuration associated with an electronic circuit of Fig. 11 is associated. Fig. 20 is a block diagram for describing an operation of an electronic circuit of Fig. 19. Fig. 21 and Fig. 22 are block diagrams illustrating configurations that can be used with an electronic circuit of Fig. 11 are associated. Fig. 23 is a block diagram showing a configuration of a memory system including an electronic circuit of Fig. 11 includes. Detailed description of the embodiments

[0013] Fig. 1 is a block diagram illustrating a configuration of an electronic system 1000 including an electronic circuit according to exemplary embodiments of the present inventive concept.

[0014] The electronic system 1000 may include electronic devices 1100 and 1300. In exemplary embodiments of the present inventive concept, each of the electronic devices 1100 and 1300 may be one of various electronic devices, such as a desktop computer, a laptop computer, a tablet computer, a smartphone, a wearable device, a video game console, an electric vehicle, home appliances, or a medical device.

[0015] However, the present inventive concept may not be limited thereto. In other exemplary embodiments of the present inventive concept, the electronic system 1000 may be a single electronic device. In these embodiments, each of the electronic devices 1100 and 1300 may be a component or intellectual property (IP) included in a single electronic device, and may be a circuit, module, chip, and / or package-level entity.

[0016] The electronic devices 1100 and 1300 can communicate with each other, in other words, the electronic devices 1100 and 1300 can exchange data signals via communication paths P1 and P2. The communication paths P1 and P2 can include a plurality of communication channels to transmit data signals in parallel, which can be described with reference to Fig. 2 is described.

[0017] The electronic device 1100 may include functional circuitry 1110, a serializer / deserializer SER / DES 1130, a transmit circuitry 1150, and a receive circuitry 1170. The electronic device 1300 may include functional circuitry 1310, a SER / DES 1330, a transmit circuitry 1350, and a receive circuitry 1370.

[0018] Functional circuits 1110 and 1310 may provide specific functions of electronic devices 1100 and 1300. For example, functional circuits 1110 and 1310 may constitute various components or IPs, such as a processor (e.g., a central processing unit (CPU) and an application processor (AP)), memory, an image sensor, and a display. Functional circuits 1110 and 1310 may process signals in different ways to provide the particular functions. In this regard, each of functional circuits 1110 and 1310 may be referred to as a "processing circuit" or "processor."

[0019] The SER / DES 1130 may serialize data generated according to operations of the functional circuits 1110. The transmission circuit 1150 may output a signal corresponding to the data serialized by the SER / DES 1130. The output signal may be transmitted from the electronic device 1100 to the electronic device 1300 through the communication path P1.

[0020] The receiving circuit 1370 may receive a signal via the communication path P1. The SER / DES 1330 may deserialize data from the signal received by the receiving circuit 1370. The deserialized data may correspond to the data generated by the functional circuits 1310. The SER / DES 1330 may provide the deserialized data to the functional circuits 1310. The functional circuits 1310 may operate based on the provided data.

[0021] The SER / DES 1330 may serialize data generated according to operations of the functional circuits 1310. The transmission circuit 1350 may output a signal corresponding to the data serialized by the SER / DES 1330. The output signal may be transmitted from the electronic device 1300 to the electronic device 1100 through the communication path P2.

[0022] The receiving circuit 1170 may receive a signal via the communication path P2. The SER / DES 1130 may deserialize data from the signal received by the receiving circuit 1170. The deserialized data may correspond to the data generated by the functional circuits 1110. The SER / DES 1130 may provide the deserialized data to the functional circuits 1110. The functional circuits 1110 may operate based on the provided data.

[0023] By using the technique described above, electronic devices 1100 and 1300 can exchange data signals with each other through communication paths P1 and P2. As a communication speed between electronic devices 1100 and 1300 increases (e.g., when transmitting circuits 1150 and 1350 and receiving circuits 1170 and 1370 operate at a higher frequency or bandwidth), electronic devices 1100 and 1300 can exchange a larger amount of data per unit time. In other words, communication performance can be improved.

[0024] In addition, a larger amount of data can be transmitted and received during the unit time when data signals are transmitted in parallel through a plurality of communication channels. A configuration implementing this will be described with reference to Fig. 2 described.

[0025] Fig. 2 is a block diagram illustrating a connection between the transmitting circuits 1150 and 1350 and the receiving circuits 1170 and 1370 of Fig. 1 represents.

[0026] Communication paths P1 and P2 may include a plurality of communication channels for transmitting data signals in parallel. For example, communication path P1 may include communication channels CH11 to CH19, and communication path P2 may include communication channels CH21 to CH29.

[0027] Each of the communication channels CH11 to CH19 and CH21 to CH29 may include a conductive material to transmit a signal. For example, each of the communication channels CH11 to CH19 and CH21 to CH29 may be a conductive pattern on a printed circuit board (PCB), a conductive wire of a cable, or a metal pin / pad of a connector.

[0028] Transmitters Tx11 to Tx19 of transmission circuit 1150 can be connected to receivers Rx11 to Rx19 of reception circuit 1370 via communication channels CH11 to CH19. Communication channels CH11 to CH19 can transmit signals between transmitters Tx11 to Tx19 and receivers Rx11 to Rx19 in parallel. For example, signals driven by transmitters Tx11 to Tx19 can be transmitted to receivers Rx11 to Rx19 in parallel via communication channels CH11 to CH19.

[0029] Transmitters Tx21 to Tx29 of transmission circuit 1350 can be connected to receivers Rx21 to Rx29 of reception circuit 1170 via communication channels CH21 to CH29. Communication channels CH21 to CH29 can transmit signals between transmitters Tx21 to Tx29 and receivers Rx21 to Rx29 in parallel. For example, signals controlled by transmitters Tx21 to Tx29 can be transmitted to receivers Rx21 to Rx29 in parallel via communication channels CH21 to CH29.

[0030] Communication channels CH11 to CH19 may be connected in parallel between transmitting circuit 1150 and receiving circuit 1170. Additionally, communication channels CH21 to CH29 may be connected in parallel between transmitting circuit 1150 and receiving circuit 1170. In this regard, communication channels CH1 to CH19 and CH21 to CH29 may be referred to as "parallel channels."

[0031] Compared to the case where a single communication channel is used, the multiple communication channels CH11 to CH19 and CH21 to CH29 can allow for the transmission of a larger amount of data. Accordingly, the communication channels CH11 to CH19 and CH21 to CH29 can be useful in an environment that transmits a large amount of data quickly.

[0032] Transmitters Tx11 to Tx19 can receive data serialized by the SER / DES 1130 in parallel and can output signals in parallel. Receivers Rx11 to Rx19 can receive signals in parallel and can provide the received signals to the SER / DES 1330 in parallel. Transmitters Tx21 to Tx29 can receive data serialized by the SER / DES 1330 in parallel and can output signals in parallel. Receivers Rx21 to Rx29 can receive signals in parallel and can provide the received signals to the SER / DES 1130 in parallel.

[0033] Fig. 3 is a diagram describing crosstalk noise occurring between the communication channels CH11 to CH19 and CH21 to CH29 from Fig. 2 occurs. Fig. 4 and Fig. 5 are graphs describing a far-end crosstalk noise occurring between the communication channels CH11 and CH12 from Fig. 3 occurs. Fig. 6 is a graph describing how far-end crosstalk noise from Fig. 5 is compensated.

[0034] Fig. Figure 3 shows two communication channels CH11 and CH12 of the communication channels CH11 to CH19 and CH21 to CH29 and the transmitters Tx11 and Tx12 and the receivers Rx11 and Rx12 connected through the communication channels CH11 and CH12. It is understood that the following descriptions for the remaining communication channels CH13 to CH19 and CH21 to CH29 are Fig. 2 may apply.

[0035] In Fig. 3, the transmitter Tx11 can transmit a signal S1(t) controlled by the transmitter Tx11 to the communication channel CH11. A time delay TD may occur while the signal S1(t) is being transmitted through the communication channel CH11 to the receiver Rx11. The receiver Rx11 can receive a signal S1(t-TD) with a delay of at most the time delay TD.

[0036] The transmitter Tx12 can transmit a signal S2(t), driven by the transmitter Tx12, to the communication channel CH12. The time delay TD can occur while the signal S2(t) is transmitted to the receiver Rx12 through the communication channel CH12. The time delay TD due to a characteristic of the communication channel CH12 can be different from the time delay TD due to a characteristic of the communication channel CH11. However, for ease of description, it is assumed that the time delay TD of the communication channel CH11 is the same as the time delay TD of the communication channel CH12. The receiver Rx12 can be expected to receive a signal S2(t-TD) having a delay of at most the time delay TD.

[0037] For example, communication channels CH11 and CH12 may be located adjacent to each other spatially or close to each other in terms of distance. In this case, due to capacitive coupling and inductive coupling between communication channels CH11 and CH12, the transmission of signal S1(t) through communication channel CH11 may influence the transmission of signal S2(t) through communication channel CH12. In addition, the transmission of signal S2(t) through communication channel CH12 may influence the transmission of signal S1(t) through communication channel CH11. These influences can cause crosstalk noise.

[0038] For a simpler explanation, the case is described where the transmission of signal S1(t) through communication channel CH11 influences the transmission of signal S2(t) through communication channel CH12. In this example, signal S1(t) can be an aggressor signal, and signal S2(t) can be a victim signal.

[0039] As a result of the aggressor signal S1(t), near-end crosstalk noise may occur at a transmitting end of the communication channel CH12, and far-end crosstalk may occur at a receiving end of the communication channel CH12. For example, far-end crosstalk may cause crosstalk noise FE(t-TD) associated with the signal S2(t-TD). Accordingly, the receiver Rx12 may receive a distorted signal "S2(t-TD) + FE(t-TD)" rather than the signal S2(t-TD).

[0040] The influence of the crosstalk noise FE(t-TD) is due to Fig. 4 and Fig. 5. In Fig. 4, for example, a level of signal S1(t) may transition from level L11 to level L12 at time T0. At time T0+TD, after the time delay TD has elapsed, receiver Rx11 may receive a delayed signal S1(t-TD).

[0041] Due to the influence of long-range crosstalk, crosstalk noise FE(t-TD) may occur at channel CH12 at a time T0+TD. Since channel CH12 is continuously affected while signal S1(t) is transmitted through channel CH11, the crosstalk noise FE(t-TD) may include a pulse.

[0042] Due to the coupling to channel CH11, the magnitude of the crosstalk noise pulse FE(t-TD) may be proportional to the slope of the signal S1(t-TD). Furthermore, the sign of the crosstalk noise pulse FE(t-TD) may be opposite to the sign of the slope of the signal S1(t-TD). For example, the crosstalk noise pulse FE(t-TD) may have a level of -L13 at time T0+TD.

[0043] In Fig. 5, for example, a level of signal S2(t) may transition from level L11 to level L12 at time T0. At time T0+TD, after the time delay TD has elapsed, receiver Rx12 can be expected to receive a delayed signal S2(t-TD). However, due to the crosstalk noise FE(t-TD), receiver Rx12 may receive a distorted signal "S2(t-TD) + FE(t-TD)" at time T0+TD. The distorted signal "S2(t-TD) + FE(t-TD)" may have an undesirable waveform that varies according to the pulse of crosstalk noise FE(t-TD). In other words, the waveform of the distorted signal “S2(t-TD) + FE(t-TD)” can vary according to the pulse of crosstalk noise FE(t-TD).

[0044] Accordingly, if the receiver Rx12 receives the distorted signal "S2(t-TD) + FE(t-TD)" instead of the signal S2(t-TD), the signal quality may deteriorate and communication errors may occur. Accordingly, embodiments of the present inventive concept may compensate for the crosstalk noise FE(t-TD) to prevent or minimize signal distortion. In an exemplary embodiment of the present inventive concept, the crosstalk noise FE(t-TD) may be compensated by applying a signal component having an opposite characteristic to a characteristic of a noise component to an intended signal to completely or partially distort the signal distortion.

[0045] In Fig. 6, embodiments of the present inventive concept may use a compensation signal -FE(t) to compensate for the signal S2(t). The compensation signal -FE(t) may have a waveform to prevent a waveform of the signal S2(t-TD) from being distorted due to crosstalk noise FE(t-TD). To achieve this, the compensation signal -FE(t) may be generated such that a characteristic of the compensation signal -FE(t) is opposite to a characteristic of the crosstalk noise FE(t-TD).

[0046] For example, the compensation signal -FE(t) may include a pulse having a characteristic opposite to a characteristic of the crosstalk noise pulse FE(t-TD). A magnitude of the pulse of the compensation signal -FE(t) may be substantially equal to a magnitude of the crosstalk noise pulse FE(t-TD). Furthermore, a sign of the pulse of the compensation signal -FE(t) may be opposite to a sign of the crosstalk noise pulse FE(t-TD). For example, the pulse of the compensation signal -FE(t) may be generated to have a level of -L13 at time T0. Furthermore, the pulse of the compensation signal -FE(t) may be generated to have various other levels at time T0, e.g., -L12, -L11.5, or -L11.

[0047] For example, a magnitude of the pulse of the compensation signal -FE(t) may be proportional to a slope of the signal S1(t-TD). Furthermore, a sign of the pulse of the compensation signal -FE(t) may be the same as a sign of the slope of the signal S1(t-TD). In this regard, in some embodiments of the present inventive concept, the compensation signal -FE(t) may be generated to include a pulse corresponding to a waveform obtained by differentiating a waveform of the signal S1(t) at time T0.

[0048] Since the compensation signal -FE(t) is applied to the signal S2(t) at time T0, a compensation signal "S2(t) + (-FE(t))" can be generated. A direction in which the pulse of the compensation signal -FE(t) compensates a waveform of the signal S2(t) may be opposite to a direction in which a waveform of the signal S2(t-TD) is distorted due to crosstalk noise FE(t). If the compensated signal “S2(t) + (-FE(t))” has an influence of the crosstalk noise FE(t-TD) while the compensated signal “S2(t) + (-FE(t))” is transmitted through the communication channel CH12, the receiver Rx12 can receive a signal “S2(t-TD) + (-FE(t-TD)) + FE(t-TD)” at the time TO+TD.

[0049] A waveform of the signal "S2(t-TD) + (-FE(t-TD)) + FE(t-TD)" can be substantially the same as or almost similar to the waveform of the intended signal S2(t-TD). Accordingly, the compensation signal -FE(t) can compensate for the crosstalk noise FE(t-TD) associated with the signal S2(t-TD). Accordingly, the signal quality can be improved and communication errors can be prevented.

[0050] Fig. 7 is a graph describing characteristics of the communication channels CH11 to CH19 and CH21 to CH29 from Fig. 2. Fig. 8 and Fig. 9 are diagrams describing intersymbol interference for the signal S2(t) transmitted through the communication channel CH12 from Fig. 3 is transferred. Fig. 10 is a graph describing how intersymbol interference from Fig. 9 is compensated.

[0051] Fig. 7 to 10 are described with respect to the signal S2(t) and the communication channel CH12, in Fig. 3. However, the descriptions are provided for easier understanding. It is therefore understood that the following descriptions for the remaining communication channels CH11, CH13 to CH19 and CH21 to CH29 from Fig. 2 may apply.

[0052] In Fig. 7, the transmitter Tx12 can transmit a signal S2(t) to the communication channel CH12. For example, a level of the signal S2(t) can transition from level L11 to level L12 at time T0. At time T0+TD, after the time delay TD has elapsed, the receiver Rx12 can be expected to receive the delayed signal S2(t-TD).

[0053] However, due to various factors, such as skin effect and dielectric loss, the communication channel CH12 may exhibit a low-pass frequency response characteristic. Due to this physical characteristic of the communication channel CH12, the receiver Rx12 may receive a distorted signal S2'(t-TD) at time T0+TD. The intensity of a high-frequency component of the distorted signal S2'(t-TD) may be weaker than the intensity of a high-frequency component of the intended signal S2(t-TD).

[0054] The low-pass frequency response characteristic of the communication channel CH12 is Fig. 8 and Fig. 9. In Fig. 8, for example, the signal S2(t) can be generated in such a way that it sequentially has signal levels corresponding to logic “0”, logic “1”, and logic “0”. While the signal S2(t) consists of Fig. 8 is transmitted from the transmitter Tx12 to the receiver Rx12 through the communication channel CH12, the signal S2(t) may be distorted due to the characteristics of the communication channel CH12. Accordingly, a waveform of the signal S2'(t-TD) received by the receiver Rx12 may differ from a waveform of the signal S2(t-TD).

[0055] In Fig. 9, for example, the signal S2(t) can be generated such that it sequentially has signal levels corresponding to logic “0”, logic “1”, logic “1”, and logic “0”. While the signal S2(t) consists of Fig. 9 is transmitted from the transmitter Tx12 to the receiver Rx12 through the communication channel CH12, symbols corresponding to logic “1” can be transmitted due to the characteristics of the communication channel CH12 with waveforms S2A and S2B.

[0056] Waveforms S2A and S2B may influence each other in a time domain (e.g., due to intersymbol interference), and signal S2(t) may be distorted. Accordingly, a waveform of signal S2'(t-TD) received by receiver Rx12 may differ from a waveform of signal S2(t-TD). While signal S2(t) is being transmitted through communication channel CH12, a waveform of signal S2(t) may be distorted, making it different from the intended waveform.

[0057] This may weaken a high-frequency component of signals transmitted through the communication channel CH12, and therefore, a bandwidth of the communication channel CH12 may be limited. In particular, as the transmission speed of signals increases, the signals may become even more distorted, and the quality of such signals may deteriorate. In some cases, erroneous data may be exchanged between the electronic devices 1100 and 1300, and errors may occur during communication. Accordingly, exemplary embodiments of the present inventive concept may compensate for intersymbol interference such that signal distortion is prevented or minimized.

[0058] In Fig. 10, embodiments of the present inventive concept may use a compensation signal PM(t) to compensate for the signal S2(t). The compensation signal PM(t) may have a waveform to prevent a waveform of the signal S2(t-TD) from being distorted due to intersymbol interference. To achieve this, the compensation signal PM(t) may be generated such that a characteristic of the compensation signal PM(t) is opposite to a low-pass frequency response characteristic of the channel CH12. For example, the compensation signal PM(t) may include a pulse to accentuate the signal S2(t).

[0059] The term "pre-emphasizing" can mean applying an effect opposite to a characteristic of the communication channel CH12 to the signal S2(t) in advance, before the transmitter Tx12 transmits the signal S2(t) to the communication channel CH12. In this case, a waveform of the signal S2(t) changes to an intended waveform (or a waveform similar to the intended waveform) while the signal S2(t) is transmitted through the communication channel CH12.

[0060] For example, a magnitude of the pulse of the compensation signal PM(t) may be proportional to a slope of the signal S2(t-TD). Furthermore, a sign of the pulse of the compensation signal PM(t) may be the same as a sign of the slope of the signal S2(t). For example, the level of the compensation signal PM(t) may be generated to have a level of L14 at time T0. In this regard, in some embodiments of the present inventive concept, the compensation signal PM(t) may be generated to include a pulse corresponding to a waveform obtained by differentiating a waveform of the signal S2(t) at time T0.

[0061] While the compensation signal PM(t) is applied to the signal S2(t) at time T0, a compensation signal “S2(t) + PM(t)” can be generated. As shown in Fig. As shown in Figure 7, the signal S2'(t-TD) may be distorted such that a level of the signal S2'(t-TD) at time T0+TD is lower than a level of the intended signal S2(t-TD). Accordingly, the compensation signal PM(t) may be generated to distort the signal S2(t) in advance such that a level of the compensated signal "S2(t)+PM(t)" at time T0 is higher than the level of the intended signal S2(t).

[0062] In other words, a direction in which the pulse of the compensation signal PM(t) compensates a waveform of the signal S2(t) may be opposite to a direction in which a waveform of the signal S2(t-TD) is distorted due to intersymbol interference. When the compensated signal "S2(t) + PM(t)" has an influence of intersymbol interference while the compensated signal "S2(t) + PM(t)" is transmitted through the communication channel CH12, the receiver Rx12 may receive a signal "S2'(t-TD) + PM'(t-TD)" at time T0+TD.

[0063] A waveform of the signal "S2(t-TD) + PM(t-TD)" can be substantially the same as or almost similar to a waveform of the intended signal S2(t-TD). Accordingly, the compensation signal PM(t) can compensate for the intersymbol interference associated with the signal S2(t-TD). Accordingly, the signal quality can be improved and communication errors can be prevented.

[0064] Although the reduction of far-end crosstalk noise and intersymbol interference with reference to Fig. 3 to 10, the present inventive concept is not limited thereto. For example, signals transmitted through communication channels CH11 to CH19 and CH21 to CH29 may be affected by various types of noise.

[0065] For example, noise affecting a signal may include noise occurring in a signal (e.g., intersymbol interference). The examples described with reference to Fig. 7 to 10 can be applied in a similar way to compensate for noise that occurs in a signal.

[0066] For example, noise affecting a signal may include noise occurring with respect to any other signal (e.g., crosstalk noise). The examples described with reference to Fig. 3 to 6 can be applied in a similar way to compensate for noise that occurs due to the influence of any other signal.

[0067] For ease of description, the following embodiments of the present inventive concept will be described as compensating for far-end crosstalk noise and intersymbol interference. However, it should be understood that the following embodiments may be modified or altered in various ways to compensate for different types of noise.

[0068] Fig. 11 is a block diagram illustrating a configuration of an electronic circuit 2000 used in the electronic system 1000 of Fig. 1 is included.

[0069] In Fig. 11, in exemplary embodiments of the present inventive concept, the electronic circuit 2000 may include a main driver 2100, a selector circuit 2300, and a compensator circuit 2400. The electronic circuit 2000 may be incorporated in the transmission circuit 1150 or 1350 of Fig. 1 must be included.

[0070] If the transmission circuit 1150 includes the electronic circuit 2000, one electronic circuit 2000 may be provided for each transmitter and each communication channel. In exemplary embodiments of the present inventive concept, in each of the transmitters Tx11 to Tx19, Fig. 2 components of the electronic circuit 2000. Alternatively, the main driver 2100 may be included in each of the transmitters Tx11 to Tx19. Furthermore, the selector circuit 2300 and the compensator circuit 2400 may be provided externally to the transmitters Tx11 to Tx19 to correspond to each of the transmitters Tx11 to Tx19.

[0071] For ease of description, the case where the transmission circuit 1150 includes the electronic circuit 2000 will be described. It should be understood that these descriptions apply similarly to the case where the transmission circuit 1350 includes the electronic circuit 2000.

[0072] The main driver 2100 can receive a signal IN1 from signals received in parallel from the SER / DES 1130. The main driver 2100 can drive the signal IN1 and can output the driven signal IN1.

[0073] The selection circuit 2300 may receive signals IN1 and IN2. The IN2 signal may be received in parallel with the IN1 signal and may be one of the signals received in parallel from the SER / DES 1130. The selection circuit 2300 may select one of the IN1 and IN2 signals. For example, the selection circuit 2300 may select the IN1 signal or the IN2 signal in response to a control signal CTL.

[0074] The selection circuit 2300 may output a signal selected from the signals IN1 and IN2. For example, the selection circuit 2300 may output the signal IN1 or the signal IN2 based on the control signal CTL. The control signal CTL is described with reference to Fig. 14 to 16.

[0075] Compensator circuit 2400 may receive a signal selected by selection circuit 2300. When selection circuit 2300 selects signal IN1 in response to control signal CTL, compensator circuit 2400 may receive signal IN1. When selection circuit 2300 selects signal IN2 in response to control signal CTL, compensator circuit 2400 may receive signal IN2.

[0076] The compensator circuit 2400 may receive a compensation signal CSG based on a signal selected by the selection circuit 2300. The compensation signal CSG may be generated based on the signal IN1 or the signal IN2 to compensate for the driven signal IN1. The compensation signal CSG may have a waveform to compensate for noise associated with the driven signal IN1. For example, the compensation signal CSG may correspond to the compensation signal -FE(t) described with reference to Fig. 6, or the compensation signal PM(t) described with reference to Fig. 10 is described.

[0077] As with reference to Fig. As described in Figures 3 to 10, the compensation signal CSG may have a waveform obtained based on a waveform of the signal IN1 or the signal IN2. Accordingly, the compensator circuit 2400 may be a hardware circuit configured to process the signal IN1 or the signal IN2 to provide a suitable waveform of the compensation signal CSG.

[0078] Since the compensation signal CSG is applied to the driven signal IN1, the driven signal IN1 can be compensated based on the compensation signal CSG. An output signal OUT may correspond to the driven signal IN1 compensated based on the compensation signal CSG. For example, the output signal OUT may correspond to the compensated signal "S2(t-TD) + (-FE(t-TD)) + FE(t-TD)" described with reference to Fig. 6, or the compensated signal “S2'(t-TD) + PM'(t-TD)” described with reference to Fig. 10. The electronic circuit 2000 can output the output signal OUT and can transmit the output signal OUT to a receiver through a communication channel.

[0079] As with reference to Fig. As described in Figures 3 to 6, while the driven signal IN1 is being transmitted through a communication channel, crosstalk noise may occur in the driven signal IN1 due to a signal driven from the signal IN2. In this case, the signal IN1 may be a victim signal, and the signal IN2 may be an aggressor signal.

[0080] Fig. 12 is a flowchart for describing an operation of the electronic circuit 2000 of Fig. 11.

[0081] For example, electronic circuit 2000 may receive a victim signal IN1 and an aggressor signal IN2 (S110). Selector circuit 2300 may provide a signal selected from the victim signal IN1 and the aggressor signal IN2 based on the control signal CTL to compensator circuit 2400 (S120).

[0082] When the selection circuit 2300 selects the aggressor signal IN2, the compensator circuit 2400 may compensate for noise (e.g., far-end crosstalk noise) of the victim signal IN1 caused by the aggressor signal IN2 based on the aggressor signal IN2 (S130). For example, when the selection circuit 2300 selects the aggressor signal IN2, the compensator circuit 2400 may output the compensation signal CSG based on the aggressor signal IN2.

[0083] For example, the compensation signal CSG generated based on the aggressor signal IN2 may correspond to the compensation signal -FE(t) calculated with reference to Fig. 6. In the victim signal IN1, crosstalk noise caused by a signal driven from the aggressor signal IN2 can be compensated based on the compensation signal CSG corresponding to the compensation signal -FE(t).

[0084] When the selection circuit 2300 selects the victim signal IN1, the compensator circuit 2400 may compensate for noise (e.g., intersymbol interference) occurring in the victim signal IN1 based on the victim signal IN1 (S140). For example, when the selection circuit 2300 selects the victim signal IN1, the compensator circuit 2400 may output the compensation signal CSG based on the victim signal IN1.

[0085] For example, the compensation signal CSG generated based on the sacrificial signal IN1 may correspond to the compensation signal PM(t) described with reference to Fig. 10. In the victim signal IN1, the intersymbol interference can be compensated based on the compensation signal CSG, which corresponds to the compensation signal PM(t).

[0086] The electronic circuit 2000 may output the output signal OUT (S150). The output signal OUT may be generated based on the driven signal IN1 and the compensation signal CSG. For example, the output signal OUT may be generated by compensating the driven signal IN1 based on the compensation signal CSG. For example, the electronic circuit 2000 may output the driven signal IN1, compensated based on the compensation signal -FE(t) or the compensation signal PM(t), as the output signal OUT. Distortion of the signal IN1 due to noise (e.g., crosstalk noise or intersymbol interference) may decrease based on the output signal OUT.

[0087] Back in Fig. 11, the main driver 2100, to perform the above operations, and the compensator circuit 2400 may be connected in parallel between a terminal for receiving the signal IN1 and a terminal for outputting the output signal OUT. In this configuration, the compensator circuit 2400 can selectively compensate for different types of noise (e.g., crosstalk noise and intersymbol interference) depending on a selection made by the selection circuit 2300.

[0088] In other words, the compensator circuit 2400 can be shared to compensate for different types of noise. Accordingly, a button size can be reduced compared to the case where separate compensator circuits are provided.

[0089] Compensation signals of the same characteristic can be used to compensate for some types of noise. For example, the compensation signal -FE(t), which has a pulse size proportional to a slope of the signal S1(t), can be used to compensate for crosstalk noise from Fig. 4. In addition, the compensation signal PM(t), which has a pulse size proportional to a slope of the signal S2(t), can be used to compensate the intersymbol interference from Fig. 9. In this example, a direction in which a pulse of the compensation signal -FE(t) compensates a waveform of the signal S2(t) may be the same as a direction in which a pulse of the compensation signal PM(t) compensates a waveform of the signal S2(t).

[0090] Accordingly, the compensator circuit 2400 can be used jointly to generate compensation signals of the same characteristic. For example, with respect to the examples of Fig. 3 to 10, the compensator circuit 2400 may generate the compensation signal CSG having a magnitude proportional to a slope of a signal input to the compensator circuit 2400. However, the signal input to the compensator circuit 2400 may be changed according to a type of noise that the compensation signal CSG compensates for and may depend on the selection of the selection circuit 2300.

[0091] Fig. 13 is a block diagram illustrating a configuration used with the electronic circuit 2000 of Fig. 11 is associated.

[0092] In exemplary embodiments of the present inventive concept, the electronic circuit 2000 may be made of Fig. 11 with an electronic circuit 2000a from Fig. 13. The electronic circuit 2000a may include a voltage mode main driver 2100a, a multiplexer 2300a, and a differentiator 2400a.

[0093] The voltage-mode main driver 2100a may correspond to the main driver 2100. The voltage-mode main driver 2100a may include a driver DV1 and a resistance component R1. The voltage-mode main driver 2100a may receive the signal IN1 and drive the signal IN1 through the resistance component R1 using the driver DV1. However, the present inventive concept is not limited thereto. For example, a configuration of the main driver 2100 may be varied or modified in various ways to a current-mode driver or any other application.

[0094] The multiplexer 2300a may correspond to the selection circuit 2300. The multiplexer 2300a may receive the signals IN1 and IN2 and may selectively output the signal IN1 or the signal IN2 in response to the control signal CTL. However, the present inventive concept is not limited thereto. For example, a configuration of the selection circuit 2300 may be variously modified or adapted to a switch circuit, a gate circuit, or any other application that can select one of the signals IN1 and IN2.

[0095] The differentiating circuit 2400a may correspond to the compensator circuit 2400. The differentiating circuit 2400a may process a signal selected by the selecting circuit 2300 to generate the compensation signal CSG. For example, with respect to the example of Fig. 6, in the case where the multiplexer 2300a outputs the signal IN2, the differentiating circuit 2400a may process the signal IN2 such that the compensation signal -FE(t) has a waveform obtained by differentiating a waveform of the signal IN2.

[0096] For example, regarding the example from Fig. 10, when the multiplexer 2300a outputs the signal IN1, the differentiating circuit 2400a may process the signal IN1 such that the compensation signal PM(t) has a waveform obtained by differentiating a waveform of the signal IN1. Accordingly, the differentiating circuit 2400a may be used jointly to process the signal IN1 and the signal IN2.

[0097] For example, the differentiating circuit 2400a may be a cap-peaking driver including an inverter INV1 and a capacitive element C1. For example, a capacitance of the capacitive element C1 may be fixed or variable.

[0098] If the capacitance of the capacitive element C1 is variable, a waveform of the compensation signal CSG generated by the differentiating circuit 2400a may be adjustable. In this case, the degree to which the differentiating circuit 2400a compensates for noise (e.g., crosstalk noise or intersymbol interference) may be variable. For example, if the influence of the noise on the signal IN1 changes (e.g., increases or decreases), a variable capacitance of the capacitive element C1 may be adjusted such that the degree to which the differentiating circuit 2400a compensates for the noise changes changes (e.g., increases or decreases).

[0099] However, the differentiating circuit 2400a is made of Fig. 13 is only one of various possible embodiments and is not intended to limit the present inventive concept. In exemplary embodiments of the present inventive concept, the differentiating circuit 2400a may comprise segmented circuits, which may be described with reference to Fig. 17 to 20. Alternatively, the differentiating circuit 2400a may be modified or altered in various ways to another implementation other than a cap-peaking driver. In exemplary embodiments of the present inventive concept, the compensator circuit 2400 may be modified or altered in various ways according to an implementation other than the differentiating circuit 2400a to generate a suitable compensation signal CSG.

[0100] Fig. 14 is a diagram for describing how compensation for far-end crosstalk noise or intersymbol interference is performed in the electronic circuit 2000 of Fig. 11 is carried out.

[0101] For example, in a CTN communications environment, signal distortion or signal loss due to intersymbol interference can become significant as the signal frequency decreases. Conversely, as the signal frequency increases, crosstalk noise can become significant.

[0102] In this communication environment CTN, when the signal frequency is lower than a frequency F0, the intersymbol interference (ISI in Fig. 14) may be more dominant than crosstalk noise. However, if the signal frequency is higher than the frequency F0, crosstalk noise may be more dominant than intersymbol interference.

[0103] For example, when a signal is transmitted through a communication channel at a frequency F1 lower than the frequency F0, the influence of intersymbol interference may be greater than the influence of crosstalk noise. In this case, it may be more advantageous to compensate for the intersymbol interference. When the control signal CTL is provided such that the selection circuit 2300 selects the signal IN1, the compensator circuit 2400 may receive the signal IN1. The compensator circuit 2400 may generate the compensation signal CSG for compensating the intersymbol interference based on the signal IN1.

[0104] On the other hand, when a signal is transmitted through a communication channel at a frequency F2 higher than the frequency F0, the influence of crosstalk noise may be greater than the influence of intersymbol interference. In this case, it may be more advantageous to compensate for the crosstalk noise. When the control signal CTL is provided such that the selection circuit 2300 selects the signal IN2, the compensator circuit 2400 may receive the signal IN2. The compensator circuit 2400 may generate the compensation signal CSG for compensating the crosstalk noise based on the signal IN2.

[0105] The control signal CTL can be provided based on the communication environment CTN, for example, the control signal CTL can be provided based on the influence of intersymbol interference and the influence of crosstalk noise. However, the communication environment CTN is Fig. 14 is only an example and therefore not limited to the present inventive concept. The influence of intersymbol interference and the influence of crosstalk noise can be changed in such a way that it differs from that in Fig. 14, depending on various factors such as circuit design and actual operating system environment.

[0106] Fig. 15 is a block diagram illustrating a configuration used with the electronic circuit 2000 of Fig. 11 is associated.

[0107] In exemplary embodiments of the present inventive concept, the electronic circuit 2000 may be made of Fig. 11 an electronic circuit 2000b from Fig. 15. The electronic circuit 2000b may include the main driver 2100, the selection circuit 2300, the compensator circuit 2400, and a register 2600.

[0108] For example, before the electronic system 1000 including the electronic circuit 2000b is shipped or delivered, the electronic system 1000 may be tested to determine whether it is operating normally. During the test, it may also be determined whether signals are transmitted normally through the communication channels CH11 to CH19 and CH21 to CH29. In the test, the influence of intersymbol interference and the influence of crosstalk noise may be measured for each communication channel.

[0109] A value corresponding to the control signal CTL may be stored in register 2600 based on a measurement result. The value corresponding to the control signal CTL may be determined based on whether intersymbol interference or crosstalk noise dominates. The selection circuit 2300 may select one of the signals IN1 and IN2 based on the control signal CTL having the value obtained from the test.

[0110] Fig. 16 is a block diagram illustrating a configuration associated with the electronic circuit 2000 of Fig. 11 is associated.

[0111] In exemplary embodiments of the present inventive concept, the electronic circuit 2000 may be made of Fig. 11 an electronic circuit 2000c from Fig. 16. The electronic circuit 2000c may include the main driver 2100, the selection circuit 2300, the compensator circuit 2400, a mode controller 2700, and a memory 2800.

[0112] For example, while the electronic system 1000 including the electronic circuit 2000c is operating, the mode controller 2700 may monitor signal streams to detect intersymbol interference and the influence of crosstalk noise. In some cases, a receiving-side device receiving signals may provide information associated with noise in the signals, and the mode controller 2700 may obtain the information provided by the receiving-side device.

[0113] The memory 2800 can store information about the communication environment CTN. For example, the information about the communication environment CTN can be collected during a test or an actual operation of the electronic system 1000.

[0114] The mode controller 2700 may provide the control signal CTL to the selection circuit 2300 based on the communication environment information CTN stored in the memory 2800, the monitored signal streams, and the information provided by the receiving-side device. The control signal CTL may be generated based on whether intersymbol interference dominates in a current communication environment or whether crosstalk noise dominates in the current communication environment. The selection circuit 2300 may select one of the signals IN1 and IN2 based on whether it is better to compensate for the intersymbol interference or to compensate for the crosstalk noise.

[0115] Fig. 17 is a block diagram illustrating a configuration used with the electronic circuit 2000 of Fig. 11 is associated. Fig. 18 is a block diagram for describing an operation of an electronic circuit 2000d of Fig. 17.

[0116] In exemplary embodiments of the present inventive concept, the electronic circuit 2000 may be made of Fig. 11 the electronic circuit 2000d from Fig. 17. In Fig. 17, the electronic circuit 2000d may include the main driver 2100, the selection circuit 2300, and compensator circuits 2400d. In Fig. 18, the compensator circuits 2400d “K” may comprise segmented compensator circuits 2401d to 2409d.

[0117] In the Fig. 17 and Fig. 18, the compensator circuits 2401d to 2409d may receive the signal IN1 or the signal IN2 according to a selection of the selection circuit 2300. A configuration and operation of each compensator circuit 2401d to 2409d may be substantially the same as the configuration and operation of the compensator circuit 2400.

[0118] For example, each compensator circuit 2401d to 2409d may generate a compensation signal for compensating intersymbol interference based on the signal IN1 or may generate a compensation signal for compensating crosstalk noise based on the signal IN2. The compensator circuits 2400d may output a final compensation signal CSG based on the compensation signals generated by the compensator circuits 2401d to 2409d.

[0119] Compensator circuits 2401d to 2409d may be controlled based on a control signal COEF[1:K]. For example, control signal COEF[1:K] may include "K" control values, and the control values ​​may respectively control operations of compensator circuits 2401d to 2409d.

[0120] The compensator circuits 2401d to 2409d can be controlled to operate or not operate based on the control signal COEF[1:K]. A compensator circuit (e.g., the compensator circuits 2401d and 2402d of Fig. 18) can output a compensation signal based on the IN1 signal or the IN2 signal. The final compensation signal CSG can be output from the compensator circuit that is operating.

[0121] In contrast, a compensator circuit (e.g. the compensator circuits 2403d and 2409d from Fig. 18) that is not operating will not output a compensation signal. For example, if elements (e.g., a switch or a transistor) included in a compensator circuit are turned off based on a control value, or if a signal output path from the compensator circuit is disconnected based on a control value, the compensator circuit can be considered non-operating.

[0122] Each of the compensator circuits 2401d to 2409d can be independently controlled to operate or not operate based on the control signal COEF[1:K], regardless of whether any other compensator circuit is operating. For example, the compensator circuit 2401d can be controlled to operate in response to a control value of "1" from the control signal COEF[1:K], regardless of the case where the compensator circuit 2403d is not operating. The compensator circuit 2403d can be controlled not to operate in response to a control value of "0" from the control signal COEF[1:K], regardless of the case where the compensator circuit 2401d is operating.

[0123] For example, the control signal COEF[1:K] can be provided to the compensator circuits based on whether an influence of noise (e.g., crosstalk noise or intersymbol interference) is large or small. As described with reference to Fig. 15 and Fig. 16, the control signal COEF[1:K] can be determined or changed based on a test result or a monitoring result.

[0124] As the noise influence changes, the number of compensator circuits operating to generate the compensation signal CSG may vary from compensator circuits 2401d to 2409d. For example, the number of compensator circuits operating may increase when the noise influence is large, and the number of compensator circuits operating may decrease when the noise influence is small.

[0125] As the number of compensating circuits operating changes, the waveform of the compensation signal CSG may change as the noise influence changes. For example, if the number of compensating circuits operating increases, the waveform of the compensation signal CSG may change such that the degree to which the signal IN1 is compensated based on the compensation signal CSG increases. Conversely, if the number of compensating circuits operating decreases, the waveform of the compensation signal CSG may change such that the degree to which the signal IN1 is compensated based on the compensation signal CSG decreases.

[0126] Accordingly, depending on the communication environment, the waveform of the compensation signal CSG can change based on the control signal COEF[1:K]. With the change in the waveform of the compensation signal CSG, the degree of noise compensation can change. Accordingly, the electronic circuit 2000d can actively cope with changes in the communication environment.

[0127] Fig. 19 is a block diagram illustrating a configuration used with the electronic circuit 2000 of Fig. 11 is associated. Fig. 20 is a block diagram for describing an operation of an electronic circuit 2000e of Fig. 19.

[0128] In exemplary embodiments of the present inventive concept, the electronic circuit 2000 may be made of Fig. 11 the electronic circuit 2000e from Fig. 19. In Fig. 19, the electronic circuit 2000e may include the main driver 2100, selection circuits 2300e, and compensator circuits 2400e. In Fig. 20, the selector circuits 2300e may include “K” selector circuits 2301e to 2309e, and the compensator circuits 2400e may include “K” compensator circuits 2401e to 2409e.

[0129] In Fig. 19 and Fig. 20, the selection circuits 2301e to 2309e may be controlled based on a control signal CTL[1:K]. For example, the control signal CTL[1:K] may include "K" control values, and the control values ​​may be provided to the selection circuits 2301e to 2309e, respectively.

[0130] Each of the selection circuits 2301e to 2309e may select the signal IN1 or the signal IN2 in response to a control value of the control signal CTL[1:K] and may provide the selected signal to the compensator circuits 2401e to 2409e. A configuration and operation of each selection circuit 2301e to 2309e may be substantially similar to the configuration and operation of the selection circuit 2300 of Fig. be 11.

[0131] Each of the selection circuits 2301e to 2309e can independently select the IN1 signal or the IN2 signal, regardless of whether any other selection circuit selects the IN1 signal or the IN2 signal. For example, the selection circuit 2301e can select the IN1 signal based on a control value of the CTL[1:K] control signal, regardless of the selection circuit 2304e selecting the IN2 signal. The selection circuit 2303e can select the IN2 signal based on a control value of the CTL[1:K] control signal, regardless of the selection circuit 2302e selecting the IN1 signal.

[0132] The compensator circuits 2401e to 2409e may be connected to the selector circuits 2301e to 2309e, respectively. Each of the compensator circuits 2401e to 2409e may generate a compensation signal based on the signal IN1 or the signal IN2, regardless of an operation of a selector circuit connected thereto.

[0133] The operations of the compensator circuits 2401e to 2409e can be similar to the operations of the compensator circuits 2401d to 2409d Fig. 18. Each of the compensator circuits 2401e through 2409e can be independently controlled to operate or not operate based on the control signal COEF[1:K], regardless of whether any other compensator circuit is operating. For example, it is possible for the compensator circuits 2406e through 2409e to not operate while the compensator circuits 2401e through 2405e are operating. For example, it is possible for the compensator circuits 2401e through 2405e to operate in response to the control signal COEF[1:K] corresponding to a value of "1," and for the compensator circuits 2406e through 2409e to not operate in response to the control signal COEF[1:K] corresponding to a value of "2."

[0134] In addition, an operating compensator circuit may generate a compensation signal, and the final compensation signal CSG may be output from the operating compensator circuit. The control signal COEF[1:K] and the final compensation signal CSG may vary due to the influence of noise.

[0135] Because the individual selection circuits 2301e to 2309e are connected, the compensator circuits 2401e to 2409e can receive different signals. In this case, the compensator circuits 2401e to 2409e can independently generate compensation signals, regardless of whether another compensator circuit generates a compensation signal for compensating intersymbol interference or a compensation signal for compensating crosstalk noise.

[0136] For example, when the selection circuit 2301e connected to the compensator circuit 2401e selects the signal IN1, the compensator circuit 2401e may generate a compensation signal to compensate for intersymbol interference based on the signal IN1. Conversely, when the selection circuit 2305e connected to the compensator circuit 2405e selects the signal IN2, the compensator circuit 2405e may generate a compensation signal to compensate for crosstalk noise based on the signal IN2.

[0137] Accordingly, for example, each of the compensator circuits 2401e to 2402e can generate a compensation signal for compensating intersymbol interference based on the signal IN1, and each of the compensator circuits 2403e to 2405e can simultaneously generate a compensation signal for compensating crosstalk noise based on the signal IN2. In this case, it is possible to compensate for the intersymbol interference and the crosstalk noise simultaneously.

[0138] The degree of intersymbol interference compensation based on the compensation signal CSG may vary with the number of compensation circuits receiving the signal IN1. The degree of crosstalk noise compensation based on the compensation signal CSG may vary with the number of compensation circuits receiving the signal IN2. Depending on the signals selected by the selection circuits 2301e to 2309e, the degree of intersymbol interference compensation may be the same as or different from the degree of crosstalk noise compensation.

[0139] Signals selected by the selection circuits 2301e to 2309e may be determined based on the control signal CTL[1:K]. Accordingly, the degree of intersymbol interference compensation and the degree of crosstalk noise compensation may change based on the control signal CTL[1:K]. As described with reference to Fig. 15 and Fig. 16, the control signal CTL[1:K] can be determined or changed based on a test result or a monitoring result.

[0140] In some cases, the compensator circuits 2401e to 2409e may receive the same signal and output compensation signals to compensate for the same noise. In this case, the operations of the compensator circuits 2401e to 2409e may be similar to the operations of the compensator circuits 2401d to 2409d. Fig. 17 and Fig. 18 be similar.

[0141] Fig. 21 is a block diagram illustrating a configuration used with the electronic circuit 2000 of Fig. 11 is associated.

[0142] In exemplary embodiments of the present inventive concept, the electronic circuit 2000 may be made of Fig. 11 an electronic circuit 2000f from Fig. 21. The electronic circuit 2000f may include main drivers 2100 and 2100f, selector circuits 2300 and 2300f, and compensator circuits 2400 and 2400f.

[0143] The embodiments from Fig. 3 to 20 describe that the signal IN1 has an influence of crosstalk noise caused by the signal IN2. The signal IN2 may be affected by the crosstalk noise caused by the signal IN1. The electronic circuit 2000f can compensate for mutual crosstalk noise between the signal IN1 and the signal IN2.

[0144] The selection circuit 2300 may select the IN1 signal or the IN2 signal in response to a control signal CTL11, and the compensator circuit 2400 may generate a compensation signal CSG11 based on a signal selected by the selection circuit 2300. An output signal OUT1 may be generated by applying the compensation signal CSG11 to the IN1 signal driven by the main driver 2100. The output signal OUT1 may correspond to data to be transmitted by the IN1 signal.

[0145] Main driver 2100f may drive signal IN2 to output the driven signal IN2. Selector circuit 2300f may select signal IN1 or signal IN2 in response to a control signal CTL12. Selector circuit 2300f may select signal IN1 or signal IN2 independently of selector circuit 2300, regardless of whether selector circuit 2300 selects signal IN1 or signal IN2. Control signal CTL12 and the selection of selector circuit 2300f may be based on a type and influence of noise associated with signal IN2.

[0146] Compensator circuit 2400f may generate a compensation signal CSG12 to compensate for driven signal IN2 based on a signal selected by selection circuit 2300f. When selection circuit 2300f selects signal IN1, compensator circuit 2400f may generate compensation signal CSG12 to compensate for crosstalk noise of driven signal IN2 caused by driven signal IN1 based on signal IN1.

[0147] In the case where the selection circuit 2300f selects the signal IN2, the compensator circuit 2400f may generate the compensation signal CSG12 to compensate for intersymbol interference of the driven signal IN2 based on the signal IN2. An output signal OUT2 may be generated by applying the compensation signal CSG12 to the driven signal IN2. The output signal OUT2 may correspond to data to be transmitted by the signal IN2.

[0148] Fig. 22 is a block diagram illustrating a configuration used with the electronic circuit 2000 of Fig. 11 is associated.

[0149] In exemplary embodiments of the present inventive concept, the electronic circuit 2000 may be made of Fig. 11 an electronic circuit 2000g from Fig. 22. The electronic circuit 2000g may include the main driver 2100, the selection circuits 2300, 2302g and 2303g and compensator circuits 2400, 2402g and 2403g.

[0150] The embodiments from Fig. 3 to 21 describe that the signal IN1 has an influence of only crosstalk noise caused by the signal IN2. In an actual operation, crosstalk noise of the signal IN1 may be caused by a plurality of signals (e.g., signals IN2, IN3, and IN4).

[0151] The IN2, IN3, and IN4 signals can be received in parallel by a SER / DES. For example, the IN1, IN2, IN3, and IN4 signals can correspond to signals to be transmitted over communication channels that are spatially adjacent or close to each other in distance. The 2000g electronic circuit can compensate for crosstalk noise of the IN1 signal caused by the IN2, IN3, and IN4 signals. In this regard, the IN1 signal can be a victim signal, and the IN2, IN3, and IN4 signals can be an aggressor signal.

[0152] The selection circuit 2300 may select the signal IN1 or the signal IN2 in response to a control signal CTL21. The compensator circuit 2400 may generate a compensation signal CSG21 based on a signal selected by the selection circuit 2300.

[0153] The selection circuit 2302g may select the signal IN1 or the signal IN3 in response to a control signal CTL22. The compensator circuit 2402g may generate a compensation signal CSG22 to compensate the driven signal IN1 based on a signal selected by the selection circuit 2302g.

[0154] When the selection circuit 2302g selects the signal IN1, the compensator circuit 2402g may generate the compensation signal CSG22 to compensate for intersymbol interference of the driven signal IN1 based on the signal IN1. When the selection circuit 2302g selects the signal IN3, the compensator circuit 2402g may generate the compensation signal CSG22 to compensate for crosstalk noise of the driven signal IN1 caused by a signal driven from the signal IN3 based on the signal IN3.

[0155] The selection circuit 2303g may select the signal IN1 or the signal IN4 in response to a control signal CTL23. The compensator circuit 2403g may generate a compensation signal CSG23 to compensate for intersymbol interference of the driven signal IN1 or crosstalk noise of the signal IN4 based on a signal selected by the selection circuit 2303g.

[0156] The selection circuit 2302g can select the signal IN1 or the signal IN3 independently of the selection circuit 2300, regardless of whether the selection circuit 2300 selects the signal IN1 or the signal IN2. The selection circuit 2303g can select the signal IN1 or the signal IN4 independently of the selection circuits 2300 and 2302g, regardless of whether the selection circuits 2300 and 2302g select the signal IN1 or the signal IN2 or IN3.

[0157] As from Fig. 21 and Fig. 22, the electronic circuit 2000 may be provided for selectively compensating noise between the communication channels CH11 to CH19 and CH21 to CH29. In addition, the Fig. 11 to 22 are described independently of each other, but it should be understood that two or more of the embodiments may be combined.

[0158] Fig. 23 is a block diagram illustrating a configuration of a memory system 3000 including the electronic circuit 2000 of Fig. 11 includes.

[0159] The memory system 3000 may include a memory device (e.g., a dynamic random access memory (DRAM) device 3100) and a memory controller (e.g., a controller 3300). The DRAM device 3100 may store data or output the stored data. The controller 3300 may control the DRAM device 3100 such that the DRAM device 3100 stores or outputs data.

[0160] The memory system 3000 may include a physical layer (PHY) 3500. The PHY 3500 may include physical circuitry to transmit a data signal between the DRAM device 3100 and the controller 3300. The physical circuitry may include digital circuitry 3510 and analog circuitry 3530.

[0161] Data processed by the digital circuits 3510 may be provided to an SER of each of the digital circuits 3530. Data processed by a DES of each of the analog circuits 3530 may be provided to the digital circuits 3510.

[0162] In each of the analog circuits 3530, the SER may serialize data and may provide the serialized data to a transmitter Tx, and the transmitter Tx may transmit a signal corresponding to the serialized data to the DRAM device 3100. A receiver Rx may provide a signal received from the DRAM device 3100 to the DES, and the DES may deserialize data from the received signal.

[0163] DQ signals DQ[1] through DQ[N] may be transmitted between the analog circuits 3530 and the DRAM device 3100. Regarding the transmission of the DQ signals DQ[1] through DQ[N] to the DRAM device 3100, each of the analog circuits 3530 may utilize the electronic circuit 2000 to selectively compensate for different types of noise (e.g., crosstalk noise and intersymbol interference).

[0164] For example, if the memory system 3000 is included in a processor device that includes a graphics processing unit (GPU), the DQ signals DQ[1] through DQ[N] may be transmitted in parallel using Graphics Double Data Rate (GDDR) technology. However, the present inventive concept is not limited thereto. It should be understood, however, that the electronic circuit 2000 may be varied or modified in various ways to apply the electronic circuit 2000 to a different communication technology and a different type of electronic system.

[0165] According to exemplary embodiments of the present inventive concept, signal distortion due to crosstalk noise or intersymbol interference may be reduced. For example, exemplary embodiments of the present inventive concept may provide an electronic circuit for compensating noise occurring in a communication channel during data transmission. In the exemplary embodiments of the present inventive concept, the electronic circuit may selectively compensate for crosstalk noise and intersymbol interference. In the exemplary embodiments of the present inventive concept, circuit area may be reduced because a compensator circuit for compensating for crosstalk noise and compensating for intersymbol interference is shared.

[0166] While the present inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present inventive concept as set forth in the following claims.

Claims

[1] Electronic circuit comprising: a first driver for outputting a driven first signal by driving a first signal from signals received in parallel; a first selection circuit for selecting one signal from the first signal and a second signal from the signals; and a first compensator circuit for generating a first compensation signal for compensating the driven first signal in response to the one signal selected by the first selection circuit, wherein, when the first selection circuit selects the first signal, the first compensator circuit generates the first compensation signal to compensate for intersymbol interference of the selected first signal, and wherein, when the first selection circuit selects the second signal, the first compensator circuit generates the first compensation signal to compensate for crosstalk noise of the driven first signal caused by a driven second signal driven from the second signal. [2] The electronic circuit of claim 1, wherein the driven first signal and the driven second signal are transmitted to adjacent parallel channels. [3] The electronic circuit of claim 1, further comprising: a second driver for outputting the driven second signal by driving the second signal; a second selection circuit for selecting the first signal or the second signal; and a second compensator circuit for generating a second compensation signal for compensating the driven second signal based on the first signal or the second signal selected from the second selection circuit. [4] The electronic circuit according to claim 3, wherein, when the second selection circuit selects the second signal, the second compensator circuit generates the second compensation signal to compensate for intersymbol interference of the driven second signal, and when the second selection circuit selects the first signal, the second compensator circuit generates the second compensation signal to compensate for crosstalk noise of the driven first signal caused by the driven first signal. [5] The electronic circuit according to claim 3, wherein the second selection circuit selects the first signal or the second signal independently of the first selection circuit, regardless of whether the first selection circuit selects the first signal or the second signal. [6] Electronic circuit according to claim 1, further comprising: a third selection circuit for selecting one signal from the first signal and a third signal from the signals; and a third compensator circuit for generating a third compensation signal for compensating the driven first signal based on the one signal selected by the third selection circuit. [7] The electronic circuit according to claim 6, wherein, when the third selection circuit selects the first signal, the third compensator circuit generates the third compensation signal to compensate for intersymbol interference of the driven first signal, and wherein, when the third selection circuit selects the third signal, the third compensator circuit generates the third compensation signal to compensate for crosstalk noise of the driven first signal caused by a driven third signal driven from the third signal. [8] The electronic circuit according to claim 6, wherein the third selection circuit selects the first signal or the third signal independently of the first selection circuit, regardless of whether the first selection circuit selects the first signal or the second signal. [9] The electronic circuit of claim 1, wherein the first selection circuit selects the first signal and the second signal in response to a control signal, and wherein the control signal is based on influencing the intersymbol interference of the driven first signal or influencing the crosstalk noise of the driven first signal. [10] Electronic circuit for transmitting an output signal, comprising: a driver for receiving a first signal and outputting a controlled first signal; and a compensator circuit for receiving a selected first or second signal received in parallel with the first signal, and for outputting a first compensation signal to compensate for intersymbol interference of the driven first signal in response to the first signal, or for outputting a second compensation signal to compensate for crosstalk noise of the driven first signal in response to the second signal. [11] The electronic circuit of claim 10, wherein the crosstalk noise is caused by a driven second signal driven from the second signal, wherein the first compensation signal has a waveform to compensate for distortion of a waveform of the first driven signal due to the intersymbol interference, and wherein the second compensation signal has a waveform to compensate for the distortion of the waveform of the driven first signal due to the crosstalk noise. [12] Electronic circuit according to claim 10, wherein the compensator circuit comprises: a differentiating circuit for processing the first signal or the second signal so that the first compensation signal or the second compensation signal has a waveform obtained by differentiating a waveform of the first signal or the second signal, and wherein the differentiating circuit is arranged to process the first signal and the second signal. [13] The electronic circuit according to claim 10, wherein the first compensation signal comprises a first pulse corresponding to a waveform obtained by differentiating a waveform of the first signal, and wherein a direction in which the first pulse compensates a waveform of the driven first signal is opposite to a direction in which the waveform of the driven first signal is distorted by the intersymbol interference. [14] The electronic circuit according to claim 10, wherein the second compensation signal comprises a second pulse corresponding to a waveform obtained by differentiating a waveform of the second signal, and wherein a direction in which the second pulse compensates for a waveform of the driven first signal is opposite to a direction in which the waveform of the driven first signal is distorted by the crosstalk noise. [15] The electronic circuit according to claim 10, wherein the first compensation signal comprises a first pulse corresponding to a waveform obtained by differentiating a waveform of the first signal, the second compensation signal comprises a second pulse corresponding to a waveform obtained by differentiating a waveform of the second signal, and wherein a direction in which the first pulse compensates a waveform of the driven first signal is the same as a direction in which the second pulse compensates the waveform of the driven first signal. [16] The electronic circuit of claim 10, wherein the compensator circuit receives the first signal when an influence of the intersymbol interference is greater than an influence of the crosstalk noise, and receives the second signal when the influence of the crosstalk noise of the driven first signal is greater than the influence of the intersymbol interference. [17] The electronic circuit according to claim 10, wherein the electronic circuit outputs the output signal with respect to the driven first signal compensated based on the first compensation signal or the second compensation signal, and wherein the driver and the compensator circuit are connected in parallel between a terminal for receiving the first signal and a terminal for outputting the output signal. [18] Electronic circuit comprising: a driver for driving a first signal from signals received in parallel; a selection circuit for selecting one signal from the first signal and a second signal from the signals; and a compensator circuit for compensating for a first noise occurring in the driven first signal in response to the first signal selected by the selection circuit, or for compensating for a second noise of the driven first signal caused with respect to the second signal in response to the second signal selected by the selection circuit. [19] The electronic circuit of claim 18, wherein when an influence of the first noise or the second noise of the driven first signal changes, a degree to which the compensator circuit compensates for the first noise or the second noise changes. [20] The electronic circuit of claim 18, wherein the first signal and the second signal are associated with DQ signals to be transmitted to a memory device having a Graphics Double Data Rate (GDDR) technology.

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