Circuit and method for generating a linear delay

Abstract

Circuit for delaying a digital input signal (421), the circuit comprising: a delay cell circuit (200, 420); and a reciprocal current digital-to-analog converter (DAC) (410) coupled to the delay cell circuit (200, 420), the reciprocal current DAC (410) being configured to output a charging current (412) to the delay cell circuit (200, 420) according to a value of a control input (207, 411); the charging current being inversely proportional to the value of the control input (207, 411); the delay cell circuit (200, 420) being configured to generate a delayed digital output signal (422) of the digital input signal (421); and wherein the delay depends on the charging current; wherein the circuit further comprises: a bias circuit (430) coupled to the "reciprocal current" DAC (410) to generate a bias current for the "reciprocal current" DAC (410);and a feedback circuit (440) coupled to the bias circuit (430) for generating an operating voltage (442) based on the bias current, wherein the operating voltage (442) is used to control the "reciprocal current" DAC (200, 410).

Description

Technical field

[0001] This document concerns the generation of a linear delay. In particular, this document concerns the generation of a digital signal delay that is linearly dependent on an input control vector. background

[0002] In general, a circuit that can generate a delayed version of an input signal (e.g., a digital input signal) can find wide use in generating a PWM signal in control loops in various applications.

[0003] Conventional circuits for generating a delay for a digital input signal typically involve changing various circuit parameters to adjust the delay to the required value. However, these conventional methods typically exhibit corresponding shortcomings and / or disadvantages.

[0004] For example, one method might involve modifying the circuit's capacitance, such as by inserting a shunt capacitor in the digital signal path. However, such a method would require a large number of capacitors to support a large number of different delay settings, and these capacitors would need to be matched to the respective delay settings. This large number of capacitors would then occupy a large area. For example, an 8-bit delay control might then require a total of 255 Unit capacitors are required.

[0005] An alternative method might involve modifying the switching threshold (e.g., a reference voltage used in a comparator). However, generating a linear delay with such a method would require the reference voltage to also change linearly. For fast control loops, a rapidly changing reference voltage can be excessively power-hungry and have a large surface area.

[0006] Another alternative could involve modifying the current, for example by using low-current, inverter-based delay elements. However, in such a method, either a linear relationship between a control vector and a delay may not be easily achieved in practice, or the performance may be unacceptable.

[0007] These conventional methods can also suffer from high power consumption and a dependence on process, voltage and temperature (PVT - process, voltage, temperature). Summary

[0008] In consideration of some or all of the above problems, the present disclosure proposes circuits and methods for delaying a digital input signal with the features of the respective independent claims. In general, the term "delay" means that the output signal has a value / amplitude proportional to that of the input signal (e.g., the same value / amplitude as the input signal), but at later (delayed) times.

[0009] One aspect of the disclosure concerns a circuit for delaying a digital input signal. Specifically, the circuit may include a delay cell circuit and a reciprocal current digital-to-analog converter (DAC). The term "reciprocal" generally means that the output current of the DAC is inversely proportional to the input of the DAC. The delay cell circuit, or simply the delay cell, may be coupled to the reciprocal current DAC. In particular, the reciprocal current DAC may be configured to output a charging current to the delay cell circuit according to a value of a control input provided to the reciprocal current DAC. The control input may, in some cases, be referred to as a (digital) control vector, which, for example, has N (input) bits, where N is an integer greater than or equal to 1.As is obvious and recognizable to experts, the number N can be chosen (determined) depending on various circumstances and / or requirements, such as the maximum required delay, etc. For example, if N is equal to 8 (i.e., an 8-bit control vector), this means that the input value provided to the "reciprocal current" DAC can be any value from 0 (i.e., all 8 bits set to 0) up to 0. 255(i.e., all 8 bits set to 1). The charging current output by the reciprocal current DAC can be inversely proportional to the value of the control input. That is, as the value of the control input increases, the charging current output by the reciprocal current DAC also decreases, specifically in an inversely proportional (reciprocal) manner. The delay cell can be configured to generate a delayed digital output signal of the digital input signal. In particular, the delay, or in other words, the length of time by which the digital output signal is delayed relative to the digital input signal, can depend on the charging current.

[0010] In the proposed configuration, a delay of the digital input signal can be generated (achieved) that is linearly proportional to the value of the control input (control vector). That is, by increasing (or decreasing) the value (magnitude) of the control vector, the delay between the digital input signal and the digital output signal also increases (or decreases) in a linearly proportional manner.

[0011] In some embodiments, the circuit may further include a bias circuit. The bias circuit may be coupled to the reciprocal current DAC. In particular, the bias circuit may be used (configured) to generate a bias current for the reciprocal current DAC. As is obvious to those skilled in the art, in some cases the generated bias current can be understood as a current that the bias circuit wants to draw (pull from) the reciprocal current DAC to the bias circuit. The circuit may further include a feedback circuit coupled to the bias circuit. The feedback circuit may be used to generate an operating voltage based on the bias current. In particular, the operating voltage may be used to control (operate) the reciprocal current DAC.As is obvious to experts, the feedback circuit can be implemented as a feedback loop coupled between an output of the "reciprocal current" DAC and an input of the "reciprocal current" DAC.

[0012] In some embodiments, the feedback circuit may include a gain circuit. The gain circuit can be used to generate the operating voltage used to control (drive) the reciprocal current DAC. In some cases, the gain circuit may be implemented as simply as an amplifier. However, other suitable implementations of the gain circuit can also be used, as is obvious to those skilled in the art.

[0013] In some embodiments, generating the operating voltage may involve comparing the bias current with a current that depends on the charging current. Accordingly, the operating voltage can be generated based on the result of this comparison. As is obvious and recognizable to those skilled in the art, the actual current drawn from the reciprocal current DAC can vary (increase or decrease) depending on circumstances (e.g., a change in the value of the control input, a change in the configuration of the reciprocal current DAC, etc.) and may therefore be greater or less than the desired bias current. Consequently, this difference would lead to a change (increase or decrease) in the operating voltage of the reciprocal current DAC due to the presence of the feedback circuit, in order to regulate the current back to the desired value.

[0014] In some embodiments, the "reciprocal current" DAC can have a plurality of first transistor devices and a second transistor device.

[0015] In particular, the second transistor device can be coupled between a supply voltage (e.g., VDD) and the delay cell circuit. Alternatively, each of the plurality of first transistor devices can be selectively switched to be coupled between the supply voltage and the bias circuit and to share a common gate with the second transistor device. The term "common gate" generally means that the respective gates of the selected number of first transistor devices and the gate of the second transistor device are (directly) connected. Thus, a configurable number of first transistor devices can be selected to be coupled between the supply voltage and the bias circuit. In some cases, the plurality of first transistor devices can be coupled in parallel.However, other suitable connections can be applied (used) between the plurality of first transistor devices, as is obvious to those skilled in the art, as long as each of the plurality of first transistor devices is selectively switchable to be coupled between the supply voltage and the bias circuit and to have a common gate with the second transistor device.

[0016] In some embodiments, the configurable number of first transistor devices is determined based on the value of the control input. In other words, depending on a specific value of the control input (to generate a corresponding specific delay), a corresponding specific configurable number of first transistor devices can be selected (activated) to be coupled between the supply voltage and the bias circuit.

[0017] In some embodiments, the operating voltage generated by the feedback circuit can be supplied to the common gate of the selected (configurable) number of first transistor devices and the second transistor device.

[0018] In some embodiments, the reciprocal current DAC can further include a third transistor device coupled in parallel to the plurality of first transistor devices between the supply voltage and the bias circuit. In particular, the third transistor device can also share a common gate with the configurable number of first transistor devices and the second transistor device. That is, the gate of the third transistor device can be connected to the common gate of the configurable number of first transistor devices and the second transistor device.

[0019] In some embodiments, the delay cell circuit may include a capacitive element. This capacitive element may be implemented as simply as a capacitor or any other suitable element, as is obvious to those skilled in the art. The capacitive element may be coupled between the reciprocal current DAC and a predetermined voltage level. The predetermined voltage level may be, for example, VSS, ground (GND), or any other suitable reference voltage level. Configured in this way, the capacitive element can be charged by the charging current to generate a charging voltage at an intermediate node based on the charge of the capacitive element. The delay cell circuit may further include a comparator coupled to the intermediate node. The comparator can be used to generate the delayed digital output signal based on a comparison between the charging voltage and a reference voltage.

[0020] In some embodiments, the delay cell circuit may further include a switching arrangement (with one or more switching devices). The switching arrangement can be configured to couple the capacitive element with the charging current on a rising edge or a falling edge of the digital input signal. That is, depending on the configuration of the switching arrangement, the rising edge or the falling edge (or in some cases even both edges) can be delayed as desired.

[0021] In some embodiments, the switching arrangement can include a first switching device and a second switching device. In particular, the first switching device can be coupled between the reciprocal current DAC and the intermediate node. The first switching device can be used to couple the capacitive element to the charging current during an ON state (conducting state) of the first switching device. In this case, the capacitive element can be charged by the charging current and accordingly generate the charging voltage at the intermediate node. As is obvious to those skilled in the art, the value of the charging voltage can vary (increase) and depends on the charging process of the capacitive element. On the other hand, the second switching device can be coupled in parallel to the capacitive element between the intermediate node and the predetermined voltage level.The second switching device can be used to decouple the capacitive element from the charging current during an ON state of the second switching device. In this case, the capacitive element can be (gradually) discharged to zero. To properly charge and discharge the capacitive element to generate the delayed digital output signal, the first and second switching devices are switched to their respective ON states in a mutually exclusive (complementary) manner based on the digital input signal. That is, depending on the value (amplitude) of the digital input signal, only one of the first and second switching devices is in the ON state, while the other is in an OFF state (non-conducting state).

[0022] In some embodiments, the switching arrangement may further include a third switching device coupled between the reciprocal current DAC and the specified voltage level. In particular, the third switching device can be switched to its ON state in conjunction with the second switching device. In other words, the third switching device can be switched to the ON state simultaneously with the second switching device, complementary to that of the first switching device.

[0023] In some embodiments, the bias current can be generated based on the same reference voltage used by the delay cell circuit. That is, the same reference voltage used in the delay cell circuit (e.g., in the delay cell comparator) can also be used for the bias circuit. Configured in this way, the delay can be generated in a manner independent of variations in the reference voltage. In particular, the feedback circuit (or the gain circuit of the feedback circuit) can sense the output of the bias circuit and adjust (control) the reciprocal current DAC according to variations in the reference voltage.

[0024] In some embodiments, the bias circuit may include a fourth transistor device. This fourth transistor device may be controlled by a reference voltage. In particular, the same reference voltage used in the delay cell circuit may be used to operate (control) the fourth switching device of the bias circuit. Configured in this way, the delay can be generated in a manner independent of variations in the reference voltage. It should be noted that the first through fourth switching devices may be implemented, for example, using a MOSFET or in some other suitable manner, as is obvious to those skilled in the art.

[0025] In some embodiments, all of the transistor devices listed above (i.e., the first through fourth transistor devices) can be of the same transistor type. That is, the transistor devices can be implemented using the same transistor type (e.g., NPN or PNP transistors). Configured in this way, the delay can be generated in a manner independent of variations in the process (during the implementation of the transistors).

[0026] Similarly, the charging current can be chosen to have a temperature coefficient of zero in order to create a delay in a way that is independent of the variation in temperature.

[0027] Configured in this way, the circuit for generating delay can be implemented to be independent of process, voltage and temperature (PVT - process, voltage and temperature).

[0028] Another aspect of the disclosure relates to a method for delaying a digital input signal to a circuit. The circuit can be implemented according to the above description. In particular, the circuit can include a delay cell circuit and a reciprocal current digital-to-analog converter (DAC). The term "reciprocal" generally means that the output current of the DAC is inversely proportional to the input of the DAC. The delay cell circuit, or simply called a delay cell, can be coupled to the reciprocal current DAC. Accordingly, the method can include a step to output, through the reciprocal current DAC, a charging current to the delay cell circuit according to a value of a control input. The control input can, in some cases, be called a (digital) control vector, which, for example, has N (input) bits, where N is an integer greater than or equal to 1.As is obvious and recognizable to experts, the number N can be chosen (determined) depending on various circumstances and / or requirements, such as the maximum required delay, etc. For example, if N is equal to 8 (i.e., an 8-bit control vector), this means that the input value provided to the "reciprocal stream" can be any value from 0 (i.e., all 8 bits set to 0) up to 0. 255(i.e., all 8 bits are set to 1). In particular, the charging current can be inversely proportional to the value of the control input. That is, as the value of the control input increases, the charging current output by the "reciprocal current" DAC decreases, specifically in an inversely proportional (reciprocal) manner. The method can further include a step of generating, by means of the delay cell circuit, a delayed digital output signal of the digital input signal. In particular, the generated delay, or in other words, the duration by which the digital output signal is delayed relative to the digital input signal, can depend on the charging current.

[0029] In some embodiments, the circuit may further include a bias circuit coupled to the reciprocal current DAC and a feedback circuit coupled to the bias circuit. Accordingly, the method may further include generating a bias current for the reciprocal current DAC via the bias circuit. As is obvious to those skilled in the art, in some cases the generated bias current can be understood as a current that the bias circuit wishes to draw (deliver) from the reciprocal current DAC to the bias circuit. The method may further include generating an operating voltage based on the bias current and controlling (operating) the reciprocal current DAC using this operating voltage.As is obvious to experts, the feedback circuit can be implemented as a feedback loop coupled between an output of the "reciprocal current" DAC and an input of the "reciprocal current" DAC.

[0030] In some embodiments, the feedback circuit may include a gain circuit. The gain circuit can be used to generate the operating voltage used to control (operate) the reciprocal current DAC. In some cases, the gain circuit may be implemented as simply as an amplifier. However, other suitable implementations of the gain circuit can also be used, as is obvious to those skilled in the art.

[0031] In some embodiments, the generation of the operating voltage may include a step of comparing the bias current with a current that depends on the charging current, and the operating voltage can be generated based on the result of this comparison. As is obvious and recognizable to those skilled in the art, the (actual) current drawn from the reciprocal current DAC can vary (increase or decrease) depending on circumstances (e.g., a change in the value of the control input, a change in the configuration of the reciprocal current DAC, etc.) and can therefore be greater or less than the (desired) bias current. Consequently, this difference would lead to a change (increase or decrease) in the operating voltage of the reciprocal current DAC due to the presence of the feedback circuit to regulate the current back to the desired value.

[0032] In some embodiments, the "reciprocal current" DAC can have a plurality of first transistor devices and a second transistor device.

[0033] In particular, the second transistor device can be coupled between a supply voltage (e.g., VDD) and the delay cell circuit. Alternatively, each of the plurality of first transistor devices can be selectively switched to be coupled between the supply voltage and the bias circuit and to share a common gate with the second transistor device. The term "common gate" generally means that the respective gates of the selected number of first transistor devices and the gate of the second transistor device are (directly) connected. Thus, a configurable number of first transistor devices can be selected to be coupled between the supply voltage and the bias circuit. In some cases, the plurality of first transistor devices can be coupled in parallel.However, other suitable connections can be applied (used) between the plurality of first transistor devices, as is obvious to those skilled in the art, as long as each of the plurality of first transistor devices is selectively switchable to be coupled between the supply voltage and the bias circuit and to have a common gate with the second transistor device.

[0034] In some embodiments, the method may further include a step to determine the configurable number of first transistor devices based on the value of the control input. In other words, depending on a specific value of the control input (to generate a corresponding specific delay), the method may determine a corresponding specific configurable number of first transistor devices that can be selected (activated) to be coupled between the supply voltage and the bias circuit.

[0035] In some embodiments, the method may further include a step to supply the operating voltage generated by the feedback circuit to the common gate of the selected (configurable) number of first transistor devices and the second transistor device.

[0036] In some embodiments, the reciprocal current DAC can further include a third transistor device coupled in parallel to the plurality of first transistor devices between the supply voltage and the bias circuit. In particular, the third transistor device can also share a common gate with the configurable number of first transistor devices and the second transistor device. That is, the gate of the third transistor device can be connected to the common gate of the configurable number of first transistor devices and the second transistor device.

[0037] In some embodiments, the delay cell circuit may include a capacitive element. This capacitive element may be implemented as simply as a capacitor or any other suitable element, as is obvious to those skilled in the art. The capacitive element may be coupled between the reciprocal current DAC and a predetermined voltage level. The predetermined voltage level may be, for example, VSS, ground (GND), or any other suitable reference voltage level. Configured in this way, the capacitive element can be charged by the charging current to generate a charging voltage at an intermediate node based on the charge of the capacitive element. The delay cell circuit may further include a comparator coupled to the intermediate node. The comparator can be used to generate the delayed digital output signal based on a comparison between the charging voltage and a reference voltage.

[0038] In some embodiments, the delay cell circuit may further include a switching arrangement (with one or more switching devices). The switching arrangement can be configured to couple the capacitive element with the charging current on a rising edge or a falling edge of the digital input signal. That is, depending on the configuration of the switching arrangement, the rising edge or the falling edge (or in some cases even both edges) can be delayed as desired.

[0039] In some embodiments, the switching arrangement can include a first switching device and a second switching device. In particular, the first switching device can be coupled between the reciprocal current DAC and the intermediate node. The first switching device can be used to couple the capacitive element to the charging current during an ON state (conducting state) of the first switching device. In this case, the capacitive element can be charged by the charging current and accordingly generate the charging voltage at the intermediate node. As is obvious to those skilled in the art, the value of the charging voltage can vary (increase) and depends on the charging process of the capacitive element. On the other hand, the second switching device can be coupled in parallel to the capacitive element between the intermediate node and the predetermined voltage level.The second switching device can be used to decouple the capacitive element from the charging current during an ON state of the second switching device. In this case, the capacitive element can be (gradually) discharged to zero. To properly charge and discharge the capacitive element to generate the delayed digital output signal, the method can further include a step of switching the first and second switching devices into their respective ON states in a mutually exclusive (complementary) manner based on the digital input signal. That is, depending on the value (amplitude) of the digital input signal, only one of the first and second switching devices is in the ON state, and the other is in an OFF state (non-conducting state).

[0040] In some embodiments, the switching arrangement may further include a third switching device coupled between the reciprocal current DAC and the specified voltage level. In particular, the third switching device can be switched to its ON state in conjunction with the second switching device. In other words, the third switching device can be switched to the ON state simultaneously with the second switching device, complementary to that of the first switching device.

[0041] In some embodiments, the method may include a further step to generate the bias current based on the same reference voltage used by the delay cell circuit. That is, the same reference voltage used in the delay cell circuit (e.g., in the delay cell comparator) can also be used to generate the bias circuit. Configured in this way, the delay can be generated in a manner independent of variations in the reference voltage. In particular, the feedback circuit (or the feedback gain circuit) can sense the output of the bias circuit and adjust (control) the reciprocal current DAC according to variations in the reference voltage.

[0042] In some embodiments, the bias circuit may include a fourth transistor device. This fourth transistor device may be controlled by a reference voltage. In particular, the same reference voltage used in the delay cell circuit may be used to operate (control) the fourth switching device of the bias circuit. Configured in this way, the delay can be generated in a manner independent of variations in the reference voltage.

[0043] In some embodiments, all of the transistor devices listed above (i.e., the first through fourth transistor devices) can be of the same transistor type. That is, the transistor devices can be implemented using the same transistor type (e.g., NPN or PNP transistors). Configured in this way, the delay can be generated in a manner independent of variations in the process (during the implementation of the transistors).

[0044] Similarly, the charging current can be chosen to have a temperature coefficient of zero in order to create a delay in a way that is independent of the variation in temperature.

[0045] Configured in this way, the delay generation method can be implemented to be independent of process, voltage and temperature (PVT).

[0046] The details of the disclosed method can be implemented as a device configured to perform some or all of the steps of the method, and vice versa, as is obvious to those skilled in the art. In particular, it is obvious that methods according to the disclosure relate to methods for operating the circuits according to the above embodiments and their variations, and that corresponding statements relating to the circuits also apply to the corresponding methods.

[0047] It is also evident that in this document the term "couple" or "coupled" refers to elements that are in electrical communication with each other, either directly connected, for example via wires, or in some other way (for example indirectly). An example of coupling is connecting.

[0048] Other and further embodiments of the present disclosure will become apparent during the course of the following discussion and with reference to the accompanying drawings. List of characters

[0049] Exemplary embodiments of the disclosure are explained below with reference to the accompanying drawings, wherein identical reference numerals denote identical or similar elements, and wherein Fig. Figure 1 schematically shows an example of an implementation of a delay cell; Fig. Figure 2 schematically shows another example of an implementation of a delay cell; Fig. Figure 3 schematically shows a block diagram of a circuit for delaying a digital input signal according to an embodiment of the present disclosure; Fig. Figure 4 schematically shows a block diagram of a circuit for delaying a digital input signal according to another embodiment of the present disclosure; Fig. Figure 5 schematically shows a block diagram of a circuit for delaying a digital input signal according to yet another embodiment of the present disclosure; Fig. Figure 6-A schematically shows an example of a simulation result of the delay cell current versus the size of the control vector; Fig. Figure 6-B schematically shows another example of a simulation result of the generated delay compared to the size of the control vector; and Fig. Figure 7 schematically shows, in the form of a flowchart, a method for delaying a digital input signal of a circuit according to an embodiment of the present disclosure. Detailed description

[0050] As stated above, identical or equivalent reference numerals in this disclosure denote identical or equivalent elements, and their repeated description may be omitted for brevity. The switching devices mentioned in this disclosure may be transistor devices, such as MOSFETs. In some figures, the switching devices may be simplified, but they should be understood as identical or similar switching devices to those shown in other figures.

[0051] Fig. Figure 1 schematically shows an example of a delay cell circuit 100 Such a delay cell circuit can also simply be called a delay cell. In particular, the delay cell has 100 a capacitive element 101 and a level detection circuit 102 as is obvious to experts, the capacitive element can 101It can be implemented as simply as a capacitor or any other suitable element. Similarly, the level-sensing circuit can be implemented in this way. 102 It can be implemented as simply as a comparator or any other suitable circuit. The delay cell 100 further features a first switching device 103 and a second switching device 104 up. The first switching device 103 and the capacitive element 101 are coupled (connected) in series between a supply voltage VDD and a predetermined voltage level. The predetermined voltage level can be, for example, VSS, ground (GND), or another suitable reference voltage level. In particular, the delay cell features 100 further a power source 105 on, which between the supply voltage VDD and the first switching device 103 is coupled, so that the capacitive element 101through a charging current from the power source 105 can be charged when the first switching device 103 is closed (i.e., in the ON state or the conducting state). Configured in this way, the capacitive element 101 are charged by the charging current and accordingly generate a charging voltage at an intermediate node that is between the first switching element 103 and a connection of the capacitive element 101 is arranged (differently from the terminal connected to the specified voltage level VSS). As is obvious to experts, the charging voltage can vary (increase) and depends on the charging process of the capacitive element. 101 dependent. On the other hand, the second switching device 104 parallel to the capacitive element 101 coupled between the intermediate node and the predetermined voltage level VSS. The second switching device 104is used to decouple the capacitive element 101 from the power source 105 during the ON state of the second switching device 104 used. In this case, the capacitive element is (gradually) discharged to zero (ground).

[0052] To generate a signal delay, a digital input signal D_in is provided and used to control (operate) the first switching device. 103 and the second switching device 104 used. For example, if the first and second switching devices 103 and 104If the MOSFETs are implemented, then the digital input signal D_in can be applied to the gate terminals (generally control terminals) of the MOSFETs. Since the input signal D_in is a digital signal, a high value ("1") of the digital input signal D_in applied to the gate terminal generally means that the respective switching device is in the ON state, while a low value ("0") of the digital input signal D_in applied to the gate terminal generally means that the respective switching device is in an OFF state (non-conducting state). As is obvious and recognizable to those skilled in the art, the OFF time for the digital input signal (i.e., the duration of a digital input signal remaining at the low value) may need to be long enough to allow the capacitive element to fully degrade. 101 to completely discharge to mass.

[0053] In particular, as also from Fig. As can be seen in 1, the capacitive element will be used. 101 to properly charge and discharge, the first switching device 103 and the second switching device 104 The switching devices are configured in their respective ON states in a mutually exclusive (complementary) manner based on the digital input signal. This means that, depending on the value (amplitude) of the digital input signal D_in, only one of the first switching devices is activated. 103 and the second switching device 104 one is in the ON state and the other is in the OFF state.

[0054] Configured in this way, a (varying) charging voltage can be generated at the intermediate node. The charging voltage is then fed to an input terminal of the comparator. 102 supplied 102is provided with a suitable reference voltage. Consequently, depending on the switching (e.g., from low to high or from high to low) of the comparator, 102 (based on a comparison of the charging voltage and the reference voltage) a delayed digital output signal D_out is generated.

[0055] In the delay cell implementation 100 from Fig. 1 represents only the rising edge of the digital input signal D_in, delayed. However, as is obvious and recognizable to experts, various variations of the delay cell circuit can be implemented, and the falling edge (or both the rising and falling edges) can also be delayed as desired. For example, the placement of the power source 105 and the capacitive element 101 be swapped, i.e., the power source 105can be placed on the lower side and the capacitive element 101 can be placed on the high side. Generally speaking, the delay time T can del The relationship between the digital output signal D_out and the digital input signal D_in can be expressed as: T d e l = C × V r e f I where C is the capacitance of the capacitive element 101 is, Vref which is connected to the comparator 102 supplied reference voltage and I of the current source 105 The supplied charging current is... Sometimes an additional (constant) delay T... fixed , caused by finite parasitic capacities and the comparator delay 102 , should be considered. In some cases, however, such a constant delay T may not be possible. fixed will be omitted (temporarily) for the sake of simplicity.

[0056] As can be seen from the equation above, in order to adjust the delay to the required value, it would generally be necessary to change (at least) one of the three parameters, namely the capacity of the capacitive element. 101 , the reference voltage of the comparator 102 and the charging current of the power source 105 Furthermore, to achieve a delay that is linearly proportional to a control input (in Fig. (1 not shown), it would be desirable for the value of the parameter to be adjusted to also be able to be changed in a linear manner.

[0057] Fig. Figure 2 schematically shows another example of an implementation of a delay cell circuit. 200 In particular, identical or the same reference numerals in Fig. 2 identical or the same elements in the delay cell circuit 100 , as in Fig. Figure 1 is shown, so that its repeated description can be omitted for the sake of brevity. In addition to the delay cell circuit 100 from Fig. 1 is also a third switching device 206 provided for. The third switching device 206 is between the power source 205 and coupled to the specified voltage level VSS. As shown in the diagram. Fig. As can be seen in section 2, the third switching device 206 through the digital input signal D_in in conjunction with the second switching device 204 controlled (operated). That is, the third switching device 206 can be used simultaneously with the second switching device 204 to be switched to the ON state, complementary to that of the first switching device 203 . Arranged in this way, the power source 205 with the specified voltage level (VSS or GND) during the discharge phase of the capacitive element 201be coupled, thereby reducing the influence of the power source 205 The delay generation is reduced (eliminated).

[0058] In particular, in the delay cell circuit 200 from Fig. 2, the power source 205 through a control input 207 controlled. That is, depending on the value of the control input. 207 Can a different charging current come from the power source? 205The control input can in some cases be referred to as a (digital) control vector, which has, for example, N (input) bits, where N is an integer greater than or equal to 1. As is obvious and recognizable to experts, the number N can be chosen (determined) depending on various circumstances and / or requirements, such as the maximum required delay, etc. For example, if N is equal to 8 (i.e., an 8-bit control vector), this means that the input value supplied to the reciprocal stream can be any value from 0 (i.e., all 8 bits set to 0) to 255 (i.e., all 8 bits can be set to 1). Arranged in this way, it can be done by varying the value of the control input. 207 The generated delay time between the digital output signal D_out and the digital input signal D_in can also be varied.

[0059] To avoid a delay time T delTo generate a value linearly related to the value of the control vector, the charging current I must change as a reciprocal function as follows: I = 1 d e l a y s e l e c t where delay select denotes the value of the control vector.

[0060] Fig. Figure 3 schematically shows a block diagram of a circuit. 300 for delaying a digital input signal according to an embodiment of the present disclosure. The circuit 300 features a "reciprocal current" DAC 310 and a delay cell 320 on, which are coupled together. The delay cell can, for example, be called the delay cell 100 from Fig. 1, the delay cell 200 from Fig. 2 or implemented in some other suitable way, as is obvious to experts. On the other hand, the "reciprocal current" DAC 310 configured to output a charging current 312to the delay cell circuit 320 according to the value of a tax receipt 311 , which is connected to the "reciprocal current" DAC 310 is provided. The control input (vector) 311 For example, the same control vector can 207 as in Fig. 2 will be shown. The delay cell 320 is then configured to generate a delayed digital output signal 322 of the digital input signal 321 based on the charging current 312 , which is through the "reciprocal current" DAC 310 is generated by introducing the "reciprocal current" DAC. 310 The generated charging current 312 a reciprocal (inversely proportional) function with respect to the control vector 311 , as shown in the equation above. Configured in this way, a delay time (between the digital output signal) can be introduced. 322 and the digital input signal 321) are generated, which changes linearly proportional to the control vector.

[0061] Fig. Figure 4 schematically shows a block diagram of a circuit. 400 for delaying a digital input signal according to another embodiment of the present disclosure. In particular, identical or equivalent reference numerals in Fig. 4 identical or the same elements in the circuit 300 , as in Fig. 3 shown, so that their repeated description can be omitted for the sake of brevity.

[0062] In addition to the circuit 300 from Fig. 3 are also a bias circuit 430 and a feedback circuit 440 The bias circuit is planned. 430 with the "reciprocal current" DAC 410 coupled to create a bias current 432to generate the "reciprocal current" DAC. As is obvious to experts, in some cases the generated bias current can 432 as a current that the bias circuit 430 from the "reciprocal current" DAC 410 wants to refer to (discard) the bias circuit 430 The feedback circuit 440 is with the bias circuit 430 and the "reciprocal current" DAC 410 coupled. The feedback circuit is used to generate an operating voltage. 442 based on the bias current 432 used. In particular, the operating voltage 442 for controlling (operating) the "reciprocal current" DAC 410 used. As is obvious to experts, the feedback circuit can be implemented as a feedback loop that connects an output of the "reciprocal current" DAC. 410 and an input of the "reciprocal current" DAC 410is coupled. In some cases, the feedback circuit can 440 They include an amplification circuit. This amplification circuit can be used to generate the operating voltage required to control (operate) the reciprocal current DAC. 410 is used. In some cases, the amplification circuit can be implemented as simply as an amplifier. However, other suitable implementations of the amplification circuit can also be used, as is obvious to experts. It should be noted that the feedback circuit 440 is chosen such that the output charging current of the "reciprocal current" DAC 410 It is immune to fluctuations in power supply. Therefore, the bias current can be controlled. 432 for the DAC 410 for a given PVT be constant and only a function of the reference voltage.

[0063] In some cases, generating the operating voltage 442(a step) of comparing the bias current 432 exhibiting a current that is determined by the charging current 412 depends. Accordingly, the operating voltage can be generated based on the result of the comparison. The result of the comparison can be fed to the feedback circuit. 440 as an entrance 441 be supplied. As is obvious and recognizable to experts, the (actual) current supplied by the "reciprocal current" DAC can 410 is related, depending on circumstances (e.g. a change in the value of the tax receipt). 411 , a change in the configuration of the "reciprocal current" DAC 410 etc.) vary (increase or decrease) and can therefore be larger or smaller than the bias current. 432 This difference would therefore lead to a change (increase or decrease) in the operating voltage. 442 of the "reciprocal current" DAC 410due to the presence of the feedback circuit 440 to regulate the current back to the desired value.

[0064] What's next? Fig. As can be seen in section 4, the delay cell 420 and the bias circuit 430 Both have a respective reference input voltage 423 and 433 . In particular the reference input 423 the delay cell 420 and the reference input 433 the bias circuit 430 They can have the same reference voltage. Configured in this way, the generated delay can be made independent of variations in the reference input due to PVT. The feedback circuit 440 then captures the output 432 the bias circuit 430 and fits the "reciprocal current" DAC 410due to variations in the reference voltage. In particular, in some cases the bias current can be generated by forcing the reference voltage across a resistor with a temperature coefficient of zero to track the threshold of the comparator of the delay cell. Alternatively, in some other cases the bias current can be a fixed bias that can be trimmed for process variation.

[0065] Fig. Figure 5 schematically shows a block diagram of another circuit. 500 for delaying a digital input signal according to a further embodiment of the present disclosure. In particular, identical or equivalent reference numerals in Fig. 5 identical or the same elements in the circuit 400 , as in Fig. 4 shown, so that their repeated description can be omitted for the sake of brevity.

[0066] Compared to the circuit 400 from Fig. 4 indicates the “reciprocal current” DAC 510 a large number of early transistor devices 513 and a second transistor device 514 on. In particular, the second transistor device 514 between the supply voltage VDD and the delay cell circuit 520 coupled. On the other hand, each of the multitude of first transistor devices is 513 selectively switchable to switch between the supply voltage VDD and the bias circuit 530 to be coupled and to share a common gate with the second transistor device 514 to have. The term "common gate" generally means that the respective gates of the selected number of first transistor devices and the gate of the second transistor device are connected together. Thus, a configurable number of first transistor devices can be 513can be selected to switch between the supply voltage VDD and the bias circuit. 530 to be coupled. In some cases, the multitude of first transistor devices can 513 They may be coupled in parallel to each other. However, other suitable connections between the multitude of first transistor devices are also possible. 513 can be used as long as each of the multitude of first transistor devices 513 is selectively switchable to switch between the supply voltage VDD and the bias circuit 530 to be coupled and to share a common gate with the second transistor device 514 to have. The feedback circuit 540 generated operating voltage 542 can then be connected to the common gate of the selected (configurable) number of first transistor devices. 513 and the second transistor device 514 will be delivered.

[0067] The configurable number of first transistor devices 513 can be based on the value of the control input (e.g., the control vector). 411 from Fig. 4, in Fig. 5 (not shown) can be determined. In other words, depending on a specific value of the control input (to generate a corresponding specific delay), a corresponding specific configurable number of first transistor devices can be selected. 513 selected (activated) to switch between the supply voltage VDD and the bias circuit 530 to be coupled.

[0068] Optionally (but not necessarily) the "reciprocal current" DAC can 510 further a third transistor device 515 exhibiting, in parallel to the multitude of first transistor devices 513 between the supply voltage VDD and the bias circuit 530 is coupled. In particular, the third transistor device can 515the same multiplicity as the second transistor device 514 have. In some cases, the second transistor device 514 compared to the third transistor device 515 They have a higher multiplicity to compensate for parasitic capacitances and delays. The third transistor device 515 The common gate can also be configured with the first transistor devices. 513 and the second transistor device 514 divide. That is, the gate of the third transistor device 515 can be connected to the common gate of the configurable number of first transistor devices 513 and the second transistor device 514 be connected.

[0069] In particular, the feedback circuit 540 ensure that the sum of the current from the configurable number of first transistor devices 513(and optionally the current from the third transistor device) 515 , if available) equal to the bias current 532 This applies to the "reciprocal current" DAC. As shown above, the number of first transistor devices is changed (configured) according to the control vector to change the delay accordingly. Consequently, the sum of the currents from the configurable number of first transistor devices 513 (and optionally the current from the third transistor device) 515 , if available) are provided for, larger or smaller than the bias current. 532 for the "reciprocal current" DAC 510 The result is an increase or decrease in voltage (or current). 541 at the input node of the feedback circuit 540 The feedback circuit increases or decreases the feedback accordingly. 540 then the gate voltage for the multitude of first transistor devices 513, the second transistor devices 514 and optionally the third transistor device 515 , if present, to regulate the output back to its original desired value via the feedback loop.

[0070] In particular, the bias circuit can be used in some examples. 530 (also the bias circuit) 430 from Fig. 4) have a fourth transistor device (in Fig. 5 not shown). The fourth transistor device can be accessed via the reference voltage. 533 can be controlled. As shown above, the same reference voltage can be used. 523 , which is used in the delay cell circuit, can be used to power the fourth switching device of the bias circuit 530to operate (to control). Configured in this way, the delay can be generated in a manner independent of variations in the reference voltage. In particular, all of the transistor devices mentioned above (i.e., the first through fourth transistor devices) can be of the same transistor type. That is, the transistor devices can be implemented using the same transistor type (e.g., NPN or PNP transistors). Configured in this way, the delay can be generated in a manner independent of variations in the process (during the implementation of the transistors). Similarly, the bias circuit can 530 It can be configured to generate a temperature-independent current to create a delay in a manner that is independent of temperature variations. Configured in this way, the delay-generating circuit can be implemented as PVT-independent.

[0071] In the Fig. 5 circuits shown 500 can the delay time T del The difference between the digital output signal and the digital input signal can be calculated according to the following equations: I u n i t = I b i a s P _ 3 + P _ 1 [ N : 1 ] T d e l = V r e f × C I u n i t × P _ 2 T d e l = V r e f × C × ( P _ 3 + P _ 1 [ N : 1 ] ) I b i a s × P _ 2 where Ibias is the one controlled by the bias circuit 530 generated bias current 532 is, P_1[N: 1] the configurable number of first transistor devices 513 Based on the N-bit input control vector, P_2 represents the second transistor device. 514 P_3 represents the third transistor device 515 represents and lunit represents the unit current, which is determined by the configurable number of first transistor devices. 513 and the (optional) third transistor device 515 is caused based on the N-bit input control vector.

[0072] As can be seen from the equations above, when the configurable number of first transistor devices 513 based on the value of the N-bit control vector changes (i.e., from 0 to 2) N - 1), the quantity T also changes accordingly. del linear, which implies that the charging current is a reciprocal function of T del (at least) in the area where the configurable number of first transistor devices 513 changes from 0 to N-1.

[0073] The Fig. 6-A and Fig. Figure 6-B schematically shows simulation results of the circuit. 500 from Fig. 5. In particular, it shows Fig. 6-A is the simulation result of the charging current versus the control vector quantity. As shown in the curve. 610 from Fig. As can be seen in diagram 6-A, when the size (value) of the control vector increases (e.g., from 0 to 127, as shown in the x-axis), the charging current decreases in an inversely proportional (reciprocal) way (as shown in the y-axis). On the other hand, diagram 6-A shows that... Fig. 6-B the simulation result of the generated delay compared to the control vector quantity. As shown by the curve 620 from Fig. 6-B shows that when the size (value) of the control vector increases (e.g. from 0 to 255 , as shown in the x-axis), the generated delay also increases in a linearly proportional way (as shown in the y-axis).

[0074] Fig. Figure 7 schematically shows a flowchart of a process. 700 for delaying a digital input signal of a circuit according to an embodiment of the present disclosure. The circuit arrangement can be one of the circuit arrangements 300 , 400 and 500 correspond, as in the Fig. 3 to Fig. Figure 5 shows that a repeated description of its circuit can therefore be omitted for the sake of brevity. In particular, the method shows that 1400 on in step S710 an output through a "reciprocal current" DAC (e.g. the "reciprocal current" DAC) 310 from Fig. 3) a charging current to a delay cell circuit (e.g. the delay cell) 320 from Fig. 3) according to a value of a control input (e.g. the control vector) 311 from Fig. 3) The charging current is inversely proportional to the value of the control input. The procedure 700 points further in step S720 a generation, by means of the delay cell circuit, of a delayed digital output signal (e.g. the digital output signal) 322 from Fig. 3) of the digital input signal (e.g. the digital input signal) 322 from Fig.3) The generated delay depends on the charging current generated by the "reciprocal current" DAC.

[0075] It should be noted that the device (circuit) features described above correspond to respective process features, which, however, may not be explicitly described for reasons of brevity. The disclosure of this document is also intended to extend to such process features. In particular, this disclosure is intended to relate to methods for operating the circuits described above and / or for providing and / or arranging corresponding elements of these circuits.

[0076] It should further be noted that the description and drawings merely illustrate the principles of the proposed circuits and methods. Those skilled in the art will be able to implement various arrangements which, although not explicitly described or shown here, embody the principles of the invention and are included in its meaning and scope. Furthermore, all examples and embodiments presented in this document are expressly intended for explanatory purposes only, to facilitate the reader's understanding of the principles of the proposed method. Moreover, all statements contained herein that provide for principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof.

Claims

[1] Circuit for delaying a digital input signal, wherein the circuit comprises: a delay cell circuit; and a “reciprocal current” digital-to-analog converter (DAC) coupled to the delay cell circuit, wherein the “reciprocal current” DAC is configured to output a charging current to the delay cell circuit according to a value of a control input; where the charging current is inversely proportional to the value of the control input; wherein the delay cell circuit is configured to generate a delayed digital output signal of the digital input signal; and the delay depends on the charging current. [2] The circuit according to claim 1, wherein the circuit further comprises: a bias circuit coupled to the "reciprocal current" DAC to generate a bias current for the "reciprocal current" DAC; and a feedback circuit coupled to the bias circuit to generate an operating voltage based on the bias current, the operating voltage being used to control the "reciprocal current" DAC. [3] The circuit according to claim 2, wherein the feedback circuit includes a gain circuit for generating the operating voltage which is used to control the “reciprocal current” DAC. [4] The circuit according to claim 2 or 3, wherein generating the operating voltage comprises comparing the bias current with a current which depends on the charging current and generating the operating voltage based on a result of the comparison. [5] The circuit according to any one of claims 2 to 4, wherein the “reciprocal current” DAC comprises a plurality of first transistor devices and a second transistor device; wherein each of the plurality of first transistor devices is selectively switchable to be coupled between a supply voltage and the bias circuit and to have a common gate with the second transistor device, so that a configurable number of first transistor devices can be selected to be coupled between the supply voltage and the bias circuit; and the second transistor device is coupled between the supply voltage and the delay cell circuit. [6] The circuit according to claim 5, wherein the configurable number of first transistor devices is determined based on the value of the control input. [7] The circuit according to claim 5 or 6, wherein the operating voltage generated by the feedback circuit is supplied to the common gate. [8] The circuit according to any one of claims 5 to 7, wherein the “reciprocal current” DAC further comprises a third transistor device coupled in parallel to the plurality of first transistor devices between the supply voltage and the bias circuit; and wherein the third transistor device shares the common gate with the configurable number of first transistor devices and the second transistor device. [9] The circuit according to one of the preceding claims, wherein the delay cell circuit comprises: a capacitive element coupled between the "reciprocal current" DAC and a predetermined voltage level, which can be charged by the charging current, to generate a charging voltage at an intermediate node based on a charge of the capacitive element; and a comparator coupled to the intermediate node to generate the delayed digital output signal based on a comparison between the charging voltage and a reference voltage. [10] The circuit according to claim 9, wherein the delay cell circuit further comprises a switching arrangement configured to couple the capacitive element with the charging current on a rising edge or a falling edge of the digital input signal. [11] The circuit according to claim 10, wherein the circuit arrangement comprises: a first switching device coupled between the "reciprocal current" DAC and the intermediate node to couple the capacitive element with the charging current during an ON state of the first switching device; and a second switching device coupled in parallel to the capacitive element between the intermediate node and the predetermined voltage level to decouple the capacitive element from the charging current during an ON state of the second switching device, and wherein the first and second switching devices are switched to the ON state in a mutually exclusive manner based on the digital input signal. [12] The circuit according to claim 11, wherein the circuit arrangement further comprises: a third switching device coupled between the "reciprocal current" DAC and the specified voltage level; and wherein the third switching device is switched to the ON state in conjunction with the second switching device. [13] The circuit according to any one of claims 2 to 12, wherein the bias current is generated based on the same reference voltage as used by the delay cell circuit. [14] The circuit according to any one of claims 2 to 13, wherein the bias circuit has a fourth transistor device which is controlled by a reference voltage. [15] The circuit according to any one of claims 5 to 13, wherein all transistor devices are of the same transistor type. [16] Method for delaying a digital input signal to a circuit, wherein the circuit comprises: a delay cell circuit; and a “reciprocal current” digital-to-analog converter (DAC) coupled to the delay cell circuit, and wherein the method features: Output, through the "reciprocal current" DAC, of ​​a charging current to the delay cell circuit according to a value of a control input, wherein the charging current is inversely proportional to the value of the control input; and Generating, by means of the delay cell circuit, a delayed digital output signal of the digital input signal, wherein the delay depends on the charging current. [17] The method according to claim 16, wherein the circuit further comprises: a bias circuit coupled with the "reciprocal current" DAC; and a feedback circuit coupled with the bias circuit, and the procedure further exhibits: Generating, through the bias circuit, a bias current for the "reciprocal current" DAC; Generating an operating voltage based on the bias current; and Controlling the "reciprocal current" DAC using the operating voltage. [18] The method according to claim 17, wherein the feedback circuit includes an amplification circuit for generating the operating voltage which is used to control the “reciprocal current” DAC. [19] The method according to claim 17 or 18, wherein generating the operating voltage comprises comparing the bias current with a current that depends on the charging current and generating the operating voltage based on a result of the comparison. [20] The method according to any one of claims 17 to 19, wherein the “reciprocal current” DAC comprises a plurality of first transistor devices and a second transistor device; wherein each of the plurality of first transistor devices is selectively switchable to be coupled between a supply voltage and the bias circuit and to have a common gate with the second transistor device, so that a configurable number of first transistor devices can be selected to be coupled between the supply voltage and the bias circuit; and the second transistor device is coupled between the supply voltage and the delay cell circuit. [21] The method according to claim 20, wherein the method further comprises determining the configurable number of first transistor devices based on the value of the control input. [22] The method according to claim 20 or 21, wherein the method further comprises supplying the operating voltage generated by the feedback circuit to the common gate. [23] The method according to any one of claims 20 to 22, wherein the “reciprocal current” DAC further comprises a third transistor device coupled in parallel to the plurality of first transistor devices between the supply voltage and the bias circuit; and wherein the third transistor device shares the common gate with the configurable number of first transistor devices and the second transistor device. [24] The method according to any one of claims 16 to 23, wherein the delay cell circuit comprises: a capacitive element coupled between the "reciprocal current" DAC and a predetermined voltage level, which can be charged by the charging current, to generate a charging voltage at an intermediate node based on a charge of the capacitive element; and a comparator coupled to the intermediate node to generate the delayed digital output signal based on a comparison between the charging voltage and a reference voltage. [25] The method according to claim 24, wherein the delay cell circuit further comprises a switching arrangement configured to couple the capacitive element with the charging current on a rising or falling edge of the digital input signal. [26] The method according to claim 25, wherein the switching arrangement comprises: a first switching device coupled between the "reciprocal current" DAC and the intermediate node to couple the capacitive element with the charging current during an ON state of the first switching device; and a second switching device coupled in parallel to the capacitive element between the intermediate node and the predetermined voltage level to decouple the capacitive element from the charging current during an ON state of the second switching device, and wherein the method further comprises switching the first and second switching devices into the ON state in a mutually exclusive manner based on the digital input signal. [27] The method according to claim 26, wherein the switching arrangement further comprises: a third switching device coupled between the "reciprocal current" DAC and the specified voltage level; and wherein the third switching device is switched to the ON state in conjunction with the second switching device. [28] The method according to any one of claims 17 to 27, wherein the method further comprises generating the bias current based on the same reference voltage as used by the delay cell circuit. [29] The method according to any one of claims 17 to 28, wherein the bias circuit has a fourth transistor device which is controlled by a reference voltage. [30] The method according to any one of claims 20 to 29, wherein all transistor devices are of the same transistor type.

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