Device with large epi in FinFETs and manufacturing process

Abstract

Device comprising: a first group of fins (103) of a first type in a first compound and a second group of fins (103) of a second type in a second compound; an RSD (203) formed on each fin of the first group of fins (103) over a substrate (105), wherein the RSD (203) has a plurality of RSD sub-areas over each of the fins of the first group of fins (103) and wherein each RSD sub-area has a width greater than 1.3 × fin spacing; and wherein an exposed side (301) is formed on one of the RSD sub-areas formed on a top surface of the first group of fins that is closest to the second group of fins; and wherein a margin is formed between the exposed side (301) of the RSD and the second group of fins and wherein the second group of fins (103') has a lower height than the first group of fins (103); a TS formed on the RSD (203);and an ILD formed above the TS;

Description

TECHNICAL AREA

[0001] The present invention relates to devices with large source / drain regions (RSD regions) for fin-type field-effect transistor devices (FinFET devices) and methods for manufacturing them. The present invention is particularly applicable to the technology node of 7 nanometers (nm) and beyond. BACKGROUND

[0002] A larger epitaxial width (epi-width) increases the performance of advanced semiconductor devices at the 7 nm technology node or beyond, such as the 5 nm technology node. In FinFET technology, the epi-RSD width is limited to 0.7 × to 1.3 × fin pitch by the tight layout and variation / facet characteristics of the epi-RSD process. A larger epi-RSD, e.g., silicon phosphorus (eSiP), is desirable because 1 nm of eSiP correlates with a 1% increase in nFET performance and a similar effect for pFETs. An epi-width greater than three times the fin pitch leads to a deterioration in yield loss because a long tail of the epi-RSD width greater than three times the fin pitch results in a smaller NP space. Therefore, there is a need to make the Epi-RSD width greater than 1.3 × fin spacing without a yield loss, and to improve the resulting device. SUMMARY

[0003] One aspect of the present invention is a device with an RSD area formed on each of a plurality of fins over a substrate, wherein the RSD has a width greater than 1.3 × fin spacing.

[0004] Another aspect of the present invention is a method for forming RSD areas by epi-growth, each with a width greater than 1.3 × fin spacing and with a distance between an exposed side of the epi-RSD on a first group of fins and a spacer of a second group of fins.

[0005] Another aspect of the present invention is a method for forming RSD areas by epi-growth, each with a width greater than 1.3 × fin spacing and with a liner on the exposed side of the epi-RSD on the first group of fins.

[0006] Additional aspects and other features of the present invention are set forth in the following description and will be apparent to a person skilled in the art upon examination of the following or can be learned from practical experience with the present invention. The advantages of the present invention can be implemented and maintained as set forth in particular in the appended claims.

[0007] According to the present invention, some technical effects can be achieved in part by a device comprising: an RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width greater than 1.3 × fin spacing; a trench silicide (TS) formed on the RSD; and a dielectric intermediate layer (ILD) formed over the TS.

[0008] Another aspect of the present invention is a method comprising: forming a first group and a second group of fins extending over a shallow trench insulation layer (STI layer); forming an RSD area by epi-growth on each fin of the first group of fins at a first joint, wherein the RSD has a width greater than 1.3 × fin spacing; depositing a first structuring varnish on the epi-RSD in the first joint; exposing a side of the epi-RSD closest to the second group of fins; and forming a sacrificial liner over and between the epi-RSD, including the exposed side in the first joint and over a spacer covering the fins of the second group.

[0009] Another aspect of the present invention is a method comprising: forming a first group and a second group of fins extending over an STI layer; forming an RSD area by epigrowth at each fin of the first group of fins at a first joint, wherein the RSD has a width greater than 1.3 × fin spacing; forming a sacrificial liner over and between the epi-RSD in the first joint and over a spacer covering the fins of the second group; depositing a first structuring varnish over the sacrificial liner in the first joint; exposing one side of the epi-RSD closest to the second group of fins; and forming a liner on the exposed side of the epi-RSD.

[0010] Additional aspects and technical effects of the present invention are readily apparent to the person skilled in the art from the following detailed description, wherein embodiments of the present invention are simply described by illustrating the best way considered for carrying out the present invention. As will be recognized, the present invention can take other and different embodiments, and its various details can be modified in several obvious ways without departing from the present invention. Accordingly, the drawings and the description are to be regarded as illustrative and not as limiting. List of characters

[0011] The present invention is illustrated by way of example and without limitation in the figures of the accompanying drawing, in which similar reference numerals refer to similar elements and in which: Fig. 1 schematically represents a top view of a logic or memory cell according to an exemplary embodiment; Fig. 2 to Fig. 7 schematic sequential steps of a procedure for forming a large RSD area by epigrowth in the logic and memory cell at an intersection line 1A-1A' out of Fig. 1 according to an exemplary embodiment; Fig. 8 to Fig. 12 schematic sequential steps of a procedure for forming a large RSD area by epigrowth in the logic and memory cell Fig. 1 according to another exemplary embodiment. DETAILED DESCRIPTION

[0012] The following description includes numerous specific details for explanatory purposes, to facilitate a thorough understanding of exemplary embodiments. However, it should be clear that exemplary embodiments can be implemented without these specific details or with an equivalent arrangement. In other cases, known structures and devices are presented in block diagram form to avoid unnecessary obfuscation of exemplary embodiments. Furthermore, unless otherwise stated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, etc., used in the specification and claims are to be understood as being modified by the term "approximately" in all cases.

[0013] The present invention addresses the current problems of the existing epi-RSD width of 0.7 × to 1.3 × fin spacing and the adverse yield loss associated with an epi-RSD width smaller than 3 × fin spacing in the formation of logic and memory cell devices at and beyond the 7 nm technology node. These problems are solved, among other things, by forming an RSD region via epi-growth with a width greater than 1.3 × fin spacing.

[0014] The method according to embodiments of the present invention comprises forming a device with an RSD area formed on each of a plurality of fins over a substrate, wherein the RSD has a width greater than 1.3 × fin spacing. A TS is formed on the RSD and an ILD is formed over the TS.

[0015] Further aspects, features, and technical effects are readily apparent to the person skilled in the art from the following detailed description, in which preferred embodiments are shown and described simply by illustrating the best mode. The invention is suitable for other and different embodiments, and its various details can be modified in several obvious ways. Accordingly, the drawings and the description are to be regarded as illustrative and not as limiting.

[0016] Fig. Figure 1 is a top view of a FinFET device with Epi's. The device includes gates. 101 across and perpendicular to the fins 103 . Fig. 2 to Fig. Figure 7 schematically illustrates successive steps of a procedure for forming a large RSD area by Epi in the logic or memory cell at an intersection line. 1A-1A' from Fig. 1 according to an exemplary embodiment. Referring to Fig. 1 is a gate 101 over the several fins 103 and 103' educated. In Fig. 2 is the group of Finns 103 and 103' on a substrate 105 (not shown for the sake of simplicity) with a first group of Finns 103 in a first / right-wing connection and a second group of Finns 103' formed in a second / left connection. The Finns 103 and 103' extend over an STI layer 201 The RSD areas 203 are diamond-shaped and are formed, for example, by epigrowth on each of the first group of fins. 103 formed in the first / right connection.

[0017] In one case, there is an important difference between Fig. 2 and a FinFET device therein, such that the RSD areas 203are larger. For example, in the FinFET device, the RSD areas are designed with a width, e.g., in a range of about 0.7 × to about 1.3 × fin spacing, so that the diamond-shaped cross-sections are only in contact with each other, whereas in Fig. 2 the RSD areas 203 on each of the Finns 103 They can be formed, for example, by epi-growth with a width greater than approximately 1.3 × fin spacing. Therefore, the rhomboid cross-sections overlap. The larger epi-RSD 203 This increases the device's performance, especially when the epi-RSD exhibits significant variation, such as eSiP on a 7 nm technology node. The RSD areas 203These materials can be formed, for example, from silicon-germanium (SiGe), silicon-phosphorus (SiP), silicon-carbon-phosphorus (SiCP), silicon-carbon-boron (SiCB), or any other materials with similar functional properties. In one case, epigrowth can be carried out at a temperature of, for example, 500°C to 800°C for a period of, for example, 0.5 minutes to 60 minutes and at a pressure of, for example, 1 Torr to 500 Torr.

[0018] With further reference to Fig. 2 are spacers 205 each above the tops and sides of the second group of fins 103' formed in the second / left connection, so that the second group of Finns 103' can be shielded by a spin-on hard mask structuring (SOH structuring) process, which is later carried out for the creation of the right compound. Fig. 2 carries a reference SOH structuring line 207 and a SOH material209 to remove sections in the first / right connection in Fig. 2. In contrast to the SOH structuring line used in the fabrication of the FinFET device, the reference SOH structuring line is 207 to the epi-RSD areas 203 shifted to reserve a margin of, for example, about 3 nm of the associated inserted pattern for lithography alignment and overlay control (OVL control), e.g., a development critical dimension (CD) control of 10 nm.

[0019] With reference to Fig. 3 will be a SOH material 209 over any Epi-RSD 203 isolated in the first / right connection and parts of the Epi-RSD 203 , which are not made of the SOH material 209Covered areas are removed, for example, by selective anisotropic etching in the first / right-hand compound. In one case, etchants such as CF3, Cl, or hydrogen bromide (HBr) can be used for selective anisotropic etching. The removed parts include an exposed surface. 301 of Epi-RSD 203 , the second group of Finns 103' nearest. For example, the width of the exposed side is 301 of Epi-RSD 203 approximately 0.1 × fin spacing.

[0020] As in Fig. 4 will be the SOH material 209 Removed, e.g., by ashing followed by cleaning, at the first / right-hand joint. Cleaning can be performed, for example, by wet etching using SC1, DHF, and SPM chemistry. These steps form the exposed side. 301 of Epi-RSD 203These are omitted during conventional processing. The well-known Epi-RSD does not contain the dry-etched parts of the Epi-RSD. 203 on (including the exposed side) 301 of Epi-RSD 203 , the second group of Finns 103' (nearest is).

[0021] According to the representation in Fig. 5 will be a liner 501 made of, for example, silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), silicon oxynitride (SiON), silicon-carbon-boron-nitrogen (SiCBN), silicon-carbon oxynitride (SiCON), silicon-carbon nitride (SiCN) or silicon nitride (SiBN) over the tops and sides of the fins. 103 and 103' or over exposed surfaces of the STI layers 201 formed. In this case, the liner can 501 for example, they can be formed with a thickness of 25 Å to 150 Å.

[0022] With reference to Fig. 6. A second structuring varnish will be applied. 601above the liner 501 on every Epi-RSD 203 using the same reference SOH structuring line 207 isolated. In this case, the known Epi-RSD does not have an exposed side like that of the Epi-RSD of the second group of fins. 103' is closest. Additionally, there is between the exposed side 301 of Epi-RSD 203 and the reference SOH structuring line 207 a rim, for example 3 nm thick, is provided to protect the exposed side 301 from the spacer of the second group of Finns 103' to keep away from the second / left connection.

[0023] According to the representation in Fig. 7 will be applied, while the second structuring coat 601Remaining in the first / right connection, a recess of the second / left connection using a third structuring varnish (not shown for simplicity) over the second / left connection for dry etching sections of the second group of fins 103' , located above the STI layer 201 in the second / left compound, formed. In one case, the dry etchant for the second / left compound recess may contain Cl, HBr, Ar, He, CF4, or O2. The third texturing varnish is then removed, for example, by ashing followed by cleaning from the second / left compound. Subsequently, the RSD 203 a trench silicide (TS) is formed, which is located on the outer edges of the fins. 103 extends past it, and an ILD is formed between and next to the TS (not shown for the sake of simplicity).

[0024] In one case, an RSD area in a diamond shape, e.g., through epigrowth, can then occur on each fin of the second group of fins. 103' in the second / left connection. In another case, the RSD regions in the first / right connection and the RSD regions in the second / left connection are of the same type, the same N-type or P-type. In yet another case, the RSD regions in the first / right connection and the RSD regions in the second / left connection are of different types, for example, one is of the N-type and the other is of the P-type.

[0025] Fig. 8 to Fig. Figure 12 schematically represents the successive steps of a procedure for forming a large RSD area by epigrowth in the logic or memory cell of Fig. 1 according to a further embodiment. According to the illustration in Fig. 8 of the second exemplary embodiment similar to the one over the several fins103 and 103' educated Gates 101 is a gate 801 (not shown for the sake of simplicity) over a large number of fins 803 and 803' trained. Similar to the group of Finns. 103 and 103' is on the substrate 105 with a first group of Finns 103 in a first / right-wing connection and a second group of Finns 103' in a second / left connection the group of Finns 803 and 803' on a substrate 805 (not shown for the sake of simplicity) with a first group of Finns 803 in a first / right-wing connection and a second group of Finns 803' formed in a second / left connection. Like the Finns 103 and 103' , which extend across the STI layer 201 extend, the Finns extend 803 and 803' via an STI layer 807Both RSD areas 203 and 809 , each in a diamond shape, are, for example, formed by epigrowth on each fin of the first group of fins. 103 and 803 Formed in the first / right connection. Over the upper surfaces and sides of the second fin groups. 103' and 803' are spacers 201 and 811 formed in the second / left connection.

[0026] With reference to Fig. 9 is the victim liner 901 about and between each Epi-RSD 809 in the first / right connection and above the spacers 811 formed, which form the ribs of the second groups 803' cover. According to the illustration in Fig. 10 will be the first textured paint 1001 above the victim liners 903 isolated in the first / right connection.

[0027] According to the representation in Fig. 11 sections of the Epi-RSD 809, which are not covered by the first structuring coat 1001 are covered, e.g. by dry etching in the first / right-hand connection, removed to reveal an exposed side 1101 to provide this without removing any of the known Epi-RSD. The dry-etched sections include the exposed side. 1101 of Epi-RSD 809 , the second group of Finns 803' nearest. A liner 1103 is applied with a thickness of, for example, 1 nm to 4 nm on the exposed side. 1101 The epi-RSD 809 is formed using a heavy nitride plasma process. In this case, the nitrogen-to-oxide ratio associated with the heavy nitrogen plasma is greater than one.

[0028] Fig. 11 is similar to Fig. 6 with the exception of the liner 1103 and the edge 603 In Fig. 6 will be the exposed side 301 of Epi-RSD 203 from the liner 501which also covers the rest of the Epi-RSD 203 covered. In Fig. The liner covers 11 1103 only the exposed side 1101 of the Epi-RSD, which belongs to the second group of Finns 803' it is closest, but does not cover the rest of the Epi-RSD 809 Furthermore, the edge 603 between the exposed side 301 from the Epi-RSD 203 and the reference SOH structuring line 207 only in Fig. 6 shown, but not in Fig. 11.

[0029] According to the representation in Fig. 12. A recess of the second / left connection is created using a second structuring varnish over the second / left connection for etching away the second group of fins by dry etching. 803' , which are located above the STI layer 807 located in the second / left connection, formed during the structuring varnish 1001The second texturing lacquer remains in the first / right joint. The second texturing lacquer above the second / left joint is then removed from the second / left joint (e.g., by ashing and cleaning). Fig. 12 is similar to Fig. 7 with the exception of the liner 1103 and the edge 603 , as explained above.

[0030] The embodiments of the present invention can achieve several technical effects that improve FinFET performance without any loss of yield; for example, 1 nm eSiP correlates with a 1% increase in nFET performance. Furthermore, the overlapping rhombic cross-sectional shape of the RSD regions eliminates 203 and 809Short circuits between the contacting rhombic shape in the cross-section of known RSDs and trench silicide (TS) on top of the known RSD increase the yield. Embodiments of the present invention are applicable in various industrial applications, such as microprocessors, smartphones, mobile phones, set-top boxes, DVD recorders and players, vehicle navigation systems, printers and peripherals, network and telecommunications equipment, gaming systems, and digital cameras. The present invention is particularly applicable to 7 nm technology nodes and beyond.

[0031] In the preceding description, the present invention is described with reference to particularly exemplary embodiments. However, it is evident that various modifications and additions can be made without deviating from the broader nature and scope of the present invention as set forth in the claims. The specifications and drawings are therefore to be regarded as illustrative and not as limiting. It is understood that the present invention can employ various other combinations and embodiments and that it can be modified or altered within the scope of the inventive concept expressed herein.

Claims

[1] Device comprising: an increased source / drain area (RSD) formed on each of a plurality of fins over a substrate, wherein the RSD has a width greater than 1.3 × fin spacing; a trench silicide (TS) formed on the RSD; and a dielectric intermediate layer (ILD) that is formed above the TS. [2] Device according to claim 1, wherein the RSD is formed by epitaxial growth (epi-growth). [3] Device according to claim 2, wherein the width of the RSD is less than 3 × fin spacing. [4] Device according to claim 3, wherein the plurality of fins comprises a first group of fins of the first type in a first compound and a second group of fins of the second type in a second compound and the RSD has a plurality of RSD sub-areas. [5] Device according to claim 4, wherein an exposed side is formed on one of the Sub-RSD, which is formed on a top side of the first group of fins that is closest to the second group of fins. [6] Device according to claim 5, wherein the width of the exposed side is greater than 0.1 × fin spacing. [7] Device according to claim 5, wherein a liner is formed on the exposed side. [8] Device according to claim 7, wherein the liner is 1 nm to 4 nm thick. [9] Device according to claim 5, wherein an edge is formed between the exposed side and a spacer of the second group of fins. [10] Device according to claim 9, wherein the edge is 3 nm thick. [11] Device according to claim 1, wherein the RSD is formed from silicon germanium (SiGe), silicon phosphorus (SiP), silicon carbon phosphorus (SiCP) or silicon carbon boron (SiCB). [12] Device according to claim 1, wherein the liner is formed from silicon nitride (SiN), silicon dioxide (SiO2), aluminium oxide (Al2O3), hafnium oxide (HfO2), silicon oxynitride (SiON), silicon carbon boron nitrogen (SiCBN), silicon carbon oxynitride (SiCON), silicon carbon nitride (SiCN) or silicon boron nitride (SiBN). [13] Procedures, including: a formation of a first group and a second group of fins extending over a shallow trench insulation layer (STI layer); a formation of an increased source / drain area (RSD) by epitaxial (epi) growth on each fin of the first group of fins at a first junction, wherein the RSD has a width greater than 1.3 × rib spacing; a deposition of a first structuring lacquer on the Epi-RSD in the first compound; an exposure of one side of the Epi-RSD closest to the second group of fins; and a sacrificial liner is formed over and between the epi-RSD with the exposed side in the first connection and over a spacer covering the fins of the second group. [14] The method of claim 13, comprising: a deposition of a second structuring lacquer over the sacrificial liner in the first compound and a third structuring lacquer over the sacrificial liner in the second compound; a removal of sections of the second group of fins located in the second compound above the STI layer; a removal of the third texturing lacquer in the second compound; and a formation of another RSD region through epigrowth at each fin of the second group of fins in the second connection. [15] Method according to claim 13, comprising a displacement of the first structuring varnish to the first group of fins in the first connection with an edge. [16] Method according to claim 15, comprising forming the edge with a thickness of 3 nm. [17] Procedures, including: a formation of a first group and a second group of fins extending over a shallow trench insulation layer (STI layer); a formation of an increased source / drain area (RSD) by epitaxial growth (epi-growth) at each fin of the first group of fins at a first junction, wherein the RSD has a width greater than 1.3 × fin spacing; a sacrificial liner forming over and between the epi-RSD in the first connection and over a spacer covering the fins of the second group; a deposition of a first structuring lacquer over the sacrificial liner in the first compound; an exposure of one side of the Epi-RSD closest to the second group of fins; and Formation of a liner on the exposed side of the epi-RSD. [18] The method of claim 17, comprising: a deposition of a second structuring lacquer over the sacrificial liner in the second compound; a removal of sections of the second group of fins located in the second compound above the STI layer; and a removal of the second texturing lacquer in the second joint; and a formation of another RSD area through EPI growth at each fin of the second group of fins in the second connection. [19] Method according to claim 17, comprising forming the liner on the exposed side of the Epi-RSD by a heavy nitride plasma process. [20] Method according to claim 19, comprising forming the liner on the exposed side with a thickness of 1 nm to 4 nm.

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