BIPOLEMAN TANSISTOR WITH GATE VIA CONNECTIONS

Abstract

Device comprising: a first group of fins (206) having a first base region (106) doped with a p-doped element, wherein an epitaxial emitter region (86) of a bipolar transistor (12) is arranged over the first group of fins (206); a second group of fins (208) having a second base region (108) doped with an n-doped element, wherein the second base region (108) contacts the first base region (106) and an epitaxial base region (84) of the bipolar transistor (12) is arranged over the second group of fins (208);a third group of fins (212) having a third base region (11) doped with a p-doped element, wherein an epitaxial collector region (82) of the bipolar transistor (12) is arranged above the third group of fins (212), wherein the epitaxial collector region (82) and the epitaxial emitter region (86) have the same conductivity type and the epitaxial base region (84) has a conductivity type opposite to that of the epitaxial collector region (82) and the epitaxial emitter region (86); a first gate structure (330) arranged above the first group of fins (206) adjacent to the epitaxial emitter region (86); a second gate structure (320) arranged above the second group of fins (208) adjacent to the epitaxial base region (84);and a third gate structure (310) arranged above the third group of fins (212) adjacent to the epitaxial collector region (82), wherein the second gate structure (320) is arranged between the first gate structure (330) and the third gate structure (310) and the first gate structure (330), the second gate structure (320) and the third gate structure (310) are physically and electrically separated.

Description

background

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. These different material layers are then structured using lithography to create circuit components and elements.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces additional problems that need to be addressed.

[0003] A bipolar junction transistor (BJT) has a base, a collector, and an emitter. BJTs are formed by two pn junctions arranged back-to-back, with one region of each junction being used. This arrangement results in either a pnp bipolar transistor or an npn bipolar transistor. In BJTs, the current flow through the emitter and collector is controlled by the voltage applied to the base and emitter. As the semiconductor industry has advanced to nanometer-scale technology in its pursuit of higher device density, higher performance, and lower costs, various methods have been implemented to improve BJT device performance. List of characters

[0004] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 shows a top-down view of a bipolar transistor device according to some embodiments. Fig. Figure 2 shows a perspective view of a bipolar transistor device according to some embodiments. The Fig. 3a and Fig. Figure 3b shows circuit diagrams for bipolar transistors according to some embodiments. The Fig. 4 to Fig. Figure 40 shows various representations of intermediate stages in the manufacture of a bipolar transistor according to some embodiments. Fig. Figure 41 shows a top-down view of a bipolar transistor device according to some embodiments. Detailed description

[0005] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] In some embodiments, BJTs are provided that are fabricated from fin field-effect transistors (FinFETs) using FinFET processes. An array of p-FinFETs can be connected to form a BJT collector terminal, an array of n-FinFETs can be connected to form a BJT base terminal, and an array of p-FinFETs can be connected to form a BJT emitter terminal. A source / drain of each of the arrays of FinFETs can be electrically interconnected and can also be electrically connected to the gate electrodes of the FinFETs. When they are brought into contact with each other via a substrate, a lateral BJT is formed. For example, in this case, the BJT is a pnp BJT. The gate structures of the FinFETs can be either polysilicon or metal.During the fabrication of the BJT, the gate structures can extend across the terminals and be separated in a subsequent process, or they can extend across certain terminals and be separated in a subsequent process, or they can be fabricated to extend across every single terminal. To improve the performance of the BJTs, in some embodiments the gate structure above the emitter terminal is separated from the gate structure above the base terminal. In some embodiments, the surface area of ​​the BJTs is also increased to provide sufficient spacing between these gate structures to prevent or reduce leakage from one gate structure to the next. It has been observed that separating the gate structures improves the stability of the base-emitter voltage ΔV. beThe performance is improved by approximately 50%. In some embodiments, the gate structures can also be connected to the respective sources / drains of the base terminal, the collector terminal, and the emitter terminal.

[0008] Fig. Figure 1 shows a top-down view of a BJT. 100 after an intermediate manufacturing stage according to some embodiments. Fig. 1 can, for example, be viewed as a top-down view of the process, which is described below with reference to Fig. 14 is described. The BJT 100 includes a BJT 12 and a BJT 14 , whereby the BJT 12 a first lateral BJT with an emitter connection 206 , a basic connection 208 and a collector connection 212 is and the BJT 14 a second lateral BJT with the emitter connection 206 , a basic connection 210 and a collector connection 214 is. In Fig. 1 will be an active area of ​​the BJT 100 through a length L1 and a width W1 defined. A total length L1 of the BJT 100 The length can be approximately 3 µm to approximately 5 µm, e.g., approximately 3.6 µm, but other values ​​are also considered. L1 can be chosen such that a mismatch between a parasitic BJT (which will be described later) in the substrate and the lateral BJTs (e.g. the BJT) 12 and the BJT 14 ) is controlled. The width W1 It can be approximately 1.5 µm to approximately 3.5 µm, e.g. approximately 2.5 µm, but other values ​​are also considered.

[0009] The BJT 100 can be considered two separate BJTs, namely as the BJT 12 and the BJT 14 , which share a common emitter connection 206 use, be understood as in the circuit diagram of Fig. 3a is shown. However, in some embodiments, the base connection may be 208 of the BJT 12 and the basic connection 210 of the BJT 14 For example, they can be interconnected in a metallization layer to connect the terminals. Similarly, the collector connection can be... 212 of the BJT 12 and the collector connection 214 of the BJT 14 For example, they can be interconnected in a metallization layer to connect the terminals. If the BJT 12 and the BJT 14 be connected to each other, as shown in the circuit diagram of Fig. As shown in 3b, they can be effective as a single BJT. 100 function with a length of approximately 2 · L1.

[0010] Gate structures are used in the active area 310 , 320 , 330 , 340 and 350 via fins or semiconductor strips (fins) 212 ,208 , 206 , 210 or 214 ) positioned above the substrate. In particular, in Fig. 1 four lines a , b , c and d These are referred to as gate structures, but it should be understood that further lines can be used. In some embodiments, a single BJT can contain multiple gates. 15 until 40 Lines of Gates are used, which are about respective fins. 212 , 208 , 206 , 210 and 214 are arranged. In some embodiments, a single BJT can be used. 20 until 30 , 1 until 15 or 40 until 55 Rows of gates are used, and in other embodiments, more than 55 rows of gates can be used. Between the individual gate structures 310 , 320 , 330 , 340 and 350are a respective epitaxial collector area 82 , epitaxial base area 84 , epitaxial emitter region 86 , epitaxial base area 84 and epitaxial collector area 82 These epitaxial regions are similar to the source / drain regions of a FinFET, and they are electrically interconnected to create the corresponding BJT connections.

[0011] Outside the active area, in an inactive area, an STI area is enclosed. 240 (STI: shallow trench isolation) the active area. The STI area 240 extends also between the Finns 212 , 208 , 206 , 210 and 214 and is described in more detail below. Inactive Gates 360The inactive area can contain dummy gates, polysilicon gates, or metal gates. If the gates are metal or polysilicon gates, no metallization reaches the inactive gates. 360 , and they are electrically floating.

[0012] As a reference point, doped trough areas of the substrate are used in Fig. 1. A p-tub 106 is doped with p-doped elements and corresponds to the common emitter terminal of the BJT 100 (the one from the BJT 12 and the BJT 14 (used together). N-bathtubs 108 and 110 are doped with n dopants and correspond to basic connections of the BJT 100 P-bathtubs 112 and 114 are doped with p-doping agents and correspond to collector connections of the BJT 100 The Finns 212 , 208 , 206 , 210 and 214are produced from these doped tub areas (as shown later in other figures and described in more detail with reference to them).

[0013] Generally, similar reference symbols are used in Fig. 1 is used to refer to similar reference symbols in the other figures, unless otherwise indicated. These reference symbols can be used in an intermediate process, so that the designated object can change from one process to another, even if its reference symbol does not change.

[0014] Fig. 1 also shows that the gate structures 320 about the Finn 208 with a distance W2 (Width W2 ) from the gate structures 330 about the Finn 206 are laterally spaced. In some embodiments, the end-to-end distance from the gate structures is... 320 up to the gate structures 330(and from the gate structures 330 up to the gate structures 340 ) approximately 100 nm to approximately 400 nm, e.g., approximately 150 nm. A minimum distance W2 The distance can be at least 100 nm to approximately 120 nm, e.g., approximately 110 nm, to reduce leakage and comply with design constraints. W3 between the gate structures 320 and the gate structures 310 (and between the gate structures 340 and the gate structures 350 ) can range from approximately 200 nm to approximately 500 nm, e.g., approximately 250 nm.

[0015] A specific part of the BJT 100 is indicated by a dashed box 10 defined, for the sake of simplicity as a building element 10 or a BJT 10 can be described as such. This part of the BJT 100is used for the sectional views and perspective drawings shown in the later figures. It should be clear that these representations of the BJT 10 can be used to represent any embodiment corresponding to the embodiments discussed here.

[0016] Fig. Figure 1 also shows sectional views, which are referenced in later figures. These sectional views are labeled in each figure. A sectional view A - A runs along a longitudinal axis of Gates. 310a , 320a , 330a , 340a and 350a (where 310a, for example, is a gate) 310 in line a (represents) and in a direction that is, for example, perpendicular to a direction of the fins 206 , 208 , 210 , 212 and 214A section view B - B is parallel to the section view A - A and runs through the epitaxial collector areas. 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 A section view C-C is perpendicular to the section view A-A and runs along a longitudinal axis of the fins. 206 A section view D-D is parallel to the section view C-C and extends between the epitaxial base regions. 84 and the epitaxial emitter regions 86 along the STI area 240 .

[0017] Fig. Figure 2 shows a perspective view of the BJT 10 (of part of the BJT 100 from Fig. 1). Fig. Figure 2 also shows the cross-sections that are referenced in later figures ( Fig. 10 and Fig. 11, Fig. 15 to Fig. 26 and Fig. 28 to Fig. 40) is referenced. Fig. Figure 2 shows the n-tubs108 and 110 and the p-tubs 106 , 112 and 114 , which have been briefly discussed above. Furthermore, it shows Fig. 2 a deep n-tub 104 as well as the STI area 240 and the Finns 206 , 208 , 210 , 212 and 214 Furthermore, the gate structures 310 , 320 , 330 , 340 and 350 in the lines a , b , c and d as well as the respective corresponding epitaxial collector areas 82 , the epitaxial base region 84 , the epitaxial emitter region 86 , the epitaxial base region 84 and the epitaxial collector area 82 depicted.

[0018] The present invention discloses a manufacturing process for a BJT according to some embodiments. In certain embodiments of the present invention, the BJT can be fabricated on solid silicon substrates. Alternatively, the BJT can be fabricated on a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. Furthermore, in some embodiments, the silicon substrate can comprise other conductive layers or other semiconductor elements, such as transistors, diodes, or the like. However, the embodiments are not limited to these possibilities.

[0019] Fig. Figure 3a shows part of a circuit diagram for the BJT. 100 , which in some embodiments features a pair of p-BJTs with a common emitter. The BJT 12 is connected to the BJT through its emitter 14connected. The base and emitter signals of each of the BJTs can be coupled elsewhere in the circuit. Fig. Figure 3b shows part of a circuit diagram for the BJT. 100 In another embodiment, a pair of p-BJTs with a common emitter, base, and collector is used, and in this embodiment, the pair of BJTs is effectively combined into a single BJT device. While the embodiments shown, which are described in more detail below, do fabricate a pair of BJTs with a common emitter, other arrangements can also be considered and used.

[0020] The Fig. 4 to Fig. Figure 40 shows various representations of intermediate stages of a process for producing a BJT. 10 according to some embodiments. Fig. 4 to Fig. 9, Fig. 12 to Fig. 14 and Fig. 27 are perspective drawings, and the Fig. 10 and Fig. 11, Fig. 15 to Fig. 26 and Fig. 28 to Fig. Figure 40 shows sectional views. While the following description corresponds to the fabrication of a specific arrangement for a p-BJT (pnp-BJT or pBJT), it is clear that the following method can also be used to fabricate variations of the described arrangements, which are likewise within the scope of protection of the embodiments. For example, the number of gate structures, fins, lengths or widths, spacings, polarity (type), dopant concentration, and the like can be adjusted as desired.

[0021] In Fig. 4. A semiconductor substrate is used. 102 provided. In Fig. 4 is part of the semiconductor substrate 102 shown. In some embodiments, the semiconductor substrate 102a crystalline silicon substrate (e.g., a wafer). The semiconductor substrate 102 It can be a p-substrate, that is, the semiconductor substrate. 102 It can be doped with p-type dopants (also known as p-type dopants). The semiconductor substrate 102It can also feature doped wells doped with n- or p-type dopant, resulting in well regions that are either n-doped or p-doped, depending on the design requirements. Generally, a SOI substrate is a layer of semiconductor material fabricated on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor substrate can be 102include: an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenophosphide; or combinations thereof.

[0022] The n-tub 104 is a deep n-tub. The n-tub 104 For example, it is doped with n-doped atoms and is arranged among other troughs that are embedded in the substrate. 102 are manufactured. The n-tub 104 also extends over the underside of the other tubs, which are embedded in the substrate 102 are produced on its surface. The n-tub 104 can be produced by areas of the substrate 102, which are not to be implanted, are masked, and deep implantation of n-doping agents is performed. The n-doping agents can be phosphorus, arsenic, antimony, or the like, or a combination thereof, and they can be in concentrations of 10 or less than 10 19 cm -3 e.g. of about 10 16 cm -3 up to about 10 19 cm -3 , into the n-tub 104 It can be implanted, but other concentrations can also be considered and used.

[0023] The p-tub 106 is doped with p-doping agents and is manufactured in such a way that it extends over a width of a central part of the substrate shown. 102 extends. The n-tub 108 and the n-tub 110 are on both sides of the p-tub 106 manufactured. The p-tub 112 and the p-tub 114 are on both sides of the n-tub 108 or the n-tub110 manufactured. The p-tub 106 serves as a common emitter for a pair of BJTs located in the component 10 (see Fig. 1a) are manufactured. In some embodiments, the collectors and bases of the pair of BJTs can also be interconnected to effectively manufacture a single BJT (see Fig. 1b). The n-tub 108 and the n-tub 110 serve as a respective base for each BJT of the pair of BJTs, and the p-tub 112 and the p-tub 114 serve as a respective collector for each BJT of the pair of BJTs.

[0024] The implantation of dopants into the different tray types can be achieved using a photoresist or other masks (not shown). For example, a photoresist can be placed over the substrate. 102 to be produced. The photoresist is structured to form the p-tub. 106 , the p-tub 112 and the p-tub 114of the substrate 102 to expose the photoresist. The photoresist can be produced by spin coating and can be structured using suitable photolithographic methods. After the photoresist has been structured, it is implanted into the p-well with a p-doping agent. 106 , the p-tub 112 and the p-tub 114 carried out, whereby the photoresist can act as a mask to largely prevent p-doping substances from entering the p-tub. 106 , the p-tub 112 and the p-tub 114 to be implanted. The p-doping agents can be boron, boron fluoride, indium, or the like, and they can be used at a concentration of 10 or less than 10. 19 cm -3 e.g. of about 10 17 cm -3 up to about 10 19 cm -3 , into the area. After implantation, the photoresist can be removed, for example, using a suitable removal procedure.

[0025] After the implantation of the p-tub 106 , the p-tub 112 and the p-tub 114 A photoresist is applied over the substrate. 102 produced. The photoresist is structured to fit the n-tub. 108 and the n-tub 110 of the substrate 102 to expose the photoresist. The photoresist can be produced by spin coating and can be structured using suitable photolithographic methods. After the photoresist has been structured, it is implanted with an n-doping material into the n-well. 108 and the n-tub 110 carried out, whereby the photoresist can act as a mask to largely prevent n-doping substances from entering the p-tub 106 , the p-tub 112 and the p-tub 114 to be implanted. The n-doping agents can be phosphorus, arsenic, antimony, or the like, and they can be present at a concentration of 10 or less.19 cm -3 e.g. of about 10 17 cm -3 up to about 10 19 cm -3 , are implanted into the area. After implantation, the photoresist is removed, for example, using a suitable removal procedure.

[0026] After the implantation of the p-tub 106 , the n-tub 108 , the n-tub 110 , the p-tub 112 and the p-tub 114 A tempering process can be performed to repair implantation damage and activate the implanted p- and n-doping substances.

[0027] In Fig. 5 will form a pad layer 120 and a layer of masks 125 one after the other over the p-tub 106 , the n-tub 108 , the n-tub 110 , the p-tub 112 and the p-tub 114 of the semiconductor substrate 102 manufactured. The pad layer 120It can be a silicon oxide thin film, which is produced, for example, by a thermal oxidation process. The pad layer 120 can act as an adhesive layer between the semiconductor substrate 102 and the mask layer 125 function. The pad layer 120 It can also be used as an etch stop layer when etching the mask layer. 125 function. The mask layer 125 This could, for example, be a silicon nitride layer produced by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The mask layer 125 can be used as a hard mask during subsequent etching processes.

[0028] In Fig. 6 can the mask layer 125 The pad layer is structured using a photolithographic process. 120 due to the structure of the mask layer 125using the mask layer as an etching mask, thereby creating top surfaces of the p-tub 106 , the n-tub 108 , the n-tub 110 , the p-tub 112 and the p-tub 114 of the semiconductor substrate 102 be exposed. The upper surfaces of the p-tub 106 , the n-tub 108 , the n-tub 110 , the p-tub 112 and the p-tub 114 , which are not from the mask layer 125 The covered areas are then etched to create grooves between the fins. 206 , which are from the p-tub 106 to be produced between the Finns 208 , which are from the n-tub 108 to be produced between the Finns 210 , which are from the n-tub 110 to be produced between the Finns 212 , which are from the p-tub 112 are produced, and between the Finns 214 , which are from the p-tub 114to be produced. The number of fins and grooves can vary depending on the design. Etching can be carried out using any suitable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching can be anisotropic. The active region, such as that described above with reference to Fig. As described in section 1, it can also be defined by etching the substrate to create fin ends. 206 , 208 , 210 , 212 and 214 to produce. In some embodiments, the fins can 206 , 208 , 210 , 212 and 214 first manufactured and then, in a later process, cut to a desired length (e.g., the length L1 ) be cut.

[0029] The Finns 206 , 208 , 210 , 212 and 214Fins can be structured using any suitable method. For example, they can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, smaller grid spacings than those achievable with a single direct photolithographic process. For instance, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process. Subsequently, the sacrificial layer is removed, and the remaining spacers can then be used to structure the fins.In some designs, the mask (or other layer) can remain on the fins.

[0030] The height of the semiconductor strips or fins 206 , 208 , 210 , 212 and 214 The fin spacing can be approximately 100 nm to approximately 150 nm, but other values ​​can also be considered and used. 206 , 208 , 210 , 212 and 214 The diameter can range from approximately 20 nm to approximately 36 nm. Each fin can have a width of approximately 5 nm to approximately 12 nm at its narrowest cross-section. The distance between a sidewall of one fin and a sidewall of an adjacent fin can range from approximately 10 nm to approximately 30 nm. Other fin dimensions are also being considered and can be used.

[0031] In Fig. 7 will be over the Finn 206 , 208 , 210 , 212 and 214an insulating material 230 isolated, the trenches between the Finns 206 , 208 , 210 , 212 and 214 fills. The insulating material 230 The insulating material can be an oxide, such as silicon oxide; a nitride, such as silicon nitride; or the like, or a combination thereof, and can be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert the material into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials deposited by a suitable method can also be used. In the illustrated embodiment, the insulating material is 230 Silicon oxide deposited using an FCVD process. After deposition of the insulating material. 230A tempering process can be carried out. In one embodiment, the insulating material is 230 so separated that excess insulating material 230 the Finns 206 , 208 , 210 , 212 and 214 covered. The insulating material 230 Although depicted as a single layer, some embodiments allow for the use of multiple layers. For example, in some embodiments, a coating (not shown) can first be applied along a surface of the substrate. 102 and the Finns 206 , 208 , 210 , 212 and 214 to be produced. Subsequently, a filler material, such as the one discussed above, can be deposited over the coating.

[0032] In Fig. 8. A removal process is used to remove excess insulating material. 230 about the Finn 206 , 208 , 210 ,212 and 214 to remove. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a re-etching process, a combination thereof, or the like, can be performed. The planarization process removes the fins. 206 , 208 , 210 , 212 and 214 exposed, so that the upper surfaces of the fins 206 , 208 , 210 , 212 and 214 and the insulating material 230 They are at the same level after the planarization process is complete. In embodiments where the mask is on the fins 206 , 208 , 210 , 212 and 214 If the remaining material is present, the planarization process can expose or remove the mask, allowing the tops of the mask or fins to be revealed. 206 , 208 , 210 , 212 or 214are at the same level after the completion of the planning process.

[0033] In Fig. 9 the insulating material 230 ( Fig. 6) omitted to avoid STI areas 240 to produce the insulating material 230 is cut out in such a way that the upper parts of the fins 206 , 208 , 210 , 212 and 214 between adjacent STI areas 240 They stand out. Furthermore, the upper surfaces of the STI areas can 240 They can have a flat surface as shown, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI areas 240 They can be produced flat, convex and / or concave by suitable etching. The STI areas 240 can be achieved with a suitable etching process, such as one that is suitable for the insulating material 230 is selective (e.g. the insulating material) 230at a higher speed than the Finnish material 206 , 208 , 210 , 212 and 214 (corrosive), should be avoided. For example, chemical oxide removal can be carried out, e.g., using dilute hydrofluoric acid (dHF acid).

[0034] The procedure, which refers to the Fig. 4 to Fig. The section described in point 9 is merely one example of how the Finns 206 , 208 , 210 , 212 and 214 can be manufactured. In some embodiments, the fins can 206 , 208 , 210 , 212 and 214 They can be produced using an epitaxial growth process. For example, a dielectric layer can be grown over one top surface of the substrate. 102 They can be produced, and trenches can be etched through the dielectric layer to expose the underlying substrate. 102to expose. Homoepitaxial structures can grow epitaxially in the trenches, and the dielectric layer can be recessed so that the homoepitaxial structures protrude from the dielectric layer and form the fins. 206 , 208 , 210 , 212 and 214 form. Furthermore, in other embodiments, heteroepitaxial structures for the fins can be used. 206 , 208 , 210 , 212 and 214 can be used. For example, the Finns can 206 , 208 , 210 , 212 and 214 in Fig. 6 are left out, and a material different from that of the Finns. 206 , 208 , 210 , 212 and 214 The difference can be seen via the recessed fin. 206 , 208 , 210 , 212 and 214 They are grown epitaxially. In these embodiments, the fins exhibit 206 ,208 , 210 , 212 and 214 The recessed material and the epitaxially grown material located above the recessed material are shown. In a further embodiment, a dielectric layer can be formed over a top surface of the substrate. 102 They can be fabricated, and trenches can be etched through the dielectric layer. Then, heteroepitaxial structures can be created using a material different from that of the substrate. 102 epitaxial growth occurs in the trenches, and the dielectric layer can be left out so that the heteroepitaxial structures protrude from the dielectric layer and form the fins. 206 , 208 , 210 , 212 and 214In some embodiments where homoepitaxial or heteroepitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thus eliminating the need for prior and subsequent implantations, but in-situ implantation and implantation doping can also be used together.

[0035] Furthermore, it can be advantageous to place a material in the n-tub. 108 and the n-tub 110 to grow epitaxially, which is derived from the material of the p-tub 106 , the p-tub 112 and the p-tub 114 It varies. In different designs, the upper parts of the fins can differ. 206 , 208 , 210 , 212 and 214 made from silicon germanium (Si x Ge 1-x, where x can be 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. Materials available for fabricating the III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0036] In some embodiments, the epitaxially grown materials of the fins can 206 , 208 , 210 , 212 and 214 They can be doped in situ during growth, thus eliminating the need for implantation, but in situ implantation and implantation doping can also be used together.

[0037] Regardless of the process used to produce the fins 206 ,208 , 210 , 212 and 214 When used, the fins can be used in some embodiments. 206 , 208 , 210 , 212 and 214 They are also doped in a separate process to increase the doping concentration in the fins. 206 , 208 , 210 , 212 and 214 to increase. In some designs, the upper parts of the fins can be... 206 , 208 , 210 , 212 and 214 optionally with a concentration of further p- or n-doping agents of about 10 19 cm -3 up to about 10 21 cm -3 to be endowed. To protect parts of the Finns 206 , 208 , 210 , 212 and 214Masks can be used while other areas are implanted. Processes and materials similar to those used for manufacturing the tubs described above are employed for this implantation. Fig. 2 have been discussed.

[0038] In Fig. Figure 10 is a sectional view along one of the fins 206 (see Fig. 9, line C - C) according to some embodiments. On the fins 206 , 208 , 210 , 212 and 214 A dielectric gate layer is created 60 manufactured. The dielectric gate layer 60This can be, for example, silicon oxide, silicon nitride, silicon oxide nitride, or a high-k dielectric, a combination thereof, or the like, and can be deposited by suitable methods or thermally grown. Examples of metal oxides used for high-k dielectrics are oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. In one embodiment, the dielectric gate layer is 60 A high-k dielectric layer with a thickness of approximately 0.2 nm to 50 nm. The dielectric gate layer 60 can be produced using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation or UV ozone oxidation.

[0039] Above the dielectric gate layer 60 A gate layer will be created 62 manufactured, and above the gate layer 62will be a mask layer 64 manufactured. The gate layer 62 can be above the dielectric gate layer 60 are separated and then, for example, planarized using a CMP. The mask layer 64 can be above the gate layer 62 be separated. The gate layer 62 The gate layer can be a conductive or non-conductive material selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. 62 The gate layer can be deposited by PVD, CVD, sputtering, or other methods known and used in the field for depositing the chosen material. In some embodiments, the gate layer can be 62 It will be a dummy gate layer that is later replaced in a gate replacement cycle. The gate layer 62It can also be made from other materials that have high etch selectivity through the etching of isolation areas.

[0040] The mask layer 64 This could be, for example, silicon nitride, silicon oxide nitride, or the like. In some embodiments, the dielectric gate layer can be... 60 so isolated that they exclude the STI areas 240 covered, so that they are located between the gate layer 62 and the STI areas 240 extends.

[0041] In Fig. 11 can the mask layer 64 (see Fig. 10) be structured using suitable photolithographic and etching processes to create masks 74 to produce. The structure of the masks 74 can then access the gate layer 62 be transferred to gate electrodes 72 to produce. In some embodiments, the structure of the masks can 74 also on the dielectric gate layer60 are transmitted. The gate electrodes 72 cover the respective canal areas of the Finns 206 , 208 , 210 , 212 and 214 The structure of the masks 74 can be used to connect any of the gate electrodes 72 to physically separate from neighboring gate electrodes, so that gates 330a , 330b , 330c and 330d similar gates are also being produced simultaneously (see Fig. 12). The gate electrodes 72 can have a longitudinal direction that is essentially perpendicular to a longitudinal direction of the respective fins 206 , 208 , 210 , 212 and 214 is.

[0042] Gates 310a until 310d , 320a until 320d , 330.a until 330d , 340a until 340d and 350a until 350denable separation between subsequently produced epitaxial connection areas (see Fig. 14) The quality and uniformity of the epitaxial regions are improved by separating them using the gates. 310a until 310d , 320a until 320d , 330.a until 330d , 340a until 340d and 350a until 350d improved. The production of the Gates 310a until 310d , 320a until 320d , 330.a until 330d , 340a until 340d and 350a until 350d It can also be done using the same processes simultaneously with the fabrication of another component that is not a BJT in a different area of ​​the die. For example, during the fabrication of the component 10The source / drain epitaxy regions, which are produced on both sides of the gates, are connected to each other, but in another component on the same device, these source / drain regions can remain separate and be connected in such a way that they electrically isolate signals, for example when manufacturing a metal oxide semiconductor field-effect transistor (MOSFET) or the like.

[0043] In another embodiment, the gates can be located in each row (see Fig. 12) all are manufactured as a single connected gate. For example, the gates can 310a , 320a , 330a , 340a and 350a a single gate structure that extends across all fins 206 , 208 , 210 , 212 and 214 extends. In another embodiment, the gates can be in each row (see Fig. 12) all are manufactured as a combination of connected gates and separate gates. For example, the gates can be 320a , 330a and 340a as a single gate structure that spans all fins 206 , 208 and 210 extends, while the gates 310a and 350a as separate gates can be manufactured, as in Fig. Figure 12 shows that in these embodiments the gates can be separated in a gate-cutting process, which is described later with reference to the Fig. 27 and Fig. 28 is described.

[0044] Furthermore, in Fig. 11 Gate seal spacers 76 on exposed surfaces of the gate electrodes 72 , the masks 74 and / or the Finns 206 , 208 , 210 , 212 and 214 They are manufactured. The gate seal spacers 76They can be produced by thermal oxidation or by deposition followed by anisotropic etching. The gate sealing spacers 76 can be made from silicon oxide, silicon nitride, silicon oxide nitride or the like.

[0045] Furthermore, in Fig. 11 Gate spacers 78 on the gate seal spacers 76 along the side walls of the gate electrodes 72 and the masks 74 manufactured. The gate spacers 78 They can be manufactured by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material of the gate spacers 78 It could be silicon oxide, silicon nitride, silicon oxide nitride, silicon carbonitride, a combination thereof, or the like.

[0046] Fig. Figure 12 is a perspective view showing the individual gates 310a until 310d ,320a until 320d , 330.a until 330d , 340a until 340d and 350a until 350d shows the respective groups of Finns 206 , 208 , 210 , 212 and 214 be manufactured. Fig. 12 shows lines a until d the Gates 310 , 320 , 330 , 340 and 350 However, it should be clear that additional lines can be used. In some embodiments, for example, for a single BJT 15 until 40 Lines of Gates are used, which are about respective fins. 206 , 208 , 210 , 212 and 214 are arranged. In some embodiments, for a single BJT 20 until 30Lines, 1 to 15 lines or 40 to 55 lines of gates are used, and in other embodiments more than 55 lines of gates can be used.

[0047] In some designs, the gates can be connected via the emitter and base signal lines (which, for example, connect the fins). 206 , 208 and 210 (correspond) are provided as a single, coherent gate, so that, for example, the gates 320a , 330a and 340a to be manufactured as a single structure. By separating the gate 320a above the base of the gate 330a However, the voltage response is improved by applying a minimum distance between the gate ends of the base gate and the emitter gate (e.g., the gate). 320a and the gate 330a) Leakage loss is reduced, and the stress behavior is also improved. These distances will be discussed later with reference to Fig. 15 discussed in more detail.

[0048] In Fig. 13 cutouts will be made in the fins 206 , 208 , 210 , 212 and 214 between the gate structures in the lines a until d The recesses can be created by etching the fins. 206 , 208 , 210 , 212 and 214 can be generated. In some embodiments, the fins can 206 , 208 , 210 , 212 and 214 They are etched in such a way that their top surface, after etching, is beneath a top surface of the STI area. 240 is located (as shown). In other embodiments, the fins can be 206 , 208 , 210 , 212 and 214 They are etched in such a way that their top surface still covers the top surface of the STI area after etching. 240 survives. The Gates 310 , 320 , 330 , 340 and350 in the lines a until d protect a part of the Finns 206 , 208 , 210 , 212 and 214 during the recessing process, creating channel areas 206a until 206d , 208a until 208d , 210a until 210d , 212a until 212d and 214a until 214d These canal sections are created. 206a until 206d , 208a until 208d , 210a until 210d , 212a until 212d and 214a until 214d provide a contact point between the gates and the collectors, emitters and bases of the BJT.

[0049] In Fig. 14 epitaxial collector areas 82 , epitaxial base areas 84 and epitaxial emitter regions 86 in the recesses and over the fins 206 , 208 , 210 , 212 and 214manufactured. The epitaxial collector areas 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 are thus in the Finns 206 , 208 , 210 , 212 and 214 manufactured so that each of the gates 310a until 310d , 320a until 320d , 330a until 330d , 340a until 340d and 350a until 350d between respective adjacent pairs of epitaxial collector areas 82 , epitaxial basal areas 84 and epitaxial emitter regions 86 is arranged. In some embodiments, the gate spacers are 78 to separate the epitaxial collector areas 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 from the gate electrodes 72by using a corresponding lateral distance, so that the epitaxial collector areas 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 no short circuit with the gate electrodes 72 or a subsequently manufactured replacement gate of the resulting BJTs.

[0050] In some embodiments, the epitaxial collector areas 82 and the epitaxial emitter regions 86 produced in a first epitaxial process, since they have the same conductivity type, and the epitaxial base areas 84 They are produced in a second epitaxy process because they have the opposite conductivity type, but either the first or the second epitaxy process can be performed first.

[0051] When creating the epitaxial collector areas 82 and the epitaxial emitter regions 86A mask can be fabricated and structured over the structure to define the areas where the epitaxial collector areas are located. 82 and the epitaxial emitter regions 86 should not be produced, such as the area of ​​the epitaxial base regions. 84 to protect the epitaxial collector areas. 82 and the epitaxial emitter regions 86 can then be selectively grown by the fins. The epitaxial collector areas 82 can be from the Finns 212 and 214 grown up, and the epitaxial emitter regions 86 can be from the Finns 206 They are grown up. In some embodiments, the epitaxial collector areas exhibit 82 and the epitaxial emitter regions 86Silicon germanium (SiGe) is grown epitaxially using a CVD process, and these can be doped in situ with a p-doped element during the epitaxial growth process. In some embodiments, the epitaxial collector regions can be 82 and the epitaxial emitter regions 86 Subsequently, or alternatively, they can be doped with a p-doped molecule via an implantation process. The p-doped molecule for the epitaxial collector regions 82 and the epitaxial emitter regions 86 can be one of the p-doping substances (or p-doping agents) discussed above.

[0052] When creating the epitaxial base areas 84 A mask can be created and structured over the structure to define the areas where the epitaxial base regions are located. 84 should not be manufactured, such as the area of ​​the epitaxial collector areas. 82 and the epitaxial emitter regions 86to protect the epitaxial base areas. 84 can then be selectively selected by the Finns 208 and 210 are grown up. In some embodiments, the epitaxial base regions are 84 Epitaxially grown silicon (Si), silicon phosphide (SiP), or silicon carbide (SiC) is grown epitaxially using a CVD process, and it can be doped in situ with an n-doping agent during the epitaxial growth process. In some embodiments, the epitaxial base regions can be 84 subsequently or instead, they can be doped with an n-doped implantation process. The n-doped implant is for the epitaxial base regions. 84 can be one of the n-doping substances (or n-doping agents) discussed above.

[0053] Through the epitaxial processes that produce the epitaxial collector areas 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86When used, the upper surfaces of these epitaxial areas have chamfers that extend laterally outwards over the sidewalls of the fins. 206 , 208 , 210 , 212 and 214 extend beyond. In some embodiments, these chamfers result in adjacent epitaxial areas of the epitaxial collector areas. 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 merge, as it says in Fig. Figure 14 shows that in other embodiments, adjacent epitaxial structures may remain separated after the epitaxial growth process.

[0054] After the growth of the epitaxial collector areas 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 The p- and n-dopeds in the epitaxial regions can each have a concentration of about 10 19 cm -3 up to about 10 21 cm-3 have. After the growth of the epitaxial collector areas 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 Tempering can be carried out in one or more tempering processes to activate the dopants.

[0055] The Finns 212 and the epitaxial collector area arranged thereon 82 , the Finns 208 and the epitaxial base region arranged thereon 84 and the Finns 206 and the epitaxial emitter region arranged thereon 86 form a first lateral pnp-BJT 12 (see also Fig. 3a). These epitaxial regions can each be used for a number n of rows of gates (e.g., 310 gates). 1-n , 320 1-n and 330 1-n ) are connected together to adjust the length of the pnp-BJT 12, so that a lateral pnp-BJT 12 with a desired length is created.

[0056] The Finns 214and the epitaxial collector area arranged thereon 82 , the Finns 210 and the epitaxial base region arranged thereon 84 and the Finns 206 and the epitaxial emitter region arranged thereon 86 form a second lateral pnp-BJT 14 (see also Fig. 3b). These epitaxial regions can each be used for a number m of rows of gates (e.g., 350 gates). 1-m , 340 1-m and 330 1-m ) are interconnected to create a lateral PNP-BJT 14 of a desired length. As in Fig. As shown in Figure 3a, the first lateral pnp-BJT 12 and the second lateral pnp-BJT 14 are separated by a common epitaxial emitter region. 86 connected. As in Fig. As shown in 3b, the first lateral pnp-BJT 12 and the second lateral pnp-BJT .14 can also be connected epitaxial base areas. 84 and associated epitaxial collector areas 82 have.

[0057] Through the epitaxial growth processes that produce the epitaxial collector areas 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 When used, the upper surfaces of these epitaxial areas have chamfers that extend laterally outwards over the sidewalls of the fins. 206 , 208 , 210 , 212 and 214 extend beyond. In some embodiments, these chamfers can cause adjacent epitaxial areas of the epitaxial collector areas to 82 , the epitaxial base areas 84 and the epitaxial emitter regions 86 each merge, as it says in Fig. Figure 14 shows that in other embodiments, adjacent epitaxial structures can be separated after the epitaxial growth process ( d . i.e. remain unfused).

[0058] The Fig. 15, Fig. 19, Fig. 23, Fig. 28, Fig. 29, Fig. 33 and Fig. 37 are along cross-section A - A (see Fig. 2) shown. The Fig. 16, Fig. 20, Fig. 24, Fig. 30, Fig. 34 and Fig. 38 are along cross-section B - B (see Fig. 2) shown. The Fig. 17, Fig. 21, Fig. 25, Fig. 31, Fig. 35 and Fig. 39 are along cross-section C - C (see Fig. 2) shown. The Fig. 18, Fig. 22, Fig. 26, Fig. 32, Fig. 36 and Fig. 40 are along the cross-section D - D (see Fig. 2) shown.

[0059] The Fig. 15, Fig. 16, Fig. 17 and Fig. Figure 18 shows sectional views of the component. 10 from Fig. 14. These descriptions provide further details on the processes described above. As in Fig. As shown in 15, the distance can be W2 between the ends of the gate 320 above the BJT base and the gate 330 The distance above the BJT emitter is approximately 100 nm to approximately 400 nm, e.g., approximately 150 nm. The minimum distance W2 The distance W3 between the ends of the gate should be at least 100 nm to approximately 120 nm, e.g., approximately 110 nm, to reduce leakage and comply with design constraints. 320 above the BJT base and the gate 310 The wavelength above the BJT collector can be approximately 200 nm to approximately 500 nm, e.g., approximately 250 nm. A width W4 of the p-trough 106 The emitter's width can range from approximately 500 nm to approximately 1000 nm, e.g., approximately 800 nm. Widths W5 and W7 of the n-wells 108 and 110 The widths of the BJT bases can range from approximately 300 nm to approximately 700 nm, e.g., approximately 500 nm. W6 and W8 the p-tubs 112 and 114The wavelengths for the collectors can also be approximately 300 nm to approximately 700 nm, e.g., approximately 500 nm. The deep basin 104 and the p-tub 112 They can overlap with a width W9 of approximately 0 nm to approximately 100 nm, e.g., from approximately 0 nm. A width W10 the deep tub 104 can range from approximately 1500 nm to approximately 2000 nm, e.g., approximately 1800 nm.

[0060] The interface between the p-tub 106 and the n-tub 108 can lead to a gap (which corresponds to the distance) W2 (corresponds) between the gate 320 and the gate 330 to be aligned. A center line c320 designates the center of the gap between the gate. 320 and the gate 330 This boundary surface can have a horizontal distance from the center line c320 of 0% to 30% of the distance. W2in both directions, but other values ​​can also be considered and used. The same applies to the interface between the p-tub. 106 and the n-tub 110 and the gap between the gate 330 and the gate 340 Similarly, the interface between the p-tub can be 112 and the n-tub 108 to a gap (corresponding to the distance W3) between the gate 310 and the gate 320 to be aligned. A center line c310 designates the center of the gap between the gate. 310 and the gate 320 This interface can have a horizontal distance from the center line c310 of 0% to 30% of the distance W3 in either direction, but other values ​​can also be considered and used. The same applies to the interface between the p-tub. 114 and the n-tub 110 and the gap between the gate 340 and the gate350 .

[0061] A distance W11 between the outermost edge of the fins 212a and an edge of the gate 310 The distance can range from approximately 100 nm to approximately 300 nm, e.g., approximately 120 nm. W12 between the outermost edge of the fins 208a and an edge of the gate 320 It can also be approximately 100 nm to approximately 300 nm, e.g., approximately 120 nm. A distance W 13 between the outermost edge of the fins 206a and an edge of the gate 330 It can also be approximately 100 nm to approximately 300 nm, e.g., approximately 120 nm. A ratio of the distance W2 to the distance W12 or the distance W 13 can be 1 to 3. A ratio of the distance W3 to the distance W11The distances and ratios can range from 2 to 5. These distances and ratios are necessary for the BJT to function effectively, but some design deviation from these ranges may be permissible.

[0062] The emitter Finns 206 are from the BJT 12 and the BJT 14 used together. Furthermore, a gap is created between the emitter fins. 206 and the substrate 102 a parasitic vertical BJT through the deep n-tub 104 The number of fins in the emitter area 106 It should therefore be dimensioned in such a way that a mismatch between the parasitic vertical BJT and the lateral BJTs is prevented. 12 and 10 arises. The number of fins in the emitter area 106 can be 3 to 8 times, e.g. 5 times, the number of fins in the collector area 112 and / or the basic area 108 This amounts to an oversizing of the emitter area. 106This leads to a reduced yield, and therefore a balance should be struck between generating the required mismatch and increasing the area / number of emitter fins. 206 in the emitter area 106 can be found.

[0063] In the Fig. 19, Fig. 20, Fig. 21 and Fig. 22 will be a first interlayer dielectric (ILD) 88 isolated above the structure, which is in the Fig. 15 to Fig. 18 is shown. The first ILD 88 is deposited above the structure that is in the Fig. 15 to Fig. 18 is shown. The first ILD 88It can be manufactured from a dielectric material and can be deposited using any suitable process, such as CVD, PECVD, or FCVD. Suitable dielectric materials include PSG, BSG, BPSG, undoped silicate glass (USG), or the like. Other insulating materials deposited using a suitable process can also be used. In some embodiments, a contact etch stop layer (CESL) is incorporated. 87 between the first ILD 88 and the epitaxial collector areas 82 , the epitaxial basal regions 84 and the epitaxial emitter regions 86 , the masks 74 and the gate spacers 78 manufactured. The CESL 87 may contain a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, which has a different etch rate than the material of the first ILD above it. 88 has.

[0064] In the Fig. 23 to Fig. 26. A planarization process, such as a CMP, can be performed to create a top surface of the first ILD. 88 at the same level as the tops of the gate electrodes 72 or the masks 74 to bring about the planarization process, the masks can also be affected. 74 on the gate electrodes 72 as well as parts of the gate seal spacers 76 and the gate spacer 78 along the side walls of the masks 74 can be removed. In some embodiments, the top surfaces of the gate electrodes can be removed after the planarization process. 72 , the gate seal spacer 76 , the gate spacer 78 and the first ILD 88 be at the same level. In these embodiments, the upper surfaces of the gate electrodes are 72 through the first ILD 88 exposed. In some embodiments, the masks can be 74remain, and in this case, the planarization process will affect the top of the first ILD 88 at the same level as the tops of the masks 74 brought.

[0065] In some embodiments, the gate electrodes can 72 These are dummy gate electrodes that can be replaced. In these embodiments, the gate electrodes are 72 and the masks 74 , if present, removed in one or more etching steps. Parts of the dielectric gate layer 60 They can also be removed. In some embodiments, only the gate electrodes are removed. 72 removed, and the dielectric gate layer 60 It remains and is exposed during the etching steps. In some embodiments, the gate electrodes can 72They can be removed using an anisotropic dry etching process. For example, the etching process can be a dry etching process that uses one or more reactive gases that etch the gate electrodes. 72 selectively etch without the first ILD 88 or the gate spacers 78 to etch. Each recess defines a channel area of ​​a respective fin (e.g. 206a , 208a , 210a , 212a and 214a ) free and / or overlaps this. The channel areas 206a until 206d , 208a until 208d , 210a until 210d , 212a until 212d and 214a until 214d are each between adjacent pairs of respective epitaxial collector areas 82 , epitaxial basal areas 84 and epitaxial emitter regions 86 arranged. During removal, the dielectric gate layer can be 60can be used as an etch stop layer when the gate electrodes 72 be etched. The dielectric gate layer 60 can occur after the removal of the gate electrodes 72 can be removed optionally.

[0066] In embodiments where the gate electrodes 72 Dummy gate electrodes are those that can be replaced; the gate electrodes can be replaced. 72 through replacement gate electrodes 72r can be replaced. Similarly, the dielectric gate layer can be replaced. 60 through a dielectric replacement gate layer 60r be replaced. The dielectric replacement gate layers 60r are deposited conformally in the recesses (from which the dummy gate has been removed), e.g. on the tops and side walls of the fins (e.g. 206a , 20.8a, 210a , 212a and 214a ) and on the side walls of the gate seal spacers 76 / the gate spacer 78The dielectric replacement gate layers 60r can also be located on the top side of the first ILD 88 are manufactured. In some embodiments, the dielectric replacement gate layers exhibit 60r silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the dielectric replacement gate layers have 60r a dielectric high-k material, and in these embodiments the dielectric replacement gate layers can 60r They have a k-value greater than approximately 7.0 and can contain a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. As a manufacturing process for the dielectric replacement gate layers 60r Molecular beam deposition (MBD), ALD, PECVD, and similar techniques can be used. In embodiments where parts of the dielectric gate layers are 60The dielectric replacement gate layers remain in the recesses. 60r a material of the dielectric gate layers 60 (e.g. SiO2).

[0067] The replacement gate electrodes 72r are each above the dielectric replacement gate layers 60r separated and fill the remaining parts of the recesses. The replacement gate electrodes 72r They may contain polysilicon or a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, or tungsten, or combinations thereof or multilayers thereof. The replacement gate electrodes 72r They can have any number of cover layers, any number of exit work adjustment layers, and a filler material. After the cavities are filled, a planarization process, such as CMP, can be performed to level the surface above the ILD. 88excess parts of the dielectric replacement gate layers are located 60r and the material of the replacement gate electrodes 72r to remove. The remaining parts of the replacement gate electrode material. 72r and the dielectric replacement gate layers 60r These thus form the replacement gates. The replacement gate electrodes 72r and the dielectric replacement gate layers 60r These can be collectively referred to as a "gate stack". The gates and gate stacks can be arranged along the side walls of the channel areas. 206a until 206d , 208a until 208d , 210a until 210d , 212a until 212d and 214a until 214d extend.

[0068] In some embodiments, the gate stack (which is a dielectric substitute gate layer) 60r and a corresponding replacement gate electrode located above it 72r(includes) recessed, so that a recess is created directly above the gate stack and between opposing parts of the gate spacers. 78 A replacement gate mask is created. 74r filled, which has one or more layers of dielectric material, such as silicon nitride, silicon oxide nitride or the like, and this is followed by a planarization process to remove excess parts of the dielectric material that are located above the first ILD 88 are located. In other embodiments, the mask can be 74 from a previous process in which the gate electrodes 72 Those that have not been replaced will remain in place.

[0069] In Fig. 27 can be in an embodiment in which the gate structures 310 , 320 , 330 , 340 and 350 in each line a until d as a coherent gate structure 310 until350 are produced that cover all Finns 206 , 208 , 210 , 212 and 214 This extends to a gate cutting process that can be performed before or after the gate replacement process (if used). Above the ILD 88 and a mask can be applied over the top surfaces of the single contiguous gate structure. 91 be separated. The mask 91 It is then structured using suitable photolithographic processes to create openings. 93 and / or openings 92 to generate parts of the connected gate structure 310 until 350 to expose the openings, which are then removed and replaced with insulating material. 92 represent a long section through several gate structures, and the openings 93 represent a cross-section through each individual gate structure. A combination of methods can be used, in which the openings 92(which extend across multiple gate structures) and / or the openings 93 (which extend across individual gate structures) can be used. With a series of etching steps, the gate material or the dummy gate material of the exposed parts of the contiguous gate structure can be used. 310 until 350 to be removed. After the gate material is removed, the contiguous gate structure is revealed. 310 until 350 into their parts 310 , 320 , 330 , 340 and 350 separated, as for example in Fig. 28 is shown.

[0070] In Fig. 28 openings 92 and / or the openings 93 from the gate cutting process using suitable methods with an insulating material 94 to be filled. In some designs, the insulating material can be 94It can be a dielectric material, such as silicon oxide, silicon nitride, PSG, BSG, BPSG, USG, or the like, and can be deposited using a suitable process such as CVD or PECVD. In these embodiments, the etch stop layer 87 , the gate seal spacer 76 and the gate spacer 78 not at the ends of the gate structures 310 , 320 , 330 , 340 and 350 produced, which are separated (compare Fig. 27). In other words, the insulating material 94 can the ends of the separated gate structures 310 , 320 , 330 , 340 and 350 Contact us. After filling the openings 92 and / or the openings 93 will the mask 91 removed through a planarization process.

[0071] In some embodiments, some of the gates can be separated using the gate cutting process, while other gates can be separated using the masking processes described above (see Fig. 8 to Fig. 10 and the associated description) can be manufactured as separate gates. For example, the gates can 310 and 350 as separate gate structures, while the gates 320 , 330 and 340 can be manufactured as a continuous gate structure that is later separated.

[0072] In the Fig. 29 to Fig. 32 will become a second ILD 98 above the first ILD 88 isolated. In some embodiments, the second ILD is 98 a flowable layer produced by flowable CVD (FCVD). In some embodiments, the second ILD 98It is made from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited using a suitable process such as CVD or PECVD. The gate contacts produced later 110 ( Fig. 33 to Fig. 36) penetrate the gate mask 74 / 74r , to the top of the recessed gate electrode 72 / 72r to contact.

[0073] In the Fig. 33 to Fig. 36. In some embodiments, gate contacts are used. 412 , 414 , 416 , 418 and 420 and connecting contacts 422 , 424 , 426 , 428 and 430 through the second ILD 98 and the first ILD 88 produced. Through the first and second ILD 88 and 98 Openings will be made for the connection contacts. 422 , 424 , 426 , 428 and 430generated, and by the second ILD 98 and the gate mask 74 Openings will be made for the gate contacts. 412 , 414 , 416 , 418 and 420 The openings can be created using suitable photolithographic and etching processes. A coating, such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are deposited within the openings. The coating can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from one surface of the second ILD. 98 to remove. The remaining coating and conductive material form the connection contacts. 422 , 424 , 426 , 428 and 430and the gate contacts 412 , 414 , 416 , 418 and 420 in the openings. Subsequently, a tempering process can be carried out to apply a silicide to the interface between the epitaxial collector areas. 82 , the epitaxial basal regions 84 and the epitaxial emitter regions 86 and to generate their respective connection contacts. The connection contacts 422 and 430 are physically and electrically connected to respective epitaxial collector areas 82 connected, the connecting contacts 424 and 428 are physically and electrically connected with respective epitaxial base regions 84 connected, and the connecting contact 426 is physically and electrically connected to the epitaxial emitter region 86 connected. The gate contacts 412 , 414 , 416 , 418 and 420 are physically and electrically connected to the gate electrodes72 / 72r the respective gates 310 , 320 , 330 , 340 and 350 connected. The connection contacts 422 , 424 , 426 , 428 and 430 and the gate contacts 412 , 414 , 416 , 418 and 420 They can be produced in different processes or in the same process. For example, in Fig. 35 showed that the connecting contacts 422 , 424 , 426 , 428 and 430 and the gate contacts 412 , 414 , 416 , 418 and 420 They can each be manufactured with the same cross-section, but it should be understood that they can be manufactured with different cross-sections so that short-circuiting of the contacts can be avoided.

[0074] In the Fig. 37 to Fig. 40 can be a metallization layer that forms a third ILD 508 and connecting elements 512 , 514 , 516 , 518 and 520 includes, above the second ILD 98 to be manufactured. In some embodiments, the third ILD 508 a flowable layer produced by flowable CVD. In some embodiments, the third ILD 508 It is made from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited using a suitable process such as CVD or PECVD. In some embodiments, the connecting elements 512 , 514 , 516 , 518 and 520 each of the gate contacts 412 , 414 , 416 , 418 and 420 together. In other words, a connecting element 512 It could, for example, be a metal wire that connects all the gate contacts. 412electrically interconnects the gate electrodes 72 / 72r the Gates 310a until 310d contact. Similarly, a connecting element can 514 all gate contacts 414 electrically connect together, a connecting element 516 can all gate contacts 416 electrically connect together, a connecting element 518 can all gate contacts 418 electrically connect them, and a connecting element 520 can all gate contacts 420 Electrically connect them together. In some embodiments, the connecting elements can be 512 , 514 , 516 , 518 and 520 each comprise several conductive structural elements, such as multiple metal conductors, to form gates of a single group, such as the gates 330a until 330d , to connect together.

[0075] In some embodiments, the connecting elements512 , 514 , 516 , 518 and 520 each of the connecting contacts 422 , 424 , 426 , 428 and 430 together. Therefore, in some embodiments, the connecting elements can 512 , 514 , 516 , 518 and 520 each of the gate contacts 412 with the connection contacts 422 , the gate contacts 414 with the connection contacts 424 , the gate contacts 416 with the connection contacts 426 , the gate contacts 418 with the connection contacts 428 and the gate contacts 420 with the connection contacts 430 electrically connect. In other words, the gate electrode 72 / 72r for each gate 310 until 350 can be used with their adjacent epitaxial area for the epitaxial collector areas 82 , the epitaxial base areas 84and the epitaxial emitter regions 86 can be connected. For example, the connecting elements can 512 the gate contacts 412 with the connection contacts 422 interconnecting, thereby connecting the epitaxial collector areas 82 on the Finns 212 with the gate electrodes 72 / 72r of the gate 310 can be interconnected. Similarly, the connecting elements can be 514 the epitaxial base areas 84 on the Finns 208 with the gate electrodes 72 / 72r of the gate 320 connect the connecting elements 516 can the epitaxial emitter regions 86 on the Finns 206 with the gate electrodes 72 / 72r of the gate 330 connect the connecting elements 518 can the epitaxial base areas 84 on the Finns 210 with the gate electrodes 72 / 72r of the gate 340 connect them, and the connecting elements 520 can the epitaxial collector areas 82 on the Finns 214 with the gate electrodes 72 / 72r of the gate 350 connect them together.

[0076] Through the third ILD 508 Openings will be made for the connecting elements 512 , 514 , 516 , 518 and 520 The openings can be created using suitable photolithographic and etching processes, so that the top surfaces of the gate contacts are visible. 412 , 414 , 416 , 418 and 420 and top sides of the connection contacts 422 , 424 , 426 , 428 and 430 (for the connecting elements) 512 , 514 , 516 , 518 or 520) are exposed. A coating, such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are deposited in the openings. The coating can consist of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material for the connecting elements 512 , 514 , 516 , 518 and 520 It could be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from a surface of the third ILD. 508 to remove. The remaining coating and the remaining conductive material form the connecting elements. 512 , 514 , 516 , 518 and 520 in the openings.

[0077] In some embodiments, the connecting elements 512 , 514 , 516 , 518 and520 Each one or more metal leads are connected to the gate contacts. 412 , 414 , 416 , 418 and 420 are connected and comprise one or more metal conductors that are individually connected to the terminal contacts. 422 , 424 , 426 , 428 and 430 are connected, so that one or more of the gate contacts 412 and the connecting contacts 422 , the gate contacts 414 and the connecting contacts 424 , the gate contacts 416 and the connecting contacts 426 , the gate contacts 418 and the connecting contacts 428 as well as the gate contacts 420 and the connecting contacts 430 are not interconnected.

[0078] In some embodiments, further insulating layers (e.g., ILDs) can be produced, and metallization layers can be produced therein, for each of which processes and materials can be used that are similar to those described above for the connecting elements. 512 , 514 , 516 , 518 and 520 or for the gate contacts 412 , 414 , 416 , 418 and 420 or for the connection contacts 422 , 424 , 426 , 428 and 430 have been described, but other suitable methods can also be used. In some embodiments, such as those which Fig. 3b, these metallization layers can be used as connecting elements 512 interconnect so that all epitaxial collector areas 82They can be electrically connected. Furthermore, the metallization layers can act as connecting elements. 514 interconnect so that all epitaxial base regions 84 be electrically interconnected.

[0079] Fig. Figure 41 shows a top-down view of a matrix of BJT devices according to some embodiments. Fig. 41 are several BJT components 100 (see Fig. 1) arranged in a 5×5 matrix, 1000 lines. Dashed lines 1010 These are boundary lines between the BJT components. 100 In some embodiments, the dashed lines correspond to 1010 Ritz trenches, along which some or all BJT building elements 100 can be separated into smaller packages. Between the active area (defined by L1 and W1, which were mentioned above with reference to Fig. 1 have been explained) of a BJT component 100 and an adjacent BJT component 100are inactive areas 1020 arranged. A distance L2 The distance between active areas in a direction parallel to the direction of the fins can be approximately 200 nm to approximately 2000 nm, but other dimensions can also be considered and used. In some embodiments, the distance can be L2 by leaving a number of gates inactive 360 The number of active areas is determined. For example, the number of inactive gates is... 360 between active areas, as in the matrix 1000 The diagram shows two, but in other designs the number of inactive gates can range from one to ten or more. The spacing W14 The distance between active areas in the direction parallel to the longitudinal direction of the gates can be approximately 120 nm to approximately 1500 nm, but other dimensions can also be considered and used.

[0080] Separating the gates 320from the Gates 330 leads to an increase in BJT 100 , to increase the distance between the gates 320 and the Gates 330 to take this into account. By ordering the BJT 100 in a matrix, such as the matrix 1000 However, the overall effect of the magnification is reduced. For example, the area for the BJT decreases. 100 in exemplary components by about 10% to about 20%, e.g. by about 15%, but the area that is in a BJT matrix, such as the matrix 1000 The effect, as demonstrated, increases only by approximately 5% to 15%, e.g., by approximately 6%, compared to components manufactured using similar structuring methods but without separate gates. The effect can also be reduced by using a gate-cutting process, such as the gate-cutting process described in the Fig. 27 and Fig. 28 has been discussed.

[0081] In some embodiments, FinFET processes are advantageously used to fabricate a BJT device. In some embodiments, separate gates are used across the BJT terminals, such as separate gates across the BJT base and the BJT emitter. Separating the gates can reduce ΔV despite the resulting increase in the gate size. be be realized. ΔV be represents a difference in voltage between the base and the emitter, measured due to differing currents at the emitter terminal. In some embodiments, a ΔV is used. be with a 50% reduction of the first sigma value of a standard deviation of ΔV be This is achieved by providing a more constant ΔV. be A ΔV that is 50% higher will be achieved. be-performance is maintained. While separating the gates via the emitter and base signal lines of the BJTs does increase the area, the device performance increases so significantly that the disadvantage of the lost device area is worth the performance and reliability gains.

[0082] One embodiment relates to a device with a first group of fins having a first base region doped with a p-type dopant, wherein an emitter of a bipolar junction transistor (BJT) is arranged above the first group of fins. The device further comprises a second group of fins having a second base region doped with an n-type dopant, wherein the second base region contacts the first base region and a base of the BJT is arranged above the second group of fins. The device further comprises a third group of fins having a third base region doped with a p-type dopant, wherein a collector of the BJT is arranged above the third group of fins. The device further comprises a first gate structure arranged above the first group of fins adjacent to the emitter.The device further comprises a second gate structure arranged above the second group of fins adjacent to the base. The device further comprises a third gate structure arranged above the third group of fins adjacent to the collector, wherein the first gate structure, the second gate structure, and the third gate structure are physically and electrically separated. In one embodiment, a minimum distance between a first end of the first gate structure and a first end of the second gate structure is at least 100 nm, the minimum distance being measured in one direction along a longitudinal direction of the first gate structure.In one embodiment, the device further comprises: a fourth gate structure arranged above a fourth group of fins adjacent to the first group of fins, the fourth group of fins corresponding to a base of a second BJT; and a fifth gate structure arranged above a fifth group of fins adjacent to the fourth group of fins, the fifth group of fins corresponding to a collector of the second BJT. In one embodiment, the emitter of the BJT is also the emitter of the second BJT. In one embodiment, the number of fins in the first group of fins is at least twice the number of fins in the second group of fins. In one embodiment, the first gate structure comprises a gate electrode, the gate electrode being electrically connected to the first group of fins.In one embodiment, a first distance is measured between the first gate structure and the second gate structure, and a second distance is measured between an outer edge of the first group of fins and the nearest outer edge of the first gate structure, wherein the ratio of the first distance to the second distance is between one and four. In one embodiment, the emitter is arranged on opposite sides of the first gate structure, the base is arranged on opposite sides of the second gate structure, and the collector is arranged on opposite sides of the third gate structure. In one embodiment, the height of the first group of fins below the emitter is less than the height of the first group of fins below the first gate structure.

[0083] Another embodiment relates to a device with a first fin, a second fin, and a third fin projecting from a substrate, wherein the first and third fins have a first conductivity, the second fin has a second conductivity opposite to the first, and the first, second, and third fins are parallel to each other. The device further comprises a gate structure arranged above and along the side walls of the first, second, and third fins. The device further comprises an emitter of a bipolar junction transistor (BJT) arranged on opposite sides of the gate structure above the first fin. The device further comprises a base of the BJT arranged on opposite sides of the gate structure above the second fin.The device further comprises a BJT collector located on opposite sides of the gate structure above the third fin. The device also includes an insulating material that completely encloses a first part of the gate structure located above the first fin, a second part of the gate structure located above the second fin, and a third part of the gate structure located above the third fin. In one embodiment, the distance between adjacent ends of the first part of the gate structure and the second part of the gate structure is at least 100 nm.In some embodiments, the gate structure is a first gate structure, and the device may have a plurality of gate structures, each arranged over and along sidewalls of the first fin, the second fin, and the third fin, with each of the plurality of gate structures being subdivided into a first part, a second part, and a third part, which are completely enclosed by the insulating material and are each arranged over the first fin, the second fin, and the third fin, respectively. In one embodiment, the emitter of the BJT is also the emitter of the second BJT. In one embodiment, the first conductance corresponds to a p-type dopant, while the second conductance corresponds to an n-type dopant. In one embodiment, the emitter of the BJT is electrically connected to a gate electrode of the gate structure.

[0084] Another embodiment relates to a method comprising structuring a first doped well of a semiconductor substrate for producing first fins, a second doped well of the semiconductor substrate for producing second fins, and a third doped well of the semiconductor substrate for producing third fins. The method further comprises fabricating a gate structure across and along the sidewalls of the first fins, the second fins, and the third fins.The method further comprises epitaxial growth of a first epitaxial layer of a bipolar junction transistor (BJT) over the first fins on opposite sides of the gate structure, a second epitaxial layer of the BJT over the second fins on opposite sides of the gate structure, and a third epitaxial layer of the BJT over the third fins on opposite sides of the gate structure, wherein the first epitaxial layer and the third epitaxial layer have a first conductivity, the second epitaxial layer has a second conductivity that is opposite to the first conductivity, wherein the gate structure has a first part, a second part, and a third part, wherein the first, second, and third parts are electrically separated from each other, with the first part being arranged over the first fins, the second part being arranged over the second fins, and the third part being arranged over the third fins.In one embodiment, the fabrication of the gate structure may include: depositing a dielectric gate layer over the first fins, the second fins, and the third fins; depositing a gate electrode layer over the first fins, the second fins, and the third fins; and structuring the gate electrode layer and the dielectric gate layer to fabricate the first part of the gate structure, the second part of the gate structure, and the third part of the gate structure.In one embodiment, the method may further comprise: depositing a first interlayer dielectric (ILD) over the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer; separating the gate structure to divide it into the first gate structure part, the second gate structure part, and the third gate structure part; and depositing an insulating material between adjacent ends of the first part and the second part, and between adjacent ends of the second part and the third part. In one embodiment, the sectional width between adjacent ends of the first and second parts of the gate structure is approximately 100 nm to approximately 400 nm.In one embodiment, the method may further comprise: depositing an insulating material over and between the first fins, the second fins, and the third fins; recessing the insulating material such that the first, second, and third fins each protrude from a top surface of the insulating material; and epitaxially growing the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer between portions of the insulating material. In one embodiment, the first conductivity corresponds to a p-type dopant, while the second conductivity corresponds to an n-type dopant. In another embodiment, the method may further comprise producing a metallization layer over the gate structure, wherein the metallization layer electrically connects the first epitaxial layer to a gate of the gate structure.In one embodiment, the method may further include performing a gate replacement process to remove a gate electrode from the gate structure and replace the gate electrode with a metal replacement gate.

[0085] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. It should be clear to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent designs do not deviate from the fundamental concept and scope of protection of the present invention and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present invention.

Claims

[1] Device with: a first group of fins having a first base region doped with a p-doped element, wherein an emitter of a bipolar junction transistor (BJT) is positioned above the first group of fins; a second group of fins having a second base area doped with an n-doped atom, wherein the second base area contacts the first base area and a base of the BJT is arranged above the second group of fins; a third group of fins having a third base area doped with a p-doped element, with a collector of the BJT positioned above the third group of fins; a first gate structure located above the first group of fins adjacent to the emitter; a second gate structure, arranged above the second group of fins adjacent to the base; and a third gate structure located above the third group of fins adjacent to the collector, wherein the first gate structure, the second gate structure and the third gate structure are physically and electrically separated. [2] Device according to claim 1, wherein a minimum distance between a first end of the first gate structure and a first end of the second gate structure is at least 100 nm, wherein the minimum distance is measured in a direction along a longitudinal direction of the first gate structure. [3] Device according to claim 1 or 2, further comprising: a fourth gate structure arranged above a fourth group of fins adjacent to the first group of fins, the fourth group of fins corresponding to a base of a second BJT; and a fifth gate structure arranged above a fifth group of fins adjacent to the fourth group of fins, the fifth group of fins corresponding to a collector of the second BJT. [4] Device according to claim 3, wherein the emitter of the BJT is also the emitter of the second BJT. [5] Device according to one of the preceding claims, wherein the first gate structure comprises a gate electrode, wherein the gate electrode is electrically connected to the first group of fins. [6] Device according to one of the preceding claims, wherein there is a first distance between the first gate structure and the second gate structure and a second distance between an outer edge of the first group of fins and a nearest outer edge of the first gate structure, wherein the ratio of the first distance to the second distance is one to four. [7] Device according to one of the preceding claims, wherein the emitter is arranged on opposite sides of the first gate structure, the base is arranged on opposite sides of the second gate structure and the collector is arranged on opposite sides of the third gate structure. [8] Device according to one of the preceding claims, wherein the height of the first group of fins below the emitter is less than the height of the first group of fins below the first gate structure. [9] Device with: a first fin, a second fin and a third fin projecting from a substrate, wherein the first fin and the third fin have a first conductivity, the second fin has a second conductivity opposite to the first conductivity, and the first, the second and the third fin are each parallel to each other; a gate structure arranged above and along the side walls of the first fin, the second fin and the third fin; an emitter of a bipolar junction transistor (BJT) located on opposite sides of the gate structure above the first fin; a base of the BJT, which is located on opposite sides of the gate structure above the second fin; a collector of the BJT, which is arranged on opposite sides of the gate structure above the third fin; and an insulating material that completely encloses a first part of the gate structure arranged above the first fin, a second part of the gate structure arranged above the second fin, and a third part of the gate structure arranged above the third fin. [10] Device according to claim 9, wherein the distance between adjacent ends of the first part of the gate structure and the second part of the gate structure is at least 100 nm. [11] Device according to claim 9 or 10, wherein the gate structure is a first gate structure and the device further comprises a plurality of gate structures, each arranged over and along side walls of the first fin, the second fin and the third fin, each of the plurality of gate structures being divided into a first part, a second part and a third part, which are completely enclosed by the insulating material and are arranged over the first fin, the second fin and the third fin respectively. [12] Device according to any one of claims 9 to 11, wherein the emitter of the BJT is also the emitter of the second BJT. [13] Device according to one of claims 9 to 11, wherein the emitter of the BJT is electrically connected to a gate electrode of the gate structure. [14] Procedure with the following steps: Structuring a first doped well of a semiconductor substrate to produce first fins, a second doped well of the semiconductor substrate to produce second fins, and a third doped well of the semiconductor substrate to produce third fins; Creating a gate structure over and along the side walls of the first fins, the second fins, and the third fins; and epitaxial growth of a first epitaxial layer of a bipolar junction transistor (BJT) over the first fins on opposite sides of the gate structure, a second epitaxial layer of the BJT over the second fins on opposite sides of the gate structure, and a third epitaxial layer of the BJT over the third fins on opposite sides of the gate structure, wherein The first epitaxial layer and the third epitaxial layer have a first conductivity, and the second epitaxial layer has a second conductivity that is opposite to the first conductivity, and the gate structure comprises a first part, a second part and a third part, wherein the first, second and third parts are electrically separated from each other, with the first part being arranged over the first fin, the second part being arranged over the second fin and the third part being arranged over the third fin. [15] The method of claim 14, wherein the manufacture of the gate structure comprises: Deposition of a dielectric gate layer over the first fin, the second fin and the third fin; Deposition of a gate electrode layer over the first fin, the second fin, and the third fin; and Structuring the gate electrode layer and the dielectric gate layer to produce the first part of the gate structure, the second part of the gate structure, and the third part of the gate structure. [16] The method of claim 14 or 15, further comprising: Deposition of a first interlayer dielectric (ILD) over the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer; Separating the gate structure to divide it into the first gate structure part, the second gate structure part, and the third gate structure part; and Deposition of an insulating material between adjacent ends of the first part and the second part, and between adjacent ends of the second part and the third part. [17] Method according to claim 16, wherein a section width between adjacent ends of the first and second part of the gate structure is about 100 nm to about 400 nm. [18] Method according to any one of claims 14 to 17, further comprising: Forming an insulating material over and between the first fins, the second fins, and the third fins; Recessing the insulating material so that the first, second, and third fins each protrude from a top surface of the insulating material; and epitaxial growth of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer between parts of the insulating material. [19] Method according to any one of claims 14 to 18, further comprising producing a metallization layer over the gate structure, wherein the metallization layer electrically connects the first epitaxial layer to a gate of the gate structure. [20] Method according to any one of claims 14 to 19, further comprising carrying out a gate replacement process to remove a gate electrode of the gate structure and to replace the gate electrode with a metal replacement gate.

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