SILICON CARBIDE SEMICONDUCTOR DEVICE

Abstract

Silicon carbide semiconductor device comprising: an active region (1); a termination region (2) provided at an edge of the active region (1); a semiconductor substrate (50) containing silicon carbide;an isolated gate structure provided on one side of an end face of the semiconductor substrate (50), wherein the isolated gate structure is provided in the active region (1) and contains a metal-oxide-semiconductor field-effect transistor formed by a 3-layer structure of a metal, an oxide layer and a semiconductor, wherein the semiconductor substrate (50) contains a semiconductor layer (51) of a first conductivity type, which configures a drift region (31) of the metal-oxide-semiconductor field-effect transistor, and a semiconductor layer (52) of a second conductivity type, which is provided on the side of the end face of the semiconductor substrate (50) and on the semiconductor layer (51) of the first conductivity type, wherein the semiconductor layer (52) of the second conductivity type configures a base region (32) of the metal-oxide-semiconductor field-effect transistor;a trench (36) provided on the side of the end face of the semiconductor substrate (50) and extending in a first direction (X) parallel to an end face of the semiconductor substrate (50); an insulating layer (37) provided on the side of the end face of the semiconductor substrate (50); a gate electrode (38) of the metal-oxide-semiconductor field-effect transistor provided over the insulating layer (37) in the trench (36);a region (35') of a second conductivity type in high concentration, which is provided in a surface region on the side of the end face of the semiconductor substrate (50) in the termination region (2), wherein the region (35') of the second conductivity type in high concentration forms a transition of the second conductivity type with the semiconductor layer (52) of the second conductivity type, wherein the region (35') of the second conductivity type in high concentration has an impurity concentration which is higher than an impurity concentration of the semiconductor layer (52) of the second conductivity type;a first gate polysilicon layer (14a) which is provided via the insulating layer (37) on the end face of the semiconductor substrate (50) in the termination region (2) and is directed in a depth direction towards the region (35') of the second conductivity type in high concentration via the insulating layer (37), wherein the first gate polysilicon layer (14a) surrounds the perimeter of the active region (1) and has a rectangular ring shape, wherein the first gate polysilicon layer (14a) is electrically connected to the gate electrode (38) at one end of the trench (36);and a field oxide layer (21) provided over the insulating layer (37) on the end face of the semiconductor substrate (50) in the termination region (2), wherein the field oxide layer (21) surrounds a perimeter of the first gate polysilicon layer (14a) and has a rectangular ring shape with four side sections, two of which extend in the first direction (X) and the other two in a second direction (Y) orthogonal to the first direction (X), wherein at least one side section of the field oxide layer (21) extending in the second direction (Y) is arranged from an outer perimeter of the termination region (2) towards the active region (1) in the first direction (X), wherein a nearest edge (21a) at the active region (1) of the at least one side section is located at a position further from the active region (1) than a position of a furthest edge from the active region (1) of the first gate polysilicon layer (14a).

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] The embodiments of the invention relate to a silicon carbide semiconductor device. Description of the related technique

[0002] A conventional trench-gate silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (trench-gate SiC MOSFET), which incorporates silicon carbide (SiC) as the semiconductor material and has a three-layer structure comprising a metal, an oxide layer, and a semiconductor material, exhibits a structure in which a polysilicon (Poly-Si) layer, configuring a gate runner, extends directly beneath a gate metal layer of an edge termination region on top of a field oxide layer. The structure of an edge termination region of a conventional semiconductor device is described.

[0003] Fig. Figure 13 is a top view of an arrangement when the conventional silicon carbide semiconductor device is viewed from an end face of a semiconductor substrate. Fig. Figure 14 is an enlarged top view of a rectangular frame AA in Fig. 13. Under the corners of the rectangular frame AA in Fig. 13 will be a corner AA1, which is closest to a corner of a semiconductor substrate. 150 is located, and a corner AA2, which is closest to a center of the semiconductor substrate 150 is located, as assumed to be a pair of corners. An area enclosed by the rectangular frame AA is a section of a border termination area. 102 of the semiconductor substrate (semiconductor chips) 150 . Fig. Figure 15 is a cross-sectional view of a structure along the section line BB-BB' in Fig. 14. Fig. Figure 16 is a cross-sectional view of a structure along the section line CC-CC' in Fig. 13.

[0004] One in the Fig. 13 to Fig. 16 conventional silicon carbide semiconductor device shown 110 is a vertical MOSFET with a trench-gate structure, which has a gate metal layer 113 and a polysilicon layer 114 in the boundary closure area 102 exhibits the extent of an active area 101 surrounds. In the active area 101 are located on one side of an end face of the semiconductor substrate 150 Sections are provided that configure a MOS gate structure. In the active area 101 are on a first area 153a , which is described below, an end face of the semiconductor substrate 150 a source contact surface 111 and a gate contact surface 112 Provided separately. The source contact surface 111 It has an essentially rectangular, flat shape in which a section is cut out.

[0005] The source contact surface 111 occupies most of the surface of the active area 101 and extends from the active area 101 into the edge closure area 102 In Fig. 13 is a scope 111a the source contact surface 111 Indicated by a finer dashed line than a field oxide layer 121 , which is described below. The gate terminal area 112 is in the recessed section of the source connection area 111 arranged and has an essentially rectangular, planar shape, bordered on three sides by the source connection surface 111 is surrounded by a gate insulating layer. 137 extends across the end face of the semiconductor substrate 150 in the edge closure area 102 from the inner walls of the trenches 136 , which defines the MOS gate structure in the active area 101 configure.

[0006] On the gate insulating layer 137 is on a second surface described below 153b the end face of the semiconductor substrate 150 the field oxide layer 121 provided for. The field oxide layer 121 extends from one end (hereinafter referred to as chip end) of the semiconductor substrate 150 towards the active area 101 (towards the center of a chip) and ends on the first surface 153a the end face of the semiconductor substrate 150 in the edge closure area 102 The field oxide layer 121 is on the first surface 153a the end face of the semiconductor substrate 150 directly under the gate metal layer 113 , directly below the gate contact surface 112 and directly beneath a metal layer (hereinafter referred to as gate-connection metal layer) 113a , which is the gate contact surface 112 and the gate metal layer 113 connects, arranged.

[0007] The polysilicon layer 114 is on the gate insulating layer 137 on the end face of the semiconductor substrate 150 closer to the center of the chip than the field oxide layer 121 planned. The polysilicon layer 114 extends from the gate insulating layer 137 on the field oxide layer 121 and towards the end of the chip and is directly below the gate metal layer 113 , directly below the gate contact surface 112 and directly beneath the gate-connection metal layer 113a arranged, wherein the polysilicon layer 114 within a plane of the first surface 153a the end face of the semiconductor substrate 150 ends. A first section 114a the polysilicon layer 114 directly under the gate metal layer 113 is the gate-runner, who is at the ends of the trenches 136 with the gate electrodes 138 is connected.

[0008] The first section 114a the polysilicon layer 114 surrounds a portion of the active area 101 A border 114a' on the side of the chip center (edge ​​closest to the chip center) of the first section 114a the polysilicon layer 114 is positioned closer to the center of the chip than an edge 121a' on the side of the chip center (edge ​​closest to the chip center) of a first section 121a the field oxide layer 121 directly under the gate metal layer 113 A border 114b' of a second section 114b the polysilicon layer 114 directly below the gate contact surface 112 It ends at a position far from the gate contact surface. 112 , as a border 121b' of a second section 121b the field oxide layer 121 directly below the gate contact surface 112 ends.

[0009] A border 114c'a third section 114c the polysilicon layer 114 directly below the gate connection metal layer 113a It ends at a position far from the gate contact surface. 112 , as a border 121c' a third section 121c the field oxide layer 121 directly below the gate connection metal layer 113a ends. The trenches 136 in the active area 101 are arranged in a striped shape along a first direction X parallel to the end face of the semiconductor substrate 150 planned and extend from the active area 101 towards the edge termination area 102 The ends of the trenches 136 lie at the edge 114a' on the side of the chip center of the first section 114a the polysilicon layer 114 opposite in a depth direction Z.

[0010] The gate electrodes 138 are across the gate insulating layer 137in the trenches 136 planned. In Fig. 13 are the edge 114a' on the side of the chip center of the first section 114a the polysilicon layer 114 , a border on the side of the chip end (border closest to the chip end) of the first section 114a and the edges 114b' , 114c' of the second and third sections 114b , 114c Indicated by bold solid lines. A margin on the side of the chip end of the first section. 121a the field oxide layer 121 is positioned at the end of the chip. In Fig. 13 are the edge 121a' on the side of the chip center of the first section 121a the field oxide layer 121 and the edges 121b' , 121c' of the second and third sections 121b , 121c the field oxide layer 121 represented by a dashed line that is thicker than the perimeter line 111athe source contact surface 111 is.

[0011] On the first section 114a the polysilicon layer 114 is the gate metal layer 113 on an intermediate layer insulating layer 122 provided. The gate metal layer 113 surrounds a portion of the active area 101 The gate metal layer 113 is via a contact hole 122a the intermediate layer insulating layer 122 with the first section 114a the polysilicon layer 114 electrically connected and is via the gate connection metal layer 113a with the gate contact surface 112 electrically connected. A section directly beneath the gate metal layer. 113 It has a 3-layer structure, in which the gate insulating layer 137 , the first section 121a the field oxide layer 121 and the first section 114a the polysilicon layer 114one after the other on the end face of the semiconductor substrate 150 are stacked.

[0012] Furthermore, the edge is located 114a' on the side of the chip center of the first section 114a the polysilicon layer 114 closer to the center of the chip than the edge 121a' on the side of the chip center of the first section 121a the field oxide layer 121 Therefore, a section that is closest to one side of the 3-layer structure near the center of the chip has a 2-layer structure, in which only the gate insulating layer 137 and the first section 114a the polysilicon layer 114 one after the other on the end face of the semiconductor substrate 150 are stacked. One level 115 a thickness of the field oxide layer 121 occurs in the first section 114a the polysilicon layer 114 between a section in the field oxide layer 121and a section in the gate insulating layer 137 on.

[0013] Due to the level 115 is a surface of the first section 114a the polysilicon layer 114 towards the semiconductor substrate 150 a section is omitted that is closer to the center of the chip than the first section 121a the field oxide layer 121 located. On the surfaces of the second and third sections 114b , 114c the polysilicon layer 114 It appears similar to the surface of the first section. 114a the polysilicon layer 114 the level 115 the thickness of the field oxide layer 121 between a section in the field oxide layer 121 and a section in the gate insulating layer 137 on. The polysilicon layer 114 and the field oxide layer 121 are through the intermediate insulating layer 122 covered.

[0014] The polysilicon layer 114 It is positioned above the contact hole 122a the intermediate layer insulating layer 122 with the gate metal layer 113 in contact and is via the contact hole 122a the intermediate layer insulating layer 122 with the gate metal layer 113 electrically connected. In the Fig. 14 and Fig. 15 is a section 141 the gate metal layer 113 , whereby he takes a section from an edge of the gate metal layer 113 closest to the end of the chip, up to an edge of the gate metal layer 113 indicates the closest point to the center of the chip. One section 142 is the contact hole 122a the intermediate layer insulating layer 122 . In the contact hole 122a is a contact between the gate metal layer 113 and the polysilicon layer 114 trained. The reference mark 143is a section between the gate metal layer 113 and the source contact surface 111 .

[0015] A boundary between the section 143 and a section 144 is an edge position of the source contact surface 111 A boundary between the section 144 and a section 145 is a position of the edge 121a' on the side of the chip center of the first section 121a the field oxide layer 121 The section 145 is a section of a structure in which the gate insulating layer 137 and the polysilicon layer 114 one after the other on the end face of the semiconductor substrate 150 are stacked. The reference sign 146 is a section of the edge 114a' on the side of the chip center of the first section 114a the polysilicon layer 114 up to an edge of the intermediate layer insulating layer 122closest to the center of the chip, where the intermediate insulating layer 122 the first section 114a the polysilicon layer 114 covered.

[0016] The semiconductor substrate 150 is an epitaxial substrate in which an n-type semiconductor layer 151 and a p-type semiconductor layer 152 one after the other on a (not shown) n + The -type starting substrate is formed by epitaxial growth. The n-type semiconductor layer 151 configures an n-type drift region 131 A section of the p-type semiconductor layer 152 The layer closest to the end of the chip is removed by etching, whereby the p-type semiconductor layer 152 left in a mesa (trapezoidal) shape in the center of the chip. The removal of the section of the p-type semiconductor layer. 152 The stage closest to the end of the chip is formed by... 153 on the end face of the semiconductor substrate150 in the edge closure area 102 . On a mesa edge 153c level 153 is a side face of the p-type semiconductor layer 152 , which was left behind in the mesa shape, was exposed.

[0017] The end face of the semiconductor substrate 150 with the level 153 as one boundary is on the second surface 153b towards the end of the chip towards a (not shown) drain electrode to a greater extent than at the first surface 153a recessed towards the center of the chip. The p-type semiconductor layer 152 configures a p-type base area 132 In other words, the p-type basal region 132 extends from the active area 101 to the edge of the mesa 153c level 153 in the edge closure area 102 The Mesa Rim 153c level 153is a section of the end face of the semiconductor substrate 150 and connects the first area 153a , which are closer to the center of the chip than the stage 153 is located, and the recessed second area 153b , which are closer to the end of the chip than the stage 153 is located.

[0018] A p ++ -Type contact area 135 (hereinafter p ++ -Type-boundary contact area 135' ), which establishes an ohmic contact with a source electrode 139 in a contact hole 122b the intermediate layer insulating layer 122 forms, extends from the active area 101 up to a section of the p-type semiconductor layer 152 (the p-type basal region) 132 ) in the edge closure area 102 The p ++ -Type-boundary contact area 135' extends closer to the end of the chip than the first section 114a the polysilicon layer 114and ends closer to the center of the chip than the edge of the mesa 153c level 153 The p ++ -Type-boundary contact area 135' It also extends directly below the gate contact surface. 112 .

[0019] A distance d101 from the edge of the mesa 153c level 153 up to p ++ -Type-boundary contact area 135' is 15 µm. A distance d102 between the respective edges on the side of the chip end of the first section. 114a the polysilicon layer 114 and the p ++ -Type-boundary contact area 135' The distance is 2 µm, with the respective edges on the chip end side being the edges closest to the chip end. A distance d103 from the edge on the chip end side of the first section. 114a the polysilicon layer 114 to the edge 121a' on the side of the chip center of the first section 121a the field oxide layer 121The distance is 73 µm. d104 from the gate metal layer 113 up to the source contact surface 111 is 10 µm. One width d105 the gate metal layer 113 is 36 µm.

[0020] By ion implantation into a surface region of a section of the n-type semiconductor layer 151 , which is the second area 153b the end face of the semiconductor substrate 150 When a p-type region is formed, it is selectively created. 163 formed. The p-type region 163 configures a stress-resistant structure that connects to the source electrode 139 is electrically connected and features a joint termination extension (JTE) structure. The p - -Type area 163 surrounds a portion of the active area 101 . Between the p-type region 163 and the active area 101 are the p + -Type areas 162a' , 162b'opposite each other and adjacent in the depth direction Z at a position closer to the drain electrode than the p-type basal region 132 planned.

[0021] The p + -Type areas 162a' are located in the p-type region 163 and the p + -Type areas 162b' in contact. The p + -Type areas 162b ' are located in the p-type region 163 and the p-type basal region 132 in contact. The p + -Type areas 162a' , 162b' surround a portion of the active area 101 . The p + -Type areas 162a' , 162b' extend directly below the gate contact surface 112 . The p + -Type areas 162a' , 162b' will be simultaneously with the p + -Type areas 162a , 162b of the active area 101 formed. The p + -Type areas 161 , 162a , 162bof the active area 101 are depleted when the MOSFET is switched OFF and exhibit a function of attenuating a signal at the bottoms of the trenches 136 applied electric field.

[0022] The p + -Type area 161 is separate from the p-type basal region 132 multiple times arranged in positions closer to the drain electrode than the p-type basal region 132 are located. The p + -Type areas 161 lie in the bottoms of the ditches 136 opposite in the depth direction Z. The p + -Type areas 162a , 162b are between the ditches 136 provided for, which are adjacent to each other, which p + -Type areas 162a , 162b are from the trenches 136 and the p + -Type areas 161 separately provided. The p + -Type areas 162a are separate from the p-type basal region 132in positions closer to the drain electrode than the p-type basal region 132 are located. The p + -Type areas 162b are between the p-type basal region 132 and the p + -Type areas 162a planned and are located in the p-type base area 132 and the p + -Type areas 162a in contact.

[0023] The source electrode 139 forms in the contact hole 122b the intermediate layer insulating layer 122 an ohmic contact with the n + -Type-Source areas 134 and the p ++ -Type contact area 135 The source electrode 139 in the contact hole 122b the intermediate layer insulating layer 122 is connected to the source contact surface 111 connected. On one side of the semiconductor substrate. 150 are a n + -Type drain area and drain electrode provided. The reference numeral123 is a passivation layer. The reference symbol 133 is an n-type region that forms a so-called current propagation layer (CSL) and is located in the n-type drift region 131 is planned.

[0024] A conventional SiC MOSFET of this type has been proposed in which a polysilicon layer is provided on a gate insulating layer between a gate metal layer of the edge termination region and the gate insulating layer on an end face of a semiconductor substrate, extending from the active region to just below the gate metal layer (see, for example, Japanese Publication No. 2018-206873, Japanese Publication No. 2018-117016, and Japanese Publication No. 2014-175314). In Japanese Publication No.2018-206873 is a p-type region for carrying charge (holes) out to a corner section (a corner of a rectangle) of the active region, forming a structure in which an electric field due to charge generated at the edge termination region is not applied to a field oxide layer between the p-type base region and a gate runner, thus preventing dielectric breakdown of the field oxide layer.

[0025] In Japanese patent application no. 2018-117016, a p-type RESURF region is arranged between an active region and a stress-resistant structure of an edge termination region such that it faces a mesa edge of a step in a depth direction, thereby forming a structure in which a section where an electric field concentration does not occur between the active region and the stress-resistant structure. In Japanese patent application no.2014-175314 a source contact surface is planarized, whereby the variations in breakdown voltage characteristics and breakdown voltage errors due to variations are prevented by reducing the thickness of an interlayer insulating layer so that it is thinner at a section in an active region than at a section in an edge termination region, and by designing a thickness of a section of the interlayer insulating layer in the edge termination region such that it is a thickness that does not affect the distribution of the electric field of the edge termination region. SUMMARY OF THE INVENTION

[0026] According to one embodiment of the invention, a silicon carbide semiconductor device comprises an active region, a termination region provided on a circumference of the active region, a semiconductor substrate containing silicon carbide, an insulated gate structure provided on one side of an end face of the semiconductor substrate, wherein the insulated gate structure is provided in the active region, and a metal-oxide-semiconductor field-effect transistor formed by a 3-layer structure of a metal, an oxide layer, and a semiconductor, wherein the semiconductor substrate comprises a semiconductor layer of a first conductivity type, which configures a drift region of the metal-oxide-semiconductor field-effect transistor, and a semiconductor layer of a second conductivity type, which is provided on the side of the end face of the semiconductor substrate and on the semiconductor layer of the first conductivity type.wherein the semiconductor layer of the second conductivity type configures a base region of the metal-oxide-semiconductor field-effect transistor, a trench provided on the side of the end faces of the semiconductor substrate and extending in a first direction parallel to an end face of the semiconductor substrate, an insulating layer provided on the side of the end face of the semiconductor substrate, a gate electrode of the metal-oxide-semiconductor field-effect transistor provided over the insulating layer in the trench, a region of a second conductivity type in high concentration provided in a surface region on the side of the end face of the semiconductor substrate in the termination region, wherein the region of the second conductivity type in high concentration forms a transition of the second conductivity type with the semiconductor layer of the second conductivity type,wherein the region of the second conductivity type has a high concentration of impurities that is higher than the impurity concentration of the semiconductor layer of the second conductivity type, a first gate polysilicon layer provided across the insulating layer on the end face of the semiconductor substrate in the termination region and facing the region of the second conductivity type in a depth direction across the insulating layer, wherein the first gate polysilicon layer surrounds the perimeter of the active region and has a rectangular ring shape, wherein the first gate polysilicon layer is electrically connected to the gate electrode at one end of the trench, and a field oxide layer provided across the insulating layer on the end face of the semiconductor substrate in the termination region,wherein the field oxide layer surrounds a perimeter of the first gate polysilicon layer and has a rectangular ring shape with four side segments, two of which extend in the first direction and the other two of which extend in a second direction orthogonal to the first direction. At least one side segment of the field oxide layer extending in the second direction is arranged from an outer perimeter of the termination region towards the active region in the first direction, wherein a nearest edge at the active region of the at least one side segment is located at a position farther from the active region than a position of a farthest edge is located from the active region of the first gate polysilicon layer.

[0027] In the embodiment, at least one side section of the field oxide layer extending in the first direction is arranged from the outer circumference of the termination area towards the active region in the second direction, wherein a nearest edge at the active region of the at least one side section extending in the first direction is located at the same position as a nearest edge of the active region of the first gate polysilicon layer.

[0028] In the embodiment, the at least one side section comprises the two side sections of the field oxide layer extending in the first direction and each arranged from the outer circumference of the termination region towards the active region in the second direction, wherein a nearest edge at the active region of each of the two side sections extending in the first direction is located at the same position as the nearest edge of the active region of the first gate polysilicon layer.

[0029] In this embodiment, a farthest edge of the active region of the second conductivity type is located in high concentration at a position closer to the active region than a position of a farthest edge of the active region of the semiconductor layer of the second conductivity type.

[0030] In at least two side sections of the field oxide layer extending in the second direction, there is a nearest edge at the active region of each of the two side sections extending in the second direction, across the insulating layer in the depth direction on the semiconductor layer of the second conductivity type, being located further from the active region than a position of the transition of the second conductivity type.

[0031] In this embodiment, an outer lateral edge of the first gate polysilicon layer is positioned in high concentration within a flat surface of the area of ​​the second conductivity type.

[0032] In this embodiment, the entire surface of the first gate polysilicon layer is flat.

[0033] In this embodiment, the silicon carbide semiconductor device further comprises a second gate polysilicon layer, which is connected to the first gate polysilicon layer and is provided via the insulating layer in the active region on the end face of the semiconductor substrate, and a gate contact surface, which is provided via an intermediate insulating layer on the second gate polysilicon layer and is electrically connected to the second gate polysilicon layer. A region between the end face of the semiconductor substrate and the second gate polysilicon layer is free of the field oxide layer.

[0034] In this embodiment, the insulating layer is a high-temperature oxide layer or a thermal oxide layer, the field oxide layer is a silicon oxide layer, and the field oxide layer has a thickness greater than the thickness of the insulating layer.

[0035] The tasks, features and advantages of the present invention are specifically set out in the following detailed description of the invention or become obvious from it when read in conjunction with the accompanying drawings. List of characters Fig. Figure 1 is a top view of an arrangement when a silicon carbide semiconductor device according to a first embodiment is viewed from one side of an end face of a semiconductor substrate. Fig. Figure 2 is an enlarged top view of a rectangular frame A in Fig. 1. Fig. Figure 3 is a cross-sectional view of a structure along the section line BB' in Fig. 2. Fig. Figure 4 is a cross-sectional view of a structure along the section line CC' in Fig. 1. Fig. Figure 5 is a cross-sectional view of a structure of a silicon carbide semiconductor device according to a second embodiment. Fig. Figure 6 is a cross-sectional view of a structure of a silicon carbide semiconductor device according to a third embodiment. Fig. Figure 7 is a top view of an arrangement when a silicon carbide semiconductor device according to a fourth embodiment is viewed from the end face of the semiconductor substrate. Fig. Figure 8 is a cross-sectional view of a structure along the section line DD' in Fig. 7. Fig. Figure 9 is a top view of an arrangement when the silicon carbide semiconductor devices are viewed from the end face of the semiconductor substrate according to a fifth embodiment. Fig. Figure 10 is a top view of an arrangement when the silicon carbide semiconductor devices are viewed from the end face of the semiconductor substrate according to a fifth embodiment. Fig. Figure 11 is a top view of an arrangement when the silicon carbide semiconductor devices are viewed from the end face of the semiconductor substrate according to a fifth embodiment. Fig. Figure 12 is a top view of an arrangement when the silicon carbide semiconductor devices are viewed from the end face of the semiconductor substrate according to a fifth embodiment. Fig. Figure 13 is a top view of an arrangement when a conventional silicon carbide semiconductor device is viewed from an end face of a semiconductor substrate. Fig. Figure 14 is an enlarged top view of a rectangular frame AA in Fig. 13. Fig. Figure 15 is a cross-sectional view of a structure along the section line BB-BB' in Fig. 14. Fig. Figure 16 is a cross-sectional view of a structure along the section line CC-CC' in Fig. 13. DETAILED DESCRIPTION OF THE INVENTION

[0036] First, the problems associated with conventional techniques are discussed. In the conventional silicon carbide semiconductor device... 110 (see the Fig. 13 to Fig. 16) In a reliability test where a voltage of 1200 V is applied between a drain and a source at a high temperature (e.g., about 175 degrees C) and a voltage is applied such that a negative bias voltage is present between a gate and the source, it was confirmed that for 1000 hours, which was defined as a target measurement period, destruction occurred within a measurement period of approximately 500hours. Consequently, a cross-sectional analysis was performed by emission analysis using an emission microscope (EMS) regarding the destroyed conventional silicon carbide semiconductor device. 110 executed.

[0037] Regarding the results of the cross-sectional analysis through emission analysis, a light emission was detected. 170 , which generates a leakage current in the section 145 indicates the 2-layer structure, which is located at the edge 121a' on the side of the chip center of the first section 121a the field oxide layer 121 and the ends 121b' , 121c' (Ends closest to the chip center) of the second and third sections 121b , 121c the field oxide layer 121 on the side of the chip center, and in which the gate insulating layer 137 and the polysilicon layer 114 one after the other on the end face of the semiconductor substrate 150are stacked, observed, which confirms that the gate insulating layer 137 at the point of light emission 170 experiences a dielectric breakdown (the Fig. 14 and Fig. 15).

[0038] One reason for the destruction, which is described in section 145 The phenomenon that occurs in the 2-layer structure is that, when a voltage is applied under the above given conditions, it is assumed that a concentration of the electric field occurs at the edge. 114a' on the side of the chip center of the first section 114a the polysilicon layer 114 and at the edges 114b' , 114c' of the second and third sections 114b , 114c occurs. In an OFF state, a portion of the hole current flows that is located in the edge termination region. 102 is generated by the p ++ -Type-boundary contact area 135' , moving towards the source electrode 139is led out, a leakage current is generated, and at a section where the electric field is concentrated, it enters the gate insulating layer. 137 is injected, causing a dielectric breakdown.

[0039] The embodiments of a silicon carbide semiconductor device according to the present invention are described in detail with reference to the accompanying drawings. In this description and in the accompanying drawings, layers and regions with a preceding n or p indicate that the majority carriers are electrons or holes. Additionally, a + or - appended to the n or p indicates that the impurity concentration is higher or lower, respectively, than in the layers and regions without the + or -. In the following description of the embodiments and in the accompanying drawings, the same reference numerals are used for the identical main sections, and they are not described repeatedly.

[0040] A structure of a silicon carbide semiconductor device according to a first embodiment is described. Fig. Figure 1 is a top view of an arrangement when the silicon carbide semiconductor device according to the first embodiment is viewed from one side of an end face of a semiconductor substrate. Fig. Figure 2 is an enlarged top view of a rectangular frame. A in Fig. 1. A rectangular frame A surrounded section, which is a pair of corners, a corner A1 towards a corner section (a corner of a semiconductor substrate (semiconductor chips) 50 (with an essentially rectangular, flat shape) of the semiconductor substrate 50 and a corner A2 towards the center of the semiconductor substrate 50 exhibits a section of an edge termination area 2 . Fig. Figure 3 is a cross-sectional view of a structure along the section line BB' in Fig. 2. Fig. Figure 4 is a cross-sectional view of a structure along the section line CC' in Fig. 1.

[0041] The silicon carbide semiconductor device 10 according to the first embodiment, which is in the Fig. 1 to Fig. Figure 4 shows a vertical MOSFET with a trench-gate structure located in the edge termination region. 2 , which surrounds a perimeter, an active area 1 , a gate metal layer 13 and a polysilicon (poly-Si) layer 14 includes the active area 1 is a region through which current flows when an element is in an ON state. The boundary termination region 2 is an area between the active area 1 and one end of the semiconductor substrate 50and is a region for weakening the electric field on one side of an end face of the semiconductor substrate. 50 and to maintain a breakdown voltage. In the edge termination area 2 A stress-resistant structure, such as a joint termination extension (JTE) structure, is arranged. The breakdown voltage is a stress limit at which no erratic operation or destruction of a component occurs.

[0042] In the active area 1 are on a first area described below 53a a front face of the semiconductor substrate 50 a source contact surface 11 and a gate contact surface 12 Provided to be separate from each other. The source contact surface 11 It has an essentially rectangular, flat shape with an inward-facing recess. The source connection surface 11occupies most of the surface of the active area 1 and extends from the active area 1 up to the edge termination area 2 . Fig. 1, a scope 11a the source contact surface 11 is indicated by a dashed line that is thinner than that for a field oxide layer described below 21 is. The gate contact surface 12 is in the recessed section of the source contact surface 11 provided and has an essentially rectangular, flat shape, bordered on three sides by the source contact surface 11 is surrounded.

[0043] In the active area 1 are located on the end face of the semiconductor substrate 50 The sections provided configure a MOS gate structure. The semiconductor substrate 50 is an epitaxial substrate in which an n - -Type semiconductor layer (first conductivity type semiconductor layer)51 and a p-type semiconductor layer (second conductivity type semiconductor layer) 52 successively through epitaxial growth on an n + -Type starting substrate 54 are formed. A major surface of the semiconductor substrate 50 with the p-type semiconductor layer 52 is assumed to be a front face, while a main face (back of the n) + -Type starting substrate 54 ) of the semiconductor substrate 50 with the n + -Type starting substrate 54 is assumed to be a back side. A chip size of the semiconductor substrate. 50 It could, for example, be a square of 3.8 mm. The MOS gate structure is characterized by a p-type basal region. 32 , the n + -Type-Source areas 34 , the p ++ -Type contact areas 35 , the trenches 36 , a gate insulating layer 37 and the gate electrodes 38 configured.

[0044] The n + -Type starting substrate 54 configures an n + -Type-Drain area 40 The n-type semiconductor layer 51 configures an n - -Type-Drift area 31 . In the n - -Type-Drift area 31 can be an n-type region 33 and the p + -Type areas 61 , 62a , 62b The n-type area is planned. 33 This is a so-called current-propagation layer (CSL), which reduces the carrier propagation resistance. The n-type region 33 is between the p + -Type areas 61 , 62a , 62a The n-type area is planned, which are adjacent to each other. 33 can extend into the edge termination area 2 extend and in this case ends, for example, closer to the chip center (inwards) than a mesa edge. 53c a level 53 . The p + -Type areas 61 , 62a ,62b They become depleted when the MOSFET is in an OFF state and exhibit a function of attenuating the current at the bottoms of the trenches. 36 applied electric field.

[0045] The p + -Type areas 61 are arranged separately from the p-type basal region 32 at positions closer to a drain electrode 15 as the p-type basal region 32. The p + -Type areas 61 lie in the bottoms of the ditches 36 opposite in the depth direction Z. The p + -Type areas 62a , 62b are between the ditches 36 , which are adjacent to each other, separated by the ditches 36 and the p + -Type areas 61 arranged. The p + -Type areas 62a are provided separately from the p-type base region 32 at positions closer to the drain electrode 15 as the p-type basal region 32. Each of the p+ -Type areas 62b is between the p-type basal region 32 and one of the p + -Type areas 62a planned and is located with the p-type base area 32 and one of the p + -Type areas 62a in contact.

[0046] A section on the side of the chip end of the p-type semiconductor layer 52 on one outer side (one chip end) is removed by etching, whereby the p-type semiconductor layer 52 The section left in the center of the chip is in a mesa (trapezoidal) shape. This involves removing the section on the end (outer) side of the p-type semiconductor layer of the chip. 52 forms the stage 53 on the end face of the semiconductor substrate 50 in the edge closure area 2 . At the edge of the mesa 53c level 53 is a side surface of the p-type semiconductor layer left behind in the mesa shape 52 exposed. The end face of the semiconductor substrate.50 with the level 53 as a boundary is in the direction of the drain electrode 15 , which is described below, on a second surface 53b towards the end of the chip to a greater extent than on the first surface 53a towards the active area 1 (towards the center of the chip) is omitted.

[0047] The p-type semiconductor layer 52 Configures the p-type base area 32. In other words, the p-type base area 32 extends from the active area. 1 to the edge of the mesa 53c level 53 in the edge closure area 2 The Mesa Rim 53c level 53 is a section of the end face of the semiconductor substrate 50 and connects the first area 53a , which are closer to the center of the chip than the stage 53 is located, and the recessed second area 53b, which are closer to the end of the chip than the stage 53 located in the active area 1 between the first area 53a the end face of the semiconductor substrate 50 and the p-type basal region 32 are the n + -Type-Source areas 34 and the p ++ -Type contact areas 35 are selectively provided in contact with the p-type basal area 32.

[0048] The trenches 36 penetrate the n + -Type-Source areas 34 and the p-type base region 32 and reach the n - -Type-Drift area 31 The trenches 36 are not directly under the gate contact surface 12 planned. The trenches 36 extend from the active area 1 in a striped shape along the first direction X parallel to the end face of the semiconductor substrate 50 into the edge closure area 2 The ends of the trenches 36lie in the depth direction Z at an edge 14a' on the side of the chip center (edge ​​closest to the chip center) of a first section (a first gate polysilicon layer) 14a, which is described below, the polysilicon layer 14 opposite each other. Furthermore, the ends of the trenches lie opposite each other. 36 in the depth direction Z at the edges 14b' , 14c' of the second and third sections 14b , 14c' the polysilicon layer described below 14 opposite.

[0049] In the trenches 36 are the polysilicon-containing gate electrodes 38 via the gate insulating layer 37 provided. The gate insulating layer 37 This could be, for example, a high-temperature oxide layer (HTO) or a thermal oxide layer. The gate electrodes 38 Examples include a polysilicon layer. The gate electrodes 38 at the ends of the trenches 36are related to any of the first to third sections 14a until 14c the polysilicon layer 14 connected. An intermediate insulating layer. 22 is located on the entire front surface of the semiconductor substrate 50 designed to be used for the gate electrodes 38 to cover. For example, an undoped silicate glass (NSG) and a borophosphate silicate glass (BPSG) can be successively used as the intermediate insulating layer. 22 be separated.

[0050] The source electrode 39 forms in a contact hole 22b the intermediate layer insulating layer 22 an ohmic contact with the n + -Type-Source areas 34 and the p ++ -Type contact areas 35 and is with the source contact surface 11 connected. The source contact surface 11 is on the intermediate layer insulating layer 22 designed so that they fit into the contact hole 22bthe intermediate layer insulating layer 22 is embedded and essentially the entire first area 53a the end face of the semiconductor substrate 50 in the active area 1 with the exception of a section of the gate contact surface 12 covered. The gate contact surface 12 is on the intermediate layer insulating layer 22 provided and covers a section of the first area 53a the end face of the semiconductor substrate 50 in the active area 1 The gate electrodes 38 are across the polysilicon layer 14 with the gate contact surface 12 electrically connected.

[0051] In the boundary closure area 2 on the end face of the semiconductor substrate 50 the gate insulating layer extends 37 from the inner walls of the trenches 36 into the active area 1 The field oxide layer 21is connected to the gate insulating layer 37 the second area 53b the end face of the semiconductor substrate 50 Intended for contact. The field oxide layer 21 extends from the end of the chip towards the center of the chip and ends on the first surface 53a the end face of the semiconductor substrate 50 closer to the end of the chip than the first section 14a the polysilicon layer 14 The field oxide layer 21 is separated from the polysilicon layer 14 arranged and surrounds a perimeter of the first section 14a the polysilicon layer 14 .

[0052] A border on the side of the chip center (border closest to the chip center) 21a of the field oxide layer 21 is closer to the center of the chip than the edge of the mesa 53c level 53 and closer to the end of the chip than a p described below ++-Type edge contact area (area of ​​the second conductivity type in high concentration) 35' positioned. In other words, the edge 21a on the side of the chip center of the field oxide layer 21 is positioned on the p-type base area 32, which is located on the first surface 53a the end face of the semiconductor substrate 50 in a section 44 between the edge of the mesa 53c level 53 and the p ++ -Type-boundary contact area 35' is exposed. As a result, a dielectric breakdown of the field oxide layer can occur. 21 in the p ++ -Type contact area 35' be prevented.

[0053] A position of the edge 21a on the side of the chip center of the field oxide layer 21 can be found in the section 44 between the edge of the mesa 53c level 53 and the p ++ -Type-boundary contact area 35'The design constraints may vary. In particular, a distance d1 from the mesa edge will be specified. 53c level 53 up to p ++ -Type-boundary contact area 35' The thickness is determined in advance by the design specifications and is, for example, approximately 15 µm. In this case, the edge ends 21a on the side of the chip center of the field oxide layer 21 at a position that is separated from the edge of the mesa 53c level 53 more than 0.5 µm towards the center of the chip and less than 15 µm from the mesa edge 53c level 53 is separated in the direction of the chip center.

[0054] If a distance d3, which the edge 21a on the side of the chip center of the field oxide layer 21 from the edge of the mesa 53c level 53 in the direction of the chip center, which is 13 µm, is a distance d3' from the edge. 21a on the side of the chip center of the field oxide layer21 up to p ++ -Type-boundary contact area 35' 2 µm. If the distance d3 is equal to 10 µm, then the distance d3' from the edge is also 21a on the side of the chip center of the field oxide layer 21 up to p ++ -Type- Edge contact area 35' 5 µm. The field oxide layer 21 This could be, for example, a silicon oxide layer (SiO2 layer), which, compared to other insulating layers, exhibits a high band gap and high heat resistance. The thickness of the field oxide layer 21 is greater than the thickness of the gate insulating layer 37 .

[0055] The polysilicon layer 14 is on the gate insulating layer 37 on the end face of the semiconductor substrate 50 closer to the center of the chip than the field oxide layer 21 planned. The polysilicon layer 14 is directly beneath the gate metal layer 13 , directly below the gate contact surface 12and directly beneath a metal layer (hereinafter referred to as the gate-connection metal layer) 13a, which forms the gate contact surface 12 and the gate metal layer 13 connects, with the polysilicon layer 14 within a plane of the first surface 53a the end face of the semiconductor substrate 50 ends. The polysilicon layer 14 is overall within a plane of p ++ -Type marginal contact area 35' positioned. The figures represent a case in which the gate insulating layer is positioned. 37 It is formed by thermal oxidation. Normally, the formation process of the field oxide layer is... 21 a process prior to a formation process of the gate insulation layer 37 , therefore, if the gate insulating layer 37 an HTO layer is a vertical stacking relationship between the field oxide layer 21 and the gate insulating layer 37is swapped.

[0056] The first section 14a the polysilicon layer 14 directly under the gate metal layer 13 is a gate runner that interacts with the gate electrodes 38 at the ends of the trenches 36 is connected. The first section 14a the polysilicon layer 14 lies the gate metal layer 13 overall in the depth direction Z opposite and surrounds a perimeter of the active area. 1 The polysilicon layer 14 extends towards the center of the chip and ends in such a way that the edge 14a' on the side of the chip center of the first section 14a is located in a position that corresponds to the scope 11a the source contact surface 11 opposite in the depth direction Z. An edge on the side of the chip end (edge ​​closest to the chip end) of the first section. 14a the polysilicon layer 14is within a plane of p ++ -Type- Edge contact area 35' positioned. A distance d2 between the respective edges of the first section. 14a the polysilicon layer 14 and the p ++ -Type-boundary contact area 35' The distance to the respective edges closest to the chip end is, for example, about 2 µm.

[0057] The second section (the second gate polysilicon layer) 14b of the polysilicon layer 14 directly below the gate contact surface 12 The gate contact surface is located 12 overall in the depth direction Z opposite. The polysilicon layer 14 extends away from the gate contact surface 12 in the directions (a first and a second direction X, Y) parallel to the end face of the semiconductor substrate 50 and ends in such a way that the edge 14b' of the second section 14b is located in a position that corresponds to the scope 11athe source contact surface 11 opposite in the depth direction Z. A third section 14c the polysilicon layer 14 directly below the gate connection metal layer 13a The gate connection metal layer is located 13a overall in the depth direction Z opposite. The polysilicon layer 14 extends in one direction (in Fig. 1 of the first direction X) parallel to the end face of the semiconductor substrate 50 and away from the gate-connection metal layer 13a and ends in such a way that an edge forms 14c' of the third section 14c is located in a position that corresponds to the scope 11a the source contact surface 11 opposite in the depth direction Z.

[0058] An inner, planar circumferential shape of the polysilicon layer 14 has become a flat form of the circumference 11a the source contact surface 11 similar and slightly smaller in circumference11a the source contact surface 11 An outer, planar circumferential shape of the polysilicon layer 14 is a rectangular shape that is slightly smaller than the inner circumference of the field oxide layer 21 is. In Fig. 1 are the edge 14a' on the side of the chip center of the first section 14a the polysilicon layer 14 , the edge on the side of the chip end of the first section 14a and the edges 14b' , 14c' of the second and third sections 14b , 14c Indicated by bold solid lines. Fig. 1 is the edge 21a on the side of the chip center of the field oxide layer 21 indicated by a dashed line that is thicker than the one for the perimeter 11a the source contact surface 11 is. An edge on the side of the chip end of the field oxide layer. 21 It is positioned at the end of the chip.

[0059] On the first section 14a the polysilicon layer 14 is the gate metal layer 13 on the intermediate layer insulating layer 22 provided. The gate metal layer 13 surrounds a portion of the active area 1 The gate metal layer 13 is via a contact hole 22a the intermediate layer insulating layer 22 with the first section 14a the polysilicon layer 14 electrically connected and is via the gate connection metal layer 13a with the gate contact surface 12 electrically connected. A section directly beneath the gate metal layer. 13 one of the first sections 14a the polysilicon layer 14 overall spanning 2-layer structure, in which the gate insulating layer 37 and the first section 14a the polysilicon layer 14 consecutively on the first surface 53athe end face of the semiconductor substrate 50 are stacked. In other words, at the first section 14a the polysilicon layer 14 is the layer thickness (thickness) of an insulating layer that is between the polysilicon layer 14 and the first area 53a the end face of the semiconductor substrate 50 is present, with the same layer thickness as the gate insulating layer 37 , which are in the active area 1 in the trenches 36 is formed. It is sufficient that the same layer thickness is produced by the same manufacturing process and that it contains a layer thickness variation of up to ±10%, which is a variation range within a plane.

[0060] The second section 14b the polysilicon layer 14 also shows the second section 14b the polysilicon layer 14overall spanning 2-layer structure, in which the gate insulating layer 37 and the second section 14b the polysilicon layer 14 one after the other on the first surface 53a the end face of the semiconductor substrate 50 are stacked. The third section 14c the polysilicon layer 14 also indicates the third section 14c the polysilicon layer 14 overall spanning 2-layer structure, in which the gate insulating layer 37 and the third section 14c the polysilicon layer 14 one after the other on the first surface 53a the end face of the semiconductor substrate 50 are stacked.

[0061] In this way the field oxide layer lies 21 the polysilicon layer 14 not in the depth direction Z opposite. Therefore, one surface of the polysilicon layer spans 14the polysilicon layer in total 14 flat, with the step 115 (the Fig. 15, Fig. 16) due to the field oxide layer 121 on the surface of the polysilicon layer 14 unlike the conventional structure. The only insulating layer between the polysilicon layer 14 and the first area 53a the end face of the semiconductor substrate 50 is the gate insulating layer 37 , whereby, therefore, during the application of a voltage under the above specified conditions, the concentration of the electric field at the edge 14a' on the side of the chip center of the first section 14a the polysilicon layer 14 and the edges 14b' , 14c' of the second and third sections 14b , 14c does not occur as with the conventional structure.

[0062] The polysilicon layer 14 and the field oxide layer21 are through the intermediate insulating layer 22 covered. The polysilicon layer 14 is via the contact hole 22a the intermediate layer insulating layer 22 with the gate metal layer 13 electrically connected in the contact hole. 22a the intermediate layer insulating layer 22 is a contact between the gate metal layer 13 and the polysilicon layer 14 trained. In Fig. The sections correspond to 3. 41 , 42 , 43 , 44 , 44' , 45 , 46 , 47 , 48 and 49 each of the sections 41 , 42 , 43 , 44 , 44' , 45 , 46 , 47 , 48 and 49 in Fig. 2. A distance d4 from the gate metal layer 13 up to the source contact surface 11For example, it is approximately 10 µm. A width d5 ​​of the gate metal layer 13 For example, it is approximately 36 µm. The distances d1 to d4 between the sections described above and the width d5 ​​of the gate metal layer. 13 are determined by design specifications and depend on the chip size of the semiconductor substrate. 50 independent.

[0063] In the edge finishing area 2 between the first area 53a the end face of the semiconductor substrate 50 and the p-type basal region 32 extend the p ++ -Type contact areas 35 (the p ++ -Type-boundary contact area 35' ) from the active area 1 The p ++ -Type-boundary contact area 35' extends closer to the end of the chip than the first section 14a the polysilicon layer 14 and ends closer to the center of the chip than the edge 21a on the side of the chip center of the field oxide layer 21 The p ++-Type-boundary contact area 35' in the contact hole 22b the intermediate layer insulating layer 22 forms an ohmic contact with the source electrode 39 .

[0064] A contact (electrical contact) between the p ++ -Type-boundary contact area 35' and the source electrode 39 is a contact for leading out of the edge termination area 2 Hole current generated during the OFF state via the p ++ -Type-boundary contact area 35' towards the source electrode 39 The p ++ -Type-boundary contact area 35' It can also be located, for example, directly under the gate contact surface. 12 extend. A surface area of ​​a section of the n - -Type semiconductor layer 51 , which is the second area 53b the end face of the semiconductor substrate 50 It forms, is ion-implanted, resulting in a p-type region. 63is selectively trained. The p - -Type area 63 is connected to the source electrode 39 electrically connected and forms a voltage-resistant structure, such as a joint termination extension (JTE) structure. The p-type region 63 surrounds a perimeter of the active region. 1 .

[0065] Between the p-type region 63 and the active area 1 are the p + -Type areas 62a' , 62b' , which are adjacent and opposite each other in the depth direction Z, are provided at positions closer to the drain electrode 15 as the p-type basal region 32 are located. The p + -Type area 62a' is located in the p-type area 63 and the p+ type area 62b' in contact. The p + -Type area 62b' is located in the p-type area 63 and the p-type basal region 32 in contact. The p +-Type areas 62a' , 62b' surround a portion of the active area 1 . The p + -Type areas 62a' , 62b' extend, for example, directly below the gate contact surface. 12 . The p + -Type areas 62a' , 62b' will be simultaneously with the p + -Type areas 62a , 62b of the active area 1 educated.

[0066] The end face of the semiconductor substrate 50 is protected by a passivation layer 23 covered. The drain electrode 15 is on the back of the semiconductor substrate 50 provided for and is connected with the n + -Type-Drain area 40 (the n + -Type starting substrate 54 ) electrically connected.

[0067] As described above, according to the first embodiment, the edge of the field oxide layer on the chip-center side terminates closer to the chip end than the polysilicon layer. This results in the entire surface of the polysilicon layer being flat, without the field oxide layer creating a step on the surface. Therefore, when a voltage is applied under the conditions specified above, the electric field concentration that occurs at the edge on the chip-center side of the first section of the polysilicon layer in the conventional structure does not occur. Consequently, a portion (leakage current) of the hole current generated at the edge termination region during the OFF state and carried by the p ++-Type edge contact area flows to be directed outwards towards the source electrode, not injected into the gate insulating layer near the contact to carry out the hole current, thus preventing dielectric breakdown of the gate insulating layer.

[0068] A structure of a silicon carbide semiconductor device according to a second embodiment is described. Fig. Figure 5 is a cross-sectional view of a structure of the silicon carbide semiconductor device according to the second embodiment. A silicon carbide semiconductor device 71 The second embodiment differs from the silicon carbide semiconductor device. 10 according to the first embodiment (see the Fig. 1 to Fig. 4) insofar as there is no field oxide layer covering the end face of the semiconductor substrate 50 in the edge closure area 2It is covered, provided for. A planar structure of the silicon carbide semiconductor device. 71 The second embodiment is similar to the one described in the Fig. 1 and Fig. 2 is shown, of which the field oxide layer 21 is removed. Fig. 5 corresponds to a cross-sectional view of a structure along the section line BB' in Fig. 2.

[0069] As described above, according to the second embodiment, no step occurs on the surface of the polysilicon layer, even if the field oxide layer is not provided, thus making it possible to obtain effects similar to those of the first embodiment.

[0070] A structure of a silicon carbide semiconductor device according to a third embodiment is described. Fig. Figure 6 is a cross-sectional view of a structure of the silicon carbide semiconductor device according to the third embodiment. A silicon carbide semiconductor device 72 According to the third embodiment, it differs from the silicon carbide semiconductor device. 10 according to the first embodiment (see the Fig. 1 to Fig. 4) insofar as a mesa edge 53c' level 53 is inclined so that it forms an obtuse angle with respect to the first surface 53a the end face of the semiconductor substrate 50 forms a planar structure of the silicon carbide semiconductor device. 72 According to the third embodiment, the following applies: Fig. 1 and Fig. 2 similar. Fig. Figure 6 corresponds to a cross-sectional view of a structure along the section line BB' in Fig. 2.

[0071] In the third embodiment, the field oxide layer 21' and the gate insulating layer37' on the mesa rim 53c' level 53 planned along the slope of the mesa rim 53c' are inclined. As a result, the field oxide layer can 21' evenly distributed along the edge of the mesa 53c' are deposited, thereby increasing reliability. Therefore, cases where variations in the process accuracy of the field oxide layer cause problems can be prevented. 21' a border 21a' on the side of the chip center of the field oxide layer 21' is moved towards the center of the chip to access the p ++ -Type-boundary contact area 35' to be positioned, or the edge 21a' on the side of the chip center of the field oxide layer 21' is moved towards the end of the chip to reach the Mesa rim 53c' level 53 to be positioned.

[0072] As described above, according to the third embodiment, effects similar to those of the first embodiment can be obtained. Furthermore, according to the third embodiment, the mesa edge of the step is inclined such that it forms an obtuse angle with respect to the first and second faces of the end face of the semiconductor substrate. This positions the edge on the side of the chip center of the field oxide layer, extending from the mesa edge of the step towards the first face of the semiconductor substrate, on the p-type base region exposed at the first face of the end face of the semiconductor substrate, between the mesa edge of the step and that of the p-type base region. ++ -Type edge contact area can be determined with good accuracy.

[0073] A structure of a silicon carbide semiconductor device according to a fourth embodiment is described. Fig. Figure 7 is a top view of an arrangement when the silicon carbide semiconductor device according to the fourth embodiment is viewed from the end face of the semiconductor substrate. Fig. Figure 8 is a cross-sectional view of a structure along the section line DD' in Fig. 7. A silicon carbide semiconductor device 73 According to the fourth embodiment, it differs from the silicon carbide semiconductor device. 10 according to the first embodiment (see the Fig. 1 to Fig. 4) insofar as a margin 21b on the side of the chip center of the field oxide layer 21 and parallel to the first direction X at the same position as that of the edge 14a' on the side of the chip center of the first section 14a the polysilicon layer 14 is located.

[0074] In particular, the edge 21bon the side of the chip center of a section (section parallel to the first direction X) of the field oxide layer 21 along the second direction Y, which leads to the end face of the semiconductor substrate 50 parallel and orthogonal to the first direction X, in the direction of the chip center up to the same position as a position of the edge 14a' on the side of the chip center of a section (section parallel to the first direction X) of the first section 14a the polysilicon layer 14 moved. Therefore, at the section of the first section, it occurs 14a the polysilicon layer 14 , which is parallel to the first direction X, on the surface of the first section 14a the polysilicon layer 14 no step due to the field oxide layer 21 up. In Fig. 7 are the edges 21a , 21b on the side of the chip center of the field oxide layer 21represented by a dashed line that is thicker than the one for the circumference 11a the source contact surface 11 is.

[0075] In this way, the sections of the first section that are parallel to the first direction X can be used. 14a the polysilicon layer 14 the edge 21b on the side of the chip center of the sections of the field oxide layer parallel to the first direction X 21 closer to the center of the chip than the first section 14a the polysilicon layer 14 are located, so that a step is formed due to the field oxide layer 21 on the surface of the first section 14a the polysilicon layer 14 does not occur. Therefore, the edge can 21b on the side of the chip center of the sections of the field oxide layer parallel to the first direction X 21 slightly closer to the center of the chip than the edge 14a'on the side of the chip center of the sections of the first section that are parallel to the first direction X 14a the polysilicon layer 14 condition.

[0076] On the other hand, a section of the first section 14a the polysilicon layer 14 (i.e., a section of it parallel to the second direction Y) a section that corresponds to the ends of the trenches 36 opposite in the depth direction Z. The edge 21a on the side of the chip center of a section of the field oxide layer 21 (i.e., a section of it parallel to the second direction Y) is located closer to the end of the chip than the first section, similar to the first embodiment. 14a of the section of the polysilicon layer parallel to the second direction Y 14 Therefore, at the sections of the first section 14a the polysilicon layer parallel to the second direction Y 14 no step due to the field oxide layer21 on the surface of the first section 14a the polysilicon layer 14 on.

[0077] In other words, at the gate metal layer 13 A section of it parallel to the first direction X is located directly below the gate metal layer. 13 a 3-layer structure in which the gate insulating layer 37 , the field oxide layer 21 and the first section 14a the polysilicon layer 14 one after the other on the end face of the semiconductor substrate 50 are stacked. At the gate metal layer 13 A section of it parallel to the second direction Y is located directly below the gate metal layer. 13 a 2-layer structure in which the gate insulating layer 37 and the first section 14a the polysilicon layer 14 one after the other on the end face of the semiconductor substrate 50are stacked. Therefore, the total layer thickness between the end face of the semiconductor substrate is 50 and the polysilicon layer 14 existing insulating layers ( 37 , 21 ) thicker compared to the sections parallel to the second direction Y and the sections parallel to the first direction X.

[0078] If the positions of the edges 21a , 21b on the side of the chip center of the field oxide layer 21 in the first and second directions X, Y at the corner sections (four corners of the semiconductor substrate) 50 (with an essentially rectangular, flat shape) of the semiconductor substrate 50 The distinction appears in this way on the surface of the first section. 14a the polysilicon layer 14 due to the field oxide layer 21 one stage. Additionally, depending on the arrangement of the gate contact surface, it takes on 12the degree of freedom of the design with regard to the arrangement of the field oxide layer 21 to, although a step due to the field oxide layer 21 on the surface of the third section 14c the polysilicon layer 14 occurs.

[0079] In the second section 14b the polysilicon layer 14 The field oxide layer is similar to the first embodiment. 21 not directly below the second section 14b the polysilicon layer 14 present, therefore on the surface of the second section 14b the polysilicon layer 14 no step due to the field oxide layer 21 occurs.

[0080] As described above, according to the fourth embodiment, the position of the edge on the side of the chip center of the field oxide layer is moved towards the chip center to the same position as the position of the edge on the side of the chip center of the first section of the polysilicon layer, whereby no step due to the field oxide layer occurs on the surface of the first section of the polysilicon layer and therefore effects similar to those of the first embodiment can be obtained.

[0081] A structure of silicon carbide semiconductor devices according to a fifth embodiment is described. Fig. 9, Fig. 10, Fig. 11 and Fig. Figure 12 are top views of an arrangement when the silicon carbide semiconductor devices according to the fifth embodiment are viewed from the end face of the semiconductor substrate. In the Fig. 9 to Fig. 12 are the polysilicon layer 14, the edges 21a , 21b on the side of the chip center of the field oxide layer 21 (in Fig. 9 only the edge 21a (on the side of the chip center) and the trenches 36 the silicon carbide semiconductor devices 74 , 75 , 76 and 77 The fifth embodiment is shown schematically, with other constituent parts not shown. Furthermore, the edges are... 21a , 21b on the side of the chip center of the field oxide layer 21 indicated by a dashed line.

[0082] The silicon carbide semiconductor devices 74 until 77 According to the fifth embodiment, positional relationships between the polysilicon layer 14 and the edges 21a , 21b on the side of the chip center of the field oxide layer 21 (in Fig. 9 only the edge 21a(on the side of the chip center) at the four edges of the semiconductor substrate 50 This represents a substantially rectangular, planar shape. At the four edges of the semiconductor substrate... 50 are the positional relationships between the polysilicon layer 14 and the edges 21a , 21b on the side of the chip center of the field oxide layer 21 specified by “reserve” at the edges to which the first embodiment is applied and “lead” at the edges to which the fourth embodiment is applied.

[0083] In other words, regarding the positional relationships between the polysilicon layer 14 and the edges 21a , 21b on the side of the chip center of the field oxide layer 21 is a “reserve” in a case where the first embodiment is applied, a case where the edge 21a on the side of the chip center of the field oxide layer21 closer to the end of the chip than the polysilicon layer 14 is positioned. A "lead-in" in a case where the fourth embodiment is applied is a case where the edge is positioned in the second direction Y. 21b on the side of the chip center of the field oxide layer 21 in the same position as the edge 14a' on the side of the chip center of the first section 14a the polysilicon layer 14 is located.

[0084] In particular, the silicon carbide semiconductor device 74 according to the fifth embodiment, which in Fig. Figure 9 shows the silicon carbide semiconductor device 10 according to the first embodiment (see Fig. 1) In other words, at the four edges of the semiconductor substrate 50 is the positional relationship between the polysilicon layer 14 and the edge 21a on the side of the chip center of the field oxide layer21 a "reserve". While this in Fig. Not shown in section 9 are the polysilicon layers. 14 and the field oxide layer 21 arranged separately from each other (similar to the "reserve" sections in the Fig. 10 to Fig. 12), as described above.

[0085] The silicon carbide semiconductor device 75 according to the fifth embodiment, which in Fig. Figure 10 shows the silicon carbide semiconductor device. 73 according to the fourth embodiment (see the Fig. 7 and Fig. 8) In other words, at the two edges of the semiconductor substrate 50 parallel to the first direction X is the positional relationship between the polysilicon layer 14 and the edge 21b on the side of the chip center of the field oxide layer 21 a "lead". Furthermore, at the two edges of the semiconductor substrate 50parallel to the second direction Y, the positional relationship between the polysilicon layer 14 and the edge 21a on the side of the chip center of the field oxide layer 21 a “reserve”.

[0086] In silicon carbide semiconductor devices 76 , 77 according to the fifth embodiment, which is in the Fig. 11 and Fig. 12 are shown, is at either of the two edges of the semiconductor substrate. 50 parallel to the first direction X, the positional relationship between the polysilicon layer 14 and the edge 21b on the side of the chip center of the field oxide layer 21 a "lead". Furthermore, at the other of the two edges of the semiconductor substrate, 50 parallel to the first direction X and at the two edges parallel to the second direction Y, the positional relationship between the polysilicon layer 14 and the edge 21aon the side of the chip center of the field oxide layer 21 a “reserve”.

[0087] From the four edges of the semiconductor substrate 50 can be used for the edges, where the positional relationship between the polysilicon layer 14 and the edge 21a on the side of the chip center of the field oxide layer 21 A "reserve" is provided, allowing the second embodiment to be used instead of the first. In this case, the silicon carbide semiconductor device... 74 according to the fifth embodiment, the field oxide layer 21 not arranged. In the silicon carbide semiconductor arrangement 75 According to the fifth embodiment, the field oxide layer 21 only at the two edges of the semiconductor substrate 50 arranged parallel to the first direction X. In the silicon carbide semiconductor arrangements 76 , 77 According to the fifth embodiment, the field oxide layer 21only at one edge of the two edges of the semiconductor substrate 50 arranged parallel to the first direction X.

[0088] From the four edges of the semiconductor substrate 50 can at least at one edge, where the positional relationship between the polysilicon layer 14 and the edge 21a on the side of the chip center of the field oxide layer 21 As a "reserve," the third embodiment can be used instead of the first. In this case, one of the four edges of the semiconductor substrate 50 at least at one edge, where the positional relationship between the polysilicon layer 14 and the edge 21a on the side of the chip center of the field oxide layer 21 a “reserve”, the Mesa rim 53c' level 53 sufficient to be inclined to form an obtuse angle with respect to the first surface 53a the end face of the semiconductor substrate 50to form.

[0089] As described above, the first to fourth embodiments are applicable to the fifth embodiment.

[0090] For the foregoing, the present invention is not limited to the embodiments described above, and various modifications are possible within a range that does not deviate from the inventive concept. The present invention is, for example, also applicable to vertical semiconductor devices with a MOS gate, such as a planar gate MOSFET, an insulated gate bipolar transistor (IGBT), etc., and exhibits similar effects.

[0091] The silicon carbide semiconductor device according to the present invention achieves an effect insofar as a step due to the oxide layer in the surface of the polysilicon layer does not occur, thereby preventing a concentration of the electric field near the inner circumferential edges of the polysilicon layer and thus making it possible to prevent dielectric breakdown.

[0092] As described above, the silicon carbide semiconductor arrangement according to the present invention is useful for vertical semiconductor arrangements with a MOS gate and is particularly suitable for a vertical MOSFET with a trench-gate structure.

[0093] Although the invention has been described for a complete and clear disclosure with respect to a specific embodiment, the attached claims are not to be limited by this, but are to be interpreted as embodying all modifications and alternative constructions that may occur to a person skilled in the art in this field which appropriately fall within the basic teaching set forth herein. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2018206873

[0024] JP 2018117016 [0024, 0025] JP 2014175314 [0024, 0025]

Claims

[1] A silicon carbide semiconductor device comprising: an active area; a termination area provided at one edge of the active area; a semiconductor substrate containing silicon carbide; an insulated gate structure provided on one side of a front surface of the semiconductor substrate, wherein the insulated gate structure is provided in the active region and includes a metal-oxide-semiconductor field-effect transistor formed by a 3-layer structure of a metal, an oxide layer, and a semiconductor, wherein the semiconductor substrate includes a semiconductor layer of a first conductivity type that configures a drift region of the metal-oxide-semiconductor field-effect transistor, and a semiconductor layer of a second conductivity type provided on the end surface side of the semiconductor substrate and on the semiconductor layer of the first conductivity type, the semiconductor layer of the second conductivity type configuring a base region of the metal oxide semiconductor field effect transistor; a trench provided on the end face side of the semiconductor substrate and extending in a first direction parallel to an end face of the semiconductor substrate; an insulating layer provided on the side of the end face of the semiconductor substrate, a gate electrode of the metal oxide semiconductor field effect transistor provided in the trench via the insulating layer; a high-concentration second conductivity type region provided in a surface region on the end face side of the semiconductor substrate in the termination region, the high-concentration second conductivity type region forming a second conductivity type junction with the second conductivity type semiconductor layer, the high-concentration second conductivity type region having an impurity concentration higher than an impurity concentration of the second conductivity type semiconductor layer; a first gate polysilicon layer provided via the insulating layer on the end face of the semiconductor substrate in the termination region and facing the second conductivity type high-concentration region via the insulating layer in a depth direction, the first gate polysilicon layer surrounding the periphery of the active region and having a rectangular ring shape, the first gate polysilicon layer being electrically connected to the gate electrode at one end of the trench; and a field oxide layer provided over the insulating layer on the end face of the semiconductor substrate in the termination region, the field oxide layer surrounding a periphery of the first gate polysilicon layer and having a rectangular ring shape with four side portions, two of which extend in the first direction and the other two in a second direction orthogonal to the first direction, wherein at least one side portion of the field oxide layer extending in the second direction is arranged from an outer periphery of the termination region toward the active region in the first direction, wherein a nearest edge to the active region of the at least one side portion is located at a position farther from the active region than a position of a farthest edge from the active region of the first gate polysilicon layer. [2] The silicon carbide semiconductor device according to claim 1, wherein at least one side portion of the field oxide layer extending in the first direction is arranged from the outer periphery of the termination region toward the active region in the second direction, wherein a nearest edge to the active region of the at least one side portion extending in the first direction is located at a same position as a nearest edge of the active region of the first gate polysilicon layer. [3] The silicon carbide semiconductor device according to claim 2, wherein the at least one side portion includes the two side portions of the field oxide layer extending in the first direction and each arranged from the outer periphery of the termination region toward the active region in the second direction, wherein a nearest edge to the active region of each of the two side portions extending in the first direction is located at the same position as the nearest edge from the active region of the first gate polysilicon layer. [4] A silicon carbide semiconductor device according to any one of claims 1 to 3, wherein a furthest edge from the active region of the high concentration second conductivity type region is located at a position closer to the active region than a position of a furthest edge from the active region of the second conductivity type semiconductor layer, and in at least two side portions of the field oxide layer extending in the second direction, a nearest edge to the active region of each of the two side portions extending in the second direction is located across the insulating layer in the depth direction on the semiconductor layer of the second conductivity type and is further from the active region than a position of the transition of the second conductivity type. [5] The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein an outer side edge of the first gate polysilicon layer is positioned within a planar surface of the second conductivity type high concentration region. [6] The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein an entire surface of the first gate polysilicon layer is flat. [7] A silicon carbide semiconductor device according to any one of claims 1 to 6, further comprising: a second gate polysilicon layer connected to the first gate polysilicon layer and provided via the insulating layer in the active region on the end face of the semiconductor substrate; and a gate pad provided on the second gate polysilicon layer via an interlayer insulating layer and electrically connected to the second gate polysilicon layer, wherein a region between the end face of the semiconductor substrate and the second gate polysilicon layer without the field oxide layer. [8] A silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the insulating layer is a high-temperature oxide layer or a thermal oxide layer, the field oxide layer is a silicon oxide layer, and the field oxide layer has a thickness that is greater than a thickness of the insulating layer.

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