Circuit diagram for low-offset switching capacitor integer

Abstract

a switching capacitor integrator circuit comprising an amplifier, at least one input capacitor configured to receive at least one input signal and transmit it to the input of the amplifier, and at least one capacitor coupled to the amplifier in a feedback configuration, wherein the switching capacitor integrator circuit comprises: at least one compound switch coupled between a corresponding plate of the at least one input capacitor and the input of the amplifier, wherein the at least one compound switch comprises a parallel combination of: a first transistor with a first width;and a second transistor with a second width that is larger than the first width, wherein a control circuit is configured to control the operation of the first and second transistors of the at least one compound switch such that, while the first transistor is closed, the second transistor is opened and then the first transistor is opened.

Description

CLAIM OF PRIORITY

[0001] The present application claims priority over the preliminary US patent application number 62 / 815,944, entitled “SWITCHING SCHEME FOR LOW OFFSET SWITCHED-CAPACITOR INTEGRATORS”, filed on March 8, 2019, by Italo Carlos Medina Sänchez Castro et al., the entire contents of which are incorporated herein by reference. AREA OF REVELATION

[0002] This document concerns, but is not limited to, integrated circuits and, in particular, switching capacitor circuits. GENERAL STATE OF THE ART

[0003] Switching capacitor circuits typically feature switches and capacitors, often in conjunction with amplifiers, in arrangements designed to implement specific input-to-output transfer functions. For example, switching capacitor circuits can be used to implement gain stages, filters, digital-to-analog converters, and many other types of circuits. The switches in switching capacitor circuits are selectively turned on and off by clock signals to realize the transfer functions.

[0004] Switching capacitor circuits have gained widespread use due to advances in CMOS (Complementary Metal Oxide Semiconductor) technology. CMOS technology is commonly used to implement switching capacitor circuits because of the availability of field-effect transistor (FET) switches and operational amplifiers with low input bias currents. A common type of switching capacitor circuit is a switching capacitor integrator. Such CMOS switching capacitor integrator circuits typically include switches, capacitors, and operational amplifiers. BRIEF SUMMARY OF THE REVELATION

[0005] The present disclosure relates, inter alia, to a switching capacitor integrator, the contribution of which to the offset from the charge injection mismatch of switches connected to the summing nodes is mitigated by using a switching scheme that basically directs all the charge injection to the output, thereby preventing the integration of a net offset.

[0006] In some aspects, the present disclosure relates to a switching capacitor integrator circuit comprising an amplifier, at least one input capacitor configured to receive at least one input signal and transmit it to the input of the amplifier, and at least one capacitor coupled to the amplifier in a feedback configuration, wherein the switching capacitor integrator circuit comprises: at least two switches coupled to each plate of the at least one input capacitor, wherein at least one of the at least four switches comprises a compound switch, comprising a parallel combination of: a first transistor having a first width;and a second transistor with a second width greater than the first width, wherein a control circuit is configured to control the operation of the first and second transistors of the at least one compound switch such that, while the first transistor is closed, the second transistor is opened and then the first transistor is opened.

[0007] In some aspects, the present disclosure relates to a method for operating a switching capacitor integrator circuit comprising an amplifier, at least one input capacitor configured to receive at least one input signal and transmit it to the input of the amplifier, at least one capacitor coupled to the amplifier in a feedback configuration, and at least two switches coupled to each plate of the at least one input capacitor, wherein at least one of the at least four switches comprises a link switch, the method comprising: controlling the operation of the link switch with a parallel combination of: a first transistor having a first width and a second transistor having a second width greater than the first width, comprising: turning off the second transistor while the first transistor is turned on, and then turning off the first transistor.

[0008] In some aspects, the present disclosure relates to a switching capacitor integrator circuit comprising an amplifier, an input capacitor configured to receive an input signal, and a capacitor coupled to the amplifier in a feedback configuration, wherein the switching capacitor integrator circuit comprises: at least one compound switch coupled to a plate of the input capacitor, the compound switch comprising a parallel combination of: a first transistor having a first width; and a second transistor having a second width greater than the first width, wherein the at least one compound switch is configured to be coupled between an input of the amplifier and the input capacitor.

[0009] This brief description is intended to provide an overview of the subject matter of the present patent application. It is not intended to be an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application. List of characters

[0010] In the drawings, which are not necessarily drawn to scale, the same numbers in different views may describe similar components. The same numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example but not as a limitation, various embodiments discussed in this document. Fig. Figure 1 is a schematic diagram of an example of a switching capacitor (SC) integrator. Fig. Figure 2 is a schematic diagram of an equivalence circuit of a section of the relevant SC network of the SC integrator of Fig. 1. Fig. Figure 3 is a schematic diagram of an equivalence circuit of a section of an SC integrator using various techniques of the present disclosure. Fig. Figure 4 is an example of a generalized compound switch that can be used to implement the parallel switching techniques of the present disclosure. Fig. Figure 5 is a schematic diagram of another example of a switching capacitor integrator that can implement the parallel switching techniques of the present disclosure. DETAILED DESCRIPTION

[0011] The analog integrator is a widely used signal processing block. The switching capacitor (SC) implementation of the integrator is particularly popular for field-effect transistor (FET) technology due to its advantages in accuracy and versatility. Integrators can generally be sensitive to offset because they integrate naturally over time, which can lead to inaccurate results and potentially saturate the device.

[0012] In the case of FET-SC integrators, the effect of most offset sources is effectively canceled by prior art techniques. The potential offset contributed by the mismatch during charge injection of the switches connected to the summing nodes of the FET-SC integrator is mitigated in the prior art by trading in settling time or by averaging its effect over time, rather than intrinsically canceling it out, as would be preferred in many situations.

[0013] An underlying problem, not satisfactorily solved in the prior art, is a trade-off between the magnitude of the offset contribution associated with the charge injection mismatch and the settling time effect of the corresponding switches. The present disclosure presents a technique that intrinsically mitigates this offset contribution without sacrificing settling time.

[0014] The present disclosure relates, inter alia, to a switching capacitor integrator, the contribution of which to the offset from the charge injection mismatch of switches connected to the summing nodes is mitigated by using a switching scheme that basically directs all the charge injection to the output, thereby preventing the integration of a net offset.

[0015] Fig. Figure 1 is a schematic diagram of an example of a switching capacitor integrator. The one in Fig. The example shown is a fully differential implementation of an SC integrator.

[0016] The operation of the SC integrator, like any SC circuit, is based on the use of switches to force voltages across capacitors. Since FET technology allows for competitive implementations of both switches and capacitors, SC circuits are particularly attractive for embodiments in FET and related technologies. Therefore, the present disclosure relates primarily to such technologies.

[0017] The fully differential SC integrator circuit 10 in Fig. 1 can be formed by an amplifier (amp) 12, which is configured in a negative feedback configuration through some feedback capacitors C op , C on works, which between the output nodes V op , V on and the summing nodes V sp , V snare switched, and an SC input network that takes a charge from the differential input V i = V ip - V in V i = V ip - V in a charge at V sp , V sn transmits. The feedback capacitors C op C op C op , C on retain the state of the differential output V i = V ip - V in V i = V ip - V in V o = V op - V on V o = V op - V on of the integrator.

[0018] A set of switches, e.g. transistors, connects the right-hand side (RHS) terminals of the input capacitors C. ip C ip V i = V ip - V in V i = V ip - V in with the summing nodes V sp , V sn These switches are known as RHS switches. 14 marked.

[0019] Another set of switches, e.g. transistors, connects the left-hand (LHS) terminals of V i = V ip - V in V i = V ip - V in with the input connections V i = V ip - V in v i = V ip - V in V ip ,V in V ip ,V in These switches are known as LHS switches. 16 marked.

[0020] As with any single-coil circuit, operation is controlled by at least two non-overlapping clock phases to prevent unwanted charge loss from the relevant capacitors. These clock phases are in Fig. The phases are labelled p1 and p2, and further distinguished between RHS phases (labelled p1r and p2r) and LHS phases (labelled p1l and p2l). A complete clock cycle contains all these phases and defines a period T. CLK, which determines the operating frequency f CLK = 1 / T CLK (Sampling frequency) of the SC integrator is set.

[0021] The RHS phases p1r and p2r control the RHS switches. 14 on, while the LHS phases p1l, p2l the LHS switches 16 head towards.

[0022] In a given phase (in this case p2), V i = V ip - V in V i = V ip - V in in V i = V ip - V in v i = V ip - V in V ip ,V in V ip ,V in by connecting the LHS connector of V i = V ip - V in v i = V ip - V in C ip C ip V i = V ip - V in v i = V ip - V in and the RHS connection of V i = V ip - V in V i = V ip - V inwith the common-mode (CM) summing node voltage V SCM sampled. Therefore, a differential charge Q is used. i in V i = V ip - V in V i = V ip - V in sampled given by (assuming C ip = C in = C i ): Q i = C i ⋅ V i

[0023] In the next phase (in this case p1), Q i into the feedback capacitors C op , C on forced by the LHS connector of C ip , C in with the common-mode (CM) input voltage V 1CM and the RHS connection of C ip , C in with the summing nodes V sp , V sn is connected. This causes a difference step ΔV. o in the integrator output, which can be expressed as follows (assuming C op = C on = C o and applying equation 1): Δ V o = Q i C o = C i C o ⋅ V i

[0024] Consequently, the SC integrator has a discrete time operation in which the output V corresponding to time n is o (n) becomes available at the end of the corresponding clock cycle (in this case at the end of p1) and modifies the previously held output V o (n - 1) with the input V sampled during the previous phase i (n - ½) to: V o ( n ) = V o ( n − 1 ) + C i C o ⋅ V i ( n − 1 2 )

[0025] From equation (2) the ideal gain of the SC integrator is given by the ratio C i / C o the input and feedback capacitors were set.

[0026] If the switches are implemented using FET transistors, a charge Q is coupled into the switch terminals whenever its state changes. This less-than-ideal effect, called charge injection, is well-known and considered a prominent drawback of FET technology.

[0027] This charge Q is mainly formed by two components: the charge in the channel Q ch trapped charge and the through-charge Q clk due to gate-source coupling. Therefore, Q can be quantified as (where W is the width of the transistor, L is the effective length of the transistor, C ox The gate oxide capacitance per unit area is C ov , the gate-source overlap capacity per unit width, V GS the gate-source voltage is V TH the threshold voltage is V H the clock high voltage level and V L the clock low voltage level is): Q = Q ch ​​+ Q clk = W ⋅ L ⋅ C ox ⋅ ( VGS − VTH ) + W ⋅ C ov ⋅ ( VH − VL )

[0028] in Fig. Figure 1 shows the relative timing of p1r, p2r and illustrates the non-overlapping nature of these clock signals. The LHS phases p1l, p2l are typically a delayed version of the corresponding RHS phases p1r, p2r to capture the input-dependent charge injection (see Equation 4) of the LHS switches into the input capacitors C. ip , C in This is avoided by making them potential-free when switching between p1l and p2l. This technique, known as ground sensing, prevents the LHS charge injection from inducing nonlinearity and is widely used in switched-mode circuits. The RHS switch terminals are connected to a voltage V SCM held; therefore, their associated charge injection is essentially input-independent and only tends to cause an offset.

[0029] The sampling edge of a given phase is the one that opens the corresponding switch; by convention, the falling edge is assumed in this disclosure to be the sampling end. Since the sampling edge of p1r, p2r precedes that associated with the corresponding LHS phase p1l, p2l, the RHS sampling in each phase can be considered the effective sampling of the integrator. FET-SC integrator offset sources

[0030] In a well-designed, fully differential integrator, the offset is dominated by the mismatch of nominally identical components.

[0031] For fully differential FET-SC integrators, the relevant offset contributions in practice are: • The amplifier offset induced by transistor mismatches, which mainly exist in its input stage. • The LHS switch charge injection mismatch (which would also cause nonlinearity). • The RHS switch charge injection mismatch.

[0032] The offset ΔV os , integrated as a result of an error that occurs in the summing node in the form of a voltage V ε The value is proportional to the integrator gain ΔV. OS (V ε ∝ (C i / C o ) · V ε This is remarkable for the amplifier's offset. 12 the case.

[0033] The offset ΔV os , integrated as a result of an error that occurs in the summing node in the form of a charge Q ε The condition present (such as the RHS switch charge injection mismatch) is inversely proportional to the feedback capacitor C. o, ΔV os (Q ε ) ∝ V ε / C o .

[0034] The effect of each of the summing nodes Vsp , V sn injected charge Q p , Q n would ΔV os (Q p ,Q n ) ∝ (Q p - Q n ) / C o be; therefore, the resulting offset is proportional to the absolute charge mismatch ΔQ = Q p - Q n instead of the relative mismatch ΔQ / Q = (Q p - Q n ) / [(Q p + Q n ) / 2]. Consequently, increasing the nominal value of Q from Q would p ,Q n This would not be an effective method to minimize their effect (as is the case for quantities that depend on relative mismatches); instead, reducing Q would be more effective (assuming that the absolute mismatch ΔQ scales with Q, which is typically the case).

[0035] The effect of amplifier offset at the integrator output can be effectively mitigated by techniques such as chopping. The offset induced by charge injection mismatch from the RHS switches can be effectively canceled by ground sampling, as previously described.

[0036] The contribution to the offset due to charge injection mismatch of RHS switches can be minimized by any combination of the following approaches: • Increasing the size of the feedback capacitor C o (possibly proportional scaling of the input capacitor C) i , in order to maintain the same amplification). • Reducing the magnitude of the charge injection by decreasing the voltage overdrive V, as suggested by equation 4 GS - V TH and / or the gate area W · L (the latter being generally more practical). • Chopping the RHS switches at a frequency f RHS, to compensate for the offset induced by the RHS switch charge injection mismatch by averaging its integration with opposite polarities over consecutive chopper half-periods T RHS / 2 = 2 / f RHS to cancel.

[0037] Increasing C o implies increasing the settling time for a given power output.

[0038] Reducing V GS - V TH will also affect the settling time, because of the on-resistance R ON of the switch (approximately given by equation 5, where µ is the mobility of charge carriers) would increase proportionally. RON = 1 μ ⋅ C ox ⋅ WL ⋅ ( VGS − VTH )

[0039] Similarly, reducing W · L (after L is at its technological minimum, or equivalently reducing W · L at the expense of reducing W / L) with offset would trade for settling time for a given power.

[0040] The chopping of the RHS switches can be accomplished by a chopper and a dechopper around the values ​​specified at f RHS The operation of the RHS switch is implemented. This represents a significant overhead for the clock phase generation and the switch control circuitry of the SC integrator.

[0041] Since the chopper and dechopper switches are in series with the RHS switches, to restore the original settling time for a given power, the W · L of these switches can be dimensioned such that an equivalent on-resistance R ON The resulting value is comparable to that of the original RHS switches. Therefore, the absolute charge injection mismatch of the RHS switches (for a given settling time) increases, but its potential contribution to the integrator offset is mitigated by being reduced over a period T. RHS is averaged.

[0042] The switches of the chopper and dechopper also contribute to the offset through the mismatch in their charge injection. Therefore, to achieve a net offset improvement, the chopping frequency f must be increased. RHS be smaller than the sampling frequency f CLK , to determine the equivalent induced offset by a ratio f CLK / f RHS > 1 to reduce due to time averaging, making it acceptable.

[0043] In such a scheme lies the chopped offset component ΔV induced by the RHS switch charge injection mismatch. os in the SC integrator output V o as a rectangular waveform with frequency f RHS before.

[0044] The fact that f RHS < f CLK This implies that the component is not removed in every integration cycle (because this would f RHS = f CLK(would require). Therefore, the corresponding square waveform would be processed by the circuitry downstream of the integrator, potentially causing distortion. This technique relies on some post-processing to filter the generated offset tone or reduce its effect, which is generally not an attractive feature. To avoid this situation, the technique that cancels the RHS switch charge injection mismatch offset must be adapted to the sampling frequency f. CLK work.

[0045] Based on the above, the prior art techniques for mitigating the offset induced by RHS switch charge injection mismatch involve a direct trade-off between offset and settling time (for a given power and technology) and / or the presence of tones. A solution that addresses these shortcomings is desirable. Solution

[0046] The present disclosure describes a solution for mitigating the offset induced by the RHS switch charge injection mismatch, which can be dynamic (to also cancel offset drifts), at the sampling frequency f CLK can work (to avoid the presence of potentially unwanted tones) and can interrupt the previously established compromise between offset and settling time.

[0047] The effect of a charge injection mismatch in the offset of a typical SC integrator is analyzed in detail below. Without loss of generalization and to simplify the analysis, only the mismatch associated with the pair of RHS switches driven by p1r is considered. Furthermore, only the mismatched charge injection ΔQ is analyzed (since the usual charge injection in the integrated output has no net effect), arbitrarily assigning the entire mismatch to a single switch and thus assuming that the complementary switch does not contribute any charge injection. This is in Fig. 2 shown.

[0048] Fig. Figure 2 is a schematic diagram of an equivalence circuit of the relevant section of the SC (single-ended) network of the SC integrator of Fig. 1. In particular, it shows Fig. 2 a typical SC integrator RHS circuit for a section of the SC integrator circuit of Fig. 1.

[0049] The charge injection of switch sw1 is described next for the associated transitions of the clock signals. The relevant events in chronological order are: • p1r goes to L (scanning): a charge ΔQ1 is placed in C o injected (causes one step ΔV1 = ΔQ1 / C o in the integrator output V o ), and a charge ΔQ2 is injected into C, which is stored. • p2r goes to H (C i -RHS plate is reset): previously in C i The stored charge ΔQ2 is transferred to the AC mass V. SCM derived and therefore permanently lost. • p1r goes to H (the next integration phase begins): a charge ΔQ3 is transferred to C o injected (causes a new step ΔV3 = ΔQ3 / C o in the integrator output V o ), and a charge ΔQ4 is placed in C iThe signal is injected, but since the amplifier is reconnected by closing sw1, ΔQ4 is supplied by the amplifier (causing a step ΔV4 = ΔQ4 / C). o in V o ).

[0050] Therefore, the following offset ΔV o in the integrator output V o caused in each cycle by the charge injection mismatch of the RHS switches controlled by p1r: Δ V o = Δ V 1 + Δ V 3 + Δ V 4 = Δ Q 1 + Δ Q 3 + Δ Q 4 C o

[0051] The charge injection of a FET switch (given by equation 4) is divided between its two terminals (arbitrarily called drain and source). This division is not necessarily symmetrical and depends on a number of factors, such as the relative impedance of the terminals and the slope of the transition in the gate signal. To model this using a division factor 0 ≤ d ≤ 1, the charge injection QT of a FET switch under its terminals as Q d , Q s subdivided as follows: QT = Q d + Q s, Q d = (1 − d) ⋅ QT, Q s = d ⋅ QT

[0052] Furthermore, the charge injection Q T The magnitude of the signal at the gate of a FET switch during a falling and a rising transition is the same for given terminal voltages.

[0053] In the case of Fig. 2. These facts imply: Δ Q 1 + Δ Q 2 = − ( Δ Q 3 + Δ Q 4 )

[0054] If ΔQ2 were integrated instead of discharged, then ΔV o = 0 according to equation 7.

[0055] In other words, if the entire charge injected when opening and closing switch sw1 is integrated, the net effect at the integrator output V is o null and the charge injection mismatch associated with sw1 does not induce an offset.

[0056] A similar analysis can be performed for the RHS switch sw2, which is connected to the common mode (CM) summing node voltage V. SCM connected and in this case driven by p2r. The conclusion is the same, but instead of being the entirety of the integrated associated charge injection to account for the effect at V o To cancel would remove the entire charge injection from switch sw2 into V SCM discharged, and similarly at V o No offset is induced. Therefore, the result obtained can be applied to any RHS switch.

[0057] The following principles are derived from the above description, in conjunction with the offset induced by the charge injection mismatch of RHS switches in an SC integrator: I. The induced offset depends on the absolute charge injection mismatch; and II. If the entire charge injection of the RHS switches is integrated, the net effect at the integrator output is zero.

[0058] Taking these two principles into account, the following solution is proposed to mitigate the offset induced by the charge injection mismatch of RHS switches without affecting the settling time: Add a smaller switch in parallel with the main, regular-sized RHS switch and drive it so that it opens only after the main switch has opened, thus integrating all the charge injection from the main RHS switch. Consequently, the residual set depends on the absolute charge injection mismatch of the smaller switch, which will be smaller (by Equation 4) than that caused by the main, regular-sized RHS switch. A possible effect on the equivalent settling time caused by this technique can be mitigated by appropriately sizing the relative impedance (by the aspect ratio W / L) of both switches and the delay T. DLYbetween the opening edge of their controlling signals are mitigated.

[0059] Fig. Figure 3 is a schematic diagram of an equivalence circuit of a section of an SC integrator using various techniques of the present disclosure. In particular, and according to this disclosure, it shows Fig. 3. An SC integrator RHS parallel circuit scheme that uses a smaller switch in parallel with the main RHS switch of regular size and controls it such that it opens only after the main RHS switch has opened, so that the entire charge injection of the main RHS switch is integrated. These two switches, e.g., transistors, together form what the present disclosure refers to as a "compound switch," which is a parallel combination of a first transistor (switch sw1s) with a first width (W / s) and a second transistor (switch (sw1f)) with a second width (W). f) is larger than the first width. As described below, a compound switch can be formed from more than two transistors.

[0060] The RHS switch sw1 of Fig. 2 is controlled by the parallel combination of a switch sw1s with a width scaled down by a factor s (e.g. W / s) and by the original phase p1r, and has been replaced by a switch sw1f controlled by a new phase p1rf, as shown in Fig. 3 can be seen. In some example training programs, the scaling factor lies within a range of 5 and 20 Including. Again, this parallel combination is referred to in the present disclosure as a compound switch.

[0061] The timing of the switches is controlled by a control circuit. 20controlled. The control circuit is designed to switch the operation of the first switch sw1s and the second switch sw1f, e.g. transistors, of the compound switch in such a way that, while the first switch is closed, the second switch is opened and then the first switch is opened.

[0062] In some example implementations, the control circuit is configured to control the operation of the first switch using a first clock signal and to control the operation of the second switch using a second clock signal, where the first clock signal is different from the second clock signal. In some examples, the first clock signal, e.g., p1r, has a first active time, and the second clock signal, e.g., p1rf, has a second active time, where the second active time is shorter than the first active time.

[0063] The sw1s switch can be described as a slow switch because its bandwidth W / s is reduced by a scaling factor s compared to the regular RHS switch sw1. Fig. Since 2 is smaller, its impedance is larger by the same factor s (according to equation 5). Accordingly, its charge injection is smaller than that associated with switch sw1 by the scaling factor s (according to equation 4). This is in Fig. 3 represented by labeling the associated charges with the lowercase letter Δq i The switch sw1s is controlled by the original phase p1r, and thus it dictates the sampling event in the integrator operation.

[0064] The switch sw1f can be described as a fast switch because its impedance is smaller compared to that associated with the slow switch sw1s, since its width W f is larger (W f> W / s). It is controlled by a new phase p1rf, generated by p1r, but with the opening edge pre-adjusted by a time delay T. DLY (as in the qualitative timing diagram of Fig. 3 shown).

[0065] The charge injection of the equivalent switch formed by sw1s and sw1f is described next for the associated transitions of the clock signals. The relevant events are, in chronological order: • p1rf goes to L: a charge ΔQ1 is transferred to C o injected (causes one step ΔV1 = ΔQ1 / C o in the integrator output V o ), and a charge ΔQ2 is placed in C o injected with the help of sw1s, which is closed (causes a step ΔV2 = ΔQ2 / C). o in the integrator output V o ), • p1r goes to L (scanning): a charge Δq1 is C o injected (causes one step Δv1 = Δq1 / C o in the integrator output Vo ) and a charge Δq2 is placed in C i injected, which is stored. • p2r goes to H (the C i -RHS plate is reset): previously in C i The stored charge Δq2 is transferred to the AC mass V. SCM The discharge is thus permanently lost. • p1r and pr1f go to H (the next integration phase begins): a charge ΔQ3 is converted to C o injected (causes one step ΔV3 = ΔQ3 / C o in the integrator output V o ) and a charge ΔQ4 is placed in C i injected, but since the amplifier is reconnected by closing sw1f and sw1s, ΔQ4 is supplied by the amplifier (causing a step ΔV4 = ΔQ4 / C). o in V o ); a charge Δq3 is placed in C o injected (causes one step Δv3 = Δq3 / C o in V o ), and a charge Δq4 is placed in C iinjected, but since the amplifier is reconnected by closing sw1f and sw1s, Δq4 is supplied by the amplifier (causing a step Δv4 = Δq4 / C). o in V o ).

[0066] Therefore, the following offset ΔV' o in the integrator output V o caused in each cycle by the charge injection mismatch of the equivalent RHS switches: Δ V o ' = V 1 + V 2 + v 1 + V 3 + V 4 + v 3 + v 4 = Δ Q 1 + Δ Q 2 + Δ q 1 + Δ Q 3 + Δ Q 4 + Δ q 3 + Δ q 4 C o

[0067] Applying equation 8 to sw1f cancels out the net effect of the associated charge injection. Thus, equation 9 simplifies to: Δ V o ' = Δ q 1 + Δ q 3 + Δ q 4 C o

[0068] Assuming, without loss of generality, that the division factor d of the sw1s charge injection is the same as that for sw1 in Fig. 2, the ratio of the induced offsets for both approaches (from equations 10, 8 and 6) is: Δ V o ' Δ V o = Δ q 1 + Δ q 3 + Δ q 4 Δ Q 1 + Δ Q 3 + Δ Q 4

[0069] Since the only difference between the two switches is the scaling of the width, as previously described (the width of sw1 is W / s if the width of sw1 is W), equations 4 and 11 yield: ΔV o ' = ΔV os

[0070] Therefore, an SC integrator with the new approach (in Fig. 3 shown and referred to as a parallel switching technique) implemented RHS switch a reduction in offset ΔV' o which is induced by the RHS switch charge injection mismatch, compared to the traditional approach (in Fig. Figure 2 shows that the ratio s of the width (or more generally gate areas) of the RHS switch performing the sampling in each case is proportional to the ratio s of the width (or more generally gate area) of the RHS switch (sw1s in Fig. 3 for parallel switching technology and sw1 in Fig. 2 for the traditional approach).

[0071] A similar analysis can again be performed by applying the parallel switching technique to the RHS switch sw2 in Fig. 3. The conclusion is the same, but instead of all the associated charge injection components of sw2 being integrated to determine their effects at V. o to cancel, everyone in V can SCM be unloaded.

[0072] Thus, the result obtained can be applied to any RHS switch in an SC integrator.

[0073] For convenience, these results were derived under the assumption of a systematic mismatch in charge injection. For the more relevant case of a random mismatch, the principles can be directly extended, and the corresponding analysis yields a reduction in the induced offset, given by s (assuming the realistic case of a normal distribution of the charge injection random mismatch).

[0074] The quick switch (swlf in Fig. 3) is only closed during a fraction of the p1r phase (as due to the time delay T). DLY dictated). Its function is to allow the transfer of most of the input charge before it opens, the moment when the slow switch (sw1s in Fig. 3) the fine settling during the remainder of the p1r phase (T DLY ) closes before opening for scanning.

[0075] To obtain an equivalent settling time comparable to that achieved by the Fig. For the approach shown in point 2 to be achieved, the on-resistance of sw1f must be smaller than the on-resistance of sw1. Similarly, the width W f sw1f should be larger than those with sw1 W f associated (W f > W).

[0076] Since the offset induced by the charge injection mismatch does not depend on sw1f (equation 10), W can f (together with the time delay T DLY ) are dimensioned such that the desired settling time can be provided without affecting the resulting offset. Therefore, the trade-off between the offset induced by the charge injection mismatch and the settling time is effectively solved by the parallel switching technique of the present disclosure, which operates at the sampling frequency f. CLK works (thus avoiding potentially unwanted sounds).

[0077] The opening flank of sw1f (the phase p1rf goes into Fig. 3 on L) can cause a disturbance that is caused by sw1s during T DLYThe sw1f gate must be synchronized with the fine transient response of the input signal charge transfer. Therefore, the sw1f gate opening should occur sufficiently before the effective sampling (opening edge of sw1s) and / or the sw1f gate area should be small enough to limit the magnitude of the corresponding disturbance.

[0078] Both parameters can be dimensioned to obtain the desired transient power while keeping the sw1s gate area as small as required (or equivalently dimensioning the scaling factor as aggressively as required) to simultaneously obtain a residual offset as low as desired.

[0079] The increase in power, area and complexity brought about by implementing the corresponding RHS switches using the described parallel switching technique (by Fig. 3 shown), compared to the other approach (in Fig. 2 shown), is negligible in practice and is dominated by the generation and routing of the additional clock signal p1rf (which is p1r with the sampling edge pre-adjusted by a given time interval).

[0080] Fig. Figure 4 is an example of a generalized compound switch that can be used to implement the parallel switching technique of the present disclosure. A more gradual operation of the parallel switching technique can be obtained by considering a number P of fast switches in parallel with the slow switch sw1s.

[0081] In Fig. 4 can be an array of fast switches sw1f <p:1>through its own clock signals p1rf <p:1>via a control circuit 30 can be controlled. The array of fast switches sw1f <p:1>opens sequentially during sampling, providing the same operation as the parallel switching technique described above, but with more flexibility to manage the disturbance of fast switching.

[0082] The closer the opening edge of a given fast switch sw1f at the sampling edge of the slow switch sw1s (that is, the smaller the associated delay T DLY_i The smaller the gate area (in practice the width W), the smaller its corresponding gate area can be. i ) are advantageously dimensioned to cause less charge injection and thus a smaller transient disturbance. This is feasible because, the closer to the sampling edge a sw1f The more it opens, the less it has to contribute to the remaining rough oscillation, since the charge transfer would be more complete and thus the required on-resistance of sw1f the smaller it is, which is a smaller W i permitted.

[0083] Consequently, an optimized transient response for a given residual level, defining the scaling factor s, can be achieved by correctly dimensioning the sw1f. <p:1>-Gate area (essentially the width W) P ,..., W1) and the sampling edge delay T DLY_P , ..., T DLY_P will be obtained.

[0084] A beneficial scaling law can be followed to determine the width W. i and the time intervals T DLY_i to measure, where a natural choice is the following relationships: W P < ... < W1 and T DLY_P < ... < T DLY_1 (In other words, the smaller the gate area of ​​a given slow switch, the closer it opens to the sampling point.) In practice, one or two additional switching levels (P ≤ 3) may suffice to achieve the required improvement over the one in Fig. to obtain the approach shown in point 2.

[0085] For example, the slow switch sw1s, e.g. a first transistor, can have a width W / s, a first fast switch sw1f(1), e.g. a second transistor, can have a width of W / s1, and a second fast switch sw1f(2), e.g. a third transistor, can have a width of W / s2, where W / s < W / s1 < W / s2 (s>s1 >s2) if the second transistor opens after the third transistor and both the second and third transistors open before the first transistor.

[0086] The parallel switching technique has been presented in the context of a typical fully differential single-coil integrator. However, the technique could be applied to any single-coil integrator topology by replacing the corresponding RHS switches with the one described in [reference to relevant section]. Fig. 3. Approach shown (or its modification by Fig. 4 generalization shown).

[0087] The technique can be directly applied to any single-mode integrator, implying no modification to the structure and operation of the RHS switches described as an example in this disclosure. For example, the integrator can operate differentially against the opposite input instead of the common-mode input. ICM scan (than the one described above and in Fig. (1 instance shown). In such a case, the parallel connection technique would be applicable.

[0088] The technique is particularly important and directly applicable even in cases where the structure and / or operation of the SC integrator's RHS switches differ from that described as an example in this disclosure. For example, the integrator can integrate during both phases instead of only during one phase (as previously described and in Fig. (Instance 1 shown) by doubling the input branches (and thus the complementary RHS switches). In this case, the parallel switching technique would be applied equally to all the RHS switches based on the same described principles and would potentially achieve the same improvements.

[0089] Parallel switching technology is also directly applicable to single-ended conversions, since it does not rely on the differential nature and / or differential operation of its components as its operating principle.

[0090] The application of parallel switching technology can be extended to other switches connected to the summing nodes of an SC integrator, whose charge injection can ultimately be directed to the output, such as: • The RHS switches of SC branches that are connected to a reference voltage instead of an input voltage; for example, the digital-to-analog converter (DAW) branches in an integrator of a discrete-time sigma-delta modulator that handles the feedback. • The RHS switches of SC branches are connected to a calibration voltage instead of an input voltage to adjust offset, gain error, or any other metric of the integrator. • The input chopper switches of the integrator's amplifier, possibly used to mitigate its offset and / or low-frequency noise.

[0091] In general, the parallel switching technique presented in the present disclosure is advantageously applicable (with minor differences) to any switch connected to the summing node of an SC integrator, particularly if the switch is operated cyclically.

[0092] The disclosure has focused on the important case of integrated circuits (ICs); however, the principles are equally applicable to discrete circuit implementations of SC integrators.

[0093] In a non-limiting specific example of an implementation, the switching capacitor integrator of the present disclosure can be used in a sigma-delta analog-to-digital converter. A non-limiting example of a sigma-delta analog-to-digital converter using a switching capacitor integrator is described in U.S. Patent No. 9,124,290 granted to Sherry et al., entitled "Method and Apparatus for Separating the Reference Current from the Input Signal in Sigma Delta Converter," the entire contents of which are incorporated herein by reference.

[0094] Fig. Figure 5 is a schematic diagram of another example of a switching capacitor integrator that implements the parallel switching techniques of the present disclosure.

[0095] The fully differential SC integrator circuit 40 in Fig. 5 can be formed by an amplifier (amp) 42, which is configured in a negative feedback configuration through some feedback capacitors C op , C on works, which between the output nodes V op , V on and the summing nodes V sp , V sn , are switched, and an SC input network that applies a charge from the differential input Vi=Vip-Vin to a charge at V sp , V sn transmits. The feedback capacitors CopC op , C on retain the state of the differential output Vi=Vip-VinVo=Vop-Von of the integrator.

[0096] A set of switches, e.g. transistors, connects the right-hand (RHS) terminals of the input capacitors CipVi=Vip-Vin to the summing nodes V sp , V sn These switches are known as RHS switches. 42 marked. Another set of switches, e.g., transistors, connect the left-hand (LHS) terminals of Vi=Vip-Vin to the input terminals Vi=Vip-Vin Vip,Vin. These switches are known as LHS switches. 44 marked.

[0097] As in the Fig. As can be seen in the 5 example training shown, all of the RHS switches are, e.g., those that control the input capacitors G. ip , C in and the summing nodes V sp , V sn connect, through the proposed topology of Fig. 3 have been replaced with at least one fast switch and one slow switch in parallel, so that the differential integrator circuit 40 has at least one compound switch in each differential input branch. That is, each of the RHS switches of Fig. 1 has been replaced with a compound switch, which has a small, slow switch sw1s with a first width (W / s) and a larger, fast switch sw1f with a second width (W f ) greater than the first width, as shown in the enlarged section 46 shown. In some example training programs, the scaling factor s lies within a range of 5 to 20 inclusive.

[0098] Switch sw1s is controlled by phase p1r, and switch sw1f is controlled by phase p1rf, as shown in Fig. 5 can be seen. The timing of the switches is controlled by a control circuit. 48 controlled. The control circuit is designed to control the operation of the first and second switches, e.g. transistors, of the compound switch in such a way that, while the first switch sw1s is closed, the second switch sw1f is opened and then the first switch sw1s is opened.

[0099] Additionally or alternatively, in some example training scenarios, the parallel switching technique can be applied to one or more of the LHS switches, e.g. 16 in Fig. 1, be applied.

[0100] In some example configurations, a compound switch can be coupled between an input-independent voltage and an input capacitor, thereby, for example, the voltage determined by p2r in Fig. 1 controlled RHS switch can be replaced, as in Fig. 5 shown. Notes

[0101] According to one aspect, a switching capacitor integrator is described whose contribution to the offset from the charge injection mismatch of switches connected to the summing nodes is mitigated by using a switching scheme that basically directs all the charge injection to the output, thereby preventing the integration of a net offset.

[0102] Each of the non-restrictive aspects or examples described herein can stand alone or can be combined in various permutations or combinations with one or more of the other examples.

[0103] The above detailed description refers to the accompanying drawings, which form part of the detailed description. The drawings illustrate predetermined embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors of the present invention also consider examples in which only those elements shown or described are provided.Furthermore, the inventors of the present invention also consider examples that use any combination or permutation of those elements shown or described (or one or more aspects thereof) either with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0104] In the event of inconsistent usage between this document and any documents incorporated by reference, the usage in this document shall prevail.

[0105] In this document, the expressions "a / an / an" are used, as is customary in patent documents, to include one or more than one, irrespective of any other instances or uses of "at least one" or "one or more". In this document, the expression "or" is used to refer to a non-exclusive "or", so that "A or B" includes "A but not B", "B but not A", and "A and B" unless otherwise specified. In this document, the expressions "with" and "in which" are used as the equivalents of the respective expressions "exhibiting" and "whereby" in plain English.Furthermore, in the following claims, the terms "with" and "comprising" are open, meaning that a system, device, article, composition, formulation, or process containing elements in addition to those listed in a claim under such a term will still be considered to fall within the scope of protection of that claim. Additionally, in the following claims, the terms "first," "second," and "third," etc., are used merely as designations and are not intended to impose any numerical requirements on their objects.

[0106] The method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable or machine-readable medium encoded with instructions that can be executed to train an electronic device to perform procedures as described in the examples above. An implementation of such procedures may include code such as microcode, assembly language code, higher-level language code, or the like. Such code may contain computer-readable instructions for performing various procedures. The code may form sections of computer program products. Furthermore, in one example, the code may be physically stored on one or more volatile, non-transient, or non-volatile physical computer-readable media, such as during execution or at other times.Examples of these physical, computer-readable media include hard drives, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or flash drives, random access memory (RAM), read-only memory (ROM), and the like. The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, as would be the case for a person skilled in the art when considering the above description. The summary is provided in compliance with 37 CFR §1.72(b) so that the reader may quickly ascertain the nature of the technical disclosure. It is provided with the understanding that it is not used to interpret or limit the scope or meaning of the claims. Furthermore, various features may be grouped together in the above detailed description to simplify the disclosure. This should not be interpreted as implying that any unclaimed disclosed feature is essential to any claim.Rather, the subject matter of the invention may consist of fewer than all features of a particular disclosed embodiment. The following claims are hereby included in the detailed description as examples or embodiments, each claim constituting a separate embodiment in itself, and it is taken into consideration that such embodiments may be combined with one another in various combinations or permutations. The scope of protection of the invention should be determined with reference to the appended claims together with the full scope of protection of equivalents to which such claims are entitled. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62 / 815944

[0001] US 9124290

[0093]

Claims

[1] Switching capacitor integrator circuit comprising an amplifier, at least one input capacitor configured to receive at least one input signal and transmit it to the input of the amplifier, and at least one capacitor coupled to the amplifier in a feedback configuration, wherein the switching capacitor integrator circuit comprises: at least two switches coupled to each plate of the at least one input capacitor, wherein at least one of the at least four switches has a compound switch, comprising a parallel combination of: a first transistor with a first width; and a second transistor with a second width that is larger than the first width, wherein a control circuit is configured to control the operation of the first and second transistors of the at least one compound switch such that, while the first transistor is closed, the second transistor is opened and then the first transistor is opened. [2] Switching capacitor integrator circuit according to claim 1, wherein the second transistor has a width W and the first transistor has a scaled width (W / s), where s is a scaling factor. [3] Switching capacitor integrator circuit according to claim 2, wherein the scaling factor is within a range of 5 and up to and including 20. [4] Switching capacitor integrator circuit according to a preceding claim, wherein the at least one compound switch further comprises: at least one third transistor, wherein the at least one third transistor has a third width, wherein the at least one third transistor is parallel to the first and second transistors, and wherein the at least one third transistor is configured to be open while the first transistor is closed. [5] Switching capacitor integrator circuit according to a preceding claim, wherein the control circuit is configured to control the operation of the first transistor using a first clock signal and to control the operation of the second transistor using a second clock signal, wherein the first clock signal is different from the second clock signal. [6] Switching capacitor integrator circuit according to claim 5, wherein the first clock signal has a first active time and the second clock signal has a second active time and wherein the second active time is shorter than the first active time. [7] Switching capacitor integrator circuit according to a preceding claim, wherein the integrator circuit is a differential integrator circuit with at least one compound switch symmetrically in each differential input branch. [8] Switching capacitor integrator circuit according to a preceding claim, wherein the compound switch is configured to be coupled between an input of the amplifier and the at least one input capacitor. [9] Switching capacitor integrator circuit according to a preceding claim, wherein the compound switch is configured to be coupled between an input configured to receive at least one input signal and the at least one input capacitor. [10] Switching capacitor integrator circuit according to a preceding claim, wherein the at least one compound switch is configured to be coupled between an input-independent voltage and the at least one input capacitor. [11] Switching capacitor integrator circuit according to a preceding claim, in combination with a sigma-delta analog-to-digital converter circuit. [12] A method for operating a switching capacitor integrator circuit comprising an amplifier, at least one input capacitor configured to receive at least one input signal and transmit it to the input of the amplifier, at least one capacitor coupled to the amplifier in a feedback configuration, and at least two switches coupled to each plate of the at least one input capacitor, wherein at least one of the at least four switches is a compound switch, wherein the method comprises: Controlling the operation of the connecting switch with a parallel combination of: a first transistor with a first width, having a second transistor with a second width that is larger than the first width: Switch off the second transistor while the first transistor is switched on, and then switch off the first transistor. [13] Method according to claim 12, wherein the control of the operation of the at least one compound switch comprises: Applying an initial clock signal to the first transistor; and Applying a second clock signal to the second transistor, where the first clock signal is different from the second clock signal. [14] Method according to claim 13, wherein the application of the first clock signal to the first transistor comprises the application of the first clock signal for a first active time, and wherein the application of the second clock signal to the second transistor comprises the application of the second clock signal for a second active time, wherein the second active time is shorter than the first active time. [15] Method according to any one of claims 12 to 14, wherein the second transistor is switched off while the first transistor is switched on, and then the first transistor is switched off during a sampling phase, wherein the method further comprises: Switching on the first and second transistors to begin an integration phase. [16] Method according to any one of claims 12 to 15, wherein the control of the operation of the at least one compound switch comprises: Coupling of at least one compound switch between an input of the amplifier and the at least one input capacitor. [17] Method according to any one of claims 12 to 16, wherein the control of the operation of the at least one compound switch comprises: Coupling the at least one compound switch between an input configured to receive at least one input signal and the at least one input capacitor. [18] Method according to any one of claims 12 to 17, wherein the control of the operation of the at least one compound switch comprises: Coupling the at least one compound switch between an input-independent voltage and the at least one input capacitor. [19] Switching capacitor integrator circuit comprising an amplifier, an input capacitor configured to receive an input signal, and a capacitor coupled to the amplifier in a feedback configuration, wherein the switching capacitor integrator circuit comprises: at least one compound switch coupled to a plate of the input capacitor, the compound switch comprising a parallel combination of: a first transistor with a first width; and a second transistor with a second width that is larger than the first width, wherein at least one compound switch is designed to be coupled between an input of the amplifier and the input capacitor. [20] Switching capacitor integrator circuit according to claim 19, wherein the second transistor has a width W and the first transistor has a scaled width (W / s), where s is a scaling factor.