Semiconductor device and method for forming a semiconductor device

Abstract

Semiconductor device (100), comprising: a first multigate field-effect transistor, FET,(110) arranged over a substrate (190), wherein the first multigate FET (110) has a first active region (111) extending on a first horizontal plane (101); and a second multigate FET (120) arranged above the first multigate FET (110), wherein the second multigate FET (120) has a second active area (121) extending on a second horizontal plane (102) parallel to the first horizontal plane (101); wherein the first active area (111) and the second active area (121) do not completely overlap when viewed from a vertical direction (Z) perpendicular to the first horizontal plane (101); wherein a first projection (121') of the second active area (121) on the first horizontal plane (101) and the first active area (111) do not overlap; and wherein the first multigate FET (110) further comprises a first gate region (113) adjacent to a plurality of side surfaces of the first active region (111) and the second multigate FET (120) further comprises a second gate region (123) adjacent to a plurality of side surfaces of the second active region (121); and where the first gate area (113) and the second gate area (123) are the same gate area, so that they are connected.

Description

STATE OF THE ART

[0001] As the semiconductor industry continually strives for higher device density, higher performance, and lower costs, challenges have arisen from both manufacturing and design issues in the development of three-dimensional designs, such as a multigate field-effect transistor (FET) comprising a FinFET and a gate-all-around FET (GAA-FET). In a typical FinFET, a gate electrode borders three side surfaces of a channel region with a gate dielectric layer sandwiched between them. A complementary FET (CFET) typically comprises a bottom FET disposed over a substrate and a top FET disposed over the bottom FET. A gate structure comprising a gate dielectric layer and a gate electrode layer is usually formed around the channel region of the bottom and top FETs. Typically, the bottom FET is a FET of a first conductivity type (e.g.,n-type) and the top-side FET is a second conductivity type (e.g. p-type) that is different from the first conductivity type, or vice versa.

[0002] US 2009 / 0 050 941 A1 relates to a method for manufacturing a semiconductor device comprising forming a first frangible layer in a first single-crystalline semiconductor substrate by ion irradiation and bonding the first single-crystalline semiconductor substrate via an insulating substrate and forming a field-effect transistor using a second single-crystalline semiconductor layer.

[0003] US 2005 / 0 151 276 A1 relates to a static random access memory (SRAM) device comprising a bulk MOS transistor on a semiconductor substrate having a source / drain region formed therein and an insulating layer on the bulk MOS transistor, and a thin film transistor having a source / drain region on the insulating layer above the bulk MOS transistor.

[0004] US 2016 / 0211 276 A1 relates to methods for producing a semiconductor device comprising forming a first semiconducting material on a substrate and forming a second semiconducting material over the first semiconducting material, as well as forming a third semiconducting material over the second semiconducting material.

[0005] JP 2015-103 531 A relates to a CMOS-type semiconductor device comprising an N-channel and P-channel MISFET with a layered structure and source-drain regions each having different conductivity types provided on a part of the lower and upper semiconductor layers.

[0006] JP 2013-197 171 A relates to a MISFET having a structure in which source-drain regions are provided by self-alignment with a gate electrode and which are formed on the first semiconductor layer, and second semiconductor layers, a part of which is regulated by a second embedded insulating film, are provided by second interlayer insulating films which are stacked. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1A is a perspective diagram illustrating an example of a CFET in accordance with some embodiments. Fig. Figure 1B is a cross-sectional diagram showing the Fig. 1A, in accordance with some embodiments. Fig. 1C is another cross-sectional diagram showing the Fig. 1A, in accordance with some embodiments. Fig. 2 is a component diagram illustrating an example of a CFET in accordance with some embodiments. Fig. 3A is a perspective diagram illustrating an example of a CFET in accordance with some unclaimed examples. Fig. Figure 3B is a cross-sectional diagram showing the Fig. 3A illustrates the example CFET. Fig. 4 is a flow diagram illustrating an example of a method for forming a CFET in accordance with some embodiments. DETAILED DESCRIPTION

[0008] The invention results from the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition is for the purpose of simplification and clarity and does not in itself imply any relationship between the different embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0010] As transistor sizes shrink, conduction overload can become a challenge. In particular, a bottom FET of a complementary FET (CFET) has fewer conduction traces compared to a top FET. Poor internal conductivity can lead to a large chip area.

[0011] The present disclosure discloses an example CFET with active regions that do not completely overlap when viewed from above. Specifically, a top-side active region of a top-side FET and a bottom-side active region of a bottom FET do not completely overlap when viewed from above. Because the bottom FET's active region is not completely covered by the top FET's active region when viewed from above, more conduction flexibility of the bottom FET is provided. Therefore, the example CFET can increase internal conductivity and potentially reduce chip areas.

[0012] Fig. 1A, Fig. 1B and Fig. 1C show an example of a CFET 100 in accordance with some embodiments. In particular, Fig. 1A is a perspective view showing portions of the example CFET 100. Fig. Figure 1B is a cross-sectional view taken along a line X1-X1 of Fig. 1A corresponds. Fig. 1C is a cross-sectional view along a line X2-X2 of Fig. 1A.

[0013] As in Fig. As shown in Figure 1A, the example CFET 100 includes at least one bottom FET 110 and one top FET 120. In some embodiments, the bottom FET 110 is a bottom multigate FET. In some embodiments, the top FET 120 is a top multigate FET. In some embodiments, the bottom FET 110 and the top FET 120 are both FinFETs. In some embodiments, the bottom FET 110 and the top FET 120 are both GAA FETs.

[0014] The bottom FET 110 is mounted over a substrate 190 (in Fig. 1B). The bottom FET 110 includes at least a first active region 111, two metal contact regions 112, and a gate (i.e., poly) region 113. For example, the bottom FET 110 may include, among other things, the first active region 111, a metal contact region 112a, a metal contact region 112b, and a gate region 113a. In this embodiment, the first active region 111 is disposed on a first horizontal plane 101. The first horizontal plane 101 is in an XY plane that is perpendicular to the vertical direction (Z). The first active region 111 may define an active region where transistors may be constructed. In this embodiment, the first active region 111 is of a first conductivity type (e.g., n-type). It is noted that the first active region 111 may be of a second conductivity type (e.g., p-type).In this embodiment, metal contact regions 112a and 112b are disposed above the first active region 111. One of the metal contact regions 112a and 112b may serve as a source of the bottom FET 110, and the other may serve as a drain of the bottom FET 110. In one example, the metal contact region 112a may serve as a source of the bottom FET 110, whereas the metal contact region 112b may serve as a drain of the bottom FET 110. A source contact and a drain contact may be further disposed above the metal contact regions 112a and 112b to form a source terminal and a drain terminal of the bottom FET 110. In this embodiment, the gate region 113a is interposed between the metal contact regions 112a and 112b. The gate region 113a is adjacent to several (e.g., three or four) side surfaces of the first active region 111. The gate region 113a can serve as a gate of the bottom FET 110.A gate electrode may be further disposed around the gate region 113a to form a gate terminal of the bottom FET 110. It is noted that the bottom FET may include a different combination of components. It is noted that the bottom FET 110 may include, among other things, the first active region 111, a metal contact region 112b, a metal contact region 112c, and a gate region 113b.

[0015] On the other hand, the top-side FET 120 is arranged above the bottom FET 110. The top-side FET 120 includes at least a second active region 121, two metal contact regions 122, and a gate region (e.g., poly region) 123). For example, the top-side FET 120 may include, among other things, the second active region 121, a metal contact region 122a, a metal contact region 122b, and a gate region 123a. In this embodiment, the second active region 121 is arranged on a second horizontal plane 102. The second horizontal plane 102 is an XY plane perpendicular to the vertical direction (Z). The second horizontal plane 102 is above the first horizontal plane 101. The second active region 121 may define an active region where transistors may be constructed. In this embodiment, the second active region 121 is a second conductivity type (e.g., p-type).It is noted that the second active region 121 may be a first conductivity type (e.g., n-type). In this embodiment, the metal contact regions 122a and 122b are disposed over the second active region 121. One of the metal contact regions 122a and 122b may serve as a source of the top-side FET 120, and the other may serve as a drain of the top-side FET 120. In one example, the metal contact region 122a may serve as a source of the top-side FET 120, whereas the metal contact region 122b may serve as a drain of the top-side FET 120. A source contact and a drain contact may be further disposed over the metal contact regions 122a and 122b to form a source terminal and a drain terminal of the top-side FET 120. In this embodiment, the gate region 123a is inserted between the metal contact regions 122a and 122b. The gate region 123a is adjacent to several (e.g.three or four) side surfaces of the second active region 121. The gate region 123a may serve as a gate of the top-side FET 120. It is noted that the gate region 123a and the gate region 113a may be the same in this embodiment. In other words, the gate region 113a / 123a is connected rather than separate. A gate electrode may be further disposed around the gate region 123a to form a gate terminal of the top-side FET 120. It is noted that the top-side FET 120 may include a different combination of components. For example, the top-side FET 120 may include, among others, the second active region 121, a metal contact region 122b, a metal contact region 122c, and a gate region 123b. It should be noted that gate region 123b and gate region 123a may be the same in this embodiment. In other words, gate region 113b / 123b is connected rather than separated.

[0016] As in Fig. As shown in Figure 1A, a plurality of conductive lines 131 are arranged above the top-side FET 120. The plurality of conductive lines 131 are arranged on a third horizontal plane 103. The third horizontal plane 103 is in an XY plane perpendicular to the vertical direction (Z). The third horizontal plane 103 is above the second horizontal plane 102.

[0017] In some embodiments, a plurality of conductive lines 131 are metal traces 131, collectively referred to as a metal zero (Mo) layer. It is noted that a different number of metal traces 131 may be used as needed, and different configurations of metal traces 131 may be used as needed. Metal traces 131 may be used to connect various terminals of bottom FET 110 and top FET 120 as needed. For example, one of metal traces 131 may be electrically connected to a drain terminal (e.g., located above metal contact region 112b) of bottom FET 110.

[0018] As in Fig. 1A, the first active region 111 and the second active region 121 do not completely overlap when viewed from the vertical direction (Z), e.g., when viewed from above. In other words, a projection of the second active region 121 on the first horizontal plane 101 and the first active region 111 do not completely overlap. In the Fig. In the illustrated example shown in FIG. 1A, the second active region 121 has a projection 121' on the first horizontal plane 101. The projection 121' of the second active region 121 does not completely overlap with the first active region 111. In unclaimed examples, the projection 121' of the second active region 121 and the first active region 111 partially overlap. In embodiments according to the invention, the projection 121' of the second active region 121 and the first active region 111 do not overlap at all. In some embodiments, an area of ​​the first active region 111 is larger than an area of ​​the second active region 121. In some embodiments, the area of ​​the first active region 111 is equal to the area of ​​the second active region 121. In some embodiments, the area of ​​the first active region 111 is smaller than the area of ​​the second active region 121.

[0019] Cross-sectional views in Fig. 1B and Fig. 1C further illustrate the Fig. 1A shown example CFET 100. As shown in the cross-sectional view in Fig. 1B, the first active region 111 of the bottom FET 110 is disposed above a substrate 190 and on the first horizontal plane 101. The second active region 121 of the top FET 120 is disposed on the second horizontal plane 102, which is above the first horizontal plane 101. The plurality of conductive lines 131 (e.g., the plurality of metal traces 131) are disposed on the third plane 103, which is above the second horizontal plane 102. The second active region 121 has the projection 121' on the first horizontal plane 101. The projection 121' of the second active region 121 on the first horizontal plane 101 does not completely overlap with the first active region 111 when viewed in the X direction, such as from above.The second active region 121 does not intersect at least a portion of the first active region 111 (in this example, the entire first active region 111) and the plurality of conductive lines 131 in the vertical direction (Z). Therefore, more conduction flexibility of the bottom FET 110 is provided.

[0020] As shown in the cross-sectional view in Fig. As shown in Figure 1C, the bottom FET 110 includes, among other things, the first active region 111 and the gate region 113a in the first horizontal plane 101, which is adjacent to at least two side surfaces of the first active region 111. The second active region 121 includes the projection 121' on the first horizontal plane 101. The projection 121' of the second active region 121 on the first horizontal plane 101 does not completely overlap the first active region 111. Therefore, more conduction flexibility of the bottom FET 110 is provided, as explained above.

[0021] Fig. 2 shows an example assembly of a CFET 200 in accordance with some embodiments. Fig. 2 is a top view of the example CFET 200. As illustrated, the example CFET 200 includes at least a bottom FET 210 and a top FET 220. The bottom FET 210 is disposed above a substrate (not shown for clarity). The bottom FET 210 includes at least a first active region 211, two metal contact regions 212, and a gate region (e.g., poly region) 213c. In this embodiment, the first active region 211 is disposed on a first horizontal plane. The first horizontal plane is an XY plane perpendicular to the vertical direction (Z). The first active region 211 may define an active region where transistors may be constructed. In this embodiment, the first active region 211 is a first conductivity type (e.g., n-type). It is noted that in other examples, the first active region 211 may be a second conductivity type (e.g., p-type).In this embodiment, metal contact regions 212a and 212b are disposed over the first active region 211. One of the metal contact regions 212a and 212b may serve as a source of the bottom FET 210, and the other may serve as a drain of the bottom FET 210. In one example, metal contact region 212a may serve as a source of the bottom FET 210, whereas metal contact region 212b may serve as a drain of the bottom FET 210. A source contact and a drain contact may be further disposed over the metal contact regions 212a and 212b to form a source terminal and a drain terminal of the bottom FET 210. In this embodiment, the gate region 213c is interposed between the metal contact regions 212a and 212b. The gate region 213c is adjacent to several (e.g., three or four) side surfaces of the first active region 211. The gate region 213c may serve as a gate of the bottom FET 210.A gate electrode may be further disposed around gate region 213c to form a gate terminal of bottom FET 210. Note that other gate regions 213a, 213b, 213d, and 213e are parallel to gate region 213c and may be used as gates of other semiconductor devices (e.g., other CFETs), which are not shown for clarity.

[0022] On the other hand, the top-side FET 220 is arranged above the bottom FET 210. The top-side FET 220 includes at least a second active region 221, two metal contact regions 222, and a gate region (i.e., poly region) 223c. In this embodiment, the second active region 221 is arranged on a second horizontal plane. The second horizontal plane is in an XY plane perpendicular to the vertical direction (Z). The second horizontal plane is above the first horizontal plane. The second active region 221 may define an active region where transistors may be constructed. In this embodiment, the second active region 221 is a second conductivity type (e.g., p-type). It is noted that in other examples, the second active region 221 may be a first conductivity type (e.g., n-type). In this embodiment, the metal contact regions 222a and 222b are arranged above the second active region 221.One of the metal contact regions 222a and 222b may serve as a source of the top-side FET 220, and the other may serve as a drain of the top-side FET 220. In one example, the metal contact region 222a may serve as a source of the top-side FET 220, whereas the metal contact region 222b may serve as a drain of the top-side FET 220. A source contact and a drain contact may be further disposed over the metal contact regions 222a and 222b to form a source terminal and a drain terminal of the top-side FET 220. In this embodiment, the gate region 223c is interposed between the metal contact regions 222a and 222b. The gate region 223c is adjacent to multiple (e.g., three or four) side surfaces of the second active region 221. Gate region 223c may serve as a gate of top-side FET 220. Note that gate region 223c and gate region 213c may be the same in this embodiment.In other words, the gate region 213c / 223c is connected rather than separated. A gate electrode may be further disposed around the gate region 223c to form a gate terminal of the top-side FET 220.

[0023] A plurality of conductive lines 231 are arranged above the top-side FET 220. The plurality of conductive lines 231 are arranged on a third horizontal plane. The third horizontal plane is an XY plane perpendicular to the vertical direction (Z). The third horizontal plane is above the second horizontal plane 102. In some embodiments, a plurality of conductive lines 231 are metal traces 231, collectively referred to as a Mo layer. It is noted that a different number of metal traces 231 may be used as needed, and different configurations of the metal traces 231 may be used as needed. The metal traces 231 may be used for electrical connection to different terminals of the bottom FET 210 and the top FET 220 as needed. For example, the metal traces 231 may be used for electrical connection to a drain terminal (e.g.,arranged above the metal contact region 112b) of the bottom FET 110.

[0024] The first active region 211 and the second active region 221 do not completely overlap when viewed from the vertical direction (Z). In particular, a projection of the second active region 221 on the first horizontal plane does not completely overlap with the first active region 211 when viewed from above, as shown in Fig. 2. A portion of the first active region 211 that does not overlap with the projection of the second active region 221 on the first horizontal plane has a rectangular shape with a length L1 in the X direction and a length L2 in the Y direction. Due to the non-overlapping portion, the first active region 211 and the second active region 221 do not completely overlap when viewed from the vertical direction (Z). Accordingly, the metal contact region 212a and the metal contact region 222a do not completely overlap when viewed from the vertical direction (Z), whereas the metal contact region 212b and the metal contact region 222b do not completely overlap when viewed from the vertical direction (Z).

[0025] The second active region 221 does not pass between at least a portion of the first active region 211 (rectangular shape portion in this example) and the conductive line 231d in the vertical direction (Z). Likewise, the metal contact region 222a does not pass between at least a portion of the metal contact region 212a and the conductive lines 231d and 231e, whereas the metal contact region 222b does not pass between at least a portion of the metal contact region 212b and the conductive lines 231d and 231e. For example, the conductive line 231e may be electrically connected downward in the vertical direction (Z) to the metal contact region 212a (through a source / drain contact, not shown for clarity) without passing through the metal contact region 222a. Therefore, more conduction flexibility of the bottom FET 110 is provided.

[0026] Fig. 3A and Fig. 3B show an example of a CFET 300 in accordance with some unclaimed examples. In particular, Fig. 3A is a perspective view of the CFET 300. Fig. 3B is a cross-sectional view taken along a line X3-X3 of Fig. 3A.

[0027] As in Fig. 3A, the example CFET 300 includes at least a bottom FET 310 and a top FET 320. The bottom FET 310 is disposed over a substrate (not shown for clarity). The bottom FET 310 includes at least a first active region 311, two metal contact regions 312, and a gate (i.e., poly) region 313. In this example, the first active region 311 is disposed on a first horizontal plane 301. The first horizontal plane 301 is on an XY plane that is perpendicular to the vertical direction (Z). The first active region 311 may define an active region where transistors may be constructed. In this example, the first active region 311 is a first conductivity type (e.g., n-type). It is noted that in other examples, the first active region 311 may be a second conductivity type (e.g., p-type). In this example, the metal contact regions 312a and 312b are arranged above the first active region 311.One of the metal contact regions 312a and 312b may serve as a source of the bottom FET 310, and the other may serve as a drain of the bottom FET 310. In one example, the metal contact region 312a may serve as a source of the bottom FET 310, whereas the metal contact region 312b may serve as a drain of the bottom FET 310. A source contact and a drain contact may be further disposed over the metal contact regions 312a and 312b to form a source terminal and a drain terminal of the bottom FET 310. In this example, the gate region 313 is inserted between the metal contact regions 312a and 312b. The gate region 313 is adjacent to multiple (e.g., three or four) side surfaces of the first active region 311. The gate region 313 may serve as a gate of the bottom FET 310. A gate electrode may be further disposed around the gate region 313 to form a gate terminal of the bottom FET 310.

[0028] On the other hand, the top-side FET 320 is arranged above the bottom FET 310. The top-side FET 320 includes at least a second active region 321, two metal contact regions 322, and a gate region (i.e., poly region) 323. In this example, the second active region 321 is arranged on a second horizontal plane 302. The second plane is in an XY plane perpendicular to the vertical direction (Z). The second horizontal plane 302 is above the first horizontal plane 301. The second active region 321 may define an active region where transistors may be constructed. In this example, the second active region 321 is a second conductivity type (e.g., p-type). It is noted that in other examples, the second active region 321 may be a first conductivity type (e.g., n-type). In this example, the metal contact regions 322a and 322b are arranged above the second active region 321.One of the metal contact regions 322a and 322b may serve as a source of the top-side FET 320, and the other may serve as a drain of the top-side FET 320. In one example, the metal contact region 322a may serve as a source of the top-side FET 320, whereas the metal contact region 322b may serve as a drain of the top-side FET 320. A source contact and a drain contact may be further disposed over the metal contact regions 322a and 322b to form a source terminal and a drain terminal of the top-side FET 320. In this example, the gate region 323 is interposed between the metal contact regions 322a and 322b. The gate region 323 is adjacent to multiple (e.g., three or four) side surfaces of the second active region 321. Gate region 323 may serve as a gate of top-side FET 320. Note that gate region 323 and gate region 313 are separated rather than connected in this example.A gate electrode may be further disposed around the gate region 323 to form a gate terminal of the top-side FET 320.

[0029] A plurality of conductive lines (not shown for clarity) may be disposed above the top-side FET 320. The plurality of conductive lines are disposed on a third level (not shown for clarity) that is in an XY plane and above the second horizontal plane 302. In some embodiments, the plurality of conductive lines are metal traces, collectively referred to as a Mo layer.

[0030] As in Fig. 3A, a reference plane 304 is a YZ plane perpendicular to a horizontal direction (X). The first active region 311 has a distance D B with respect to the reference plane 304 in the X-direction. The second active region 321 has a distance D Twith respect to the reference plane 304 in the X direction. The first active region 311 has a width W B in the X-direction. The second active region 321 has a width W T in the X-direction. The relationships under D B , D T , W B and W T are made with reference to Fig. 3B discussed in detail.

[0031] As in Fig. 3B, the bottom FET 310 includes, among other things, the first active region 311 and the gate region 313 in the first horizontal plane 301, which is adjacent to at least two side surfaces of the first active region 311. The second active region 321 includes the projection 321' on the first horizontal plane 301. The projection 321' of the second active region 321 on the first horizontal plane 301 does not completely overlap the first active region 311. In other words, the first active region 311 and the projection 321' of the second active region do not completely overlap when viewed from the vertical direction (Z). The second active region 321 does not come between at least a portion of the first active region 311 (in this example, a portion 311a of the first active region 311 comprising two portions 311a and 311b) and the plurality of conductive lines in the vertical direction (Z).Therefore, more conduction flexibility of the ground FET 110 is created, as explained above.

[0032] In addition, in some embodiments, the distance D B be smaller than the distance D T In some embodiments, the distance D B the same as the distance D T In some embodiments, the distance D B be greater than the distance D T In some embodiments, the width W B smaller than the width W T In some embodiments, the width W B the same as the width W T In some embodiments, the width W B greater than the width W T In other words, different combinations of the relationship between D B and D T and the relationship between W B and W T are within the intended scope of the present disclosure.

[0033] Fig. 4 is a flow diagram illustrating an example of a method 400 for forming a semiconductor device such as that shown in Fig. 1A. In step 402, a first multigate FET is formed, such as the one shown in Fig. 1A, arranged above a substrate. The first multigate FET has a first active region extending along a first horizontal plane. In step 404, a second multigate FET is formed, such as the one shown in Fig. 1A, formed above the first multigate FET. The second multigate FET has a second active region extending on a second horizontal plane parallel to the first horizontal plane. The first active region and the second active region do not completely overlap when viewed from a vertical direction perpendicular to the first horizontal plane.

[0034] In accordance with some disclosed embodiments, a semiconductor device may be provided. The semiconductor device comprises, among other things: a first multigate field-effect transistor (FET) arranged over a substrate, the first multigate FET having a first active region extending on a first horizontal plane; and a second multigate FET arranged over the first multigate FET, the second multigate FET having a second active region extending on a second horizontal plane parallel to the first horizontal plane. The first active region and the second active region do not completely overlap when viewed from a vertical direction perpendicular to the first horizontal plane.

[0035] In accordance with some disclosed embodiments, a semiconductor device may be provided. The semiconductor device comprises, among other things: a substrate; a first multigate FET arranged above the substrate, the first multigate FET having a first active region extending on a first horizontal plane parallel to the substrate and having a first projection of the first active region on the substrate; and a second multigate FET arranged above the first multigate FET, the second multigate FET having a second active region extending on a second horizontal plane parallel to the substrate and having a second projection of the second active region on the substrate. The first projection and the second projection do not completely overlap.

Claims

[1] A semiconductor device (100) comprising: a first multigate field-effect transistor, FET, (110) disposed over a substrate (190), the first multigate FET (110) having a first active region (111) extending on a first horizontal plane (101); and a second multigate FET (120) disposed above the first multigate FET (110), the second multigate FET (120) having a second active region (121) extending on a second horizontal plane (102) parallel to the first horizontal plane (101); wherein the first active region (111) and the second active region (121) do not completely overlap when viewed from a vertical direction (Z) perpendicular to the first horizontal plane (101); wherein a first projection (121') of the second active region (121) on the first horizontal plane (101) and the first active region (111) do not overlap; and wherein the first multigate FET (110) further comprises a first gate region (113) adjacent to a plurality of side surfaces of the first active region (111), and the second multigate FET (120) further comprises a second gate region (123) adjacent to a plurality of side surfaces of the second active region (121); and wherein the first gate region (113) and the second gate region (123) are the same gate region so that they are connected. [2] The semiconductor device according to claim 1, wherein the first active region (111) and the second active region (121) have different conductivity types from each other. [3] A semiconductor device according to any one of claims 1 or 2, wherein a first area of ​​the first active region (111) is smaller than a second area of ​​the second active region (121). [4] A semiconductor device according to any one of claims 1 or 2, wherein a first area of ​​the first active region (111) is equal to a second area of ​​the second active region (121). [5] A semiconductor device according to any one of claims 1 or 2, wherein a first area of ​​the first active region (111) is larger than a second area of ​​the second active region (121). [6] The semiconductor device according to claim 1, wherein the first multi-gate FET (110) further comprises a first metal contact region (112a) disposed over the first active region (111) and a second metal contact region (112b) disposed over the first active region (111), and wherein the second multi-gate FET (120) further comprises a third metal contact region (122a) disposed over the second active region (121) and a fourth metal contact region (122b) disposed over the second active region (121), wherein the first metal contact region (112a) and the third metal contact region (122a) do not completely overlap when viewed from the vertical direction (Z), and the first metal contact region (112a) and the fourth metal contact region (122b) do not completely overlap when viewed from the vertical direction (Z). [7] The semiconductor device according to claim 6, wherein the second metal contact region (112b) and the third metal contact region (122a) do not completely overlap when viewed from the vertical direction (Z), and the second metal contact region (112b) and the fourth metal contact region (122b) do not completely overlap when viewed from the vertical direction (Z). [8] A semiconductor device according to any one of the preceding claims 1 to 7, wherein a first width (W_B) of the first active region (111) is equal to a second width (W_T) of the second active region (121). [9] A semiconductor device according to any one of the preceding claims 1 to 7, wherein a first width (W_B) of the first active region (111) differs from a second width (W_T) of the second active region (121). [10] A method of forming a semiconductor device, comprising: Forming a first multigate FET (110) disposed over a substrate (190), the first multigate FET (110) having a first active region (111) extending on a first horizontal plane (101); the first multigate FET (110) having a first gate region (113) adjacent to a plurality of side surfaces of the first active region (111); and Forming a second multigate FET (120) arranged above the first multigate FET (110), wherein the second multigate FET (120) has a second active region (121) extending on a second horizontal plane (102) parallel to the first plane (101), wherein the first active region (111) and the second active region (121) do not completely overlap when viewed from a vertical direction (Z) perpendicular to the first horizontal plane (101); wherein the second multigate FET (120) has a second gate region (123) adjacent to a plurality of side surfaces of the second active region (121); wherein a first projection (121') of the second active region (121) on the first horizontal plane (101) and the first active region (111) do not overlap; and wherein the first gate region (113) and the second gate region (123) are the same gate region so that they are connected. [11] The method of claim 10, wherein the first active region (111) and the second active region (121) have different conductivity types from each other.

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