TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

comprising a semiconductor device: featuring a first GAA transistor (260A): - several first vertically stacked channel elements (2081); - a boundary layer (222) over the first several channel elements (2081); - a gate dielectric layer (228) over the interface layer (222); - a first exit work layer (238) above and in contact with the gate dielectric layer (228); and - a detention shift (244) above the first exit work shift (234); featuring a second GAA transistor (260B): - several second vertically stacked channel elements (2082); - the interface layer (222) over the several second channel elements (2082); - the gate dielectric layer (228) above the interface layer (222); - a second exit working layer (234) above and in contact with the gate dielectric layer (228); - the first exit work shift (238) above and in contact with the second exit work shift (234); and - the adhesive layer (244) above the first exit working layer (238); and comprising a third GAA transistor (260C): - several third vertically stacked channel elements (2083); - the interface layer (222) over the several third channel elements (2083); - the gate dielectric layer (228) above the interface layer (222); and - the adhesive layer (244) over the gate dielectric layer (228), - wherein the first output layer and the second output layer (238, 234) are removed in the third GAA transistor; and wherein the first output layer (238) is an n output layer and the second output layer (234) is a p output layer.

Description

TECHNICAL BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and IC design have spawned generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be formed using a manufacturing process) has decreased. This process of downscaling generally realizes benefits by increasing production efficiency and reducing the costs associated with production. Such downscaling has also increased the complexity of IC processing and manufacturing.

[0002] For example, as integrated circuit (IC) technology evolved toward smaller technology nodes, multi-gate devices were introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). A multi-gate device generally refers to a device that has a gate structure, or a portion thereof, disposed over more than one side of a channel region. Fin-type field-effect transistors (FinFETs) and gate-all-around transistors (GAA transistors) (both also called non-planar transistors) are examples of multi-gate devices that have become popular and promising candidates for high-power, low-leakage applications.A FinFET has a raised channel encased on more than one side by a gate (for example, the gate encases the top and sidewalls of a "fin" of semiconductor material extending from a substrate). Compared to planar transistors, such a configuration offers better control of the channel and a drastic reduction in SCEs (particularly by reducing subthreshold leakage currents (i.e., the coupling between a FinFET's source and drain in the "off" state)). A GAA transistor has a gate structure that can extend—partially or completely—around a channel region to provide access to the channel region on two or more sides. The channel region of the GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures.In some implementations, such a channel region contains multiple nanowires (which extend horizontally, thereby forming horizontally aligned channels) stacked vertically. Such a GAA transistor can be referred to as a vertically stacked horizontal GAA (VGAA) transistor.

[0003] If GAA transistors with different threshold voltages are desired, one or more layers can be deposited en masse over all channel regions and selectively removed from a subset of the channel regions. Sometimes, it can be difficult to remove materials deposited between nanostructures in the channel region. Failure to remove such materials, or incomplete removal, can result in a failed device or reduced performance. Therefore, while currently existing GAA transistors and processes for their formation are generally suitable for their intended purposes, they have not been entirely satisfactory.

[0004] US 2019 / 0 198 498 A1 discloses a semiconductor device having first, second and third transistors on a substrate and having mutually different threshold voltages, wherein each of the first, second and third transistors comprises: a gate insulating layer, a first work function metal layer and a second work function metal layer.

[0005] US 2016 / 0 225 868 A1 discloses a semiconductor device comprising a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film.

[0006] US 2019 / 0 081 148 A1 discloses a semiconductor device having first semiconductor patterns stacked vertically on a substrate and vertically spaced from each other, and a first gate electrode on the first semiconductor patterns, wherein the first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern and a first electrode pattern on the barrier pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is defined in the independent claims. The dependent claims relate to corresponding embodiments. Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be exaggerated or reduced as needed for clarity of discussion. Fig. 1 is a flowchart illustrating a method of forming a semiconductor device according to an embodiment of the present invention. Fig. 2A is a diagrammatic perspective view of a first portion of a workpiece according to various aspects of the present invention. Fig. 2B is a diagrammatic perspective view of a second portion of a workpiece according to various aspects of the present invention. Fig. 2C is a diagrammatic perspective view of a third portion of a workpiece according to various aspects of the present invention. Fig. 3-23 illustrate fragmentary cross-sectional views of the first region and the second region of the workpiece at various stages of manufacture according to the method in Fig. 1. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first structural element over or on a second structural element in the following description may include embodiments where the first and second structural elements are formed in direct contact, and may also include embodiments where additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not automatically create a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the FIGS. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the FIGS. The device may also be oriented differently (rotated 90 degrees, or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] Furthermore, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to include numbers that are within a reasonable range containing the stated number, such as within ±10% of the stated number or other values ​​as understood by one skilled in the art. For example, the term "about 5 nm" encompasses the dimensional range from 4.5 nm to 5.5 nm.

[0011] The present disclosure relates to GAA transistors, and more particularly, to GAA transistors of different threshold voltages included in a semiconductor device. A semiconductor device according to embodiments of the present disclosure includes a GAA transistor of a first type in a first region, a GAA transistor of a second type in a second region, and a GAA transistor of a third type in a third region. The first type GAA transistor includes first vertically stacked channel elements, the second type GAA transistor includes second vertically stacked channel elements, and the third type GAA transistor includes third vertically stacked channel elements.The first type GAA transistor includes an interface layer over the first vertically stacked channel elements, a gate dielectric layer over the interface layer, an n-type work function layer over the gate dielectric layer, a passivation layer over the n-type work function layer, an adhesion layer over the passivation layer, and a metal fill layer over the adhesion layer. The second type GAA transistor includes an interface layer over the second vertically stacked channel elements, the gate dielectric layer over the interface layer, a p-type work function layer over the gate dielectric layer, an n-type work function layer over the p-type work function layer, the passivation layer over the n-type work function layer, the adhesion layer over the passivation layer, and the metal fill layer over the adhesion layer.The third type GAA transistor includes an interface layer over the third vertically stacked channel elements, the gate dielectric layer over the interface layer, the adhesion layer over the gate dielectric layer, and the metal fill layer over the adhesion layer. According to embodiments of the present disclosure, the process for forming the semiconductor device includes forming a sacrificial layer between channel elements to prevent hard-to-remove work function layers from being deposited between channel elements. Having little or no hard-to-remove work function layers between channel elements facilitates the removal of materials between channel elements, and subsequently deposited layers can be deposited around channel elements.

[0012] Fig. 1 illustrates a flowchart of a method 100 for manufacturing a semiconductor device according to various aspects of the present disclosure. Fig. 1 will be used in conjunction with the Fig. 2A, 2B, 2C and 3-23, which are fragmentary cross-sectional views of a workpiece at various stages of manufacture according to the methods 100 in Fig. 1 before the semiconductor device is fabricated on the workpiece. Throughout the present disclosure, the workpiece and the semiconductor device may be used interchangeably for simplicity, because the workpiece is intended to become the semiconductor device after completion of its fabrication processes and may have the same reference number. Additional steps may be provided before, during, and after the method 100, and some of the described steps may be shifted, replaced, or omitted to obtain additional embodiments of the method 100. In the Fig. Additional features may be added to the semiconductor device shown in Figures 2A, 2B, 2C and 3-23, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0013] We now turn to the Fig. 1, Fig. 2A, Fig. 2B and Fig. 2C, where the method 100 includes a block 102 in which a plurality of alternating semiconductor layers 204 are disposed over a first region 1000, a second region 2000, and a third region 300 on a substrate 202 of a workpiece 200. The first region 1000 of the workpiece 200 is in Fig. 2A illustrates, the second area 2000 of the workpiece 200 is in Fig. 2B, and the third area 3000 of the workpiece 200 is in Fig. 2C. In some embodiments, the substrate 202 includes silicon. Alternatively or additionally, the substrate 202 includes another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In some implementations, the substrate 202 includes one or more Group III-V materials, one or more Group II-IV materials, or combinations thereof. In some implementations, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.Semiconductor-on-insulator substrates may be fabricated using separation through implantation of oxygen (SIMOX), wafer bonding, and / or other suitable techniques. Substrate 202 may include various doped regions configured according to the design requirements of semiconductor device 200. P-doped regions may include p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. N-doped regions may include n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof. In some implementations, substrate 202 includes doped regions formed with a combination of p-type and n-type dopants.The various doped regions may be formed directly on and / or within the substrate 202, for example, forming a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and / or another suitable doping process may be performed to form the various doped regions. In some embodiments, p-GAA devices are formed over n-wells, and n-GAA devices are formed over p-wells.

[0014] The first region 1000, the second region 2000, and the third region 3000 are device regions for transistors having different threshold voltages. In some embodiments, the first region 1000 may be an n-type device region characterized by a first threshold voltage, the third region 3000 may be a p-type device region characterized by a third threshold voltage, and the second region 2000 may be a mid-level device region characterized by a second threshold voltage between the first threshold voltage and the third threshold voltage. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other.For example, the first threshold voltage may be between about 4.3 eV and about 4.5 eV, the second threshold voltage may be between about 4.5 eV and about 4.7 eV, and the third threshold voltage may be between about 4.7 eV and about 4.9 eV. Depending on the design parameters, the mid-level devices in the second region 2000 may function as n-type devices or p-type devices to reduce leakage current.

[0015] In the embodiments described in the Fig. 2A, Fig. 2B and Fig. 2C, the plurality of alternating semiconductor layers 204 include a plurality of first semiconductor layers 208 interleaved with a plurality of second semiconductor layers 206. That is, two adjacent first semiconductor layers 208 sandwich a second semiconductor layer 206. The plurality of first semiconductor layers 208 are formed from a first semiconductor material, and the plurality of second semiconductor layers 206 are formed from a second semiconductor material that is different from the first semiconductor material. In some embodiments, the first semiconductor material is or includes substantially silicon (Si), and the second semiconductor material is or includes substantially silicon-germanium (SiGe). In some other embodiments, the first semiconductor material is or includes substantially silicon (Si), and the second semiconductor material is or includes substantially germanium (Ge).In some alternative embodiments, the first semiconductor material includes silicon germanium (SiGe) having a first germanium content, and the second semiconductor material includes silicon germanium (SiGe) having a second germanium content higher than the first germanium content. The plurality of alternating semiconductor layers 204 may be formed by alternately depositing or epitaxially growing the plurality of first semiconductor layers 208 and the plurality of second semiconductor layers 206. In some implementations, after the plurality of alternating semiconductor layers 204 are patterned into fin structures (fin-shaped active regions), a portion of the plurality of second semiconductor layers 206 in channel regions may be selectively removed to detach channel elements formed from the plurality of first semiconductor layers 208.In this regard, the second semiconductor layers 206 act as sacrificial semiconductor layers and may be referred to as such.

[0016] As further stated in the Fig. 1, Fig. 2A, Fig. 2B and Fig. 2C, the method 100 includes a block 104 in which a first fin structure 210A is formed in the first region 1000, a second fin structure 210B is formed in the second region 2000, and a third fin structure 210C is formed in the third region 3000. As shown in Fig. 2A, the plurality of alternating semiconductor layers 204 may be patterned such that the first fin structure 210A is formed in the first region 1000. As shown in Fig. 2B, the plurality of alternating semiconductor layers 204 may be patterned such that the second fin structure 210B is formed in the second region 2000. As shown in Fig. 2C, the plurality of alternating semiconductor layers 204 may be patterned to form the third fin structure 210C in the third region 3000. In block 104, the first fin structure 210A, the second fin structure 210B, and the third fin structure 210C may be patterned using suitable processes, such as photolithography and etching processes. In some embodiments, the fin structures are etched from the plurality of alternating semiconductor layers 204 using dry etching or plasma etching processes. In some other embodiments, the fin structures may be formed by a double-patterning lithography (DPL) process, a quadruple-patterning lithography (QPL) process, or a multiple-patterning lithography (MPL) process.Generally, DPL, QPL, and MPL processes combine photolithography and self-aligned processes, allowing the creation of structures with, for example, smaller pitches than those otherwise obtainable with a single, direct photolithography process. In some implementations, dielectric isolation features 212 are formed at the first fin structures 210A, the second fin structures 210B, and the third fin structures 210C. The dielectric isolation features 212 may also be referred to as shallow trench isolation (STI) features 212.

[0017] As further stated in the Fig. 1, Fig. 2A, Fig. 2B and Fig. 2C, the method 100 includes a block 106 in which a dummy gate structure 214 is formed over a first channel region 1100 of the first fin structure 210A, a second channel region 2100 of the second fin structure 210B, and a third channel region 3100 of the third fin structure 210C. As shown in the Fig. 2A, Fig. 2B and Fig. 2C, the dummy gate structure 214 may include a dummy gate dielectric layer 216, a dummy gate electrode 218, a top-side gate hard mask 220, and a gate spacer 221. In some implementations, the dummy gate electrode 218 may be formed from polysilicon, and the dummy gate dielectric layer 216 may be formed from silicon oxide or silicon oxynitride. The top-side gate hard mask 220 may be formed from silicon oxide or silicon nitride. In some implementations, the top-side gate hard mask 220 may include multiple layers. For example, the top-side gate hard mask 220 may include a silicon oxide layer adjacent to the dummy gate electrode 218 and a silicon nitride layer over the silicon oxide layer. The gate spacer 221 extends along sidewalls of the dummy gate electrode 218 and defines the first channel region 1100 and the second channel region 2100.In some implementations, the gate spacer 221 may be formed from silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbonitride, a low-k dielectric material having a dielectric constant lower than that of silicon dioxide (i.e., about 3.9), or a combination thereof.

[0018] To clarify the description and illustration, each of the Fig. 3-23 is a fragmentary cross-sectional view of a first fin structure 210A along the Fig. 2A, a fragmentary cross-sectional view of a second fin structure 210B along the section I-I' shown in Fig. 2B and a fragmentary cross-sectional view of a third fin structure 21CA along the section II-II' shown in Fig. 2C shown section III-III'. As in Fig. 2A, the cut II' extends along the dummy gate structure 214 and passes the first channel region 1100. As shown in Fig. 2B, the cut II-II' extends along the dummy gate structure 214 and passes the second channel region 2100. As shown in Fig. As shown in Figure 2C, the cut III-III' extends along the dummy gate structure 214 and passes through the third channel region 3100.

[0019] With reference to the Fig. 1 and 3-5, the method 100 includes a block 108 in which the first channel elements 2081 are detached in the first channel region 1100, the second channel elements 2082 are detached in the second channel region 2100, and the third channel elements 2083 are detached in the third channel region 3100. In some embodiments, after the dummy gate structure 214 is formed in block 106, the dummy gate structure 214 is used as an etch mask to recess the first fin structure 210A, the second fin structure 210B, and the third fin structure 210C to form source / drain trenches to expose sidewalls of the plurality of first semiconductor layers 208 and the plurality of second semiconductor layers 206 in the first channel region 1100, in the second channel region 2100, and in the third channel region 3100.In some embodiments, the plurality of second semiconductor layers 206 in the first channel region 1100, the second channel region 2100, and the third channel region 3100 may be selectively and partially etched to form internal spacer recesses between two of the plurality of first semiconductor layers 208. An internal spacer feature is then formed within the internal spacer recesses. Epitaxial source / drain features may then be formed in the source / drain trenches. After the epitaxial source / drain features are formed, an interlayer dielectric (ILD) layer may be deposited over the workpiece 200. A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to planarize the workpiece 200 until the dummy gate electrode 218 is exposed.The exposed dummy gate electrode 218 may then be selectively removed using a suitable dry or wet etching process. Fig. 3 illustrates the multiple alternating semiconductor layers 204 in the first channel region 1100, the second channel region 2100, and the third channel region 3100 after the dummy gate electrode 218 has been removed. In some embodiments, the dummy gate dielectric layer 216 may be removed using a suitable etch process different from that used to remove the dummy gate electrode 218. Fig. 4 illustrates the multiple alternating semiconductor layers 204 in the first channel region 1100, the second channel region 2100, and the third channel region 3100 after the dummy gate dielectric layer 216 has been removed. After the dummy gate dielectric layer 216 has been removed, the multiple second semiconductor layers 206 may be selectively removed. In some implementations, the multiple second semiconductor layers 206 are formed from silicon germanium, and the selective removal process includes oxidizing the multiple second semiconductor layers 206 using a suitable oxidizing agent, such as ozone. Thereafter, the oxidized second semiconductor layers 206 may be selectively removed. At this point, as in Fig. 5, the first channel elements 2081 are formed in the first region 1000, and the second channel elements 2082 are formed in the second region 2000, and third channel elements 2083 are formed in the third region 3000.

[0020] With reference to the Fig. 1 and Fig. 6, the method 100 includes a block 110 in which an interface layer 222 is formed over the first channel elements 2081 in the first region 1000, second channel elements 2082 are formed in the second region 2000, and the third channel elements 2083 are formed in the third region 3000. In some embodiments, the interface layer 222 may include silicon oxide or silicon oxynitride or another suitable material. In some embodiments, the interface layer 222 may be deposited using a suitable method such as atomic layer deposition (ALD), chemical vapor deposition (CVD), ozone oxidation, thermal oxidation, or another suitable method. The interface layer 222 functions to control and reduce gate leakage current and to improve interfacial adhesion between the gate dielectric layer 228 (in Fig. 7) and the channel elements (including the first channel elements 2081, the second channel elements 2082 and the third channel elements 2083).

[0021] With reference to the Fig. 1 and Fig. 7, the method 100 includes a block 112 in which a gate dielectric layer 228 is deposited over the interface layer 222 in the first region 1000, the second region 2000, and the third region 3000. In some embodiments, the gate dielectric layer 228 is a high-k dielectric layer because its dielectric constant is greater than that of silicon dioxide (about 3.9). In some implementations, the gate dielectric layer 228 may include doped or undoped hafnium oxide (HfO2), doped or undoped zirconium oxide (ZrO2), doped or undoped titanium oxide (TiO2), or doped or undoped aluminum oxide (Al2O3). For example, the gate dielectric layer 228 may include hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), or hafnium aluminum oxide (HfAlO), hafnium tantalum oxide (HfTaO), hafnium zirconium oxide (HfZrO), zirconium silicon oxide (ZrSiO2), hafnium titanium oxide (HfTiO), or a combination thereof.After completion of the operations in block 112, each of the first channel elements 2081, the second channel elements 2082, and the third channel elements 2083 is encased by the interface layer 222 and the gate dielectric layer 228.

[0022] With reference to the Fig. 1 and Fig. 8, the method 100 includes a block 114 in which a sacrificial layer 230 is deposited over the gate dielectric layer 228. According to the present disclosure, the sacrificial layer 230 is formed from a material that can be selectively removed without significantly damaging the gate dielectric layer. In some embodiments, the sacrificial layer 230 is formed from a dielectric material (such as silicon oxide, silicon nitride, aluminum oxide, titanium oxide, zirconium oxide), a semiconductor material (such as silicon or germanium or SiGe), a low-density metal nitride (such as titanium nitride), or other suitable materials. In some examples, the sacrificial layer 230 may be formed from silicon oxide or silicon nitride. The sacrificial layer 230 may be deposited using atomic layer deposition (ALD) or another suitable method.

[0023] With reference to the Fig. 1 and Fig. 9, the method 100 includes a block 116 in which a portion of the sacrificial layer 230 is removed. In some embodiments, at block 116, each of the first channel elements 2081, second channel elements 2082, and third channel elements 2083 serves as an etch mask or etch shield when etching the sacrificial layer 230. Removing the sacrificial layer 230 at block 116 includes a dry etch process or a wet etch, which is selected based on the material forming the sacrificial layer 230. In some embodiments, Fig. 9, after completion of the operations in block 116, a portion of the sacrificial layer 230 remains, disposed between adjacent channel elements. This remaining portion of the sacrificial layer 230 may be referred to as a remaining sacrificial layer 230'. In other words, operations in block 116 may remove the sacrificial layer 230 over the top surfaces and side surfaces of the first channel elements 2081, second channel elements 2082, and third channel elements 2083 to expose the gate dielectric layer 228 deposited thereover. Here, the top surfaces refer to the top surfaces of the topmost channel elements in the first channel elements 2081, second channel elements 2082, and third channel elements 2083. As in Fig. 9, the remaining sacrificial layer 230' is arranged vertically between adjacent first channel elements 2081, second channel elements 2082 and third channel elements 2083.

[0024] With reference to the Fig. 1, Fig. 10, Fig. 11 and Fig. 12, the method 100 includes a block 118 in which the remaining sacrificial layer 230' in the second region 2000 is selectively removed. In some Fig. In the embodiments illustrated in Figure 10, a patterned hard mask 232 may be formed such that the first region 1000 and the third region 3000 are covered by the patterned hard mask 232, and the second region 2000 is exposed. In an exemplary process, a hard mask layer is first deposited over the workpiece 200, a bottom antireflective coating (BARC) is deposited over the deposited hard mask layer, and then a photoresist layer is deposited over the BARC layer. The photoresist layer is pre-baked, patterned by exposure to patterned radiation that passes through or is reflected from a mask, post-baked, and developed in a development process using a developer to form a patterned photoresist layer.The patterned photoresist layer is used as an etch mask to pattern the BARC layer. Then, the patterned BARC layer is used as an etch mask to pattern the hardmask layer to create the patterned hardmask 232. In some cases, the hardmask layer can be a single layer or a multilayer. We now turn to . Fig. 11, where the remaining sacrificial layer 230' is removed from the exposed second region 2000, while the first region 1000 and the third region 3000 remain masked by the patterned hard mask 232. We now turn Fig. 12. The structured hard mask 232 is removed by means of a suitable etching process.

[0025] With reference to the Fig. 1 and Fig. 13, the method 100 includes a block 120 in which a first work function layer 234 is deposited over the first channel elements 2081, second channel elements 2082, and third channel elements 2083. In some embodiments, the first work function layer 234 may be a p-type work function layer and may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), molybdenum (Mo), or another suitable p-type work function material. The first work function layer 234 may be formed using an ALD process. Because the remaining sacrificial layer 230' remains between adjacent first channel elements 2081 and the third channel elements 2083, the first work function layer 234 is prevented from being deposited around each of the first channel elements 2081 and each of the third channel elements 2083.In contrast, the second region 2000 is substantially free of remaining sacrificial layer 230', and the first work function layer 234 may form in such a manner that it wraps around each of the second channel elements 2082.

[0026] The prior art allows the deposition of a previously deposited work function layer between adjacent channel elements. If the previously deposited work function layer is to be removed, an overetch or enhanced etch may be required to remove the work function material in the space between the channel elements. The overetch or enhanced etch would likely damage the required work function layers in adjacent transistors. Leaving the previously deposited work function layer in the space between channel elements may prevent a subsequently deposited work function layer from penetrating between adjacent channel elements due to the presence of a previously deposited work function layer.The resulting device may have a threshold voltage greater than the required threshold voltage, or different channel elements within a transistor may have different threshold voltages. As will be seen in the following descriptions and illustrations, the remaining sacrificial layer 230' prevents difficult-to-remove work function layers from being deposited between adjacent first channel elements 2081 and adjacent third channel elements 2083. Therefore, a subsequent etch process for detaching the first channel elements 2081 or third channel elements 2083 from one or more work function layers does not require an overetch to remove work function layer material between adjacent first channel elements 2081 and adjacent third channel elements 2083.By allowing the desired work function layer to wrap around the channel elements without overetching, processes of the present disclosure can produce transistors with low threshold voltages, improving threshold voltage uniformity and increasing production yield.

[0027] With reference to the Fig. 1, Fig. 14, Fig. 15 and Fig. 16, the method 100 includes a block 122 in which the first work function layer 234 and the remaining sacrificial layer 230' over the first channel elements 2081 are selectively removed. In some Fig. In the embodiments illustrated in Figure 14, a patterned hard mask 236 may be formed such that the second region 2000 and the third region 3000 are covered by the patterned hard mask 236, leaving the first region 1000 exposed. In an exemplary process, a hard mask layer is first deposited over the workpiece 200, a bottom antireflective coating (BARC) is deposited over the deposited hard mask layer, and then a photoresist layer is deposited over the BARC layer. The photoresist layer is pre-baked, patterned by exposure to patterned radiation that passes through or is reflected from a mask, post-baked, and developed in a development process using a developer to form a patterned photoresist layer.The patterned photoresist layer is used as an etch mask to pattern the BARC layer. Then, the patterned BARC layer is used as an etch mask to pattern the hard mask layer. In some cases, the hard mask layer can be a single layer or a multi-layer. We now turn to . Fig. 15, where the first work function layer 234 and the remaining sacrificial layer 230' are removed from the exposed first region 1000, while the second region 2000 and the third region 3000 remain masked by the patterned hard mask layer 236. In some implementations, the first work function layer 234 and the remaining sacrificial layer 230' may be removed using different etchants in two different etching processes, such that each of the etching processes is tailored to the material to be removed. We now turn Fig. 16. The patterned hard mask 236 is removed using a suitable etching process. In some cases, the first work function layer 234 has a thickness between about 0.5 nm and about 2 nm.

[0028] With reference to the Fig. 1 and Fig. 17, the method 100 includes a block 124 in which a second work function layer 238 is deposited over the first channel elements 2081, second channel elements 2082, and third channel elements 2083. The second work function layer 238 is different from the first work function layer 234. In some embodiments, the second work function layer 238 may be an n-type work function layer and may include aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi), hafnium carbide (HfC), an aluminum-containing layer, or another suitable n-type work function layer. The second work function layer 238 can be formed using an ALD process.Because the remaining sacrificial layer 230' is removed from the first region 1000 and the second region 2000, the second work function layer 238 may be deposited in such a manner that the second work function layer 238 wraps around each of the first channel elements 2081 and each of the second channel elements 2082. With respect to the third region 3000, the second work function layer 238 is deposited over the first work function layer 234 and may not wrap around each of the third channel elements 2083. In some cases, the second work function layer 238 has a thickness between about 1 nm and about 3 nm. As shown in FIG. Fig. 18, the second work function layer 238 does not pinch off the space between adjacent first channel elements 2081 and between adjacent second channel elements 2082, such that a subsequent layer (for example, the one shown in Fig. 18) can be deposited between adjacent first channel elements 2081 and between adjacent second channel elements 2082.

[0029] With reference to Fig. 1 and Fig. 18, method 100 includes a block 126 in which a passivation layer 240 is deposited over the second work function layer 238. The operations in block 126 are optional and, if performed, are performed immediately after the deposition of the second work function layer 238 in the same process chamber without breaking the vacuum. This is because the passivation layer 240 functions to prevent aluminum in the second work function layer 238 from oxidizing when the second work function layer 238 contains aluminum. If the second work function layer 238 does not contain aluminum, the operations in block 126 are omitted. In embodiments where the second work function layer 238 contains aluminum, the operations in block 126 are performed. The passivation layer 240 may also be referred to as a protection layer 240.The material for the passivation layer 240 is chosen so that the passivation layer 240 can either block oxygen diffusion or has a lower reduction potential than aluminum. If the material for the passivation layer 240 has a lower reduction potential than aluminum, it acts as an oxygen sink through preferential oxidation. In some embodiments, the passivation layer 240 can be formed from titanium nitride (TiN), titanium silicon nitride (TiSiN), silicon (Si), tantalum nitride (TaN), tungsten carbonitride (WCN), or another suitable material. In some cases, the passivation layer 240 can be formed to a thickness between about 0.5 nm and about 2 nm. In some other cases, the passivation layer 240 can be omitted.In embodiments in which the passivation layer 240 is implemented, the passivation layer 240 is deposited to pinch off the space between adjacent first channel elements 2081 and between adjacent second channel elements 2082 such that a subsequent layer (for example, the layer shown in FIG. Fig. 18) cannot be deposited between adjacent first channel elements 2081 and between adjacent second channel elements 2082.

[0030] With reference to the Fig. 1, Fig. 19, Fig. 20 and Fig. 21, the method 100 includes a block 128 in which the second work function layer 238, the passivation layer 240, the first work function layer 234, and the remaining sacrificial layer 230' in the third region 3000 are selectively removed. In some Fig. In the embodiments illustrated in Figure 19, a patterned hard mask 242 may be formed such that the first region 1000 and the second region 2000 are covered by the patterned hard mask 242, and the third region 3000 is exposed. In an exemplary process, a hard mask layer is first deposited over the workpiece 200, a bottom antireflective coating (BARC) is deposited over the deposited hard mask layer, and then a photoresist layer is deposited over the BARC layer. The photoresist layer is pre-baked, patterned by exposure to patterned radiation that passes through or is reflected from a mask, post-baked, and developed in a development process using a developer to form a patterned photoresist layer.The patterned photoresist layer is used as an etch mask to pattern the BARC layer. Then, the patterned BARC layer is used as an etch mask to pattern the hard mask layer. In some cases, the hard mask layer can be a single layer or a multi-layer. We now turn to . Fig. 20, where the passivation layer 240, the second work function layer 238, the first work function layer 234, and the remaining sacrificial layer 230' are removed from the exposed third region 3000, while the first region 1000 and the second region 2000 remain masked by the patterned hard mask layer 242. We now turn Fig. 21. The structured hard mask 242 is removed by means of a suitable etching process.

[0031] With reference to the Fig. 1 and Fig. 22, the method 100 includes a block 130 in which an adhesion layer 244 is deposited over the first channel elements 2081, second channel elements 2082, and third channel elements 2083. In some embodiments, the adhesion layer 244 may be a p-type work function layer and may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), molybdenum (Mo), or another suitable p-type work function material. That is, a composition of the adhesion layer 244 may be identical to the composition of the first work function layer 234. In some implementations, the adhesion layer 244 may be formed by ALD to a thickness between about 2 nm and about 5 nm. In some cases, the adhesive layer 244 is deposited such that the space between adjacent third channel elements 2083 is pinched off such that a subsequent layer cannot be deposited between adjacent third channel elements 2083.

[0032] With reference to Fig. 1 and Fig. 23, the method 100 may include a block 132 in which further processes are performed. Examples of such further processes may include depositing a metal fill layer 246 over the channel regions (including the first channel region 1100, the second channel region 2100, and the third channel region 3100). The metal fill layer 246 may include tungsten (W) or cobalt (Co). After depositing the metal fill layer 246, a first metal gate stack 250A is formed in the first region 1000, a second metal gate stack 250B is formed in the second region 2000, and a third metal gate stack 250C is formed in the third region 3000. The first metal gate stack 250A includes the interface layer 222, the gate dielectric layer 228, the second work function layer 238, the passivation layer 240, the adhesion layer 244, and the metal fill layer 246.The second metal gate stack 250B includes the interface layer 222, the gate dielectric layer 228, the first work function layer 234, the second work function layer 238, the passivation layer 240, the adhesion layer 244, and the metal fill layer 246. The third metal gate stack 250C includes the interface layer 222, the gate dielectric layer 228, the adhesion layer 244, and the metal fill layer 246. Examples of the further processes in block 132 may also include forming an interlayer dielectric (ILD) layer, forming the source / drain contacts through the ILD layer for coupling to the source / drain features, and forming gate interconnects for coupling to the gate structures.

[0033] After completion of the operations in method 100, a first GAA transistor 260A is formed in the first region 1000, a second GAA transistor 260B is formed in the second region 2000, and a third GAA transistor 260C is formed in the third region 3000. The first GAA transistor 260A is provided with the first metal gate stack 250A. The second GAA transistor 260B is provided with the second metal gate stack 250B. The third GAA transistor 260C is provided with the third metal gate stack 250C. As shown in Fig. 23, the first GAA transistor 260A may be an n-type GAA transistor with a threshold voltage lower than a potential threshold voltage without an intervening p-type work function layer because the second work function layer 238 is an n-type work function layer formed directly on the gate dielectric layer 228 without an intervening p-type work function layer (i.e., the first work function layer 234). The absence of an intervening p-type work function layer in the first region 1000 is enabled, or at least facilitated, by the use of the remaining sacrificial layer 230' (in Fig. 13), which prevents the first work function layer 234 (or too much of the first work function layer 234) from penetrating between adjacent first channel elements 2081. Thanks to the reduced amount or absence of the first work function layer 234 between adjacent first channel elements 2081, no wet overetch is required to remove the difficult-to-remove first work function layer 234 from the space between the first channel elements 2081.

[0034] Similarly, because adhesion layer 244 is a p-type work function layer formed directly on gate dielectric layer 228 without an adjacent n-type work function layer (i.e., second work function layer 238), third GAA transistor 260C may be a p-type GAA transistor with a threshold voltage lower than a potential threshold voltage without an adjacent n-type work function layer. N-type work function layers may contain highly diffusible components that may diffuse into an adjacent p-type work function layer to undesirably shift the work function away from the valence band. For example, aluminum in an n-type work function layer may diffuse into a p-type work function layer of a p-type device, thereby shifting the work function away from the valence band and undesirably increasing the threshold voltage.By removing the second work function layer 238 (i.e., an n-type work function layer) from the third region 3000, no highly diffusible components from an n-type work function layer are allowed to diffuse into the adhesion layer 244 (i.e., a p-type work function layer). The absence of an adjacent n-type work function layer in the third region 3000 is compensated for by using the remaining sacrificial layer 230' (shown in FIGS. Fig. 13 and Fig. 17), thereby preventing the first work function layer 234 (or too much of the first work function layer 234) and the second work function layer 238 (or too much of the second work function layer 238) from penetrating between adjacent third channel elements 2083. Due to the reduced amount or absence of the first work function layer 234 and the second work function layer 238 between adjacent third channel elements 2083, no wet overetch is required to remove the difficult-to-remove first work function layer 234 and the second work function layer 238 from the space between third channel elements 2083.

[0035] In the Fig.In the embodiments shown in Figure 23, the second GAA transistor 260B includes a mid-level threshold voltage that is between an n-type threshold voltage for the first GAA transistor 260A and the p-type threshold voltage for the third GAA transistor 260C. Unlike the first metal gate stack 250A and the third metal gate stack 250C, the second metal gate stack 250B of the second GAA transistor 260B includes both the first work function layer 234 and the second work function layer 238.

[0036] In some embodiments not explicitly shown here, one or more dipole layers may optionally be integrated into the first metal gate stack 250A, the second metal gate stack 250B, and the third metal gate stack 250C to further diversify the threshold voltages in the semiconductor device 200. For example, dipole layers may be either an n-type dipole layer or a p-type dipole layer, depending on the electron affinity and oxygen atom density. One or more dipole layers, each incorporated into the first metal gate stack 250A, the second metal gate stack 250B, and the third metal gate stack 250C, may further move the work function closer to the valence band or the conduction band, thereby shifting the resulting threshold voltages of the first GAA transistor 260A, the second GAA transistor 260B, and the third GAA transistor 260C.Example materials for an n-type dipole layer include lanthanum oxide, magnesium oxide, and yttrium oxide. Example materials for a p-type dipole layer include aluminum oxide, titanium oxide, and niobium oxide. In some cases, dipole materials can be thermally incorporated into the gate dielectric layer 228 without significantly increasing the thickness of the gate dielectric layer 228. By selectively treating the gate dielectric layer 228 in some of the first GAA transistors 260A, but not in some of the other first GAA transistors 260A, the two first GAA transistors 260A can be further converted into two subsets of the first GAA transistors 260A with different threshold voltages. The same applies to the second GAA transistors 260B and the third GAA transistors 260C.That is, by selectively incorporating a specific dipole material, three types of GAA transistors with three threshold voltage levels can be formed into six types of GAA transistors with six threshold voltage levels. Thus, it can be seen that the processes and semiconductor devices of the present disclosure open up ways to form GAA transistors with diversified threshold voltages.

[0037] Based on the above discussions, the present invention offers advantages over conventional GAA transistors and processes for their fabrication. However, it should be understood that other embodiments may offer additional advantages, that not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. The present invention provides a semiconductor device formation process in which a sacrificial layer is used to prevent work function layers to be removed from penetrating the space between adjacent channel elements. This arrangement enables satisfactory removal of the work function layers to be removed without overetching, which can cause damage to adjacent structures.The disclosed processes allow an n-type work function layer to completely wrap around the channel elements in an n-type GAA transistor and allow an n-type work function layer to be substantially completely removed around channel elements in a p-type GAA transistor. As a result, n-type GAA transistors and p-type GAA transistors according to the present invention have lower threshold voltages.

[0038] The present invention provides embodiments of semiconductor devices and methods for fabricating them. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor. The first GAA transistor includes a plurality of first channel elements, an interface layer over the plurality of first channel elements, a gate dielectric layer over the interface layer, a first work function layer, which is an n-type work function layer, over and in contact with the gate dielectric layer, and an adhesion layer over the first work function layer.The second GAA transistor includes a plurality of second channel elements, the interface layer over the plurality of second channel elements, the gate dielectric layer over the interface layer, and a second work function layer, which is a p-type work function layer, over and in contact with the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the adhesion layer over the first work function layer. The third GAA transistor includes a plurality of third channel elements, the interface layer over the plurality of third channel elements, the gate dielectric layer over the interface layer, and the adhesion layer over the gate dielectric layer, and the first work function layer and the second work function layer are removed in the third GAA transistor.

[0039] In some embodiments, the first work function layer includes aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi), or hafnium carbide (HfC), and the second work function layer includes titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo). In some implementations, the adhesion layer includes titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo).In some cases, the first GAA transistor further includes a passivation layer disposed between the first work function layer and the adhesion layer, the second GAA transistor further includes the passivation layer disposed between the first work function layer and the adhesion layer, and the third GAA transistor is free of the passivation layer. In some embodiments, the first work function layer has a thickness between 1 nm and about 3 nm, the second work function layer has a thickness between about 0.5 nm and about 2 nm, the passivation layer has a thickness between about 0.5 nm and about 2 nm, and the adhesion layer has a thickness between about 2 nm and about 5 nm. In some implementations, the passivation layer includes titanium nitride (TiN), titanium silicon nitride (TiSiN), silicon (Si), tantalum nitride (TaN), or tungsten carbonitride (WCN).In some embodiments, the first GAA transistor, the second GAA transistor, and the third GAA transistor each further include a metal fill layer over the adhesion layer, and the metal fill layer includes tungsten (W) or cobalt (Co). In some implementations, the first work function layer completely wraps around each of the plurality of first channel elements.

[0040] In another embodiment, a method is provided. The method includes: providing a workpiece including a substrate, first vertically stacked channel elements in a first region of the substrate, second vertically stacked channel elements in a second region of the substrate, and third vertically stacked channel elements in a third region of the substrate; depositing a gate dielectric layer over the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements; depositing a sacrificial layer over the gate dielectric layer; etching the sacrificial layer such that a portion of the sacrificial layer remains disposed between adjacent ones of the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements; selectively removing all of the sacrificial layer in the second region;Depositing a first work function layer over the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements; selectively removing the first work function layer and the sacrificial layer in the first region; depositing a second work function layer over the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements, wherein the second work function layer is different from the first work function layer, the first work function layer is an n-type work function layer, and the second work function layer is a p-type work function layer, or vice versa; depositing a passivation layer over the second work function layer;and selectively removing the passivation layer, the first work function layer, the second work function layer and the sacrificial layer in the third region;

[0041] In some embodiments, providing the workpiece includes: forming a plurality of alternating semiconductor layers over the first region, the second region, and the third region of the substrate; patterning the plurality of alternating semiconductor layers to form a first active region in the first region, a second active region in the second region, and a third active region in the third region; and selectively removing the second plurality of second semiconductor layers to form the first vertically stacked channel elements in the first active region, the second vertically stacked channel elements in the second active region, and the third vertically stacked channel elements in the third active region. The plurality of alternating semiconductor layers includes a first plurality of first semiconductor layers interleaved with a second plurality of second semiconductor layers.In some implementations, etching the sacrificial layer exposes the gate dielectric layer deposited over side surfaces of the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements. In some cases, the sacrificial layer includes silicon oxide or silicon nitride. In some embodiments, the first work function layer includes aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi), or hafnium carbide (HfC), and the second work function layer includes titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo). In some implementations, the passivation layer contains titanium nitride (TiN), titanium silicon nitride (TiSiN), silicon (Si), tantalum nitride (TaN), or tungsten carbonitride (WCN).In some embodiments, the method may further include: selectively removing the passivation layer, the first work function layer, the second work function layer, and the sacrificial layer in the third region; depositing an adhesion layer over the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements; and depositing a metal fill layer over the adhesion layer. In some implementations, the adhesion layer includes titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo), and the metal fill layer includes tungsten (W) or cobalt (Co).

[0042] In another embodiment, a method is provided. The method includes: providing a workpiece having a substrate, first vertically stacked channel elements in a first region of the substrate, second vertically stacked channel elements in a second region of the substrate, and third vertically stacked channel elements in a third region of the substrate; depositing a gate dielectric layer over the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements; depositing a sacrificial layer over the gate dielectric layer; partially and selectively etching the sacrificial layer such that a portion of the sacrificial layer is disposed between adjacent ones of the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements;selectively removing the entire sacrificial layer in the second region; depositing a first work function layer over the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements; selectively removing the first work function layer and the sacrificial layer in the first region; depositing a second work function layer over the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements, wherein the second work function layer is different from the first work function layer, the first work function layer is a p-type work function layer, and the second work function layer is an n-type work function layer; depositing a passivation layer over the second work function layer; selectively removing the passivation layer, the first work function layer, the second work function layer, and the sacrificial layer in the third region; selectively removing the passivation layer, the first work function layer, the second work function layer, and the sacrificial layer in the third region; depositing an adhesion layer over the first vertically stacked channel elements, the second vertically stacked channel elements, and the third vertically stacked channel elements; and depositing a metal fill layer over the adhesion layer. The first work function layer is different from the second work function layer, and a composition of the first work function layer is substantially identical to a composition of the adhesion layer.

[0043] In some embodiments, the second work function layer includes aluminum (Al). In some implementations, the portion of the sacrificial layer disposed between adjacent ones of the third vertically stacked channel elements prevents the first work function layer and the second work function layer from being deposited between adjacent ones of the third vertically stacked channel elements. In some cases, selectively removing the entire sacrificial layer in the second region requires the use of an etchant that has etch selectivity for the sacrificial layer.

Claims

[1] Semiconductor device comprising: a first GAA transistor (260A) comprising: - a plurality of first vertically stacked channel elements (2081); - an interface layer (222) over the plurality of first channel elements (2081); - a gate dielectric layer (228) over the interface layer (222); - a first work function layer (238) above and in contact with the gate dielectric layer (228); and - an adhesion layer (244) over the first work function layer (234); a second GAA transistor (260B) comprising: - a plurality of second vertically stacked channel elements (2082); - the interface layer (222) over the plurality of second channel elements (2082); - the gate dielectric layer (228) over the interface layer (222); - a second work function layer (234) above and in contact with the gate dielectric layer (228); - the first work function layer (238) above and in contact with the second work function layer (234); and - the adhesion layer (244) over the first work function layer (238); and a third GAA transistor (260C) comprising: - several third vertically stacked channel elements (2083); - the interface layer (222) over the plurality of third channel elements (2083); - the gate dielectric layer (228) over the interface layer (222); and - the adhesion layer (244) over the gate dielectric layer (228), - wherein the first work function layer and the second work function layer (238, 234) are removed in the third GAA transistor; and wherein the first work function layer (238) is an n-type work function layer and the second work function layer (234) is a p-type work function layer. [2] A semiconductor device according to claim 1, wherein the first work function layer (238) contains aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi) or hafnium carbide (HfC), wherein the second work function layer (234) contains titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN) or molybdenum (Mo). [3] The semiconductor device according to claim 2, wherein the adhesion layer contains titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN) or molybdenum (Mo). [4] Semiconductor device according to one of the preceding claims, wherein the first GAA transistor (260A) further comprises a passivation layer (240) disposed between the first work function layer (238) and the adhesion layer (244), wherein the second GAA transistor (260B) further comprises the passivation layer (240) disposed between the first work function layer and (238) the adhesion layer (244), wherein the third GAA transistor (260C) is free of the passivation layer (240). [5] A semiconductor device according to claim 4, wherein the first work function layer (238) has a thickness of 1 nm to about 3 nm, wherein the second work function layer (234) has a thickness of about 0.5 nm to about 2 nm, wherein the passivation layer (240) has a thickness of about 0.5 nm to about 2 nm, wherein the adhesive layer (244) has a thickness of about 2 nm to about 5 nm. [6] A semiconductor device according to claim 4 or 5, wherein the passivation layer (240) comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), silicon (Si), tantalum nitride (TaN) or tungsten carbonitride (WCN). [7] Semiconductor device according to one of the preceding claims, wherein the first GAA transistor (260A), the second GAA transistor (260B) and the third GAA transistor (260C) each further comprise a metal fill layer (246) over the adhesion layer (244), wherein the metal fill layer (246) comprises tungsten (W) or cobalt (Co). [8] A semiconductor device according to any one of the preceding claims, wherein the first work function layer (238) is arranged completely around each of the plurality of first channel elements (2081). [9] Method (100) comprising: Providing a workpiece (200) comprising a substrate (202), first vertically stacked channel elements (2081) in a first region (1000) of the substrate (202), second vertically stacked channel elements (2082) in a second region (2000) of the substrate (202), and third vertically stacked channel elements (2083) in a third region (3000) of the substrate (202); Depositing a gate dielectric layer (228) over the first vertically stacked channel elements (2081), the second vertically stacked channel elements (2082), and the third vertically stacked channel elements (2083); depositing a sacrificial layer (230) over the gate dielectric layer (228); Etching the sacrificial layer (230) such that a portion of the sacrificial layer (230) remains disposed between those of the first vertically stacked channel elements (2081), the second vertically stacked channel elements (2082), and the third vertically stacked channel elements (2083) which are adjacent; selectively removing the entire sacrificial layer (230) in the second region (2000); Depositing a first work function layer (234) over the first vertically stacked channel elements (2081), the second vertically stacked channel elements (2082) and the third vertically stacked channel elements (2083); selectively removing the first work function layer (234) and the sacrificial layer (230) in the first region (1000); Depositing a second work function layer (238) over the first vertically stacked channel elements (2081), the second vertically stacked channel elements (2082), and the third vertically stacked channel elements (2083), wherein the second work function layer (238) is different from the first work function layer (234), the first work function layer (234) is an n-type work function layer and the second work function layer (238) is a p-type work function layer, or the first work function layer (234) is a p-type work function layer and the second work function layer (238) is an n-type work function layer; and Depositing a passivation layer (240) over the second work function layer (238); and selectively removing the passivation layer (240), the first work function layer (234), the second work function layer (238), and the sacrificial layer (230) in the third region (3000). [10] The method (100) of claim 9, wherein providing the workpiece comprises: Forming a plurality of alternating semiconductor layers (204) over the first region (1000), the second region (2000) and the third region (3000) of the substrate (202), the plurality of alternating semiconductor layers (204) comprising a first plurality of first semiconductor layers (208) interleaved with a second plurality of second semiconductor layers (206); Structuring the plurality of alternating semiconductor layers (204) to form a first active region in the first region (1000), a second active region in the second region (2000), and a third active region in the third region (3000); and selectively removing the second plurality of second semiconductor layers (206) to form the first vertically stacked channel elements (2081) in the first active region and the second vertically stacked channel elements (2082) in the second active region and the third vertically stacked channel elements (2083) in the third active region. [11] The method (100) of claim 9 or 10, wherein etching the sacrificial layer (230) exposes the gate dielectric layer (228) deposited over side surfaces of the first vertically stacked channel elements (2081), the second vertically stacked channel elements (2082), and the third vertically stacked channel elements (2083). [12] The method (100) of any one of the preceding claims 9 to 11, wherein the sacrificial layer (230) comprises silicon oxide or silicon nitride. [13] Method (100) according to one of the preceding claims 9 to 12, wherein the first work function layer (234) contains aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi) or hafnium carbide (HfC), wherein the second work function layer (238) contains titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN) or molybdenum (Mo). [14] The method (100) of any one of the preceding claims 9 to 13, wherein the passivation layer (240) contains titanium nitride (TiN), titanium silicon nitride (TiSiN), silicon (Si), tantalum nitride (TaN) or tungsten carbonitride (WCN). [15] Method (100) according to one of the preceding claims 9 to 14, further comprising: Depositing an adhesion layer (244) over the first vertically stacked channel elements (2081), the second vertically stacked channel elements (2082), and the third vertically stacked channel elements (2083); and depositing a metal fill layer (246) over the adhesion layer (244). [16] Method (100) according to claim 15, wherein the adhesion layer (244) contains titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN) or molybdenum (Mo), wherein the metal fill layer (246) contains tungsten (W) or cobalt (Co). [17] The method (100) of claim 15, wherein the first work function layer (234) is a p-type work function layer and the second work function layer (238) is an n-type work function layer, wherein a composition of the first work function layer (234) is substantially identical to a composition of the adhesion layer (244). [18] The method (100) of claim 17, wherein the second work function layer (238) contains aluminum (Al). [19] The method (100) of claim 18, wherein the portion of the sacrificial layer (230) disposed between adjacent ones of the third vertically stacked channel elements (2083) prevents the first work function layer (234) and the second work function layer (234) from being deposited between the adjacent ones of the third vertically stacked channel elements (2083). [20] The method (100) of any one of the preceding claims 17 to 19, wherein selectively removing the entire sacrificial layer (230) in the second region (2000) comprises using an etchant having an etch selectivity for the sacrificial layer (230).

Images