Rough buffer layer for group III-V devices on silicon and methods for its production

Abstract

comprising a semiconductor device (100): a substrate (104); a group III-V buffer structure (108) that lies above the substrate; a group III-V heterotransition structure (100) that lies above the group III-V buffer structure; a pair of source / drain electrodes (130, 132) located above the group III-V heterojunction structure (100); a gate electrode (134) located laterally between the source / drain electrodes (130, 132) above the group III-V heterojunction structure (100); and a rough buffer layer (102) between the substrate (104) and the group III-V buffer structure (108), wherein the rough buffer layer (102) directly contacts the substrate and the group III-V buffer structure at a first interface (106a) and a second interface (106b), wherein the first interface (106a) is rough throughout and / or the second interface (106b) is rough throughout, and wherein the rough buffer layer (102) and the substrate (104) comprise monocrystalline silicon.

Description

GENERAL STATE OF THE ART

[0001] Silicon-based semiconductor devices have been the standard for several decades. However, semiconductor devices based on alternative materials are receiving increasing attention due to their advantages over silicon-based semiconductor devices. Semiconductor devices based on Group III-V semiconductor materials, for example, have received increased attention due to their high electron mobility and wide band gaps compared to silicon-based semiconductor devices. Such high electron mobility and wide band gaps enable improved performance and high-temperature applications.

[0002] US 2018 / 0 286 954 A1 relates to a structure having a nucleation layer and a group III nitride structure arranged on a surface of the nucleation layer, wherein the group III nitride structure comprises a plurality of pairs of stacked group III nitride layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 illustrates a cross-sectional view of some embodiments of a Group III-V device having a rough buffer layer. The Fig. 2A-2E illustrate enlarged cross-sectional views of various embodiments of the rough buffer layer of Fig. 1. The Fig. 3A-3C illustrate graphical representations of various embodiments of a curve showing the doping concentration of a buffer element along a thickness of the rough buffer layer of Fig. 1 describes. The Fig. 4A and Fig. 4B illustrate cross-sectional views of some alternative embodiments of the Group III-V device of Fig. 1, in which the rough buffer layer has several sublayers. The Fig. 5A to 5E illustrate cross-sectional views of various alternative embodiments of the Group III-V device of Fig. 1, in which source / drain electrodes and gate electrodes are varied. Fig. Figure 7 illustrates a cross-sectional view of some embodiments of the Group III-V device of Fig. 1, in which an interconnect structure covers a gate electrode and a pair of source / drain electrodes. The Fig. 6 to 16 illustrate a series of cross-sectional views of some embodiments of a method for forming a Group III-V device having a rough buffer layer. Fig. Figure 17 illustrates a flow diagram of some embodiments of the method of Fig. 6-16. DETAILED DESCRIPTION

[0004] The present disclosure provides many different embodiments or examples for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and also embodiments where additional functions may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.

[0005] Furthermore, for ease of discussion, spatially relative terms such as "beneath," "under," "lower," "over," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device during use or operation of the device, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] A Group III-V device is formed on a silicon substrate because, among other things, silicon substrates are inexpensive and readily available in a wide variety of sizes. Furthermore, in some embodiments, the Group III-V device includes an aluminum nitride (e.g., AlN) buffer layer and a Group III-V heterojunction structure overlying the aluminum nitride buffer layer. The aluminum nitride buffer layer directly contacts the silicon substrate at an interface and serves as a seed for epitaxially forming an overlying layer (e.g., another buffer layer).

[0007] A challenge with Group III-V devices is that the aluminum nitride buffer layer induces band bending at the interface, resulting in the formation of a two-dimensional hole gas (2DHG) in the silicon substrate. The 2DHG extends along the interface and has a high concentration of holes. Furthermore, the interface is flat, so the charge carrier mobility at the interface is high. The 2DHG and the high charge carrier mobility result in a low resistance at the interface, thus reducing the average resistance of the silicon substrate. This leads to substrate losses, which reduce the power efficiency (PAE) of the Group III-V device when used for radio frequency (RF) applications.

[0008] Various embodiments of the present application are directed to a Group III-V device comprising a rough buffer layer. The rough buffer layer overlies a silicon substrate, a Group III-V buffer structure overlies the rough buffer layer, and a Group III-V heterojunction structure overlies the Group III-V buffer structure. The Group III-V buffer structure causes band bending between the silicon substrate and the Group III-V buffer structure, and the band bending leads to the formation of a 2DHG in the rough buffer layer. The rough buffer layer comprises silicon and, in some embodiments, is doped with carbon, magnesium, zinc, arsenic, phosphorus, another suitable element(s), or any combination of the foregoing. A top surface of the rough buffer layer and / or a bottom surface of the rough buffer layer is / are rough to promote carrier scattering along the top and bottom surfaces.Charge carrier scattering reduces charge carrier mobility at the 2DHG, which increases the resistance at the 2DHG. This increased resistance increases the overall resistance of the silicon substrate, which increases the PAE of the Group III-V device when used for RF applications.

[0009] With reference to Fig. 1 provides a cross-sectional view 100 of a Group III-V device having a rough buffer layer 102. The Group III-V device is located on a substrate 104 and may be, for example, a Group III nitride device and / or a depletion-mode high-electron mobility transistor (D-HEMT). However, other device types are possible. The substrate 104 comprises monocrystalline silicon and, in at least some embodiments, is free of Group III-V semiconductor materials.

[0010] In some embodiments, a top surface of the substrate 104 is the same or substantially the same as the lattice plane (111) of the substrate 104. Substantially the same may mean, for example, that the lattice plane (111) and the top surface of the substrate 104 intersect at an offset angle of 4 degrees or less in each of the X, Y, and Z dimensions. However, other suitable offset angles are possible in the X, Y, and Z dimensions. In some embodiments, the substrate 104 is a bulk semiconductor substrate and / or a semiconductor wafer.

[0011] The rough buffer layer 102 overlies and directly contacts the substrate 104 at a first buffer interface 106a. Furthermore, a group III-V buffer structure 108 overlies and directly contacts the rough buffer layer 102 at a second buffer interface 106b, and a group III-V heterojunction structure 110 overlies the group III-V buffer structure 108. The group III-V buffer structure 108 and the rough buffer layer 102 can, for example, compensate for differences in lattice constants, crystalline structures, thermal expansion coefficients, or any combination of the foregoing between the substrate 104 and the group III-V heterojunction structure 110. The group III-V buffer structure 108 includes, among other layers, a seeding buffer layer 112.

[0012] The seed buffer layer 112 overlies and directly contacts the rough buffer layer 102 at the second buffer interface 106b. Furthermore, the seed buffer layer 112 serves as a seed or nucleation layer for growing a Group III-V semiconductor layer on the substrate 104. The seed buffer layer 112 may comprise, for example, aluminum nitride (e.g., AlN), another suitable Group III nitride, or another suitable Group III-V material. In some embodiments, the seed buffer layer 112 is a binary Group III-V semiconductor material. Furthermore, the seed buffer layer 112 may, for example, have a thickness of approximately 10 to 35 nm (100 to 350 angstroms) or another suitable value. The seeding buffer layer 112 induces band bending in the rough buffer layer 102 and the substrate 104.In at least some embodiments, such as when the substrate 104 and the rough buffer layer 102 are or comprise monocrystalline silicon, the band bending induces the formation of a 2DHG 114. The 2DHG 114 extends along the first buffer interface 106a and / or the second buffer interface 106b at the rough buffer layer 102. Furthermore, the 2DHG 114 has a high concentration of holes and therefore a low resistance. The low resistance of the 2DHG 114 reduces the overall resistance of the substrate 104, which increases substrate losses and reduces the PAE when the Group III-V device is used for RF applications.

[0013] The rough buffer layer 102 counteracts the negative effects of the 2DHG 114. An upper surface of the rough buffer layer 102 and a lower surface of the rough buffer layer 102 are rough, so that the first and second buffer interfaces 106a, 106b are rough. The roughness increases charge carrier scattering at the first and second buffer interfaces 106a, 106b and therefore reduces charge carrier mobility at the 2DHG 114. The reduced charge carrier mobility increases the resistance at the 2DHG 114 and therefore increases an overall resistance of the substrate 104. The increased overall resistance reduces substrate losses and increases the PAE when the Group III-V device is used for RF applications. For example, the PAE can be increased from approximately 54% to approximately 57% at a frequency of approximately 6 gigahertz (GHz).Furthermore, the increased total resistance improves coplanar waveguide (CPW) performance when the Group III-V device is used for RF applications. CPW is a short-loop test used to measure substrate losses by comparing the output power with the input power to determine how much power loss occurs during signal transmission. For example, CPW can be improved from approximately -0.51 decibels (dB) to approximately -0.45 dB at a frequency of approximately 6 GHz.

[0014] In some embodiments, the top and bottom surfaces of the rough buffer layer 102 are "rough" in that the top and bottom surfaces are uneven and have slopes that vary periodically or randomly across the top and bottom surfaces. In some embodiments, the top and bottom surfaces of the rough buffer layer 102 are "rough" in that the top and bottom surfaces have bumps, hills, protrusions, some other suitable features, or any combination of the foregoing features, periodically or randomly arranged across the top and bottom surfaces. For example, the top and bottom surfaces may have sawtooth-like profiles. As another example, the top and bottom surfaces may have wavy profiles. However, other profiles are possible.

[0015] In some embodiments, a thickness Tr of the rough buffer layer 102 is approximately 2 to 20 nm (20 to 200 angstroms), approximately 2 to 11 nm (20 to 110 angstroms), approximately 11 to 20 nm (110 to 200 angstroms), or another suitable value. In some embodiments, a total thickness variation (TTV) of the rough buffer layer 102 is approximately 1.2 to 5.0:1, approximately 1.2 to 3.1:1, approximately 3.1 to 5.0:1, or another suitable ratio. In some embodiments, TTV is a ratio of the largest thickness value of the rough buffer layer 102 to the smallest thickness value of the rough buffer layer 102. For example, assuming the rough buffer layer 102 has a maximum thickness value of 6.8 nm (68 angstroms) and a minimum thickness value of 3.2 nm (32 angstroms), then the TTV would be approximately 2.1. If the thickness Tr is too small (e.g., less than approximately 2 nm (20 angstroms) or another suitable value) and / or the TTV is too small (e.g.,less than approximately 1.2:1 or another suitable ratio), the rough buffer layer 102 may not be sufficiently rough to counteract the adverse effects of the 2DHG 114. If the thickness Tr is too large (e.g., greater than approximately 20 nm (200 angstroms) or another suitable value) and / or the TTV is too large (e.g., greater than approximately 5.0:1 or another suitable ratio), the crystalline quality of the seed buffer layer 112 may be poor and therefore lead to leakage currents and increased substrate losses.

[0016] The rough buffer layer 102 comprises a semiconductor material with a narrow band gap, such as silicon. A narrow band gap can, for example, be a band gap that is smaller than that of the seed buffer layer 112 and / or smaller than approximately 1.3 electron volts (eV), 1.0 eV, or another suitable value. In some embodiments, the band gap of the rough buffer layer 102 is smaller than that of a smallest band gap in the Group III-V buffer structure 108. In some embodiments, a band gap of the rough buffer layer 102 and a band gap of the substrate 104 are within approximately 0.1 eV, 0.5 eV, 0.7 eV, or another suitable value of each other. In some embodiments, the rough buffer layer 102 is or comprises a same material as the substrate 104. The rough buffer layer 102 and the substrate 104 comprise monocrystalline silicon.In at least some embodiments, the rough buffer layer 102 is free of Group III-V semiconductor materials. In some embodiments, the rough buffer layer 102 is a material that can serve as a seed for epitaxially growing the seed buffer layer 112.

[0017] In some embodiments, the rough buffer layer 102 is doped with a buffer element. The buffer element may then, for example, assist in the formation of the rough buffer layer 102 and / or cause the rough buffer layer 102 to be formed with rough surfaces. The buffer element may, for example, be carbon (e.g., C), magnesium (e.g., Mg), zinc (e.g., Zn), arsenic (e.g., Ar), phosphorus (e.g., P), or another suitable buffer element. In some embodiments, the buffer element is an n-type dopant. If the rough buffer layer 102 is or comprises silicon, the buffer element may, for example, be arsenic, phosphorus, or another suitable n-type dopant for silicon. The n-type dopant has excess electrons that counteract the holes in the 2DHG 114. By counteracting the holes, the n-type dopant increases a resistance of the 2DHG 114.This increased resistance, in turn, reduces substrate losses, increases PAE, and improves CPW. In alternative embodiments, the buffer element is a p-type dopant. In some embodiments, the rough buffer layer 102 is doped with multiple buffer elements, each of which is as described above.

[0018] Referring again to the Group III-V buffer structure 108, the Group III-V buffer structure 108 further includes a graded buffer layer 116 and an isolation buffer layer 118 stacked on top of one another. The graded buffer layer 116 overlies the seed buffer layer 112 and is or includes a Group III-V semiconductor material having, respectively, a first element and a second element having atomic percents that are graded. For example, the first element may have an atomic percent that increases from a lower surface of the graded buffer layer 116 to an upper surface of the graded buffer layer 116, whereas the second element may have an atomic percent that decreases from the lower surface to the upper surface. The graded buffer layer 116 may be or include, for example, aluminum gallium nitride (e.g., AlGaN), another suitable Group III nitride, or another suitable Group III-V material.

[0019] In some embodiments, the graded buffer layer 116 is or comprises a ternary Group III-V material, and the first and second elements of the graded buffer layer 116 are Group III elements. The graded buffer layer 116 may be or comprise aluminum gallium nitride, where the first element may be germanium (e.g., Ge) and the second element may be aluminum (e.g., Al). In some embodiments, the seed buffer layer 112 is or comprises a binary III-V group, the second element of the graded buffer layer 116 is the group III element of the seed buffer layer 112, and a group V element of the graded buffer layer 116 is the same as that of the seed buffer layer 112. For example, the graded buffer layer 116 may be or comprise aluminum gallium nitride, the seed buffer layer 112 may be or comprise aluminum nitride, and the second element may be aluminum.In some embodiments, the graded buffer layer 116 has a thickness of approximately 0.5 to 1.5 micrometers or another suitable value.

[0020] The isolation buffer layer 118 overlies the graded buffer layer 116 and is or comprises a Group III-V semiconductor material doped with a buffer element such that it has a high resistance. The high resistance may, for example, be a resistance higher than that of a channel layer 120, which will be described below. The high resistance allows the isolation buffer layer 118 to act as a "back barrier" for the channel layer 120 to reduce substrate losses and increase the soft breakdown voltage of the Group III-V device. The buffer element may, for example, be carbon, iron (e.g., Fe), other suitable buffer elements, or any combination of the foregoing. The isolation buffer layer 118 may, for example, be or comprise gallium nitride (e.g., GaN), another suitable Group III nitride, or another suitable Group III-V material.

[0021] In some embodiments, the isolation buffer layer 118 is or comprises a binary Group III-V material that includes a Group III element of the graded buffer layer 116 and further includes a Group V element of the graded buffer layer 116. For example, the isolation buffer layer 118 may be or comprise gallium nitride, and the graded buffer layer 116 may be or comprise aluminum gallium nitride. In some embodiments, a thickness of the isolation buffer layer 118 is approximately 0.5 to 2.5 micrometers, or another suitable value.

[0022] The group III-V heterojunction structure 110 overlies the group III-V buffer structure 108 and includes the channel layer 120 and a barrier layer 122. The barrier layer 122 overlies the channel layer 120 and is or includes a group III-V semiconductor material. Furthermore, the barrier layer 122 is polarized such that positive charge is shifted to a lower surface of the barrier layer 122 and negative charge is shifted to an upper surface of the barrier layer 122. The polarization may result, for example, from spontaneous polarization effects and / or piezoelectric polarization effects. The barrier layer 122 may be or include, for example, aluminum gallium nitride, another suitable group III nitride, or another suitable group III-V material.

[0023] In some embodiments, the barrier layer 122 is or comprises a ternary Group III-V material and / or comprises the same elements as the graded buffer layer 116. For example, the barrier layer 122 and the graded buffer layer 116 may be or comprise aluminum gallium nitride. In some embodiments, the barrier layer 122 is or comprises Al y Ga 1-y N, where y is approximately 0.1 to 0.2. In some embodiments, the barrier layer 122 has a thickness of approximately 5 to 30 nanometers or another suitable thickness value.

[0024] The channel layer 120 lies beneath the barrier layer 122 and directly contacts it. Furthermore, the channel layer 120 is an undoped Group III-V semiconductor material with a band gap that is unequal to that of the barrier layer 122. Due to the unequal band gaps, the channel layer 120 and the barrier layer 122 define a heterojunction at a heterojunction interface 124 where the channel layer 120 and the barrier layer 122 directly contact each other. Since the barrier layer 122 is polarized, a two-dimensional electron gas (2DEG) 126 forms in the channel layer 120. The 2DEG 126 extends along the heterojunction interface 124 and has a high concentration of mobile electrons. Due to the high concentration of mobile electrons, the 2DEG 126 is conductive. The channel layer 120 may be or comprise, for example, aluminum gallium nitride, another suitable Group III nitride, or another suitable Group III-V material.

[0025] In some embodiments, channel layer 120 is or includes a binary Group III-V material and / or the same elements as isolation buffer layer 118, but without the doping. Channel layer 120 and isolation buffer layer 118 may be or include aluminum gallium nitride, for example. In some embodiments, channel layer 120 has a thickness of approximately 0.2 to 0.6 micrometers or another suitable thickness.

[0026] A first passivation layer 128 overlies the group III-V heterojunction structure 110. A first source / drain electrode 130 and a second source / drain electrode 132 are laterally spaced apart from each other and extend through the first passivation layer 128 to the group III-V heterojunction structure 110. In some embodiments, the first and second source / drain electrodes 130, 132 make ohmic contact with the group III-V heterojunction structure 110. Further, a gate electrode 134 is laterally located between the first and second source / drain electrodes 130, 132 and extends through the first passivation layer 128 to the group III-V heterojunction structure 110. The first passivation layer 128 may be or include silicon oxide and / or other suitable dielectric(s). The first and second source / drain electrodes 130, 132 and / or the gate electrode 134 may comprise metal and / or another suitable material.other suitable conductive materials.

[0027] During use of the Group III-V device, the gate electrode 134 generates an electric field that affects the continuity of the 2DEG 126 from the first source / drain electrode 130 to the second source / drain electrode 132. For example, when the gate electrode 134 is biased at a voltage greater than a threshold voltage, the gate electrode 134 may generate an electric field that depletes an underlying portion of the 2DEG 126 of mobile electrons and breaks the continuity. As another example, the 2DEG 126 may be continuous from the first source / drain electrode 130 to the second source / drain electrode 132 when the gate electrode 134 is biased at a voltage less than the threshold voltage.

[0028] The substrate 104 comprises monocrystalline silicon; the rough buffer layer 102 comprises monocrystalline silicon doped with carbon, magnesium, zinc, phosphorus, or arsenic in some embodiments; the seed buffer layer 112 is or comprises aluminum nitride; the graded buffer layer 116 is or comprises aluminum gallium nitride; the isolation buffer layer 118 is or comprises gallium nitride doped with carbon or iron; the channel layer 120 is or comprises undoped gallium nitride; and the barrier layer 122 is or comprises aluminum gallium nitride. However, other materials are possible for one or more of the layers described above (e.g., the seed buffer layer 112 and / or the rough buffer layer 102).

[0029] With reference to Fig. 2A is an enlarged cross-sectional view 200A of some embodiments of the rough buffer layer 102 of Fig. 1. The enlarged cross-sectional view 200 can, for example, be viewed from within the circle in Fig. 1. The upper and lower surfaces of the rough buffer layer 102 include a plurality of features 202 arranged in periodic structures across the upper and lower surfaces. Further, the features 202 are uniform or substantially uniform in shape and size and have a tooth-like profile, such that the upper and lower surfaces have sawtooth profiles. However, other shapes, sizes, profiles, or any combination of the foregoing are possible for the features 202. For example, the features 202 may be bumps, etch bumps, protrusions, some other suitable feature type, or any combination of the foregoing.

[0030] With reference to Fig. 2B is an enlarged cross-sectional view 200B of some alternative embodiments of the rough buffer layer 102 of Fig. 2A, in which the features 202 are randomly distributed across the top and bottom surfaces of the rough buffer layer 102 and exhibit random variation in shape and size.

[0031] With reference to Fig. 2C is an enlarged cross-sectional view 200C of some alternative embodiments of the rough buffer layer 102 of Fig. 2B, in which the upper and lower surfaces of the rough buffer layer 102 are smoother. As such, the upper and lower surfaces of the rough buffer layer 102 have wavy profiles.

[0032] With reference to the Fig. 2D and Fig. 2E are enlarged cross-sectional views 200D, 200E of some alternative embodiments of the rough buffer layer 102 of Fig. 2A, in which the lower surface or the upper surface of the rough buffer layer 102 is flat or substantially flat. In Fig. 2D, the lower surface of the rough buffer layer 102 is flat or substantially flat. In Fig. 2E, the upper surface of the rough buffer layer 102 is flat or substantially flat.

[0033] While the Fig. 2D and Fig. 2E alternative embodiments of the rough buffer layer 102 of Fig. 2A, in which the bottom surface or the top surface of the rough buffer layer 102 is flat or substantially flat, alternative embodiments of the rough buffer layer 102 of Fig. 2B may also have a lower surface or upper surface, as shown in the Fig. 2D and Fig. 2E is flat or substantially flat. Similarly, alternative embodiments of the rough buffer layer 102 of Fig. 2C may also have a lower surface or upper surface formed as shown in Fig. 2D and Fig. 2E is flat or essentially flat.

[0034] With reference to the Fig. 3A to 3C, graphical representations 300A-300C of various embodiments of a curve 302 are provided illustrating the doping concentration of the buffer element along a thickness Tr of the rough buffer layer 102 of Fig. 1. As stated above, the buffer element may be, for example, carbon, magnesium, zinc, arsenic, phosphorus, or another suitable buffer element. The horizontal axis corresponds to the doping concentration, and the vertical axis corresponds to the location in the rough buffer layer 102. The vertical axis may, for example, correspond to line B in Fig. 1 correspond.

[0035] In the graphic representation 300A of Fig. 3A, the doping concentration of the buffer element is constant or substantially constant from the lower surface of the rough buffer layer 102 to the upper surface of the rough buffer layer.

[0036] In the graphic representation 300B of Fig. 3B, the doping concentration of the buffer element increases continuously and linearly from the bottom surface of the rough buffer layer 102 to the top surface of the rough buffer layer 102. Gradually varying the doping concentration of the buffer element can help minimize strain and / or lattice mismatch between different crystalline structures of the substrate 104 and the seed buffer layer 112.

[0037] In the graphic representation 300C of Fig. 3C, the doping concentration of the buffer element increases continuously and linearly from the lower surface of the rough buffer layer 102 to a midpoint between the upper surface of the rough buffer layer 102 and the lower surface. Furthermore, the doping concentration of the buffer element is constant or substantially constant from the midpoint to the upper surface of the rough buffer layer 102.

[0038] While the Fig. 3A to 3C illustrate some embodiments of the curve 302, other embodiments are possible. For example, the curve 302 may be in any of the Fig. 3B and Fig. 3C. As another example, the curve 302 of Fig. 3B may increase discretely and / or have a step profile from the lower surface of the rough buffer layer 102 to the upper surface of the rough buffer layer 102. As yet another example, the curve 302 of Fig. 3C may rise discretely and / or have a step profile from the lower surface of the rough buffer layer 102 to the midpoint between the upper and lower surfaces of the rough buffer layer 102.

[0039] With reference to Fig. 4A is a cross-sectional view 400A of some alternative embodiments of the Group III-V device of Fig. 1, in which the rough buffer layer 102 comprises a first rough buffer sublayer 102a and a second rough buffer sublayer 102b overlying the first rough buffer sublayer 102a. The first and second rough buffer sublayers 102a, 102b are each individual, like the rough buffer layer 102 in Fig. 1. However, the first and second rough buffer sublayers 102a, 102b have different buffer elements and / or different doping concentrations for respective buffer elements. For example, the first rough buffer sublayer 102a may be doped with carbon, and the second rough buffer sublayer 102b may be doped with magnesium. As another example, the first and second rough buffer sublayers 102a, 102b may be doped with carbon and each have different doping concentrations.

[0040] With reference to Fig. 4B is a cross-sectional view 400B of some alternative embodiments of the Group III-V device of Fig. 4A, in which the first and second rough buffer sublayers 102a, 102b repeat several times to define a periodic structure.

[0041] While the first rough buffer sublayer 102a of the Fig. 4A and Fig. 4B is how the rough buffer layer 102 in Fig. 1, the first rough buffer sublayer 102a may alternatively be like the rough buffer layer 102 as shown in any of the Fig. 2A to 2E. While the second rough buffer sublayer 102b of the Fig. 4A and Fig. 4B as the rough buffer layer 102, which in Fig. 1, the second rough buffer sublayer 102b may alternatively be like the rough buffer layer 102 as shown in any of the Fig. 2A to 2E. In some embodiments, the first and second rough buffer sublayers 102a, 102b correspond to the same embodiments of the rough buffer layer 102 in the Fig. 1 and 2A to 2E. In other embodiments, the first and second rough buffer sublayers 102a, 102b correspond to different embodiments of the rough buffer layer 102 in the Fig. 1 and 2A to 2E.

[0042] With reference to Fig. 5A is a cross-sectional view 500A of some alternative embodiments of the Group III-V device of Fig. 1, in which the first and second source / drain electrodes 130, 132 extend through the barrier layer 122 to the channel layer 120. As a result, the barrier layer 122 is cleared directly below the first and second source / drain electrodes 130, 132, and the 2DEG 126 has a discontinuity directly below the first and second source / drain electrodes 130, 132.

[0043] With reference to Fig. 5B is a cross-sectional view 500B of some alternative embodiments of the Group III-V device of Fig. 1, in which a cap layer 502 is located between the Group III-V heterojunction structure 110 and the first passivation layer 128. The cap layer 502 is or comprises an undoped Group III-V semiconductor material having a band gap different from that of the barrier layer 122. The cap layer 502 may be or comprise, for example, aluminum gallium nitride, another suitable Group III-nitride, or another suitable Group III-V material. In some embodiments, the cap layer 502 is or comprises a binary Group III-V material and / or the same elements as the channel layer 120.

[0044] In some embodiments, cap layer 502 is or comprises gallium nitride, barrier layer 122 is or comprises aluminum gallium nitride, and cap layer 502 and barrier layer 122 are formed in situ within a common process chamber and / or a common multi-chamber process tool. Cap layer 502 protects barrier layer 122 during formation of the Group III-V device, so that no native oxide forms from barrier layer 122. Instead, native oxide can form from cap layer 502. The native oxide of gallium nitride is more stable and easier to clean than native oxide of aluminum gallium nitride. Furthermore, cleaning native oxide from cap layer 502 poses no risk of damaging barrier layer 122.

[0045] With reference to Fig. 5C is a cross-sectional view 500C of some alternative embodiments of the Group III-V device of Fig. 5B, in which the cap layer 502 is doped with p-type dopants. In alternative embodiments, the cap layer 502 may be n-type doped. As a result of the p-type doping of the cap layer 502, the mobile electrons are distributed at the 2DEG 126, and the 2DEG 126 is dispersed toward the first and second source / drain electrodes 130, 132. Therefore, the Group III-V device is an enhancement-mode high-electron-mobility transistor (E-HEMT) or another suitable device type.

[0046] With reference to Fig. 5D is a cross-sectional view 500D of some alternative embodiments of the Group III-V device of Fig. 5A, in which a gate dielectric layer 504 separates the gate electrode 134 from the Group III-V heterojunction structure 110. As such, the Group III-V device is a depletion-mode metal-insulator-semiconductor HEMT (MIS-HEMT) or another suitable device type. The gate dielectric layer 504 may be, for example, aluminum oxide, silicon oxide, other suitable dielectric(s), or any combination of the foregoing.

[0047] With reference to Fig. 5E is a cross-sectional view 500E of some alternative embodiments of the Group III-V device of Fig. 5D, in which the gate electrode 134 and the gate dielectric layer 504 extend further through the barrier layer 122. As a result, the 2DEG 126 has a pause at the gate electrode 134. Further, the Group III-V device is an enhancement-mode MIS-HEMT or other suitable device type.

[0048] While the first and second source / drain electrodes 130, 132 extend to an upper surface of the barrier layer 122 in the Fig. 5B to 5E, the first and second source / drain electrodes 130, 132 may alternatively extend through the barrier layer 122 to the channel layer 120. While the gate electrode 134 may directly form combinations of the channel layer 120, the barrier layer 122 and the cap layer 502 in the Fig. 5A to 5C, the gate electrode 134 may alternatively be contacted from the channel layer 120, the barrier layer 122 and the cap layer 502 through the gate dielectric layer 504 of the Fig. 5D and Fig. 5E be separated. While the Fig. 5A to 5E illustrate the rough buffer layer 102 as having a single layer, the rough buffer layer 102 may alternatively have multiple layers than in the Fig. 4A and Fig. 4B. While the Fig. 5A to 5E, the rough buffer layer 102 having an upper surface and a lower surface as in Fig. 1, the rough buffer layer 102 may alternatively have a top surface and / or a bottom surface as in any of the Fig. 2A to 2E.

[0049] With reference to Fig. 6 is a cross-sectional view 600 of some embodiments of the Group III-V device of Fig. 1, in which an interconnect structure 602 covers the gate electrode 134 and the first and second source / drain electrodes 130, 132. Furthermore, a second passivation layer 604 is located between the first passivation layer 128 and the interconnect structure 602, and the first passivation layer 128 includes a lower dielectric layer 128a and an upper dielectric layer 128b overlying the lower dielectric layer 128a.

[0050] In some embodiments, the lower dielectric layer 128a is or comprises silicon oxide, silicon nitride, another suitable dielectric(s), or any combination of the foregoing. In some embodiments, the upper dielectric layer 128b is or comprises plasma-enhanced silicon oxide and / or another suitable dielectric(s). In some embodiments, the second passivation layer 604 is or comprises plasma-enhanced silicon nitride and / or another suitable dielectric(s).

[0051] The interconnect structure 602 includes an interlayer dielectric (ILD) layer 606 and an ILD liner 608 stacked over the gate electrode 134. The ILD liner 608 underlies the ILD layer 606 and separates the ILD layer 606 from the gate electrode 134 and the second passivation layer 604. The ILD liner 608 may be or include, for example, plasma-enhanced silicon oxide and / or other suitable dielectrics, whereas the ILD layer 606 may be or include, for example, non-plasma-enhanced silicon oxide and / or other suitable dielectrics. The interconnect structure 602 further includes a field plate 610 and a plurality of contact vias 612.

[0052] The field plate 610 wraps around an upper corner of the gate electrode 134 while remaining separated from the gate electrode 134 by the ILD liner 608. The contact vias 612 extend through the ILD layer 606 and the ILD liner 608 to the first and second source / drain electrodes 130, 132, respectively. While not shown, one or more other contact vias extend through the ILD layer 606 to the gate electrode 134 and / or the field plate 610. Further, while not shown, wires and additional vias are alternatively stacked over and electrically coupled to the contact vias. The field plate 610 and the contact vias 612 may, for example, be or include metal and / or other suitable conductive materials.

[0053] While Fig. 6 Changes to the Group III-V device of Fig. 1 describes the changes in Fig. 6 to the Group III-V device in any of the Fig. 4A, 4B and 5A-5E applicable. Fig. 5A, for example, the interconnect structure 602 of Fig. 6.

[0054] With reference to the Fig. 7-16, a series of cross-sectional views 700 to 1600 of some embodiments of a method for forming a Group III-V device having a rough buffer layer is provided. The method is described using embodiments of the Group III-V device in Fig. 6, but may also include embodiments in any of the Fig. 1, 4A, 4B and 5A to 5E.

[0055] As illustrated by the cross-sectional view 700 of Fig. 7, a substrate 104 is provided. The substrate 104 comprises silicon and, in at least some embodiments, is free of Group III-V semiconductor materials. The substrate 104 comprises monocrystalline silicon. In some embodiments, the substrate 104 is a bulk semiconductor substrate and / or a semiconductor wafer. In some embodiments, a top surface 104t of the substrate 104 is flat or substantially flat. Further, in some embodiments, the top surface 104t of the substrate 104 is the same or substantially the same as the lattice plane (111) of the substrate 104. Substantially the same may mean, for example, that the lattice plane (111) and the top surface 104t of the substrate 104 intersect at an offset angle of 4 degrees or less in each of the X, Y, and Z dimensions. However, other suitable offset angles are possible in the X, Y, and Z dimensions.

[0056] In some embodiments, before proceeding to the acts described thereafter with respect to Fig. 8, the upper surface 104t of the substrate 104 is pre-roughened. Such pre-roughening can, for example, improve the roughness of a subsequently formed rough buffer layer (see, for example, Fig. 8). The pre-roughening may be performed, for example, by a wet or dry blanket etch into the top surface 104t of the substrate 104, by a selective etch into the top surface 104t, or by another suitable pre-roughening process. The selective etching may, for example, use photolithography to transfer a rough structure to the top surface 104t of the substrate 104. In some embodiments where the top surface 104t of the substrate 104 is pre-roughened, the top surface 104t has the profile illustrated by a dashed line 702. However, other profiles are possible.

[0057] As shown in cross-sectional view 800 of Fig. As illustrated in Figure 8, a rough buffer layer 102 is formed overlying and directly contacting the top surface 104t of the substrate 104 at a first buffer interface 106a. Furthermore, the rough buffer layer 102 is formed within a first process chamber 802. A lower surface of the rough buffer layer 102 is rough, so that the top surface 104t of the substrate 104 and the first buffer interface 106a are rough. Furthermore, an upper surface of the rough buffer layer 102 is rough. Fig. Figure 2A illustrates an enlarged cross-sectional view 200A of some embodiments of the rough buffer layer 102 within circle A and the Fig. 2B to 2D illustrate enlarged cross-sectional views 200B to 200D of some alternative embodiments of the rough buffer layer 102 within circle A. As can be seen thereafter, the roughness increases resistance at the first buffer interface 106a to increase the PAE when the Group III-V device is used for RF applications.

[0058] In some embodiments, the upper and lower surfaces of the rough buffer layer 102 are "rough" in that the upper and lower surfaces are uneven and have slopes that vary periodically or randomly across the upper and lower surfaces. In some embodiments, the upper and lower surfaces of the rough buffer layer 102 are "rough" in that the upper and lower surfaces have bumps, hills, protrusions, some other suitable feature, or any combination of the foregoing features, periodically or randomly arranged across the upper and lower surfaces. In some embodiments, the upper and lower surfaces have sawtooth profiles, wavy profiles, serpentine profiles, or other suitable profiles.In some embodiments, a thickness Tr of the rough buffer layer 102 is approximately 2 to 20 nm (20 to 200 angstroms), approximately 2 to 11 nm (20 to 110 angstroms), approximately 11 to 20 nm (110 to 200 angstroms), or another suitable value. In some embodiments, a TTV of the rough buffer layer 102 is approximately 1.2 to 5.0, approximately 1.2 to 3.1, approximately 3.1 to 5.0, or another suitable value.

[0059] The rough buffer layer 102 comprises a semiconductor material with a narrow band gap, such as silicon. A narrow band gap can be, for example, a band gap that is smaller than that of the seed buffer layer 112 and / or smaller than approximately 1.3, 1.0, or another suitable value. In some embodiments, a band gap of the rough buffer layer 102 and a band gap of the substrate 104 are within approximately 0.1 eV, 0.5 eV, 0.7 eV, or another suitable value of each other. In some embodiments, the rough buffer layer 102 is or comprises a same material as the substrate 104. In at least some embodiments, the rough buffer layer 102 is free of Group III-V semiconductor materials. In some embodiments, the rough buffer layer 102 is a material that can serve as a seed for epitaxially growing a seed buffer layer, which is described below.

[0060] In some embodiments, the rough buffer layer 102 is doped with a buffer element. The buffer element can, for example, assist in or otherwise effect the formation of the rough buffer layer 102 with a rough upper and lower surface. The buffer element can, for example, replace a semiconductor element in the crystalline lattice of the rough buffer layer 102 to effect the roughness on the upper and lower surfaces of the rough buffer layer 102. Fig. 3A to 3C illustrate various embodiments of a curve 302 describing the doping concentration of the buffer element along the thickness Tr of the rough buffer layer 102 and / or along the line B. The buffer element may be or include, for example, carbon, magnesium, zinc, arsenic, phosphorus, or another suitable buffer element. In some embodiments, the buffer element is an n-type dopant. If the rough buffer layer 102 is or includes silicon, the buffer element may be, for example, arsenic, phosphorus, or another suitable n-type dopant for silicon. In alternative embodiments, the buffer element is a p-type dopant. In some embodiments, the rough buffer layer 102 is doped with multiple buffer elements, each of which is as described above.

[0061] The rough buffer layer 102 can be formed, for example, by an individual metal organic chemical vapor deposition (MOCVD) process, a split MOCVD process, a silicon epitaxy deposition process, or another suitable deposition process. The individual MOCVD process is unique to the rough buffer layer 102 and is not used to form the rough buffer layer 102 with a subsequently described seeding buffer layer. The split MOCVD process is shared by the rough buffer layer 102 and the subsequently described seeding buffer layer, so that the rough buffer layer 102 and the seeding buffer layer are formed together.

[0062] In at least some embodiments where the buffer element is or includes arsenic or phosphorus, the rough buffer layer 102 is formed by the silicon epitaxy deposition process. The silicon epitaxy deposition process may be or include, for example, molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), another suitable silicon epitaxy deposition process, or any combination of the foregoing. In at least some embodiments where the buffer element is or includes magnesium or zinc, the rough buffer layer 102 is formed by the individual MOCVD process. In at least some embodiments where the buffer element is or includes carbon, the rough buffer layer 102 is formed by the individual or split MOCVD process or the silicon epitaxy process.

[0063] In some embodiments, the individual MOCVD process comprises introducing a silicon-containing precursor and a buffer element-containing precursor into the first process chamber 802 at a process temperature of approximately 600 to 1000 degrees Celsius. However, other process temperatures are possible. The silicon-containing precursor may be or comprise, for example, silane (e.g., SiH4) or another suitable precursor containing silicon. In embodiments where the buffer element is or comprises carbon, the buffer element-containing precursor may be, for example, cyclohexane (e.g., C6H 12), trimethylaluminum (e.g., Al2(CH3)6), or another suitable precursor containing carbon. In embodiments where the buffer element is or comprises magnesium, the buffer element-containing precursor may be, for example, bis(cyclopentadienyl)magnesium (e.g., Cp2Mg) or another suitable precursor containing magnesium. In embodiments where the buffer element is or comprises zinc, the buffer element-containing precursor may be, for example, dimethylzinc (e.g., C2H6Zn) or another suitable precursor containing zinc.

[0064] As shown in cross-sectional view 900 of Fig. As illustrated in Figure 9, a seed buffer layer 112 is epitaxially formed overlying and directly contacting the rough buffer layer 102 at a second buffer interface 106b. Furthermore, the seed buffer layer 112 is formed using the rough buffer layer 102 as a seed or nucleation layer and within a second process chamber 902. The seed buffer layer 112 serves as a seed or nucleation layer for growing a Group III-V semiconductor layer that is subsequently formed on the seed buffer layer 112. The seed buffer layer 112 may comprise, for example, aluminum nitride, another suitable Group III-nitride, or another suitable Group III-V material. Furthermore, the seeding buffer layer 112 may, for example, have a thickness Ts of approximately 10 to 35 nm (100 to 350 angstroms) or another suitable value.

[0065] The seed buffer layer 112 may be formed, for example, by an MOCVD process or another suitable deposition process. In some embodiments, the seed buffer layer 112 is formed at a process temperature of approximately 700 to 1150 degrees Celsius and / or while the second process chamber 1102 has a chamber pressure of approximately 50 to 200 millibars. However, other process temperatures and / or combustion chamber pressures are possible.

[0066] In some embodiments, the seed buffer layer 112 and the rough buffer layer 102 are formed together in a common process chamber by the split MOCVD process specified above with respect to the formation of the rough buffer layer 102. In such embodiments, the first and second process chambers 802, 902 are configured according to the Fig. 8 and Fig. 9. Forming the seed buffer layer 112 and the rough buffer layer 102 by the split MOCVD process can, for example, improve throughput and reduce costs. In alternative embodiments, the seed buffer layer 112 and the rough buffer layer 102 are formed independently of each other in separate process chambers. In such embodiments, the first and second process chambers 802, 902 are configured according to the Fig. 8 and Fig. 9 different.

[0067] In some embodiments, the split MOCVD process comprises at least two steps: 1) a first step to form the rough buffer layer 102 doped with carbon; and 2) a second step to form the seed buffer layer 112 on the rough buffer layer 102. During the first step, a carbon-containing aluminum precursor is introduced into the common process chamber (e.g., the first and second process chambers 802, 902 according to the Fig. 8 and Fig. 9, which are the same in these embodiments). During the second step, a nitrogen precursor is also introduced into the common process chamber. Therefore, the carbonaceous aluminum precursor, but not the nitrogen precursor, is introduced into the common process chamber during the first step, and both the carbonaceous aluminum precursor and the nitrogen precursor are introduced into the common process chamber during the second step. The carbonaceous aluminum precursor may, for example, be or comprise trimethylaluminum or another suitable precursor. In some embodiments where the carbonaceous aluminum precursor is or comprises trimethylaluminum, the carbonaceous aluminum precursor is introduced into the common process chamber at approximately 90 to 120 standard cubic centimeters per minute (SCCM) or another suitable rate.The nitrogen precursor may be or comprise, for example, ammonia (e.g., NH3) or another suitable precursor. The first step may, for example, continue for approximately 30 to 180 seconds or another suitable period of time, and / or the second step may, for example, continue for approximately 3 to 30 minutes or another suitable period of time.

[0068] Because the seed buffer layer 112 is a different semiconductor material than the rough buffer layer 102 and the substrate 104, band bending occurs at the rough buffer layer 102 and the substrate 104. In at least some embodiments, the band bending induces the formation of a 2DHG 114 extending along the first and second buffer interfaces 106a, 106b at the rough buffer layer 102. The 2DHG 114 has a high concentration of holes and therefore a low resistance. The low resistance of the 2DHG 114 reduces the overall resistance of the substrate 104. The reduction in overall resistance increases the substrate losses and reduces the PAE when the Group III-V device is used for RF applications. Furthermore, the reduction in overall resistance degrades CPW when the Group III-V device is used for RF applications.

[0069] However, the rough buffer layer 102 counteracts the negative effects of the 2DHG 114. The roughness on the top and bottom surfaces of the rough buffer layer 102 increases charge carrier scattering on the top and bottom surfaces and therefore reduces charge carrier mobility at the 2DHG 114. The reduced charge carrier mobility increases a resistance at the 2DHG 114 and therefore increases a total resistance of the substrate 104. The increased total resistance reduces substrate losses and increases the PAE when the Group III-V device is used for RF applications. Furthermore, the increased total resistance improves CPW when the Group III-V device is used for RF applications.In at least some embodiments where the rough buffer layer 102 is doped with n-type dopants, excess electrons of the rough buffer layer 102 counteract holes of the 2DHG 114 and further increase the resistance at the 2DHG 114 to further reduce substrate losses.

[0070] As shown by the cross-sectional view 1000 of Fig. 10, a graded buffer layer 116 is formed on the seed buffer layer 112. The graded buffer layer 116 is or comprises a Group III-V semiconductor material having, respectively, a first element and a second element having atomic percents that are graded. For example, the first element may have an atomic percent that increases from a lower surface of the graded buffer layer 116 to an upper surface of the graded buffer layer 116, whereas the second element may have an atomic percent that decreases from the lower surface to the upper surface. The first and second buffer layers may, for example, be Group III elements. The second element may, for example, be a Group III element of the seed buffer layer 112 and / or the first may, for example, be a Group III element found in Group III-V layers subsequently formed on the graded buffer layer.The graded buffer layer 116 may be or include, for example, aluminum gallium nitride, another suitable Group III nitride, or another suitable Group III-V material. In some embodiments, the graded buffer layer 116 has a thickness Tg of approximately 0.5 to 1.5 micrometers or another suitable value.

[0071] The graded buffer layer 116 may be formed, for example, by MOCVD, another suitable epitaxial process, or another suitable deposition process. In some embodiments, the graded buffer layer 116 is formed at a process temperature of approximately 1000 to 1150 degrees Celsius and / or within a process chamber with a chamber pressure of approximately 50 to 200 millibars. However, other process temperatures and / or combustion chamber pressures are possible.

[0072] As shown in cross-sectional view 1100 of Fig. As illustrated in Figure 11, an isolation buffer layer 118 is formed on the graded buffer layer 116. The isolation buffer layer 118 is or comprises a group III-V semiconductor material doped with a buffer element so that it has a high resistance. The high resistance may, for example, be a resistance higher than that of a channel layer described below (see, for example, Fig. 12). The high resistance allows the isolation buffer layer 118 to act as a "back barrier" for a subsequently formed channel layer to reduce substrate losses and increase the soft breakdown voltage of the Group III-V device being formed. The buffer element may be, for example, carbon, iron, or another suitable buffer element. The isolation buffer layer 118 may be or include, for example, gallium nitride, another suitable Group III nitride, or another suitable Group III-V material. In some embodiments, the isolation buffer layer 118 shares a Group III element and / or a Group V element with the graded buffer layer 116 and / or the seed buffer layer 112. In some embodiments, a thickness of the isolation buffer layer 118 is approximately 0.5 to 2.5 micrometers or another suitable value.

[0073] The insulation buffer layer 118 may be formed, for example, by MOCVD, another suitable epitaxial process, or another suitable deposition process. In some embodiments, the insulation buffer layer 118 is formed at a process temperature of approximately 900 to 1050 degrees Celsius and / or within a process chamber with a chamber pressure of approximately 50 to 500 millibars. However, other process temperatures and / or combustion chamber pressures are possible.

[0074] Together, the seed buffer layer 112, the graded buffer layer 116, and the isolation buffer layer 118 define a Group III-V buffer structure 108. The Group III-V buffer structure 108 and the rough buffer layer 102 can, for example, compensate for differences in lattice constants, crystalline structures, thermal expansion coefficients, or any combination of the foregoing between the substrate 104 and a heterojunction structure subsequently formed on the Group III-V buffer structure 108. By compensating for these differences, the Group III-V buffer structure 108 and the rough buffer layer 102 can mitigate stress, which can, for example, reduce leakage current and / or warpage of the substrate 104.

[0075] As shown in cross-sectional view 1200 of Fig. 12, a channel layer 120 is formed on the isolation buffer layer 118. The channel layer 120 is or comprises an undoped Group III-V semiconductor material. In some embodiments, the channel layer 120 is or comprises the same Group III-V semiconductor material as the isolation buffer layer 118, except that the channel layer 120 is undoped, whereas the isolation buffer layer 118 is doped. The channel layer 120 may be or comprise, for example, aluminum gallium nitride, another suitable Group III nitride, or another suitable Group III-V material. In some embodiments, the channel layer 120 has a thickness Tc of approximately 0.2 to 0.6 micrometers, or another suitable thickness value.

[0076] The channel layer 120 may be formed, for example, by MOCVD, another suitable epitaxial process, or another suitable deposition process. In some embodiments, the channel layer 120 is formed at a process temperature of approximately 950 to 1050 degrees Celsius and / or within a process chamber with a chamber pressure of approximately 100 to 650 millibars. However, other process temperatures and / or combustion chamber pressures are possible.

[0077] As shown in cross-sectional view 1300 of Fig. As illustrated in Figure 13, a barrier layer 122 is formed over and directly contacting the channel layer 120. The barrier layer 122 is a Group III-V semiconductor material with a band gap unequal to that of the channel layer 120. Due to the unequal band gaps, the channel layer 120 and the barrier layer 122 define a heterojunction at a heterojunction interface 124 where the channel layer 120 and the barrier layer 122 directly contact each other. Therefore, the channel layer 120 and the barrier layer 122 together define a Group III-V heterojunction structure 110. Furthermore, the barrier layer 122 is polarized such that positive charge is shifted to a lower surface of the barrier layer 122 and negative charge is shifted to an upper surface of the barrier layer 122. Because the barrier layer 122 is polarized, a 2DEG 126 forms in the channel layer 120.The 2DEG 126 extends along the heterojunction interface 124 and has a high concentration of mobile electrons. Due to the high concentration of mobile electrons, the 2DEG 126 is conductive. The barrier layer 122 may, for example, be or comprise aluminum gallium nitride, another suitable Group III nitride, or another suitable Group III-V material. In some embodiments, the barrier layer 122 is or comprises Al. y Ga 1-y N, where y is approximately 0.1 to 0.2. In some embodiments, the barrier layer 122 has a thickness Tb of approximately 5 to 30 nanometers or another suitable thickness value.

[0078] The barrier layer 122 may be formed, for example, by MOCVD, another suitable epitaxial process, or another suitable deposition process. In some embodiments, the barrier layer 122 is formed at a process temperature of approximately 1000 to 1100 degrees Celsius and / or within a process chamber with a chamber pressure of approximately 50 to 100 millibars. However, other process temperatures and / or combustion chamber pressures are possible.

[0079] While not shown, a cap layer may be formed on the graded buffer layer 116 before a first passivation layer is subsequently deposited at Fig. 14 is formed. The cap layer is or comprises an undoped Group III-V semiconductor material having a band gap different from that of the barrier layer 122. The cap layer may be or comprise, for example, aluminum gallium nitride, another suitable Group III nitride, or another suitable Group III-V material. In some embodiments, the cap layer 502 is or comprises a binary Group III-V material and / or the same elements as the channel layer 120. In one embodiment, the cap layer is undoped, an example of which is described with respect to Fig. 5B. In alternative embodiments, the cap layer is doped with p- or n-type dopants, an example of which is described with reference to Fig. 5C is described.

[0080] In some embodiments, the cap layer is or comprises gallium nitride, the barrier layer 122 is or comprises aluminum gallium nitride, and the cap layer and barrier layer 122 are formed in situ within a common process chamber and / or a common multi-chamber process tool. The cap layer protects the barrier layer 122 during formation of the Group III-V device, so that no native oxide forms from the barrier layer 122. Instead, native oxide can form from the cap layer. The native oxide of gallium nitride is more stable and easier to clean than native oxide of aluminum gallium nitride. Furthermore, cleaning native oxide from the cap layer does not pose a risk of damaging the barrier layer 122.

[0081] As shown in cross-sectional view 1400 of Fig. As illustrated in Figure 14, a first passivation layer 128 is formed over the Group III-V heterojunction structure 110. The first passivation layer 128 includes a lower dielectric layer 128a and an upper dielectric layer 128b overlying the lower dielectric layer 128a. In alternative embodiments, the lower or upper dielectric layer 128a, 128b is omitted. The lower dielectric layer may be or include, for example, silicon oxide, silicon nitride, other suitable dielectric(s), or any combination of the foregoing. The upper dielectric layer 128b may be or include, for example, plasma-enhanced silicon oxide and / or other suitable dielectric(s).The first passivation layer 128 may be formed, for example, by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), atomic layer deposition (ALD), other suitable deposition process(es), or any combination of the foregoing.

[0082] As also shown by the cross-sectional view 1400 of Fig. 14, a first source / drain electrode 130 and a second source / drain electrode 132 are formed overlying the first passivation layer 128. Further, the first and second source / drain electrodes protrude through the first passivation layer 128 and terminate at an upper surface of the barrier layer 122. In alternative embodiments, the first and second source / drain electrodes 130, 132 protrude through the barrier layer 122 and terminate at the channel layer 120. See, for example, Fig. 5A. The first and second source / drain electrodes 130, 132 may be or comprise, for example, metal and / or other suitable conductive materials.

[0083] A process for forming the first and second source / drain electrodes 130, 132 may, for example, include: 1) patterning the first passivation layer 128 to form openings corresponding to the first and second source / drain electrodes 130, 132; 2) depositing a metal layer covering the first passivation layer and filling the openings; and 3) patterning the metal layer into the first and second source / drain electrodes 130, 132. However, other processes are possible. Patterning the first passivation layer 128 and the metal layer may, for example, each be performed by a photolithography / etching process or another suitable patterning process. The photolithography / etching process for at least the first passivation layer 128 may, for example, use dry etching or another suitable etching type. Deposition of the metal layer may, for example, be performed by PECVD, LPCVD, APCVD, ALD, or another suitable method.other suitable deposition processes or any combination of the foregoing.

[0084] As shown in the cross-sectional view 1500 of Fig. 15, a second passivation layer 604 and a gate electrode 134 are formed over the first and second source / drain electrodes 130, 132 and the first passivation layer 128. The gate electrode 134 overlies the second passivation layer 604 and protrudes through the first and second passivation layers 128, 604. Further, the gate electrode 134 protrudes to and terminates at a top surface of the barrier layer 122. The second passivation layer 604 may, for example, be or include plasma-enhanced silicon nitride and / or other suitable dielectric(s). The second passivation layer 604 may, for example, be formed in the same way as the first passivation layer 128 is formed. The gate electrode 134 may, for example, be or include metal and / or other suitable conductive materials.The gate electrode 134 may, for example, be formed in the same way as the first and second source / drain electrodes 130, 132 are formed.

[0085] While the first and second source / drain electrodes 130, 132 and the gate electrode 134 are illustrated as being formed separately, the first and second source / drain electrodes 130, 132 and the gate electrode 134 may alternatively be formed together. In such embodiments, the second passivation layer 604 is omitted. Furthermore, the aforementioned process for forming the first and second source / drain electrodes 130, 132 forms the gate electrode 134 parallel to the first and second source / drain electrodes 130, 132. While the gate electrode 134 extends to the group III-V heterojunction structure 110, a gate dielectric layer may alternatively be formed separating the gate electrode 134 from the group III-V heterojunction structure 110. Examples of such a gate dielectric layer are shown in FIGS. Fig. 5D and Fig. 5E given.

[0086] As shown in the cross-sectional view 1600 of Fig. 16, an interconnect structure 602 is formed over the second passivation layer 604 and the gate electrode 134. The interconnect structure 602 includes an ILD layer 606 and an ILD liner 608. The ILD liner 608 underlies the ILD layer 606 and separates the ILD layer 606 from the gate electrode 134 and the second passivation layer 604. The interconnect structure 602 further includes a field plate 610 and a plurality of contact vias 612 in the ILD layer 606. The field plate 610 wraps around an upper corner of the gate electrode 134 while remaining separated from the gate electrode 134 by the ILD liner 608. The contact vias 612 extend through the ILD layer 606 and the ILD liner 608 to the first and second source / drain electrodes 130, 132, respectively.

[0087] While the Fig. 7 to 16 are described with reference to a method, it is understood that the Fig. 7 to 16 are not limited to the method, but rather can be independent and separate from the method. While the Fig. 7 to 16 are described as a series of acts, it is understood that the order of the acts may be changed in other embodiments. While the Fig. 7 to 16 as a specific set of acts, some acts illustrated and / or described may be omitted in other embodiments. Furthermore, acts not illustrated and / or described may be included in other embodiments.

[0088] With reference to Fig. 17 is a block diagram 1700 of some embodiments of the method of Fig. 7 to 16 provided.

[0089] At 1702, a rough buffer layer is deposited on a substrate. See, for example, Fig. 8.

[0090] In 1704, a group III-V buffer structure is formed on the rough buffer layer. See, for example, the Fig. 9 to 11. In 1704a, forming the Group III-V buffer structure comprises depositing a seeding buffer layer on the rough buffer layer. See, for example, Fig. 9. In 1704b, forming the group III-V buffer structure comprises depositing a graded buffer layer on the seeding buffer layer. See, for example, Fig. 10. In 1704c, forming the Group III-V buffer structure comprises depositing an insulating buffer layer on the graded buffer layer. See, for example, Fig. 11. In alternative embodiments, the Group III-V buffer structure is completely omitted. In alternative embodiments, the Group III-V buffer structure is partially omitted, so that the seeding buffer layer, the graded buffer layer, the isolation buffer layer, other buffer layer(s) (not shown in the Fig. 7 to 16) or any combination of the foregoing is / are omitted.

[0091] The seeding buffer layer induces the formation of a 2DHG in the rough buffer layer. This, in turn, reduces substrate resistance and increases substrate losses, thereby reducing the PAE when the Group III-V device is used for RF applications. However, the rough surfaces of the rough buffer layer counteract the negative effects of the 2DHG caused by stray charge carriers at the rough surfaces. This reduces charge carrier mobility at the 2DHG and increases the resistance at the 2DHG. The increased resistance, in turn, reduces substrate losses and increases the PAE.

[0092] At 1706, a group III-V heterojunction structure is formed on the group III-V buffer structure. See, for example, the Fig. 12 and Fig. 13.

[0093] At 1708, a pair of source / drain electrodes and a gate electrode are formed on the group III-V heterojunction structure. See, for example, the Fig. 14 and Fig. 15.

[0094] While the block diagram 1700 of Fig. 17 is illustrated and described herein as a series of acts or events, it is understood that the illustrated order of such acts or events is not intended to be limiting. For example, some acts other than those illustrated and / or described herein may occur in a different order and / or concurrently with other acts or events. Further, not all of the illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.

[0095] The present invention provides a semiconductor device comprising: a substrate; a group III-V buffer structure overlying the substrate; a group III-V heterojunction structure overlying the group III-V buffer structure; a pair of source / drain electrodes overlying the group III-V heterojunction structure; a gate electrode overlying the group III-V heterojunction structure laterally between the source / drain electrodes; and a rough buffer layer between the substrate and the group III-V buffer structure, wherein the rough buffer layer directly contacts the substrate and the group III-V buffer structure at a first interface and a second interface, respectively, wherein the first interface is continuously rough and / or the second interface is continuously rough, wherein the rough buffer layer shares a common semiconductor element with the substrate, and wherein the rough buffer layer and the substrate comprise monocrystalline silicon.In some embodiments, the first or second interface has a corrugated profile alternating between randomly sized bumps. In some embodiments, a thickness of the rough buffer layer varies throughout the rough buffer layer. In some embodiments, the thickness of the rough buffer layer has a maximum thickness value and a minimum thickness value, where the maximum thickness value is approximately 1.2 to 5.1 times the minimum thickness value. In some embodiments, the first and second interfaces are continuously rough. In some embodiments, the monocrystalline silicon is doped with carbon, magnesium, zinc, arsenic, or phosphorus.In some embodiments, the Group III-V buffer structure comprises: an aluminum nitride layer overlying and directly contacting the rough buffer layer; and a graded aluminum gallium nitride layer overlying the aluminum nitride layer and having an atomic percentage of aluminum that is graded from top to bottom.

[0096] The present invention provides another semiconductor device comprising: a silicon substrate; a group III-V buffer structure overlying the silicon substrate; a group III-V heterojunction structure overlying the group III-V buffer structure; a pair of source / drain electrodes overlying the group III-V heterojunction structure; a gate electrode laterally overlying the group III-V heterojunction structure between the source / drain electrodes; a buffer layer between the silicon substrate and the group III-V buffer structure; and a 2DHG in the buffer layer, wherein an upper surface of the buffer layer and / or a lower surface of the buffer layer is configured to scatter holes in the 2DHG to reduce carrier mobility in the 2DHG, wherein the rough buffer layer and the substrate comprise monocrystalline silicon.In some embodiments, the top and bottom surfaces of the buffer layer include a plurality of randomly sized bumps arranged throughout. In some embodiments, one of the top and bottom surfaces of the buffer layer is rough compared to another of the top and bottom surfaces of the buffer layer. In some embodiments, the buffer layer includes silicon doped with an n-type dopant, wherein the silicon substrate is substantially free of the n-type dopant. In some embodiments, the Group III-V buffer structure includes a Group III-V layer consisting essentially of aluminum and nitride, the Group III-V layer overlying and directly contacting the buffer layer. In some embodiments, the buffer layer consists essentially of doped silicon.

[0097] The present invention provides a method of forming a semiconductor device, the method comprising: depositing a rough buffer layer over and in direct contact with a top surface of a substrate, wherein the depositing of the rough buffer layer roughens the top surface of the substrate, wherein the rough buffer layer and the substrate comprise monocrystalline silicon; depositing a seed buffer layer over and in direct contact with the rough buffer layer; forming a heterojunction structure overlying the seed buffer layer; forming a pair of source / drain electrodes on the heterojunction structure; and forming a gate electrode on the heterojunction structure laterally between the source / drain electrodes.In some embodiments, the rough buffer layer is deposited in a first process chamber, and the seed buffer layer is deposited in a second process chamber that is different from the first process chamber. In some embodiments, depositing the rough buffer layer comprises MOCVD using a first precursor comprising silicon and a second precursor comprising carbon, magnesium, or zinc. Deposition of the rough buffer layer is performed by a silicon epitaxy tool and forms the rough buffer layer including silicon, which in some embodiments is doped with arsenic or phosphorus. In some embodiments, the rough buffer layer and the seed buffer layer are deposited in a common process chamber.In some embodiments, the rough buffer layer and the seed buffer layer are deposited using a split MOCVD process, the split MOCVD process comprising: introducing a first precursor, but not a second precursor, into the common process chamber to form the rough buffer layer; and after forming the rough buffer layer, introducing both the first and second precursors into the common process chamber to form the seed buffer layer. In some embodiments, the seed buffer layer induces the formation of a 2DHG along the top surface of the substrate.

Claims

[1] A semiconductor device (100) comprising: a substrate (104); a group III-V buffer structure (108) overlying the substrate; a group III-V heterojunction structure (100) overlying the group III-V buffer structure; a pair of source / drain electrodes (130, 132) overlying the group III-V heterojunction structure (100); a gate electrode (134) disposed over the group III-V heterojunction structure (100) laterally between the source / drain electrodes (130, 132); and a rough buffer layer (102) between the substrate (104) and the Group III-V buffer structure (108), wherein the rough buffer layer (102) directly contacts the substrate and the Group III-V buffer structure at a first interface (106a) and a second interface (106b), respectively, wherein the first interface (106a) is continuously rough and / or the second interface (106b) is continuously rough, and wherein the rough buffer layer (102) and the substrate (104) comprise monocrystalline silicon. [2] A semiconductor device according to claim 1, wherein the first or second interface (106a, 106b) has a wavy profile alternating between randomly sized bumps. [3] A semiconductor device according to claim 1 or 2, wherein the thickness (Tr) of the rough buffer layer (102) varies over the entire rough buffer layer. [4] The semiconductor device according to claim 3, wherein the thickness (Tr) of the rough buffer layer (102) has a maximum thickness value and a minimum thickness value, and wherein the maximum thickness value is approximately 1.2 to 5.1 times the minimum thickness value. [5] A semiconductor device according to any preceding claim, wherein the first and second interfaces (106a, 106b) are continuously rough. [6] A semiconductor device according to any preceding claim, wherein the monocrystalline silicon of the rough buffer layer (102) is doped with magnesium, zinc, arsenic or phosphorus. [7] A semiconductor device according to any preceding claim, wherein the group III-V buffer structure (108) comprises: an aluminum nitride layer (112) overlying and directly contacting the rough buffer layer (102); and a graded aluminum gallium nitride layer (1116) overlying the aluminum nitride layer (112) and having a top-to-bottom graded atomic percentage of aluminum. [8] Semiconductor device (100) comprising: a silicon substrate (104); a group III-V buffer structure (108) overlying the silicon substrate; a group III-V heterojunction structure (100) overlying the group III-V buffer structure (108); a pair of source / drain electrodes (130, 132) overlying the group III-V heterojunction structure (100); a gate electrode (134) overlying the group III-V heterojunction structure (100) laterally between the source / drain electrodes (130, 132); a rough buffer layer (102) between the silicon substrate (104) and the group III-V buffer structure (108); and a two-dimensional hole gas 2DHG in the rough buffer layer (102), wherein an upper surface of the buffer layer and / or a lower surface of the buffer layer is / are configured to scatter mobile holes in the 2DHG to reduce the charge carrier mobility in the 2DHG, wherein the rough buffer layer (102) and the substrate (104) comprise monocrystalline silicon. [9] The semiconductor device of claim 8, wherein the upper and lower surfaces (106a, 106b) of the buffer layer (102) include a plurality of randomly sized bumps (202) arranged continuously. [10] A semiconductor device according to claim 8 or 9, wherein one of the upper and lower surfaces (106a, 106b) of the buffer layer (102) is rough compared to another of the upper and lower surfaces of the buffer layer (102). [11] A semiconductor device according to any one of the preceding claims 8 to 10, wherein the silicon of the buffer layer (102) is doped with an n-type dopant, and wherein the silicon substrate is substantially free of the n-type dopant. [12] A semiconductor device according to any one of the preceding claims 8 to 11, wherein the group III-V buffer structure (108) comprises a group III-V layer (112) consisting essentially of aluminum and nitride, and wherein the group III-V layer (112) overlies and directly contacts the buffer layer (102). [13] A semiconductor device according to claim 12, wherein the buffer layer (102) consists essentially of doped silicon. [14] A method (700) for forming a semiconductor device (600), the method comprising: Depositing a rough buffer layer (102) over and in direct contact with an upper surface of a substrate (104), wherein the deposition of the rough buffer layer (102) is performed by a silicon epitaxy tool and roughens the upper surface of the substrate (104), wherein the rough buffer layer (102) and the substrate (104) comprise monocrystalline silicon; Depositing a nucleation buffer layer (112) over and in direct contact with the rough buffer layer (102); Forming a heterojunction structure (110) overlying the seeding buffer layer (112); Forming a pair of source / drain electrodes (130, 132) on the heterojunction structure (110); and Forming a gate electrode (134) on the heterojunction structure (110) laterally between the source / drain electrodes (130, 132), wherein the rough buffer layer (102) has an upper and / or lower surface having bumps, hillocks, or protrusions, or a combination thereof, arranged periodically or randomly across the upper and lower surfaces of the rough buffer layer (102). [15] The method of claim 14, wherein the rough buffer layer (102) is deposited in a first process chamber (802), and wherein the seeding buffer layer (112) is deposited in a second process chamber (902) different from the first process chamber. [16] The method of claim 14 or 15, wherein depositing the rough buffer layer (102) comprises metal organic chemical vapor deposition, MOCVD, using a first precursor comprising silicon and a second precursor comprising carbon, magnesium, or zinc. [17] A method according to any one of the preceding claims 14 to 16, wherein the rough buffer layer (102) comprises silicon doped with arsenic or phosphorus. [18] The method of claim 14, wherein the rough buffer layer (102) and the seeding buffer layer (112) are deposited in a common process chamber (802, 902). [19] The method of claim 18, wherein the rough buffer layer (102) and the seed buffer layer (112) are deposited by a split metal organic chemical vapor deposition, MOCVD, process, and wherein the split MOCVD process comprises: introducing a first precursor, but not a second precursor, into the common process chamber to form the rough buffer layer (102); and after forming the rough buffer layer (102), introducing both the first and second precursors into the common process chamber to form the seeding buffer layer (112). [20] The method of any one of the preceding claims 14 to 19, wherein the seeding buffer layer (112) induces the formation of a two-dimensional hole gas (114) along the upper surface of the substrate (104).

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