FIELD PLATE AND INSULATION STRUCTURE FOR HIGH-VOLTAGE ELEMENT

Abstract

Featuring an integrated chip: a gate electrode (110) located above a substrate (102) between a source region (104) and a drain region (106); an etch stop layer (122) extending laterally from an upper surface of the gate electrode (110) to a front face (102f) of the substrate (102), wherein the etch stop layer (122) lies over a drift region (114) located between the source region (104) and the drain region (106); a field plate (124) arranged within a first ILD layer (118) lying above the substrate (102), the field plate (124) extending from a top surface of the first ILD layer (124) to a top surface of the etch stop layer (122); and an insulation structure (132) arranged within the substrate (102) and extending from the front (102f) of the substrate (102) to a point below the front (102f) of the substrate (102), wherein the insulation structure (132) is arranged laterally between the gate electrode (110) and the drain region (106), wherein the field plate (124) lies above the insulation structure (132), and wherein the field plate (124) has the following: a first field plate structure (126) extending from the top surface of the first ILD layer (118) to the top surface of the etch stop layer (122); and a second field plate structure (128) extending from the top surface of the first ILD layer (118) to the top surface of the etch stop layer (122), wherein the second field plate structure (128) is offset laterally from the first field plate structure (126) by a distance greater than zero, wherein at least one section of the second field plate structure (128) lies directly above the insulation structure (132).

Description

STATE OF THE ART

[0001] Today's integrated chips feature millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Integrated chips (ICs) can use many different types of transistor devices depending on an IC's application. In recent years, the growing market for mobile and RF devices has resulted in a significant increase in the use of high-voltage transistor devices. For example, high-voltage transistor devices are often used in power amplifiers in RF transmit / receive chains due to their ability to handle high breakdown voltages (e.g., greater than about 50 V) and high frequencies. US 2019 / 0088777 A1 relates to an integrated chip.In some embodiments, the integrated chip includes a gate structure disposed over a substrate between the source and drain regions and a dielectric layer extending laterally from above the gate structure to between the gate structure and the drain region. A composite etch stop layer comprising a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts the top and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and extends vertically from the top of the first ILD layer, through the contact etch stop layer, into the composite etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 illustrates a cross-sectional view of some embodiments of a high voltage transistor device having a field plate over a buried isolation structure. Fig. Figure 2 illustrates a cross-sectional view of some alternative embodiments of the high voltage transistor of Fig. 1. Fig. 3A-3F illustrate cross-sectional views of various alternative embodiments of an integrated chip including a high voltage side-diffused metal oxide semiconductor field effect transistor (MOSFET-LDMOS) device having a field plate overlying a buried isolation structure. Fig. 4-11 illustrate cross-sectional views of some embodiments of a method for forming an integrated chip including a high voltage LDMOS device having a field plate over a buried isolation structure. Fig. 12 illustrates a methodology in flowchart format illustrating some embodiments of a method for forming a high voltage LDMOS device having a field plate over a buried isolation structure. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments, or examples, for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition is for the purpose of simplification and clarity and does not in itself imply any relationship between the different embodiments and / or configurations discussed.

[0004] Furthermore, spatially relative terms such as "below," "beneath," "under," "above," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the drawings. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0005] High-voltage transistor devices are often designed to include field plates. Field plates are conductive elements placed over a drift region of a high-voltage transistor device to improve device performance by manipulating electric fields (e.g., reducing peak electric fields) generated by a gate electrode. By manipulating the electric field generated by the gate electrode, the high-voltage transistor device can achieve higher breakdown voltages. For example, LDMOS (side-diffused metal-oxide-semiconductor) transistor devices often include field plates extending from a channel region to an adjacent drift region located between the channel region and a drain region.

[0006] In an attempt to increase the number of high-voltage transistor devices arranged over / on a single substrate, a distance between the gate electrode and the drain region is reduced, so that a lateral distance of the drift region is reduced. Therefore, more high-voltage transistor devices can be arranged laterally adjacent to each other over the single substrate. Further, by reducing the lateral distance of the drift region, a resistance of the high-voltage transistor device can be reduced. However, if the lateral distance of the drift region is reduced, the electric fields generated by the gate electrode can accumulate at an edge of the field plate adjacent to the drain region. The accumulation of the electric fields can damage a crystal lattice of the substrate (e.g.,a crack in the substrate), resulting in device malfunction and / or a significant increase in drift region resistance. Furthermore, the accumulation of electric fields at the edge of the field plate can adversely affect the transfer of charge carriers (e.g., electrons) from the source region to the drain region, thereby reducing the performance of the high-voltage transistor device.

[0007] Accordingly, the present disclosure relates to a high-voltage transistor device having a field plate over a buried isolation structure disposed within the drift region. In some embodiments, the high-voltage transistor device includes a gate electrode disposed over a substrate between a source region and a drain region disposed within the substrate. A contact etch stop layer (CESL) extends from a sidewall of the gate electrode to a drift region disposed between the gate electrode and the drain region. A field plate lies within a first interlayer dielectric (ILD) layer disposed over the substrate. The field plate is disposed laterally between the sidewall of the gate electrode and the drain region and extends vertically from the CESL to a top surface of the first ILD layer.Furthermore, the buried isolation structure is arranged within the drift region laterally between the sidewall of the gate electrode and the drain region. An edge of the field plate lies directly above the buried isolation structure, such that it is separated from the isolation structure by the CESL. During operation of the high-voltage transistor device, electric fields generated by the gate electrode may accumulate at the edge of the field plate that lies above the buried isolation structure. The buried isolation structure is configured to mitigate and / or prevent damage to the substrate due to the accumulation of electric fields. Furthermore, the buried isolation structure may mitigate and / or prevent the accumulated electric field therein from adversely affecting the transfer of charge carriers (e.g., electrons) from the source region to the drain region.Therefore, stability, durability, and / or performance of the high-voltage transistor device is increased while increasing a number of high-voltage transistor devices that can be arranged over / on the substrate.

[0008] Fig. 1 illustrates a cross-sectional view of some embodiments of a high voltage transistor device 100 having a field plate 124 over an isolation structure 132 disposed within a substrate 102.

[0009] The high-voltage transistor device 100 includes a source region 104 and a drain region 106 disposed within the substrate 102. The substrate 102 includes a first doping (e.g., p-type), while the source and drain regions 104, 106 each include a second doping (e.g., n-type) with a higher doping concentration than the substrate 102. In some embodiments, the first doping may be p-type and the second doping may be n-type, or vice versa.

[0010] A gate structure 116 overlies the substrate 102 at a position laterally disposed between the source region 104 and the drain region 106. The gate structure 116 includes a gate electrode 110 separated from the substrate 102 by a gate dielectric layer 108. Upon receiving a bias voltage, the gate electrode 110 is configured to generate an electric field that controls the movement of charge carriers (e.g., electrons) within a channel region 112 laterally disposed between the source region 104 and the drain region 106. For example, during operation, a gate-to-source voltage may be selectively applied to the gate electrode 110 relative to the source region 104, thereby forming a conductive channel in the channel region 112. While the gate-source voltage is applied to form the conductive channel, a drain-to-source voltage is applied to conduct charge carriers (e.g.shown by arrow 105) between the source region 104 and the drain region 106. The channel region 112 extends laterally from the source region 104 to an adjacent drift region 114 (or "drain extension region"). The drift region 114 includes the second doping (e.g., n-type), which has a relatively low doping concentration, providing higher resistance at higher operating voltages. The gate structure 116 is disposed over the channel region 112. In some embodiments, the gate structure 116 may extend from over the channel region 112 to a position overlying a portion of the drift region 114.

[0011] An etch stop layer 122 is disposed over the gate structure 116 and a top surface of the substrate 102. The etch stop layer 122 extends from a top surface of the gate electrode 110 along a sidewall of the gate electrode 110 and a sidewall of the gate dielectric layer 108 to the top surface of the substrate 102. A first interlayer dielectric (ILD) layer 118 overlies the substrate 102. One or more conductive structures are disposed within the first ILD layer 118. In some embodiments, the one or more conductive structures comprise a plurality of contacts 120 configured to provide a vertical connection between the source region 104, the drain region 106, and / or the gate electrode 110 and a plurality of conductive backend-of-line (BEOL) wires (not shown) overlying the contacts 120 and disposed within a second ILD layer (not shown).

[0012] The one or more conductive structures may further comprise a field plate 124 disposed within the first ILD layer 118 at a position laterally between the drain region 106 and the gate electrode 110. In some embodiments, the field plate 124 comprises a first field plate structure 126 and a second field plate structure 128. In further embodiments, the field plate 124 comprises a metal material that is different from the gate electrode 110. In still further embodiments, the field plate 124 comprises the same metal material as the contacts 120. The field plate 124 is disposed over the etch stop layer 122, in which the etch stop layer 122 is configured to separate the field plate 124 from the drift region 114 and the gate electrode 110.In some embodiments, the field plate 124 may be configured to lower a breakdown voltage of the high-voltage transistor device 100 and / or to lower a resistance of the drift region 114.

[0013] Furthermore, the isolation structure 132 is arranged within the drift region 114 such that an upper surface of the isolation structure 132 is flush with an upper surface of the substrate 102. In some embodiments, the isolation structure 132 comprises a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing) that is different from a material of the substrate 102. In some embodiments, the isolation structure 132 includes or is a first material (e.g., silicon dioxide) and the etch stop layer 122 includes or is a different second material (e.g., silicon carbide, silicon nitride, etc.). The field plate 124 lies over the isolation structure 132 and is separated from the isolation structure 132 by the etch stop layer 122.An edge 124e of the field plate 124 lies directly above the isolation structure 132, in which the edge 124e is separated from the drain region 106 by a first distance. In some embodiments, the first distance is a shortest distance between the field plate 124 and the drain region 106. In further embodiments, a bottom surface of the second field plate structure 128 is laterally spaced between outer side walls of the isolation structure 132.

[0014] During operation, the field plate 124 is configured to act on the electric field generated by the gate electrode 110. The field plate 124 may be configured to change the distribution of the electric field generated by the gate electrode 110 in the drift region 114. This partially improves the breakdown voltage capacity of the high-voltage transistor device 100. In some embodiments, a lateral distance Ld of the drift region 114 is reduced to increase the number of high-voltage transistor devices that may be arranged within / above the substrate 102. In such embodiments, when the lateral distance Ld of the drift region 114 is reduced, the electric field generated by the gate electrode 110 may accumulate at the edge 124e of the field plate 124.This accumulation may be due to the tendency of electrons to accumulate near edges / corners on outer surfaces of conductive bodies, and / or because the edge 124e is a closest portion of the field plate 124 to the drain region 106. Because the isolation structure 132 includes a dielectric material that is different from the material of the substrate 102, the isolation structure 132 may not be adversely affected by the high electric field that accumulates at and / or near the edge 12e of the field plate 124. Therefore, the lateral distance Ld of the drift region 114 can be reduced while preventing damage to a crystal lattice of the substrate 102. This, in part, increases the reliability and durability of the high-voltage transistor device 100.

[0015] In further embodiments, during operation of the high-voltage transistor device 100, current may flow along a shortest path between the source region 104 and the drain region 106 (e.g., illustrated by arrow 105). Because the isolation structure 132 includes the dielectric material that is different from the material of the substrate 102, the current will migrate around the isolation structure 132. Therefore, the current may flow around a sidewall 132sw of the isolation structure 132 and may flow parallel to a bottom surface 132ls of the isolation structure 132. This, in turn, may increase a resistance of the drift region 114. However, the field plate 124 is configured to decrease the lateral distance Ld of the drift region 114, such that the resistance of the drift region 114 is reduced.In some embodiments, the increase in the resistance of the drift region 114 due to the isolation structure 132 may be eliminated and / or mitigated by the reduction in the resistance of the drift region 114 due to the field plate 124. Furthermore, in some embodiments, due to the current traveling around the isolation structure 132, the accumulation of the electric field at the edge 124e of the field plate 124 may not adversely affect the path (e.g., represented by arrow 105) and / or flow of the current between the source region 104 and the drain region 106. This, in turn, may further increase the breakdown voltage of the high-voltage transistor device 100.

[0016] Fig. 2 illustrates a cross-sectional view of some additional embodiments of a high voltage transistor device including a high voltage side-diffused MOSFET (LDMOS) device 200 having a field plate 124 overlying an isolation structure 132.

[0017] The LDMOS device 200 includes a source region 104 and a drain region 106 disposed within a substrate 102. In some embodiments, the substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate. The substrate 102 has a first doping (e.g., p-type), while the source region 104 and the drain region 106 each include highly doped regions having a second doping (e.g., n-type) that is different from the first doping. In some embodiments, the first doping may be p-type and the second doping may be n-type, or vice versa. In some embodiments, the source region 104 and / or the drain region 106 may each have doping concentrations of approximately 2.5*10 17 atoms / cm 3 , 2.88*10 17 atoms / cm 3 , 5.5*10 17 atoms / cm 3 , within a range of about 1017 -10 19 atoms / cm 3 , larger than about 10 19 or another suitable doping concentration. In some embodiments, the p-type dopants of the first doping layer may be or contain, for example, boron, difluoroboron (e.g., BF2), indium, other suitable p-type dopants, or any combination of the foregoing. In various embodiments, the n-type dopants of the second doping layer may be or contain, for example, phosphorus, arsenic, antimony, other suitable n-type dopants, or any combination of the foregoing.

[0018] The drain region 106 is adjacent to a drift region 114 formed within the substrate 102. The drift region 114 includes the second doping (e.g., n-type) having a relatively low doping concentration that provides high resistance when the LDMOS device 200 is operated at a high voltage. In some embodiments, the drift region 114 may have a doping concentration of approximately 2.0*10 14 atoms / cm 3 , 2.5*10 14 atoms / cm 3 , 3.0*10 14 atoms / cm 3 , 5.7*10 14 atoms / cm 3 or within a range of about 10 18 up to 10 20 atoms / cm 3Furthermore, a trench isolation (STI) structure 202 extends from a top surface of the substrate 102 to a point below the top surface of the substrate 102. The drain region 106 may be adjacent to the STI structure 202. The STI structure 202 is configured to electrically isolate the LDMOS device 200 from adjacent semiconductor devices (not shown). In some embodiments, the STI structure 202 includes a dielectric material that is different from a semiconductor substrate material of the substrate 102. In further embodiments, the dielectric material may be or include, for example, silicon dioxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, another suitable dielectric material, or any combination of the foregoing.In still further embodiments, the substrate material may be or include, for example, silicon, monocrystalline silicon, or other suitable semiconductor substrate material.

[0019] A gate structure 116 is disposed over the substrate 102 at a position laterally disposed between the source region 104 and the drain region 106. In some embodiments, the gate structure 116 may extend laterally from over a channel region 112 to a position overlying a portion of the drift region 114. The gate structure 116 includes a gate electrode 110 separated from the substrate 102 by a gate dielectric layer 108. In some embodiments, the gate dielectric layer 108 may be or include, for example, silicon dioxide, a high-k dielectric material, or the like. As used herein, a high-k dielectric material is a dielectric material having a dielectric constant greater than 3.9. In some embodiments, the gate electrode 110 includes polysilicon and / or a metal gate material (e.g., tungsten, titanium, tantalum, and / or aluminum).

[0020] An etch stop layer 122 extends along a top surface of the gate electrode 110, a sidewall of the gate electrode 110, a sidewall of the gate dielectric layer 108, and a top surface of the substrate 102. In some embodiments, the etch stop layer 122 extends continuously from the gate electrode 110, across the drift region 114, to a point beyond sidewalls of the field plate 124. In further embodiments, the etch stop layer 122 may be or include, for example, silicon nitride, silicon carbide, another suitable material, or the like. A first interlayer dielectric (ILD) layer 118 further overlies the substrate 102 and the gate structure 116. A plurality of contacts 120 overlies the substrate 102 and extends through the first ILD layer 118.In some embodiments, the first ILD layer 118 may be or include, for example, silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, another suitable material, or any combination of the foregoing. In further embodiments, the plurality of contacts 120 may be or include, for example, aluminum, copper, tungsten, titanium, another conductive material, or any combination of the foregoing.

[0021] The field plate 124 extends vertically from the etch stop layer 122 to a top surface of the first ILD layer 118. In some embodiments, a top surface of the field plate 124 is flush with a top surface of the plurality of contacts 120. In further embodiments, the field plate 124 may include a first field plate structure 126 and a second field plate structure 128. In some embodiments, the first and second field plate structures 126, 128 may be or contain the same material and / or be laterally separated from each other by a distance greater than zero. The first field plate structure 126 may directly contact a sidewall of the etch stop layer 122. Sidewalls of the field plate 124 are surrounded by the first ILD layer 118. In some embodiments, the field plate 124 may include the same material as the contacts 120.In various embodiments, the first and / or second field plate structure 126, 128 may be or include, for example, aluminum, copper, tungsten, titanium, another suitable material, or any combination of the foregoing.

[0022] The isolation structure 132 is disposed beneath the field plate 124 and within the drift region 114. The isolation structure 132 may be or include a dielectric material that is different from a semiconductor substrate material of the substrate 102. In some embodiments, the isolation structure 132 includes the same dielectric material as the STI structure 202. In further embodiments, the dielectric material may be or include, for example, silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination of the foregoing. The isolation structure 132 lies directly beneath the second field plate structure 128, such that the isolation structure 132 is separated from the second field plate structure 128 by the etch stop layer 122.In some embodiments, an outer side wall of the isolation structure 132 extends laterally past an outer side wall of the etch stop layer 122. The isolation structure 132 is configured to prevent and / or mitigate damage to the substrate 102 due to a buildup of an electric field at an edge of the field plate 124. In further embodiments, side walls of the isolation structure 132 are sloped.

[0023] Fig. 3A illustrates a cross-sectional view of some embodiments of an integrated chip 300a including a first side-diffused metal oxide semiconductor field-effect transistor (MOSFET-LDMOS) device 316 and a second LDMOS device 318, each including a field plate 124 overlying an isolation structure 132.

[0024] The first LDMOS device 316 and the second LDMOS device 318 are arranged laterally adjacent to each other and share a drain region 106. Furthermore, the first and second LDMOS devices 316, 318 each include a gate structure 116 and a sidewall spacer structure 314 laterally surrounding sidewalls of the gate structure 116. In some embodiments, the spacer structure 314 may be or include, for example, silicon nitride, silicon carbide, another suitable material, or any combination of the foregoing. The gate structure 116 includes a gate electrode 110 overlying a gate dielectric layer 108 overlying a substrate 102. An etch stop layer 122 extends from a top surface of the gate electrode 110 along a sidewall of the sidewall spacer structure 314, to a top surface of the substrate 102. In some embodiments, the substrate 102 may be, for example, a bulk substrate (e.g.The substrate 102 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or another suitable substrate and / or may have a first doping (e.g., p-type). A contact region 308 is disposed within the substrate 102 and abuts the source region 104. The drain region 106 and the source region 104 each have a second doping (e.g., n-type) opposite to the first doping. Furthermore, the contact region 308 has the first doping (e.g., p-type), which provides an ohmic connection for the substrate 102 to an overlying contact 120.

[0025] In some embodiments, the contact region 308 may have a p-doping concentration that is approximately 10 19 atoms / cm 3or greater. The contact region 308 is arranged within a body region 306. The body region 306 has the first doping (e.g., p) with a doping concentration that is higher than that of the substrate 102. For example, the substrate 102 may have a doping concentration that is within a range of about 10 14 up to 10 16 atoms / cm 3 while the body region 306 may have a doping concentration that is within a range of about 10 16 up to 10 18 atoms / cm 3 In further embodiments, the source region 104 is arranged within a shallow well region 310, wherein the shallow well region 310 may have the first doping (eg, p) and / or a doping concentration within a range of about 10 16 up to 10 19 atoms / cm 3The shallow well region 310 is adjacent to the source region 104 and / or a drift region 114. In some embodiments, the shallow well region 310 may be configured as a channel region in which a conductive channel is formed between the source region 104 and the drift region 114 when appropriate bias conditions are applied to the gate electrode 110, the source region 104, and / or the drain region 106.

[0026] The drift region 114 is arranged laterally between the source region 104 and the drain region 106. The drift region 114 may have the second doping (e.g., n-type) and / or may have a doping concentration within a range of approximately 10 18 up to 10 20 atoms / cm 3 The drift region 114 is arranged within a high-voltage well region 304. The high-voltage well region 304 may contain the second doping (e.g., n-type) with a doping concentration within a range of approximately 1014 up to 10 16 atoms / cm 3 In some embodiments, the drift region 114 is part of the high-voltage well region 304, so that the drift region 114 is omitted (not shown), and the high-voltage well region 304 is laterally disposed between the source region 104 and the drain region 106 and functions as a drift region. A shallow well region 312 is disposed around the drain region 106 and is laterally spaced between the first LDMOS device 316 and the second LDMOS device 318. The shallow well region 312 may, for example, have the second doping (e.g., n-type) and may have a doping concentration within a range of about 10 14 up to 10 16 atoms / cm 3or another suitable doping concentration. In some embodiments, the drift region 114 extends continuously laterally from the shallow well region 310 to the drain region 106, such that the drift region 114 abuts the drain region 106 (not shown).

[0027] A deep well region 302 comprising the first doping (e.g., p) is disposed within the substrate 102 and directly beneath the high-voltage well region 304. In some embodiments, the deep well region 302 may, for example, have a doping concentration that is within a range of about 10 14 up to 10 16 atoms / cm 3or have another suitable doping concentration. The deep well region 302 may be configured to enhance formation of a depletion region within the high-voltage well region 304 and / or the drift region 114, thereby reducing a magnitude of the electric field at a surface of the substrate 102. This, in part, facilitates application of high voltages to the first and / or second DMOS devices 316, 318. An isolation structure 132 is disposed within the substrate 102 and abuts the drift region 114 and the shallow well region 312. In some embodiments, the isolation structure 132 abuts the high-voltage well region 304 (not shown). The isolation structure 132 comprises a different material than the substrate 102 and is laterally disposed between the drain region 106 and the source region 104.

[0028] Further, a first interlayer dielectric (ILD) layer 118 is disposed over a top surface of the substrate 102. A plurality of contacts 120 are disposed within the first ILD layer 118 and overlie a doped region of the substrate 102 and / or over a conductive structure disposed over a top surface of the substrate 102. In some embodiments, a silicide layer (not shown) is disposed between a contact 120 and a doped region of the substrate 102 directly underlying the contact 120, such that the silicide layer is configured to enhance electrical connection between the contact 120 and the doped region of the substrate 102. The field plate 124 includes a first field plate structure 126 that extends continuously from a top surface of the first ILD layer 118 to a top surface of the etch stop layer 122.In some embodiments, a first lower edge of the first field plate structure 126 lies directly above the isolation structure 132, and a second lower edge of the first field plate structure 126 is offset from the first lower edge and laterally from the first isolation structure 132 by a distance greater than zero. In further embodiments, the first lower edge of the first field plate structure 126 is separated from the drain region 106 by a distance such that the distance is a shortest distance between the field plate 124 and the drain region 106.

[0029] Fig. 3B illustrates a cross-sectional view of an integrated chip 300b according to some alternative embodiments of the integrated chip 300a of Fig. 3A.

[0030] In some embodiments, the field plate 124 includes the first field plate structure 126 and a second field plate structure 128. In some embodiments, the second field plate structure 128 is laterally spaced between outer side walls of the insulation structure 132. In further embodiments, a first edge overlies the first field plate structure 126 of the insulation structure 132, and a second edge of the first field plate structure 126 is laterally offset from the insulation structure 132 by a distance greater than zero.

[0031] Fig. 3C illustrates a cross-sectional view of an integrated chip 300c according to some alternative embodiments of the integrated chip 300a of Fig. 3A.

[0032] A trench isolation structure (STI structure) 202 extends from the top surface of the substrate 102 to a first point below the top surface of the substrate 102. In some embodiments, the STI structure 202 comprises the same material as the isolation structure 132. In further embodiments, the isolation structure 132 extends from the top surface of the substrate 102 to a second point below the top surface of the substrate 102, in which the first point is vertically below the second point. The STI structure 202 is configured to electrically isolate the first and / or second LDMOS devices 316, 318 from other semiconductor devices arranged above and / or within the substrate 102.

[0033] Fig. 3D illustrates a cross-sectional view of an integrated chip 300d according to some alternative embodiments of the integrated chip 300a of Fig. 3A.

[0034] The contacts 120 each have an inner conductive body 322 surrounded by an outer conductive liner 320. In some embodiments, the inner conductive body 322 may be or include, for example, tungsten, aluminum, copper, another suitable conductive material, or any combination of the foregoing. In further embodiments, the outer conductive liner 320 may be or include, for example, titanium, tantalum, titanium nitride, tantalum nitride, another suitable conductive material, or any combination of the foregoing. In various embodiments, the first field plate structure 126 of the field plate 124 may be configured as the contacts 120, such that the first field plate structure 126 includes the inner conductive body 322 and the outer conductive liner 320. In still further embodiments, if the field plate 124 has a second field plate structure (e.g., 128 of Fig. 3B) (not shown), the second field plate structure may include the inner conductive body 322 and the outer conductive liner 320.

[0035] Fig. 3E illustrates a cross-sectional view of an integrated chip 300e according to some alternative embodiments of the integrated chip 300a of Fig. 3A.

[0036] In some embodiments, a bottom surface 1321s of the isolation structure 132 is arranged vertically below the drain region 106, the source region 104, and / or the contact region 308. In various embodiments, this may increase a resistance of the first and / or second LDMOS device 316, 318 while further reducing adverse effects of an electric field accumulation at an edge of the field plate 124 on the substrate 102.

[0037] Fig. 3F illustrates a cross-sectional view of an integrated chip 300f according to some alternative embodiments of the integrated chip 300a of Fig. 3A.

[0038] In some embodiments, a plurality of conductive wires 324 (e.g., containing aluminum, copper, tungsten, titanium, tantalum, etc.) overlie the contacts 120. A second ILD layer 321 overlies the first ILD layer 118, and a third ILD layer 323 overlies the second ILD layer 321. In some embodiments, the conductive wires 324 overlying the contacts 120, which are directly electrically coupled to the contact region 308, the source region 104, the drain region 106, and the field plate 124, are disposed within the second ILD layer 321. In another embodiment, the conductive wires 324 overlying the contacts 120 that are directly electrically coupled to the gate electrode 110 are disposed within the third ILD layer 323 and vertically offset from the second ILD layer 321 by a distance greater than zero. Therefore, a top surface of each contact 120 (e.g.,Contacts 120, each overlying source region 104, drain region 106 and / or contact region 308) and a top surface of field plate 124 are arranged within a first plane, each arranged along a first substantially straight horizontal line, wherein a top surface of each contact 120 is arranged within a second plane (e.g., contacts 120 overlying gate electrode 110), each arranged along a second substantially straight horizontal line that is vertically offset from the first substantially straight horizontal line.

[0039] Fig. 4-11 illustrate cross-sectional views 400-1100 of some embodiments of a method for forming an integrated chip including a high-voltage LDMOS device having a field plate overlying a buried isolation structure. Although the Fig. 4-11 are described in relation to a method, it will be seen that the cross-sectional views 400-1100 shown in Fig. 4-11 are not limited to the process, but rather can stand independently from the process. Although Fig. 4-11 as a sequence of acts, it will be appreciated that these acts are not limited, as the order of acts may be changed in other embodiments and the disclosed methods are also applicable to other structures. In other embodiments, some acts illustrated and / or described may be omitted in whole or in part.

[0040] As shown in cross-sectional view 400 of Fig. 4, a substrate 102 is provided, and isolation structures 132 are formed on a front side 102f of the substrate 102. In some embodiments, the substrate 102 may be, for example, a semiconductor substrate material (e.g., silicon), a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate. In some embodiments, before the isolation structures 132 are formed, an implantation process is performed to dope the substrate 102 with a first doping (e.g., p-type). In some embodiments, a process for forming the isolation structure 132 may include: forming a masking layer (not shown) over the front side 102f of the substrate; selectively etching the substrate 102 according to the masking layer to form an opening extending from the front side 102f to a point below the front side 102f; Fill (e.g.by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.) of the opening with a dielectric material; and performing a removal process to remove the masking layer. In some embodiments, after filling the opening with the dielectric material, a planarization process (e.g., a chemical mechanical planarization (CMP) process) may be performed on the dielectric material, thereby defining the isolation structure 132. In different embodiments, the planarization process may be performed on the dielectric material such that it continues after it reaches the front side 103f of the substrate, thereby removing at least a small portion of the substrate 102.In still further embodiments, the planarization process may be performed on the dielectric material until the front side 102f of the substrate 102 is reached. In some embodiments, the dielectric material is different from that of the semiconductor substrate material. In still further embodiments, the dielectric material may be or include, for example, silicon dioxide, silicon nitride, silicon carbide, another suitable dielectric material, or a combination of the foregoing. In still further embodiments, a trench isolation (STI) structure (e.g., 202 of FIG. Fig. 3C) (not shown) may be formed on the front side 102f of the substrate 102. In some embodiments, the STI structure may be formed simultaneously with the isolation structure 132 and / or may include the dielectric material. In some embodiments, the p-type dopants of the first doping may be, for example, boron, difluoroboron (e.g., BF2), indium, other suitable p-type dopants, or any combination of the foregoing.

[0041] As shown in cross-sectional view 500 of Fig. 5, one or more implantation processes may be performed on the substrate 102 to form one or more doped regions with the substrate 102. In some embodiments, the one or more implantation processes may be performed to form a deep well region 302, a high voltage well region 304, a body region 306, a drift region 114, and / or a shallow well region 312. In some embodiments, the deep well region 302, the high voltage well region 304, the shallow well region 312, and / or the drift region 114 may each have a second doping (e.g., n-type) opposite the first doping. In some embodiments, the first doping is p-type and the second doping is n-type, or vice versa. In still other embodiments, the deep well region 302 and / or the body region 306 may each have the first doping (e.g., p-type).In some embodiments, the one or more implantation processes may each include: forming a masking layer (not shown) over the front side 102f of the substrate 102; selectively implanting dopants according to the masking layer into the substrate 102; and performing a removal process to remove the masking layer. In some embodiments, the n-type dopants of the second doping may be or include, for example, phosphorus, arsenic, antimony, other suitable n-type dopants, or any combination of the foregoing.

[0042] In some embodiments, the drift region 114 and / or the high voltage well region 304 may each have a doping concentration that is approximately 2.0*10 14 atoms / cm 3 , 2.5*10 14 atoms / cm 3 , 3.0*10 14 atoms / cm 3 , 5.7*10 14 atoms / cm 3 , or within a range of about 10 14up to 10 15 atoms / cm 3 or another suitable doping concentration. In some embodiments, the deep well region 302 may have a doping concentration that is approximately 1.5*10 14 atoms / cm 3 , 1.0*10 15 atoms / cm 3 , within a range of about 10 14 up to 10 16 atoms / cm 3 or another suitable doping concentration. In some embodiments, the shallow well region 312 may have a doping concentration that is approximately 7.0*10 14 atoms / cm 3 , 1.0*10 15 atoms / cm 3 , 1.12*10 15 atoms / cm 3 , within a range of about 10 14 up to 10 16 atoms / cm 3 or another suitable doping concentration. In some embodiments, the body region 306 may have a doping concentration that is approximately 5.0*10 14 atoms / cm 3 , 8.0*10 14atoms / cm 3 , 1.4*10 15 atoms / cm 3 , within a range of about 10 14 up to 10 16 atoms / cm 3 or another suitable doping concentration.

[0043] As shown in cross-sectional view 600 of Fig. 6, gate structures 116 are formed over the front side 102f of the substrate. In some embodiments, the gate structure 116 includes a gate dielectric layer 108 and a gate electrode 110 overlying the gate dielectric layer 108. In some embodiments, a process for forming the gate structures 116 may include: depositing a gate dielectric film over the front side 102f by, for example, CVD, PVD, ALD, or another suitable deposition process; depositing a gate electrode layer over the gate dielectric film by, for example, CVD, PVD, ALD, sputtering, or another suitable deposition or growth process; and patterning the gate dielectric film and the gate electrode layer through a masking layer (not shown) to define the gate dielectric layer 108, the gate electrode 110, and the gate structures 116.In some embodiments, the gate electrode 110 may be, for example, titanium nitride, tantalum nitride, titanium, tantalum, tungsten, aluminum, copper, polysilicon, intrinsic polysilicon, doped polysilicon, another suitable conductive material, or any combination of the foregoing. In further embodiments, the gate dielectric layer 108 may be or include, for example, silicon dioxide, a high-k dielectric material, another suitable gate dielectric material, or any combination of the foregoing.

[0044] As shown in section 700 of Fig. 7, an implantation process is performed on the substrate 102 to form a shallow well region 310 within the substrate 102. In further embodiments, a plurality of lightly doped regions (not shown) may be formed simultaneously with the shallow well region 310. In some embodiments, the shallow well region 310 abuts the body region 306, the drift region 114, and / or the high voltage well region 304. The shallow well region 310 may, for example, have the first doping (e.g., p-type). In further embodiments, the implantation process includes: forming a masking layer (not shown) over the substrate 102; selectively implanting dopants into the substrate 102 according to the masking layer; and performing a removal process to remove the masking layer. In further embodiments, the shallow well region 310 may be configured as a channel region.In some embodiments, the shallow well region 310 may have a doping concentration that is approximately 1.0*10. 15 atoms / cm 3 , 1.6*10 15 atoms / cm 3 , 5.4*10 15 atoms / cm 3 , 5.0*10 16 atoms / cm 3 , within a range of about 10 15 up to 10 17 atoms / cm 3 or another suitable doping concentration.

[0045] As shown in cross-sectional view 800 of Fig. 8, a sidewall spacer structure 314 is formed around sidewalls of the gate structures 116. In some embodiments, the sidewall spacer structure 314 may be or include, for example, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing. In further embodiments, a process for forming the sidewall spacer structure 314 may include: depositing (e.g., by a CVD process, a PVD process, an ALD process, or another suitable deposition process) a sidewall spacer layer over the substrate 102 and the gate structures 116; and performing a patterning process on the sidewall spacer layer to remove the sidewall spacer layer from horizontal surfaces, thereby defining the sidewall spacer structure 314.

[0046] As shown in cross-sectional view 900 of Fig. 9, an implantation process is performed on the substrate 102 to define a source region 104, a drain region 106, and a contact region 308 within the substrate 102. In some embodiments, the source region 104 and / or the drain region 106 may comprise the second doping (e.g., n-type). In further embodiments, the contact region 308 may comprise the first doping (e.g., p-type). In different embodiments, the implantation process may include: forming a masking layer (not shown) over the front side 102f of the substrate 102; selectively implanting dopants into the substrate 102 according to the masking layer; and performing a removal process to remove the masking layer. In some embodiments, the source region 104 and / or the drain region 106 may each have doping concentrations of approximately 2.5*10 17 atoms / cm 3 , 2.88*10 17 atoms / cm 3 , 5.5*1017 atoms / cm 3 , within a range of about 10 17 up to 10 19 atoms / cm 3 , larger than about 10 19 or another suitable doping concentration. In some embodiments, the contact region 308 may have a doping concentration that is approximately 3.0*10 15 atoms / cm 3 , 3.2*10 17 atoms / cm 3 , within a range of about 10 15 up to 10 18 atoms / cm 3 or another suitable doping concentration.

[0047] As shown in cross-sectional view 1000 of Fig. 10, an etch stop layer 122 is formed over the gate structures 116. In some embodiments, the etch stop layer 122 extends continuously from a top surface of the gate electrode 110, along a sidewall of the sidewall spacer structure 314, to the front side 102f of the substrate 102. In some embodiments, the etch stop layer 122 may be or include, for example, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing. In further embodiments, the etch stop layer 122 may directly contact the isolation structure 132. In still further embodiments, the etch stop layer 122 may be deposited, for example, by PVD, CVD, ALD, or another suitable deposition or growth process.

[0048] As shown in cross-sectional view 1100 of Fig. 11, a first interlayer dielectric (ILD) layer 118 is formed over the substrate 102. In some embodiments, the first ILD layer 118 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process. In further embodiments, the first ILD layer 118 may be or include, for example, silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, another suitable dielectric material, or any combination of the foregoing. Further, after formation of the first ILD layer 118, a plurality of contacts 120 and field plates 124 may be formed within the first ILD layer 118, thereby defining a first laterally diffused metal-oxide-semiconductor field-effect transistor (MOSFET-LDMOS) device 316 and a second LDMOS device 318.In some embodiments, the plurality of contacts 120 and the field plates 124 may be formed simultaneously. In various embodiments, a process for forming the contacts 120 and / or the field plates 124 may include: forming a masking layer (not shown) over the first ILD layer 118; patterning the first ILD layer 118 according to the masking layer, thereby defining a plurality of openings within the first ILD layer 118; filling the plurality of openings with a conductive material (e.g., titanium, copper, aluminum, tungsten, tantalum nitride, another suitable conductive material, or any combination of the foregoing); and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) into the conductive material, thereby defining the contacts 120 and / or the field plates 124.In further embodiments, the contacts 120 and / or the field plates 124 may each be formed by a single damascene process.

[0049] In some embodiments, the field plate 124 is formed in such a way that it lies directly over at least a portion of the isolation structure 132. Furthermore, the field plate 124 is separated from the substrate 102 and / or the isolation structure 132 by the etch stop layer 122. In different embodiments, the field plate 124 may include a first field plate structure 126 and / or a second field plate structure (not shown) (e.g., 128 of Fig. 3B). In such embodiments, the first field plate structure 126 and / or the second field plate structure (not shown) (e.g., 128 of Fig. 3B) are formed simultaneously.

[0050] Fig. 12 illustrates a method 1200 for forming an integrated chip including an LDMOS device having a field plate overlying an isolation structure. Although the method 1200 is illustrated and / or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated order or acts. Therefore, in some embodiments, the acts may be performed in different orders than illustrated and / or may be performed concurrently. Further, in some embodiments, the illustrated acts or events may be divided into multiple acts or events that may be performed at separate times or concurrently with other acts or subacts.In some embodiments, some illustrated acts or events may be omitted and other non-illustrated acts or events may be included.

[0051] At act 1202, an isolation structure is formed in a substrate, where the isolation structure extends from a front surface of the substrate to a point below the front surface of the substrate. Fig. 4 illustrates a cross-sectional view 400 according to some embodiments of act 1202.

[0052] At act 1204, a well region, a body region, and a drift region are formed within the substrate, with the drift region adjacent to the isolation structure. Fig. 5 illustrates a cross-sectional view 500 according to some embodiments of act 1204.

[0053] At act 1206, a gate structure is formed over the substrate, the gate structure including a gate electrode and a gate dielectric layer underlying the gate electrode. The gate structure overlies at least a portion of the drift region. Fig. 6 illustrates a cross-sectional view 600 according to some embodiments of act 1206.

[0054] At act 1208, a source region and a drain region are formed within the substrate on opposite sides of the gate structure. The isolation structure is laterally spaced between the gate structure and the drain region. Fig. 9 illustrates a cross-sectional view 900 according to some embodiments of act 1208.

[0055] At act 1210, an etch stop layer is formed over the gate electrode and the substrate, the etch stop layer extending from a top surface of the gate electrode to a top surface of the isolation structure. Fig. 10 illustrates a cross-sectional view 1000 according to some embodiments of act 1210.

[0056] At act 1212, a first interlayer dielectric (ILD) layer is formed over the substrate and the gate structure. Fig. 11 illustrates a cross-sectional view 1100 according to some embodiments of act 1212.

[0057] At act 1214, a plurality of contacts and a field plate are formed over the substrate and within the first ILD layer, in which at least a portion of the field plate lies directly over the isolation structure. Fig. 11 illustrates a cross-sectional view 1100 according to some embodiments of act 1214.

[0058] Accordingly, in some embodiments, the present disclosure relates to a high voltage device having a field plate at least partially directly overlying an isolation structure disposed within a drift region.

[0059] In some embodiments, the present application provides an integrated chip comprising a gate electrode overlying a substrate between a source region and a drain region; an etch stop layer extending laterally from a top surface of the gate electrode to a front side of the substrate, the etch stop layer overlying a drift region disposed between the source region and the drain region; a field plate disposed within a first interlayer dielectric (ILD) layer overlying the substrate, the field plate extending from a top surface of the first ILD layer to a top surface of the etch stop layer;and an isolation structure disposed within the substrate and extending from the front side of the substrate to a point below the front side of the substrate, the isolation structure being disposed laterally between the gate electrode and the drain region, and the field plate overlying the isolation structure;

[0060] In some embodiments, the present application provides an integrated chip comprising a first laterally diffused metal oxide semiconductor field effect transistor (MOSFET-LDMOS) device having a first gate structure overlying a substrate, the first LDMOS device further comprising a first source region and a first drift region disposed within the substrate; a second LDMOS device having a second gate structure, a second source region, and a second drift region; a drain region disposed between the first and second LDMOS devices, the first drift region disposed between the first source region and the drain region, and the second drift region disposed between the second source region and the drain region; a first field plate laterally spaced between the drain region and the first gate structure;and a first isolation structure disposed within the substrate, the first isolation structure being laterally spaced between the drain region and the first source region, a first edge of the first field plate directly overlying the first isolation structure and a second edge of the first field plate laterally offset from the first isolation structure by a distance greater than zero in a direction toward the first gate structure;

[0061] In some embodiments, the present application provides a method comprising forming an isolation structure within a substrate, wherein the isolation structure includes a dielectric material and the substrate includes a substrate material that is different from the dielectric material; performing an implantation process to form a drift region within the substrate, wherein the drift region is adjacent to the isolation structure; forming a gate structure over the substrate, wherein the gate structure is at least partially overlying the drift region; performing an implantation process to form a source region and a drain region within the substrate, wherein the drift region is laterally disposed between the source region and the drain region; forming a first interlayer dielectric (ILD) layer over the substrate;and forming a field plate over the drift region and within the ILD layer, wherein at least a portion of the field plate lies directly over the isolation structure;

Claims

[1] Integrated chip comprising: a gate electrode (110) disposed over a substrate (102) between a source region (104) and a drain region (106); an etch stop layer (122) extending laterally from a top surface of the gate electrode (110) to a front side (102f) of the substrate (102), the etch stop layer (122) overlying a drift region (114) disposed between the source region (104) and the drain region (106); a field plate (124) disposed within a first ILD layer (118) overlying the substrate (102), the field plate (124) extending from a top surface of the first ILD layer (124) to a top surface of the etch stop layer (122); and an isolation structure (132) disposed within the substrate (102) and extending from the front side (102f) of the substrate (102) to a point below the front side (102f) of the substrate (102), the isolation structure (132) being disposed laterally between the gate electrode (110) and the drain region (106), the field plate (124) overlying the isolation structure (132), the field plate (124) comprising: a first field plate structure (126) extending from the top surface of the first ILD layer (118) to the top surface of the etch stop layer (122); and a second field plate structure (128) extending from the top surface of the first ILD layer (118) to the top surface of the etch stop layer (122), the second field plate structure (128) being laterally offset from the first field plate structure (126) by a distance greater than zero, at least a portion of the second field plate structure (128) directly overlying the isolation structure (132). [2] The integrated chip of claim 1, wherein the isolation structure (132) includes a first material and the substrate (102) includes a second material different from the first material. [3] The integrated chip of claim 2, wherein the first material is silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, and the second material is silicon. [4] The integrated chip of any preceding claim, wherein the gate electrode (110) includes a first conductive material and the field plate (124) includes a second conductive material different from the first conductive material. [5] Integrated chip according to one of the preceding claims, further comprising: a plurality of contacts (120) disposed within the first ILD layer (118) and overlying the substrate (102), wherein a top surface of the plurality of contacts (120) is flush with a top surface of the field plate (124). [6] The integrated chip of any preceding claim, wherein the first field plate structure (126) is laterally offset from the isolation structure (132) by a distance greater than zero in a direction toward the gate electrode (110). [7] Integrated chip according to one of the preceding claims, wherein outer side walls of the second field plate structure (128) are laterally spaced between outer side walls of the isolation structure (132). [8] Integrated chip according to one of the preceding claims, wherein the first field plate structure (126) directly contacts a sidewall of the etch stop layer (122). [9] Integrated chip comprising: a first laterally diffused LDMOS device (316) having a first gate structure (116) overlying a substrate (102), the first LDMOS device (316) further comprising a first source region (104) and a first drift region (114) disposed within the substrate (102); a second LDMOS device (318) having a second gate structure (116), a second source region (104) and a second drift region (114); a drain region (106) disposed between the first LDMOS device (316) and the second LDMOS device (318), wherein the first drift region (114) is disposed between the first source region (104) and the drain region (106), wherein the second drift region (114) is disposed between the second source region (104) and the drain region (106); a first field plate (124) laterally spaced between the drain region (106) and the first gate structure (116); a first isolation structure (132) disposed within the substrate (102), the first isolation structure (132) being laterally spaced between the drain region (106) and the first source region (104), a first edge (124e) of the first field plate (124) directly overlying the first isolation structure (132), and a second edge of the first field plate (124) being laterally offset from the first isolation structure (132) by a distance greater than zero in a direction toward the first gate structure (116); a second field plate (124) laterally spaced between the drain region (106) and the second gate structure (116); and a second isolation structure (132) disposed within the substrate (102), the second isolation structure (132) being laterally spaced between the drain region (106) and the second source region (104), a first edge of the second field plate (124) directly overlying the second isolation structure (132). [10] The integrated chip of claim 9, wherein a lower surface of the first isolation structure (132) is arranged vertically below a lower surface of the drain region (106). [11] Integrated chip according to one of claims 9 to 10, wherein the first isolation structure (132) directly contacts the first drift region (106). [12] Integrated chip according to one of claims 9 to 11, further comprising: a first ILD layer (118) overlying the substrate (102); and a plurality of contacts (120) disposed within the first ILD layer (118) and overlying the substrate (102), wherein a top surface of the plurality of contacts (120) is flush with a top surface of the first field plate (124), wherein the contacts (120) and the first field plate (124) comprise a same material. [13] Integrated chip according to one of claims 9 to 12, further comprising: a first etch stop layer (122) extending continuously from a top surface of the first gate structure (116) to a top surface of the substrate (102), wherein the first field plate (124) directly contacts a top surface of the first etch stop layer (122). [14] The integrated chip of claim 13, wherein the first etch stop layer (122) directly contacts the first drift region (114) and directly contacts the first isolation structure (132). [15] The integrated chip of claim 13 or 14, wherein the first etch stop layer (122) contains a different material than the first isolation structure (132). [16] Procedure comprising: Forming an isolation structure (132) within a substrate (102), the isolation structure (132) including a dielectric material and the substrate (102) including a substrate material different from the dielectric material; performing an implantation process to form a drift region (114) within the substrate (102), the drift region (114) being adjacent to the isolation structure (132); Forming a gate structure (116) over the substrate (102), wherein the gate structure (116) lies at least partially over the drift region (114): performing an implantation process to form a source region (104) and a drain region (106) within the substrate (102), wherein the drift region (114) is arranged laterally between the source region (104) and the drain region (106); Forming a first ILD layer (118) over the substrate (102); and Forming a field plate (124) over the drift region (114) and within the ILD layer (118), wherein at least a portion of the field plate (124) lies directly over the isolation structure (132), wherein the field plate (124) comprises a first field plate structure (126) and a second field plate structure (128) extending from the top surface of the first ILD layer (118) to the top surface of the etch stop layer (122), wherein the second field plate structure (128) is laterally offset from the first field plate structure (126) by a distance greater than zero, and wherein at least a portion of the second field plate structure (128) lies directly over the isolation structure (132). [17] The method of claim 16, further comprising: Forming a plurality of contacts (120) within the first ILD layer (118) and over the substrate (102), wherein the contacts (120) are formed simultaneously with the field plate (124). [18] The method of claim 16 or 17, wherein forming the isolation structure (132) comprises: Forming a masking layer over the substrate (102); Structuring the substrate (102) according to the masking layer, thereby defining an opening extending from a front side (102f) of the substrate (102) to a point below the front side (102f) of the substrate (102); depositing the dielectric material within the opening; and Performing a planarization process on the dielectric material, thereby forming the isolation structure (132).

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