Vertical semiconductor memory with body-gate layer

Abstract

Semiconductor device comprising: a channel structure (C140) on a substrate (110) extending in a first direction (Z-direction) perpendicular to an upper surface of the substrate (110), wherein the channel structure (C140) comprises: a body-gate layer (146) extending in the first direction (Z-direction); a charge storage structure (144) surrounding a side wall of the body-gate layer (146); and a channel layer (142) surrounding a side wall of the charge storage structure (144); several gate electrodes (130; 130B) on the substrate (110) and spaced apart from each other in the first direction (Z-direction) on a side wall of the channel structure (C140); a gate insulating layer (132; 132B; 132C) between each of the several gate electrodes (130; 130B) and the channel structure (C140); a bit conductor pad (150) at a level higher than a topmost gate electrode of the several gate electrodes (130;130B) is, wherein the bit line pad (150) is located on the channel layer (142), wherein an inner wall of the bit line pad (150) defines an opening (150OP); a bit line contact (162) which is connected to the bit line pad (150);and a body-gate contact (166) that penetrates the opening and is connected to the body-gate layer (146), wherein the bit line pad (150) has a first width (w11) in a second direction (X-direction) that is parallel to the upper surface of the substrate (110), and a second width (w12) that is smaller than the first width (w11) in a third direction (Y-direction) that is parallel to the upper surface of the substrate (110) and perpendicular to the second direction (X-direction), wherein the first width (w11) is larger than a third width of the channel structure in the second direction (X-direction), and wherein the semiconductor device further comprises: a bit line (164) that is connected to the bit line contact (162) and extends in the third direction (Y-direction); and a body-gate line (168) which is connected to the body-gate contact (166), wherein the body-gate line (168) runs in the third direction (Y-direction).

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of Korean Patent Application 10-2019-0093370, filed on July 31, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND

[0002] The inventive concepts relate to semiconductor devices and methods of operation thereof, and more particularly to semiconductor devices comprising a channel structure extending in a vertical direction, methods of operation thereof, and methods of fabrication thereof.

[0003] Due to the increasing integration of memory devices, memory devices with vertical transistor structures are being proposed instead of memory devices with conventional planar transistor structures. Memory devices with vertical transistor structures may include a channel structure extending in a vertical direction on a substrate. However, due to the increasing degree of integration of memory devices, the number of gate electrode layers stacked in the vertical direction increases, thus making the manufacturing processes for the memory devices increasingly difficult. SUMMARY

[0004] The inventive concepts provide semiconductor devices that can exhibit improved electrical properties while having a large vertical height.

[0005] The inventive concepts provide methods of operating a semiconductor device that can exhibit improved electrical properties while having a large vertical height.

[0006] According to one aspect of the inventive concepts, a semiconductor device is provided comprising: a channel structure on a substrate extending in a first direction that is perpendicular to a top surface of the substrate, the channel structure comprising a body gate layer extending in the first direction, a charge storage structure surrounding a sidewall of the body gate layer, and a channel layer surrounding a sidewall of the charge storage structure; a plurality of gate electrodes on the substrate and spaced from each other in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure.

[0007] According to another aspect of the inventive concepts, there is provided a semiconductor device comprising: a plurality of gate electrodes on a substrate and spaced from each other in a first direction that is perpendicular to a top surface of the substrate; a channel structure in a channel hole penetrating the plurality of gate electrodes and extending in the first direction, the channel structure comprising a channel layer on an inner wall of the channel hole and a charge storage structure on the channel layer on the inner wall of the channel hole; a gate insulating layer between each of the plurality of gate electrodes and the channel layer, lining a top surface and a bottom surface of each of the plurality of gate electrodes, and the channel layer being located between each of the plurality of gate electrodes and the charge storage structure.

[0008] According to another aspect of the inventive concepts, a semiconductor device is provided, comprising: a channel structure on a substrate extending in a first direction perpendicular to a top surface of the substrate, the channel structure comprising a body gate layer extending in the first direction, a charge storage structure surrounding a sidewall of the body gate layer, and a channel layer surrounding a sidewall of the charge storage structure; a plurality of gate electrodes on the substrate and spaced from each other in the first direction on a sidewall of the channel structure; a gate insulating layer between each of the plurality of gate electrodes and the channel structure; a bit line pad formed at a level higher than a topmost gate electrode of the plurality of gate electrodes and located on the channel layer; a bit line contact connected to the bit line pad;and a bit line connected to the bit line contact and extending in a second direction parallel to the top surface of the substrate; Character list

[0009] Exemplary embodiments of the inventive concepts will be better understood from the following detailed description taken in conjunction with the accompanying drawings: Fig. 1 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to some example embodiments; Fig. 2 is a plan view illustrating a representative structure of a semiconductor device according to some example embodiments; Fig. 3 is a schematic perspective view of a section A1 the Fig. 2; Fig. 4A and Fig. 4B are enlarged plan views of a section A2 the Fig. 2; Fig. 5 is a cross-sectional view taken along the line B1-B1' the Fig. 2; Fig. 6 is a cross-sectional view taken along the line B2-B2' the Fig. 2; Fig. 7 is an enlarged view of a section CX1 the Fig. 6; Fig. 8 illustrates a timing diagram of a programming voltage applied to a memory cell being programmed in an exemplary programming operation of a semiconductor device, according to some example embodiments; Fig. 9 is a schematic diagram illustrating voltages applied to a program string, a lock string, and a body gate line in a program operation, according to some example embodiments; Fig. Figure 10 illustrates a schematic energy band diagram of components included in a memory cell used in step 3 of the Fig. 9 has been programmed; Fig. 11 is a schematic diagram illustrating voltages applied to a string and a body gate line on which reading is performed in an example read operation of a semiconductor device, according to some example embodiments; Fig. 12 is a schematic diagram illustrating voltages applied to a string and a body gate line on which erasure is performed in an exemplary erase operation of a semiconductor device, according to some exemplary embodiments, Fig. 13 is a cross-sectional view illustrating a semiconductor device according to some example embodiments; Fig. 14 is an enlarged cross-sectional view of a section CX2 the Fig. 13; Fig. 15 is a cross-sectional view illustrating a semiconductor device according to some example embodiments; Fig. 16 is an enlarged cross-sectional view of a section CX3 the Fig. 15; Fig. 17 is a cross-sectional view illustrating a semiconductor device according to some example embodiments; Fig. 18 is an enlarged cross-sectional view of a section CX4 the Fig. 17; Fig. 19 is a cross-sectional view illustrating a semiconductor device according to some example embodiments; Fig. 20 is a cross-sectional view illustrating a semiconductor device according to some example embodiments; Fig. 21 to Fig. 30 are schematic diagrams illustrating a method of manufacturing a semiconductor device in a process sequence according to some example embodiments; Fig. 31 and Fig. 32 are schematic diagrams illustrating a method of manufacturing a semiconductor device according to some example embodiments in a process sequence; and Fig. 33 to Fig. 38 are schematic diagrams illustrating a method of manufacturing a semiconductor device in a process sequence according to some example embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] Exemplary embodiments of the inventive concept are described in detail below with reference to the accompanying drawings.

[0011] It is understood that an element located "on top" of another element may be above or below the other element. It is further understood that an element located "on top" of another element may be "directly" on the other element, such that the elements are in direct contact with each other, or it may be "indirectly" on the other element, such that the elements are isolated from direct contact with each other by one or more intervening spaces and / or structures.

[0012] Spatially related terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to simplify the description of the relationship of one element or feature to another element(s) or feature(s) as illustrated in the drawings. It is understood that the spatially related terms are intended to encompass different orientations of the component used or operation in addition to the orientation shown in the figures. For example, if the component is flipped in the figures, then elements described as being "below" or "below" other elements would be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an above and below orientation.The building element may be oriented differently (rotated 90 degrees or with other orientations), and the spatially related descriptors used here can be interpreted accordingly. Additionally, when an element is described as being "between" two elements, the element may be the only element between the two elements, or one or more other intervening elements may be present.

[0013] Fig. 1 is an equivalent circuit diagram of a memory cell array ( MCA , Memory Cell Array) of a semiconductor device according to some exemplary embodiments, in particular an equivalent circuit diagram of a vertical NAND (VNAND) flash memory device having a vertical channel structure.

[0014] With reference to Fig. 1, the memory cell array MCA Memory cell strings MCS11 until MCS33 , word lines WL1 until WL8 , ground selection lines GSLs, string selection lines SSL1 until SSL3 and a common source line CSL include.

[0015] The memory cell strings MCS11 , MCS21 and MCS31 can be switched between a first bit line BL1 , a first body gate line BGL1 and the common source line CSL provided, and the memory cell strings MCS12 , MCS22 and MCS32 can be connected between a second bit line BL2, a second body gate line BGL2 and the common source line CSL provided, and the memory cell strings MCS13 , MCS23 and MCS33 can be switched between a third bit line BL3 , a third body gate line BGL3 and the common source line CSL Each memory cell string (e.g. MCS11 ) can have a string selection transistor SST , several memory cells MCT1 until MCT8 and a ground selection transistor GST connected in series.

[0016] The string selection transistor SST can be used with the appropriate string selection lines SSL1 until SSL3 The multiple memory cells MCT1 until MCT8 can be connected to the corresponding word lines WL1 until WL8 The ground select transistor GST can be connected to the corresponding ground selection lines GSL1 until GSL3 The string selection transistor SST can be connected to the corresponding bit lines BL1 until BL3 connected, and the ground selection transistor GST can be connected to the common source line CSL be connected.

[0017] In some exemplary embodiments, word lines of the same height (e.g., WL1) may be connected together, the string selection lines SSL1 until SSL3 can be separated from each other, and the ground selection lines GSL1 until GSL3 can also be separated from each other. Fig. 1 illustrates that three string selection lines SSL1 until SSL3 share a word line of the same height, but the inventive concept is not limited thereto. In some examples, two string select lines may share a word line of the same height. In other examples, four string select lines may share a word line of the same height.

[0018] Fig. 2 is a plan view showing a representative structure of a semiconductor device 100 according to some exemplary embodiments. Fig. 3 is a schematic perspective view of a section A1 the Fig. 2, and the Fig. 4A and Fig. 4B are enlarged plan views of a section A2 the Fig. 2. Fig. 5 is a cross-sectional view along a line B1-B1' the Fig. 2, Fig. 6 is a cross-sectional view along a line B2-B2' the Fig. 2, and Fig. 7 is an enlarged view of a section CX1 the Fig. 6. In the Fig. 2 to Fig. 4B, for convenience of illustration and understanding, only a portion of the components of the semiconductor device 100 illustrated schematically.

[0019] With reference to the Fig. 2 to Fig. 7 can be a substrate 110 a memory cell area MCR, a connection area CON and a peripheral circuit area PERI. The memory cell array MCA can be arranged on the memory cell area MCR, and the memory cell array MCA may comprise a NAND memory device having a vertical channel structure, wherein the NAND memory device is based on the structure described in relation to Fig. 1 described manner. A peripheral circuit transistor 190T to control the memory cell array MCA can be arranged on the peripheral circuit area PERI. The peripheral circuit transistor 190T can have a peripheral circuit active area 192 , a peripheral gate circuit electrode 194 , which are located on the peripheral circuit active area 192 and a peripheral circuit contact 196 , which is connected to the peripheral circuit active area 192 and the peripheral gate circuit electrode 194The connection area CON may be an area in which a pad part PAD for connecting the memory cell array MCA , which is arranged in the memory cell area MCR, is formed with the peripheral circuit transistor PERI.

[0020] The substrate 110 can be a main interface 110M which runs in a first direction (X-direction) and a second direction (Y-direction). The substrate 110 may comprise a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may comprise silicon (Si), germanium (Ge), and / or silicon-germanium. The substrate 110 may comprise a bulk wafer or an epitaxial layer. In some exemplary embodiments, the substrate 110a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0021] On the memory cell area MCR of the substrate 110 several first insulation layers 120 and multiple gate electrodes 130 alternately in a third direction (Z-direction) perpendicular to the main surface 110M of the substrate 110 For example, the first insulating layer 120 and the gate electrode 130 alternately and repeatedly on the substrate 110 A second insulating layer 122 can be placed on a top gate electrode 130 be arranged.

[0022] The multiple gate electrodes 130 can form a metal layer 130M and a conductive boundary layer 130UB which cover the top, bottom and side surfaces of the metal layer130M The conductive boundary layer 130UB may comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), tantalum (Ta), and / or combinations thereof. The metal layer 130M may comprise at least one of the following: cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), silicides, and / or alloys thereof. In some exemplary embodiments, each of the plurality of gate electrodes 130 a thickness of about 1 nm to about 30 nm in the third direction (Z-direction) or about 1 nm to about 15 nm or about 15 nm to about 30 nm or about 15 nm. However, the thickness of each of the plurality of gate electrodes 130 not limited to that.

[0023] When the terms "about" or "substantially" are used in this specification in conjunction with a numerical value, the associated numerical value is intended to have a tolerance of ±10% around the specified numerical value. When ranges are specified, the range includes all values ​​in between, such as increments of 0.1%.

[0024] In some exemplary embodiments, the plurality of gate electrodes 130 the ground selection lines GSL1 until GSL3 , the word lines WL1 until WL8 and the string selection lines SSL1 until SSL3 correspond, where they represent the memory cell strings MCS11 until MCS33 form (see Fig. 1). For example, a bottom gate electrode 130 than the ground selection lines GSL1 until GSL3 function, the top gate electrode 130 can be used as the string selection lines SSL1 until SSL3 function, and the remaining gate electrodes 130 can be used as the word lines WL1 until WL8 In some embodiments, the gate electrode 130 which is directly below the top gate electrode 130 is arranged, or the gate electrode 130 which is directly above the lowest gate electrode 130 arranged, function as a dummy word line. Accordingly, the memory cell strings MCS11 until MCS33 , in which the ground selection transistor GST , the selection transistor SST and the memory cells MCT1 until MCT8 between the ground selection transistor GST and the selection transistor SST connected in series.

[0025] Multiple channel structures C140 can be moved in the third direction (Z-direction) from the main surface 110M of the substrate 110in the memory cell area MCR, while they cover the multiple gate electrodes 130 penetrate. The multiple channel structures C140 may be spaced apart from each other at desired (or, alternatively, predetermined) distances in the first direction (X-direction), the second direction (Y-direction), and a fourth direction (e.g., a diagonal direction). The plurality of channel structures C140 can be arranged in a zigzag or staggered pattern.

[0026] Each of the multiple channel structures C140 can be in a sewer hole C140H arranged that the plurality of gate electrodes 130 , the several first insulating layers 120 and the second insulating layer 122 penetrates. A channel layer 142 , a charge storage structure 144 and a body gate layer 146 can be sequentially applied to an inner wall of the channel hole C140H be arranged.

[0027] The channel layer 142 can be uniformly applied to the inner wall of the channel hole C140H are formed, and the channel layer 142 can have a lower section 142L which the substrate 110 contacted. The lower section 142L the channel layer 142 (or a lower surface C142L the channel structure C140 ) can be arranged at a level lower than the main surface 110M of the substrate 110 For example, a lower section of the channel hole C140H from the main interface 110M of the substrate 110 be sunk, and the lower section 142L the channel layer 142 can be found at the lower section of the channel hole C140H be arranged, and the lower section 142L the channel layer 142 can be in contact with an upper surface of the substrate 110which are located at the bottom of the channel hole C140H is arranged.

[0028] The charge storage structure 144 may have a structure comprising a dielectric tunnel layer 144A , a charge storage layer 144B and a dielectric barrier layer 144C which is mounted on a side wall 142IS the channel layer 142 are formed sequentially. That is, the channel layer 142 , the dielectric tunnel layer 144A , the charge storage layer 144B and the dielectric barrier layer 144C can be sequentially applied to the inner wall of the channel hole C140H The relative thicknesses of the dielectric tunnel layer 144A , the charge storage layer 144B and the dielectric barrier layer 144C including the charge storage structure 144 are not limited to the Fig. 7 illustrated and can be modified in various ways.

[0029] In exemplary embodiments, the dielectric tunnel layer 144A Silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide and / or the like. The charge storage layer 144B can be an area in which electrons emitted from the channel layer 142 through the dielectric tunnel layer 144A run, can be stored, and may comprise silicon nitride, boron nitride, silicon boron nitride and / or doped polysilicon with impurities. The dielectric barrier layer 144C may comprise silicon oxide, silicon nitride, and / or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide may comprise hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and / or combinations thereof.

[0030] The Body Gate Layer 146can have a remaining space of the channel hole C140H on the charge storage structure 144 In exemplary embodiments, the body gate layer 146 a doped polysilicon layer, but is not limited to this. When a data write operation, a read operation, or an erase operation of the memory cells MCT1 until MCT8 (see Fig. 1), a desired (or, alternatively, a predetermined) voltage (or signal) can be applied via the body gate lines BGL1 until BGL3 to the body gate layer 146 be created (see Fig. 1).

[0031] In exemplary embodiments, the body gate layer 146 have a columnar shape which in the third direction (Z-direction) in the channel hole C140H An upper surface of the body-gate layer 146can be at the same level as an upper surface of the second insulating layer 122 and a lower surface of the body gate layer 146 may be at a lower level than a lower surface of the lowest gate electrode 130 A side wall 146S and the lower surface of the body gate layer 146 can the charge storage structure 144 As described in the Fig. 7, the charge storage structure 144 for example the side wall 146S the body gate layer 146 surrounded, and the channel layer 142 can an exterior wall 144S the charge storage structure 144 surrounded. The gate electrode 130 an outer wall of the channel layer 142 surrounded, and an inner wall 142IS the channel layer 142 the outer wall can 144S the charge storage structure 144 contact.

[0032] A gate insulating layer 132 can be located between the gate electrode 130 and the channel structure C140 The gate insulating layer 132 can be located between the gate electrode 130 and the channel layer 142 and between the gate electrode 130 and the first insulating layer 120 and can have an upper surface 130U and a lower surface 130L the gate electrode 130 In exemplary embodiments, the gate insulating layer 132 include, but are not limited to, silicon oxide.

[0033] A bitline pad 150 can be found on the channel structure C140 be arranged, whereby the bit line pad 150 electrically with the channel layer 142 As in the Fig. 4A, the bit line pad 150for example, have a ring-shaped shape, and an opening 150OP can be penetrated by an inner wall of the bit line pad 150 be defined. The bitline pad 150 may overlap the body gate layer 146 not vertical, and thus the bit line pad 150 may not be electrically connected to the body gate line 146 In a top view, an outer wall of the bit line pad 150 for example, have an oval shape, and an inner wall of the bit line pad 150 may have a circular shape. In plan view, the inner wall of the bit line pad may 150 (e.g. an interface of the opening 150OP ) are arranged so that they cover the side wall of the body gate layer 146 with a desired (or, alternatively, a predetermined) distance, and thus the bit line pad 150 and the body gate layer 146spaced apart from each other. In some exemplary embodiments, the outer wall of the bitline pad 150 at least one of the following: a rounded rectangular shape, a polygonal shape, a circular shape or an oval shape, and the inner wall of the bit line pad 150 may have at least one of the following: a rounded rectangular shape, a polygonal shape, a circular shape, or an oval shape.

[0034] A third insulating layer 124 can be placed on the second insulation layer 122 and the third insulating layer 124 a sidewall of the bit line pad 150 surrounded and can be on the same vertical level as the bit line pad 150 A fourth insulating layer 126 can be placed on the third insulation layer 124 be arranged.

[0035] Multiple bit lines 164can be in the second direction (Y-direction) on the fourth insulating layer 126 A bit line contact 162 can be in a bit line contact hole 162H arranged to form the fourth insulating layer 126 penetrates, and the bit line contact 162 the bit line pad can 150 electrically with the bit line 164 connect. Multiple body gate lines 168 can be in the second direction (Y-direction) on the fourth insulating layer 126 A body gate contact 166 can be in a body gate contact hole 166H arranged to form the fourth insulating layer 126 and the third insulating layer 124 penetrates, and the body gate contact 166 the body gate line 168 electrically with the body gate layer 146 connect. A fifth insulating layer 128 can be placed on the fourth insulation layer 126arranged so that they form sidewalls of the plurality of bit lines 164 and the multiple body gate lines 168 surrounds.

[0036] In exemplary embodiments, as shown in the Fig. 4A, the bit line contact 162 to a center of the canal structure C140 be offset or located separately, for example in the first direction (X direction). The bit line pad 150 may have a first width w11 in the first direction (X direction) and a second width w12, which is smaller than the first width w11, in the second direction (Y direction). Accordingly, the bit line contact 162 on the bitline pad 150 be arranged (e.g. at a position further from the center of the channel structure C140 removed), and the body gate contact 166 can be on the body gate layer 146be arranged (e.g. at a position that is closer than the bit line contact 162 to the center of the channel structure C140 spaced apart), and the multiple body gate lines 168 can be on the same level as the multiple bit lines 164 Two bit lines 164 arranged side by side can be alternately and repeatedly connected to two adjacent body gate lines 168 be arranged.

[0037] In exemplary embodiments, as shown in the Fig. 4A is shown when two channel structures C140 in the second direction (Y-direction) between a string insulation layer 184 and a word line intersection area WLC be arranged, a first bit line 164_1 and a first body gate line 168_1 , which is provided with a first channel structure C140_1 , which is one of the two channel structures C140is connected, and the second bit line 164 2 and the second body gate line 168 2, which has a second channel structure C140_2 , which is the other of the two channel structures C140 are connected, are parallel to each other in the second direction (Y direction). Accordingly, the first bit line 164_1 , the first body gate line 168_1 , the second body gate line 168 2 and the second bit line 164 2 are arranged sequentially in the first direction (X direction).

[0038] In some exemplary embodiments, as shown in the Fig. 4B, a first bit line 164_1 and a first body gate line 168_1 , which is provided with a first channel structure C140_1 , which is one of the two channel structures C140 are connected, are arranged side by side in the second direction (Y-direction), and the second bit line164 2 and the second body gate line 168 2, which has a second channel structure C140_2 , which is the other of the two channel structures C140 can run parallel to each other in the second direction (Y-direction), with the first bit line 164_1 , the second body gate line 168 2, the first body gate line 168_1 and the second bit line 164 2 can be arranged sequentially in the first direction (X-direction). In this case, a separation distance between the first bit line contact 162 , which is connected to the first bit line 164_1 connected, and the first body gate contact 166 , which is connected to the first body gate line 168_1 connected, can be relatively large, and thus the process tolerance in processes for forming the bit line contact hole 162H and the body gate contact hole 166H be enlarged.

[0039] In still other exemplary embodiments, other than those described in the Fig. 4A and Fig. 4B, the multiple body gate lines 168 in the second direction (Y-direction) at a different vertical level than the plurality of bit lines 164 get lost.

[0040] As in the Fig. 2, several word line intersection areas WLC in the first direction (X-direction) parallel to the main surface 110M of the substrate 110 on the substrate 110 Several gate electrodes 130 , which is located between a pair of word line intersections WLC arranged can form a block, and the one pair of word line intersection areas WLC can be a width of the multiple gate electrodes 130 in the second direction (Y-direction).

[0041] Multiple common source lines 180, which the multiple word line intersection areas WLC vertically overlap, can be applied to the substrate 110 in the first direction (X-direction). Insulating spacers 182 can be located on both sidewalls of the multiple common source lines 180 be arranged. Fig. 6 illustrates that the multiple common source lines 180 have a lower surface at a lower level than the main surface 110M of the substrate 110 arranged, however, in some exemplary embodiments, the plurality of common source lines 180 have a lower surface which is at the same level as the main surface 110M of the substrate 110 is arranged.

[0042] Multiple shared source areas 112 can be found in the substrate 110 under the common source management 180in the first direction (X-direction). The multiple common source areas 112 may be impurity regions doped with n-type impurities in a high concentration. The multiple common source regions 112 can function as source regions for supplying current to the memory cells. The multiple common source regions 112 can be arranged at positions which cover the multiple word line intersection areas WLC overlap.

[0043] As in the Fig. 2, in one block the top gate electrode 130 through the string insulation layer 184 be divided into two sections in a plan view. Although not shown, the string insulation layer can 184 from the same level as the upper surface of the second insulation layer 122to a level lower than a lower surface of the top gate electrode 130 is, gone.

[0044] The multiple gate electrodes 130 can run in the connection area CON to form the pad part PAD. Since the multiple gate electrodes 130 from the main interface 110M of the substrate 110 get away, the multiple gate electrodes 130 in the first direction (X-direction) with a shorter length. The pad part PAD can refer to sections of the multiple gate electrodes 130 which are arranged in a stepped shape. The second insulating layer 122 can be applied to the multiple gate electrodes 130 which form the pad part PAD, and the multiple pad contacts 172 can be arranged in the connection area CON, while forming the second insulating layer 122 penetrate and the multiple gate electrodes 130connect.

[0045] As in the Fig. 5, several dummy channel structures D140 in the dummy channel holes D140H, which the multiple gate electrodes 130 penetrate, are arranged in the connection area CON, and the several dummy channel structures D140 can be accessed from the main interface 110M of the substrate 110 in the third direction (Z-direction). The dummy channel structure D140 can be formed to ensure the structural stability of the semiconductor device 100 in the manufacturing process of the semiconductor device 100 Each of the several dummy channel structures D140 can have the same structure as the channel structure C140 Each of the several dummy channel structures D140 can have the same width as the channel structure C140 or a greater width than the channel structure C140 have.

[0046] Since data storage in a semiconductor device is generally performed by using a method of injecting charge into a charge storage structure through Fowler-Nordheim (FN) tunneling, the charge storage structure can be arranged between a gate electrode and a channel layer, and the charge storage structure and the channel layer are sequentially formed in this order in a channel hole. However, as a vertical height of the semiconductor device increases, the difficulty of a process for forming a cell contact layer by selective epitaxial growth (SEG) at a bottom portion of a channel hole so that a channel layer and a substrate are electrically connected, or a process for etching a memory structure at the bottom portion of the channel hole, significantly increases, limiting the increase in the vertical height of the semiconductor device.

[0047] However, according to the exemplary embodiments described above, the channel layer 142 , the charge storage structure 144 and the body gate layer 146 sequentially in the channel hole C140H formed, and data storage can be achieved by injecting charge into the charge storage structure 144 by voltages that are applied independently to the gate electrode 130 and the body gate layer 146 This means that a manufacturing process with a high degree of difficulty, such as the process of forming the cell contact layer by selective epitaxial growth (SEG) at the bottom of the channel hole or the process of etching the memory structure at the bottom of the channel hole, may not be required. Accordingly, the semiconductor device 100increase in height in the vertical direction or high integration. In addition, as described below, applying the programming voltage via the body gate layer 146 significantly reduce the noise between word lines, and thus the cell operation characteristics or the electrical characteristics of the semiconductor device 100 be improved.

[0048] An exemplary control method for the semiconductor device 100 with reference to the Fig. 8 to Fig. 12 described.

[0049] Fig. 8 illustrates a timing diagram of a programming voltage applied to a memory cell used in an exemplary programming operation of the semiconductor device 100 is programmed. Fig. Figure 9 is a schematic diagram illustrating voltages applied to a program string, a blocking string, and a body gate line in a programming operation. Fig. Figure 10 illustrates a schematic energy band diagram of components included in a memory cell used in step 3 of the Fig. 9 has been programmed. Fig. 11 is a schematic diagram illustrating voltages applied to a string and a body gate line on which, in an exemplary read operation of the semiconductor device 100 Reading is carried out. Fig. 12 is a schematic diagram illustrating voltages applied to a string and a body gate line on which, in an exemplary erase operation of the semiconductor device 100 Deletion is performed.

[0050] In the Fig. 8 to Fig. 12 shows exemplary programming, reading and erasing operations of a memory cell MCT1 (see Fig. 1), which is located between a bit line BL1 (see Fig. 1), a body gate line BGL1 (see Fig. 1) and a word line WL1 (see Fig. 1) is described as an example.

[0051] First, with reference to the Fig. 8 to Fig. 9 can be an exemplary programming operation of the semiconductor device 100 be carried out by a sequence comprising steps 1 to 3 in order.

[0052] In step 1, a voltage of 0 V may be applied to a string STRpg (hereinafter referred to as a "programming string") including a memory cell MCPG to be programmed via a bit line connected thereto. A power supply voltage Vcc may be applied to the strings STRin (hereinafter referred to as an "inhibit string") connected to the remaining bit lines, except for the bit line connected to the programming string STRpg, via the bit line. A pass voltage Vpass may be applied to all word lines WL(Unsel) and WL(Sel) (that is, to both the unselected word line WL(Unsel) and the selected word line WL(Sel)). A voltage of 0 V may be applied to the body gate line BGpg (hereinafter referred to as a "programming body gate line") adjacent to the memory cell to be programmed.During step 1, the charging of electrons can be performed on a channel of the programming string STRpg.

[0053] In step 2, while the forward voltage Vpass is applied to the selected word line WL(Sel), a voltage of 0 V may be applied to the unselected word line WL(Unsel), and a voltage of 0 V may be applied to the program body gate line BGpg. During step 2, electrons may accumulate in the channel of the selected word line WL(Sel).

[0054] In step 3, a programming voltage Vpgm may be applied to the programming body gate line BGpg, and a voltage of 0 V may be applied to the selected word line WL(Sel). Also, the bit line connected to the programming string STRpg and the unselected word line WL(Unsel) may be made floating. In exemplary embodiments, the programming voltage Vpgm may have a greater value than the forward voltage Vpass. In step 3, as exemplified in the Fig. 10, electrons from the channel layer 142 of the memory cell MCPG, which is connected by the selected word line WL(Sel) (e.g. the selected gate electrode 130 ) is formed, to the body gate layer 146 tunneled, and electrons can enter the charge storage structure 144 (e.g. the charge storage layer 144B) between the channel layer 142 and the body gate layer 146injected. In some exemplary embodiments, the programming voltage Vpgm may have a lower value than, but is not limited to, a programming voltage applied to a selected word line in the conventional semiconductor device.

[0055] With reference to Fig. 11 can show an exemplary read operation of the semiconductor device 100in a page unit. For example, a sweep voltage Vsweep can be applied to the selected word line WL(Sel) of the string STRread on which the read operation is to be performed, and a read voltage Vread can be applied to the unselected word line WL(Unsel). A voltage of 0 V can be applied to the body gate line BGread on which the read operation is to be performed, and thus the read operation can be performed. In this case, a string select voltage Vssl and a ground select voltage Vgsl can be applied to the string select line SSL and the ground select line GSL of the string STRead on which the read operation is to be performed.

[0056] With reference to Fig. 12 may show an exemplary erase operation of the semiconductor device 100in a block unit. For example, an erase voltage Vers can be applied to a well region PPW of a string STRers on which the erase operation is to be performed, and a voltage of 0 V can be applied to a body gate line BGers on which the erase operation is to be performed. Thus, the erase operation of a memory cell block can be performed by floating all word lines WL.

[0057] According to the exemplary embodiments described above, the semiconductor element 100Apply the programming voltage Vpgm to the programming body gate line BGpg in a sequence sequentially comprising steps 1 to 3, particularly during step 3, and thus can perform the programming operation of the memory cell MCPG. In a conventional semiconductor device, a programming operation is performed by applying a programming voltage to a selected word line and applying a forward voltage to a non-selected word line. In such a case, voltages with a relatively large voltage difference may be applied between adjacent word lines having a relatively small separation distance, and the cell operation error due to noise between adjacent word lines may occur.However, according to exemplary embodiments, since a relatively low voltage (e.g., a forward voltage) can be applied to the word line compared to the programming voltage applied to the body gate line, the noise between the word lines can be significantly reduced, and thus the semiconductor device can be . 100 have improved cell operating characteristics or improved electrical properties.

[0058] Fig. 13 is a cross-sectional view showing a semiconductor device 100A according to exemplary embodiments, and Fig. 14 is an enlarged cross-sectional view of a section CX2 the Fig. 13. In the Fig. 13 and Fig. 14 have the same reference numerals as in the Fig. 1 to Fig. 12 similar components.

[0059] With reference to the Fig. 13 and Fig. 14 can be a channel structure C140A furthermore a conductive boundary layer 148 between the charge storage structures 144 and the body gate layer 146 Accordingly, the side wall 146S the body gate layer 146 from the conductive boundary layer 148 be surrounded.

[0060] In exemplary embodiments, the body gate layer 146 at least one of the following: cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), silicides thereof, and / or alloys thereof. The conductive boundary layer 148 may comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), titanium (Ti), tantalum (Ta), and / or combinations thereof. Optionally, a high-k layer (not shown) may be further disposed between the conductive interface 148 and the charge storage structure 144 be formed.

[0061] Fig. 15 is a cross-sectional view showing a semiconductor device 100B according to exemplary embodiments, and Fig. 16 is an enlarged cross-sectional view of a section CX3 the Fig. 15. In the Fig. 15 and Fig. 16 have the same reference numerals as in the Fig. 1 to Fig. 14 similar components.

[0062] With reference to the Fig. 15 and Fig. 16 can be a gate insulating layer 132B between a side wall 140S a channel structure C140B and a gate electrode 130B and the gate insulating layer 132B may not be located between the gate electrode 130B and the first insulating layer 120 . An upper surface 130U and a lower surface 130L the gate electrode 130 can be the first insulation layer 120contact, and the first insulating layer 120 can be a side wall C140S (for example, an outer wall of the channel layer 142 ) of the channel structure C140B contact.

[0063] In exemplary embodiments, the gate insulating layer 132B a thermal oxide layer formed by a thermal oxidation process. For example, after a sacrificial layer 310 (see Fig. 31) to form a gate room 130GS has been removed, the gate insulation layer 132B on side walls of the channel layer 142 formed, which lead to the gate room 130GS exposed by performing the thermal oxidation process, but is not limited to this.

[0064] Fig. 17 is a cross-sectional view showing a semiconductor device 100C according to exemplary embodiments, and Fig. 18 is an enlarged cross-sectional view of a section CX4 the Fig. 17. In the Fig. 17 and Fig. 18 have the same reference numerals as in the Fig. 1 to Fig. 16 similar components.

[0065] With reference to the Fig. 17 and Fig. 18 may be a lower section of a channel structure C140C from a first semiconductor layer 174 and a second semiconductor layer 176 The first semiconductor layer 174 may comprise doped polysilicon or undoped polysilicon, and the second semiconductor layer 176 may also comprise doped polysilicon or undoped polysilicon. The first semiconductor layer 174 may serve as a common source line extension region and may be a section corresponding to the common source line CSL the Fig. 1. The second semiconductor layer 176can serve as a carrier layer to prevent a mold stack from being damaged in the process of removing a sacrificial layer to form the first semiconductor layer 174 collapses or falls down.

[0066] The channel structure C140C the first semiconductor layer 174 and the second semiconductor layer 176 and may extend to a level lower than a main surface 110M a substrate 110 A gate insulating layer 132C can be on an inner wall of the channel hole C140H and arranged so that they cover the entire side wall C140S and the entire lower surface of the channel structure C140C with the exception of a section of the side wall C140S the channel structure C140C , which is formed by the first semiconductor layer 174 Accordingly, the gate insulating layer can 132C between the channel layer142 and the gate electrode 130 and between the channel layer 142 and the first insulating layer 120 and also an upper surface 130U and a lower surface 130L the gate electrode 130 the first insulating layer 120 contact.

[0067] Fig. 19 is a cross-sectional view showing a semiconductor device 100D according to some exemplary embodiments. In the Fig. 19 denote the same reference numerals as in the Fig. 1 to Fig. 18 the same components.

[0068] With reference to Fig. 19 can be a body gate layer 146 have an upper surface which is at a lower level than an upper surface of a second insulating layer 122 and a sixth insulating layer 129 can be on the body gate layer 146be arranged, whereby the sixth insulating layer 129 an upper inlet of a manhole C140H fills, and a body gate contact 166 the fourth insulation layer 126 , the third insulating layer 124 and the sixth insulating layer 129 penetrate to the body gate layer 146 For example, since the upper surface of the body gate layer 146 at a lower level than the upper surface of the second insulating layer 122 can be arranged, even if in a pattern process for the bit line pad 150 Misalignment occurs, unwanted electrical connection or short circuit between the bit line pad 150 and the body gate layer 146 reduced or prevented.

[0069] Fig. 20 is a cross-sectional view showing a semiconductor device 200according to some exemplary embodiments. In the Fig. 20 denote the same reference numerals as in the Fig. 1 to Fig. 19 the same components.

[0070] With reference to Fig. 20 can be a lower substrate 210 at a lower vertical level than the substrate 110 An active region (not shown) can be arranged in the lower substrate 210 through a component insulation layer 222 be defined, and several control transistors 230T can be formed on the active region. The multiple drive transistors 230T can have a drive circuit gate structure 232 and contamination areas 212 which are deposited on sections of the lower substrate 210 under both sides of the drive circuit gate structure 232 be arranged.

[0071] Multiple connection layers 242, multiple contact connectors 246 , which connects the multiple layers 242 connect each other or which connect the multiple layers 242 with the control transistors 230T connect, and a lower intermediate insulating layer 250 , which connects the multiple layers 242 and the multiple contact connectors 246 can be applied to the lower substrate 210 be arranged.

[0072] The substrate 110 can be applied to the lower intermediate insulation layer 250 The first several insulating layers 120 and the multiple gate electrodes 130 , the channel structure C140 , the bit line 164 (see Fig. 5) and the body gate line 168 can be on the substrate 110 be arranged.

[0073] The Fig. 21 to Fig. 30 are schematic diagrams showing a method of manufacturing a semiconductor device 100 according to some exemplary embodiments in a process sequence. In particular, the Fig. 21 to Fig. 30 cross sections corresponding to a cross section along a line B2-B2' the Fig. 2. In the Fig. 21 to Fig. 30 denote the same reference numerals as in the Fig. 1 to Fig. 20 are used, the same components.

[0074] With reference to Fig. 21, the several first insulating layers 120 and several layers of victims 310 alternately on the main interface 110M of the substrate 110 In exemplary embodiments, the plurality of first insulating layers 120 an insulating material, such as silicon oxide or silicon oxynitride, and the plurality of sacrificial layers310 may comprise silicon nitride, silicon oxynitride or doped polysilicon with impurities and / or the like.

[0075] Subsequently, although it is not shown, the pad part PAD (see Fig. 2) in the connecting surface CON (see Fig. 2) by sequentially patterning the plurality of first insulating layers 120 and the multiple victim layers 310 In some exemplary embodiments, the pad part PAD may be formed in a step shape having a difference in the first direction (X-direction) at an upper surface level.

[0076] Afterwards, the second insulation layer 122 be formed to form a top sacrificial layer 310 and the pad part PAD. The second insulating layer 122 may comprise an insulating material such as silicon oxide or silicon oxynitride.

[0077] With reference to Fig. 22, a mask pattern (not shown) may be formed on the second insulating layer 122 formed, and then sections of the second insulating layer 122 , the several first insulating layers 120 and the multiple victim layers 310 etched to create channel holes C140H using the mask pattern as an etching mask. The channel hole C140H may extend to a level lower than the main surface 110M of the substrate 110 is.

[0078] With reference to Fig. 23 can the channel layer 142 , the dielectric tunnel layer 144A , the charge storage layer 144B , the dielectric barrier layer 144C and the body gate layer 146 sequentially on the inner wall of the channel hole C140H Afterwards, a planarization process can be further carried out to form sections of the channel layer 142, the dielectric tunnel layer 144A , the charge storage layer 144B , the dielectric barrier layer 144C and the body gate layer 146 which is on the second insulating layer 122 Here, the dielectric tunnel layer 144A , the charge storage layer 144B and the dielectric barrier layer 144C as the charge storage structure 144 As a result of the planarization process, the body gate layer 146 have an upper surface that is substantially coplanar with the upper surfaces of the charge storage structure 144 , the channel layer 142 and the second insulating layer 122 is arranged.

[0079] In exemplary embodiments, a lower surface of the channel layer 142 an upper surface of the substrate 110leading to a lower section of the channel hole C140H exposed. Therefore, a manufacturing process with a high degree of difficulty, such as an SEG process, which has been conventionally required, may not be required, and thus the difficulty of the manufacturing process for forming the channel structure C140 be relatively low.

[0080] With reference to Fig. 24, a mask pattern (not shown) may be formed on the second insulating layer 122 and the channel structure C140 formed, and a word line cut opening 180H can be achieved by removing the sacrificial layers 310 and the first insulating layers 120 by using the mask pattern as an etching mask. The upper surface of the substrate 110 can be formed at a lower portion of the word line cut opening 180H be exposed.

[0081] With reference to Fig. 25 can the multiple victim layers 310 (see Fig. 24), which is formed by the word line cut opening 180H are exposed, removed to create several gate rooms 130GS to form. Side walls of the channel layer 142 can be found in the gate rooms 130GS In exemplary embodiments, the removal of the multiple sacrificial layers 310 by a wet etching process using a phosphoric acid solution as an etchant.

[0082] With reference to Fig. 26 can the gate insulating layer 132 and a preliminary gate electrode layer 130P on inner walls of the word line cut opening 180H and the several gate rooms 130GS To form the preliminary gate electrode layer 130P to form, the conductive boundary layer 130UB (see Fig. 7) and the metal layer 130M (see Fig. 7) are formed sequentially.

[0083] With reference to Fig. 27, sections of the gate insulating layer 132 and the preliminary gate electrode layer 130P which is on the second insulating layer 122 and on the inner wall of the word line cut opening 180H formed, can be removed, and thus the gate insulating layer 132 and the gate electrode 130 in the gate rooms 130GS be formed.

[0084] Subsequently, impurities can enter the substrate 110 injected, which again leads to the lower section of the word line cut opening 180H exposed, and thus the common source area 112 in a section of the substrate 110 formed on the lower portion of the word line cut opening 180H After that, an insulating spacer can be 182on a sidewall of the word line cut opening 180H formed, and a common source line 180 can be placed on the insulating spacer 182 formed while forming an interior of the word line cut opening 180H fills.

[0085] With reference to Fig. 28, a conductive layer (not shown) can be applied to the channel structure C140 and the second insulating layer 122 formed, and then the bit line pad can 150 formed by patterning the conductive layer. The bit line pad 150 can be formed to have a ring-like shape, as shown in the Fig. 4A, and the inner wall of the bit line pad 150 the body gate layer 146 surrounded by the body gate layer 146 at a desired (or, alternatively, a predetermined) distance. Since the bit line pad 150can be formed by patterning the conductive layer, a thickness of the second insulating layer 122 compared to a semiconductor device according to a comparative example in which a bit line pad in the channel hole C140H formed, be relatively thin.

[0086] With reference to Fig. 29 a third insulating layer 124 on the bitline pad 150 and the second insulating layer 122 formed, and then a planarization for an upper surface of the third insulating layer 124 be performed until an upper surface of the bit line pad 150 exposed. A fourth insulation layer can then be 126 formed to form the upper surfaces of the third insulating layer 124 and the bitline pad 150 In some exemplary embodiments, when the third insulating layer 124may have an upper surface that is at a higher level than the upper surface of the bit line pad 150 exposed, the planarization of the third insulating layer 124 be omitted, in this case the fourth insulation layer 126 may not be formed.

[0087] Afterwards, the bit line contact hole 162H (see Fig. 5) and the body gate contact hole 166H which is the third insulating layer 124 and the fourth insulating layer 126 Then the bit line contact hole 162H and the body gate contact hole 166H filled with a conductive material to form the bit line contact 162 and the body gate contact 166 in the bit line contact hole 162H or in the Body-Ga contact hole 166H to form.

[0088] With reference to Fig. 30 can the bit line 164and the body gate line 168 which is connected to the bit line contact 162 or the body gate contact 166 connected, on the fourth insulating layer 126 be formed.

[0089] The semiconductor element 100 can be completed by performing the processes described above.

[0090] In the semiconductor device according to the comparative example, the charge storage structure 144 (that is, the dielectric barrier layer 144C , the charge storage layer 144B and the dielectric tunnel layer 144A) in the sewer hole C140H formed, and then a section of the charge storage structure 144 , which is located on a lower section of the hole C140H is arranged, and then an anisotropic etching process or an etch-back process is performed to form an upper surface of the substrate 110 Afterwards, the channel layer142 on an inner wall of the sewer hole C140H Since the vertical height of the semiconductor device 100 increases, however, the aspect ratio of the channel hole also increases C140H , so that the difficulty of the anisotropic etching process or the etch-back process with respect to the lower portion of the channel hole C140H can increase significantly. If the upper surface of the substrate 110 at the lower section of some of the canal holes C140H is not sufficiently exposed (if the lower section of the charge storage structure 144 is partially removed), the electrical properties of the channel structure C140 which in the manhole C140H formed may not be excellent.

[0091] In addition, in the semiconductor device according to the comparative example, in order to achieve a low contact resistance between the channel structure C140 and the substrate 110to obtain a cell contact by growing a semiconductor layer from the upper surface of the substrate 110 , which leads to the lower section of the channel hole C140H exposed, can be formed by a selective epitaxial growth (SEG) process. However, it can be difficult to form the semiconductor layer with a uniform height by the SEG process, and thus the multiple channel structures C140 are unlikely to have uniform electrical properties.

[0092] According to the method of manufacturing the semiconductor device 100 However, according to the exemplary embodiments, a manufacturing process with high degree of difficulty as described above can be omitted by forming the channel layer 142 directly on the inner wall of the sewer hole C140H In addition, the difficulty of forming the bit line pad 150Therefore, the semiconductor element 100 according to the exemplary embodiments may be advantageous in that it increases the height in the vertical direction and improves the degree of integration.

[0093] The Fig. 31 to Fig. 32 are schematic diagrams showing a method of manufacturing a semiconductor device 100B according to some example embodiments in a process sequence.

[0094] First, the word line cut opening 180H and the several gate rooms 130GS by carrying out the measures referred to in Fig. 21 to Fig. 25 described processes.

[0095] With reference to Fig. 31 can be a gate insulating layer 132B on a surface of the channel layer 142 leading to the several gate rooms 130GS exposed.

[0096] In exemplary embodiments, a process for forming the gate insulating layer 132B a thermal oxidation process, and a surface section of the channel layer 142 can be converted into silicon oxide by the thermal oxidation process, and thus the gate insulating layer 132B Meanwhile, the gate insulating layer 132B may not be on the upper and lower surfaces of the first insulation layer 120 leading to the gate room 130GS For example, the gate insulating layer 132B a thermal oxide layer formed in the thermal oxidation process and silicon oxide.

[0097] With reference to Fig. 32 may be a preliminary gate electrode layer 130P on the word line cut opening 180H and the interior walls of the several gate rooms 130GS be formed.

[0098] The semiconductor component can then 100B by carrying out the measures referred to in Fig. 27 to Fig. 30 processes described are completed.

[0099] The Fig. 33 to Fig. 38 are schematic diagrams showing a method of manufacturing a semiconductor device 100C according to some exemplary embodiments in a process sequence. The Fig. 33 to Fig. 35 are cross-sectional views corresponding to a cross section along the line B2-B2' the Fig. 2, and the Fig. 36 to Fig. 38 are enlarged cross-sectional views corresponding to a section CX5 of the Fig. 35 correspond.

[0100] With reference to Fig. 33 the first insulating layer 120 on the main interface 110M of the substrate 110 formed, and then a lower sacrificial layer 320and a second semiconductor layer 176 sequentially on the first insulating layer 120 formed, and then several first insulating layers 120 and several layers of victims 310 alternately on the second semiconductor layer 176 The lower sacrificial layer 320 may comprise silicon nitride or silicon oxynitride, and the second semiconductor layer 176 may comprise doped polysilicon or undoped polysilicon.

[0101] Afterwards, sections of the several sacrificial layers 310 , the several first insulating layers 120 , the second semiconductor layer 176 and the lower victim class 320 etched to create a channel hole C140H to form a gate insulating layer 132C , a channel layer 142 , a dielectric tunnel layer 144A , a charge storage layer 144B , a dielectric barrier layer144C and a body gate layer 146 can be found in the sewer hole C140H be formed sequentially, and then a section of the channel layer 142 , the dielectric tunnel layer 144A , the charge storage layer 144B , the dielectric barrier layer 144C and the body gate layer 146 which is on the second insulating layer 122 formed can be removed by performing the planarization process. Accordingly, the channel structure C140C be formed.

[0102] With reference to Fig. 34 sections of the sacrificial layers 310 , the several first insulating layers 120 , the second semiconductor layer 176 and the lower victim class 320 etched to create a word line cut opening 180H to form, and then a coating insulating layer 330 which the side walls of the word line cut opening 180HIn exemplary embodiments, the coating insulating layer 330 all side walls of the several sacrificial layers 310 through the word line cut opening 180H are exposed, and can side walls of the lower sacrificial layer 320 For example, the coating insulation layer 330 formed using a material that has poor step coverage properties, and thus the overcoat insulating layer 330 may not be on a lower portion of the word line cut opening 180H and the upper surface of the substrate 110 formed.

[0103] With reference to the Fig. 35 and Fig. 36 the lower sacrificial layer 320 (see Fig. 34), which leads to the lower section of the word line cut opening 180H exposed, and then a lower opening can be 174Hbe formed at a position from which the lower sacrificial layer 320 has been removed. Sidewalls of the gate insulation layer 132C can be accessed through the lower opening 174H In exemplary embodiments, the removal of the lower sacrificial layers 320 by a wet etching process using a phosphoric acid solution as an etchant.

[0104] With reference to Fig. 37, a portion of the gate insulating layer 132C through the lower opening 174H exposed, removed to form side walls of the channel layer 142 Removing the gate insulation layer 132C can be carried out by a wet etching process. In the wet etching process, a section of the gate insulating layer 132C between the channel layer 142 and the second semiconductor layer 176 through the lower opening 174Hexposed and removed together, and a portion of the gate insulating layer 132C between the channel layer 142 and the lowest first insulation layer 120 can also be accessed through the lower opening 174H exposed and removed together. However, the inventive concept is not limited to this.

[0105] With reference to Fig. 38 may be a first semiconductor layer 174 in the word line cut opening 180H (see Fig. 35) and the lower opening 174H The first semiconductor layer 174 the inside of the lower opening 174H between the lowest first insulation layer 120 and the second semiconductor layer 176 fill and a side wall C140S the channel structure C140C contact.

[0106] Subsequently, a section of the first semiconductor layer 174, which is on the inner wall of the word line cut opening 180H is formed, are removed by the etching-back process, and the upper surface of the substrate 110 can return to the lower section of the word line cut opening 180H exposed.

[0107] Afterwards, the several layers of victims 310 (see Fig. 24), which is formed by the word line cut opening 180H are exposed, are removed to create the several gate rooms 130GS at the positions where the multiple sacrificial layers 310 can be removed, and then the preliminary gate electrode layer 130P on the interior walls of the several gate rooms 130GS be formed.

[0108] The semiconductor component can then 100C by carrying out the measures referred to in Fig. 27 to Fig. 30 processes described are completed.

[0109] As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although exemplary embodiments have been described herein using specific terms, they are used only for the purpose of describing the inventive concept of the present disclosure and are not intended to limit the scope of the inventive concept as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalents to some exemplary embodiments are possible based on the exemplary embodiments. Therefore, the true technical scope of the present disclosure is defined by the inventive concept of the appended claims.

[0110] Although the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 1020190093370

[0001]

Claims

[1] Semiconductor device comprising: a channel structure on a substrate extending in a first direction perpendicular to a top surface of the substrate, the channel structure comprising: a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding a sidewall of the charge storage structure; a plurality of gate electrodes on the substrate and spaced from each other in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure. [2] The semiconductor device of claim 1, wherein the charge storage structure is located between the body gate layer and the channel layer, and the charge storage structure is in contact with an inner wall of the channel layer. [3] Semiconductor device according to claim 1, wherein the channel layer is located on an inner wall of a channel hole that penetrates the plurality of gate electrodes and extends in the first direction, wherein the charge storage structure lies uniformly along the inner wall of the channel hole on the channel layer and the body gate layer fills the channel hole on the charge storage structure. [4] A semiconductor device according to claim 1, wherein the charge storage structure comprises: a dielectric barrier layer on the sidewall of the body gate layer, a charge storage layer on the dielectric barrier layer and a dielectric tunnel layer on the charge storage layer, which contacts the channel layer. [5] Semiconductor device according to claim 1, wherein the channel layer comprises a lower portion in contact with the upper surface of the substrate and an entirety of a lower surface of the charge storage structure is covered by the channel layer, so that the lower surface of the charge storage layer is not in contact with the substrate. [6] A semiconductor device according to claim 1, further comprising: a plurality of insulating layers each located between two adjacent gate electrodes of the plurality of gate electrodes, wherein the gate insulating layer covers upper and lower surfaces of each of the plurality of gate electrodes and the multiple insulation layers contact the side wall of the channel structure. [7] A semiconductor device according to claim 1, further comprising: a plurality of insulating layers each located between two adjacent gate electrodes of the plurality of gate electrodes, wherein the gate insulating layer is located only between each of the plurality of gate electrodes and the channel structure, and the multiple insulation layers contact the side wall of the channel structure. [8] A semiconductor device according to claim 1, further comprising: a plurality of insulating layers each located between two adjacent gate electrodes of the plurality of gate electrodes, wherein the gate insulating layer extends in the first direction along an entire length of the sidewall of the channel structure and the multiple insulation layers do not contact the side wall of the channel structure. [9] A semiconductor device according to claim 1, further comprising: a bit line pad at a level higher than a top gate electrode of the plurality of gate electrodes, the bit line pad being located on the channel layer, an inner wall of the bit line pad defining an opening; a bitline contact connected to the bitline pad; and a body-gate contact that penetrates the opening and is connected to the body-gate layer. [10] The semiconductor device of claim 9, wherein the opening vertically overlaps the body gate layer in a plan view and the inner wall of the bit line pad surrounds the body gate layer. [11] A semiconductor device according to claim 9, further comprising: a bit line connected to the bit line contact and extending in a second direction parallel to the top surface of the substrate; and a body gate line connected to the body gate contact, the body gate line extending in the second direction. [12] The semiconductor device of claim 1, wherein an upper surface of the body gate layer is at a same level as an upper surface of the channel layer. [13] The semiconductor device of claim 1, wherein an upper surface of the body gate layer is at a lower level than an upper surface of the channel layer. [14] A semiconductor device according to claim 1, further comprising: a conductive interface between the body gate layer and the charge storage structure. [15] Semiconductor device comprising: a plurality of gate electrodes on a substrate and spaced from each other in a first direction perpendicular to a top surface of the substrate; a channel structure in a channel hole penetrating the plurality of gate electrodes and extending in the first direction, the channel structure comprising: a channel layer on an inner wall of the channel hole; and a charge storage structure on the channel layer on the inner wall of the channel hole; and a gate insulating layer between each of the plurality of gate electrodes and the channel layer, the gate insulating layer covering an upper surface and a lower surface of each of the plurality of gate electrodes, wherein the channel layer is located between each of the plurality of gate electrodes and the charge storage structure. [16] The semiconductor device of claim 15, wherein the channel structure further comprises a body gate layer filling an interior of the channel hole on the charge storage structure. [17] A semiconductor device according to claim 16, further comprising: a bit line pad at a level higher than a top gate electrode of the plurality of gate electrodes and on the channel layer, wherein an inner wall of the bit line pad defines an opening; a bitline contact connected to the bitline pad; and a body-gate contact that penetrates the opening and is connected to the body-gate layer. [18] A semiconductor device according to claim 17, further comprising: a bit line connected to the bit line contact and extending in a second direction parallel to the top surface of the substrate; and a body gate line connected to the body gate contact, the body gate line extending in the second direction. [19] Semiconductor device according to claim 16, wherein the charge storage structure is located between the body gate layer and the channel layer, the channel layer comprises a lower portion in contact with the upper surface of the substrate and an entirety of a lower surface of the charge storage structure is covered by the channel layer, so that the lower surface of the charge storage layer is not in contact with the substrate. [20] Semiconductor device comprising: a channel structure on a substrate extending in a first direction perpendicular to a top surface of the substrate; the channel structure comprising: a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding a sidewall of the charge storage structure; a plurality of gate electrodes on the substrate and spaced from each other in the first direction on a sidewall of the channel structure; a gate insulating layer between each of the plurality of gate electrodes and the channel structure; a bit line pad formed at a level higher than a top gate electrode of the plurality of gate electrodes and located on the channel layer; a bitline contact connected to the bitline pad; and a bit line connected to the bit line contact and extending in a second direction parallel to the top surface of the substrate. [21] The semiconductor device of claim 20, wherein an inner wall of the bit line pad defines an opening, the semiconductor device further comprising: a body-gate contact penetrating the opening and connected to the body-gate layer; and a body gate line connected to the body gate contact, the body gate line extending in the second direction. [22] The semiconductor device of claim 20, wherein the body gate layer comprises polysilicon or a metal. [23] A semiconductor device according to claim 20, further comprising: a conductive interface between the body gate layer and the charge storage structure. [24] A semiconductor device according to claim 20, further comprising: a plurality of insulating layers each located between two adjacent gate electrodes of the plurality of gate electrodes, wherein the gate insulating layer is located only between each of the plurality of gate electrodes and the channel structure, and the gate insulating layer comprises a thermal oxide layer.

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