Ferroelectric field defect transmitter using charge capture belt misalignment and method for forming the same

Abstract

Ferroelectric field-effect transistor, comprising: a semiconductor substrate (10) comprising a semiconductor channel (35) extending between a source region (32) and a drain region (38) and having a doping of a first conductivity type; a ferroelectric dielectric gate layer (53) arranged above the semiconductor channel (35) and containing a ferroelectric material with a charge-trapping band (53T) containing electronic states generated by interfacial trapping of the ferroelectric material; and a gate electrode (54) which is arranged on the ferroelectric dielectric gate layer (53) and is configured to provide an on state and an off state for the ferroelectric field-effect transistor by applying an on voltage or an off voltage from a gate bias circuit (120), wherein an energy level (53T) of the charge-capture band is offset during the on state from an energy level of an energy band (35V, 35C) of minority charge carriers of the semiconductor channel (35).

Description

BACKGROUND

[0001] A ferroelectric material is a material that can exhibit non-zero spontaneous electric polarization (i.e., non-zero electric dipole moment) when the external electric field is zero. The spontaneous electric polarization can be reversed by a strong external electric field applied in the opposite direction. The electric polarization depends not only on the external electric field at the time of measurement, but also on the history of the external electric field, and thus has a hysteresis loop. The maximum electric polarization is called the saturation polarization. The electric polarization that remains after an external electric field that induces saturation polarization is no longer applied (i.e., turned off) is called the residual polarization.The magnitude of the electric field that must be applied in the opposite direction of the residual polarization to achieve zero polarization is called the electric coercive field. For the purposes of forming memory devices, it is generally desirable to have a high residual polarization and a high coercive field. High residual polarization can increase the magnitude of an electrical signal. A high coercive field makes memory devices more stable against disturbances caused by electrical noise fields and interference.

[0002] The prior art relating to the subject matter of the invention can be found, for example, in DE 11 2017 007 888 T5.

[0003] The invention provides a ferroelectric field-effect transistor according to claim 1, a method according to claim 13, and a method according to claim 17. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practices, various features are not drawn to scale. Indeed, the dimensions of various features may be exaggerated or reduced as desired for clarity. Fig. 1A is a top view of an exemplary structure after forming a shallow trench isolation structure in an upper portion of a semiconductor substrate according to a first embodiment of the present disclosure. Fig. Figure 1B is a vertical cross-sectional view of the first exemplary structure taken along plane B - B' in Fig. 1A. Fig. 2A is a top view of the first exemplary structure after depositing gate stack material layers according to the first embodiment of the present disclosure. Fig. Figure 2B is a vertical cross-sectional view of the first exemplary structure taken along plane B - B' in Fig. 2A. Fig. 3A is a top view of the first exemplary structure after formation of a gate stack structure according to the first embodiment of the present disclosure. Fig. Figure 3B is a vertical cross-sectional view of the first exemplary structure taken along plane B - B' in Fig. 3A. Fig. 4A is a top view of the first exemplary structure after forming a source extension region, a drain extension region, and a gate spacer according to the first embodiment of the present disclosure. Fig. Figure 4B is a vertical cross-sectional view of the first exemplary structure taken along plane B - B' in Fig. 4A. Fig. 5A is a top view of the first exemplary structure after forming a deep source region and a deep drain region according to the first embodiment of the present disclosure. Fig. Figure 5B is a vertical cross-sectional view of the first exemplary structure taken along plane B - B' in Fig. 5A. Fig. 6A is a top view of the first exemplary structure after formation of a contact-level dielectric layer and contact via cavities according to the first embodiment of the present disclosure. Fig. Figure 6B is a vertical cross-sectional view of the first exemplary structure taken along plane B - B' in Fig. 6A. Fig. 7A is a top view of the first exemplary structure after forming a contact via structures according to the first embodiment of the present disclosure. Fig. Figure 7B is a vertical cross-sectional view of the first exemplary structure taken along plane B - B' in Fig. 7A. Fig. Figure 7C is a circuit diagram of a ferroelectric memory device embodying the first exemplary structure of the Fig. 7A and Fig. 7B contains. Fig. 8A is a band diagram of a material stack including the semiconductor channel and the gate stack structure in the field effect transistor in the first example structure when the voltage applied to the gate electrode is zero, according to the first embodiment of the present disclosure. Fig. 8B is a band diagram of a material stack including the semiconductor channel and the gate stack structure in the field effect transistor in the first example structure when the voltage applied to the gate electrode is a positive voltage that turns on the field effect transistor, according to the first embodiment of the present disclosure. Fig. 9A is a band diagram of a comparative exemplary material stack formed from the material stack in Fig. 8A is derived by removing a charge trapping band misalignment layer when the voltage applied to the gate electrode is zero. Fig. 9B is a band diagram of the comparative exemplary material stack in Fig. 9A when the voltage applied to the gate electrode is a positive voltage that turns on the field effect transistor. Fig. 10A is a top view of a second exemplary structure after depositing gate stack material layers according to a second embodiment of the present disclosure. Fig. 10B is a vertical cross-sectional view of the second exemplary structure taken along plane B - B' in Fig. 10A. Fig. 11A is a top view of the second exemplary structure after formation of a gate stack structure according to the second embodiment of the present disclosure. Fig. 11B is a vertical cross-sectional view of the second exemplary structure taken along plane B - B' in Fig. 11A. Fig. 12A is a top view of the second exemplary structure after forming a source extension region, a drain extension region, and a gate spacer according to the second embodiment of the present disclosure. Fig. 12B is a vertical cross-sectional view of the second exemplary structure taken along plane B - B' in Fig. 12A. Fig. 13A is a top view of the second exemplary structure after forming a deep source region and a deep drain region according to the second embodiment of the present disclosure. Fig. 13B is a vertical cross-sectional view of the second exemplary structure taken along plane B - B' in Fig. 13A. Fig. 14A is a top view of the second exemplary structure after forming a raised source region and a raised drain region according to the second embodiment of the present disclosure. Fig. 14B is a vertical cross-sectional view of the second exemplary structure taken along plane B - B' in Fig. 14A. Fig. 15A is a top view of the second exemplary structure after formation of a contact-level dielectric layer and contact via cavities according to the second embodiment of the present disclosure. Fig. 15B is a vertical cross-sectional view of the second exemplary structure taken along plane B - B' in Fig. 15A. Fig. 16A is a top view of the second exemplary structure after forming a contact via structures according to the second embodiment of the present disclosure. Fig. 16B is a vertical cross-sectional view of the second exemplary structure taken along plane B - B' in Fig. 16A. Fig. 16C is a circuit diagram of a ferroelectric memory device using the second exemplary structure of the Fig. 16A and Fig. 16B contains. Fig. 17A is a band diagram of a material stack including the semiconductor channel and the gate stack structure in the field effect transistor in the second example structure when the voltage applied to the gate electrode is zero, according to the second embodiment of the present disclosure. Fig. 17B is a band diagram of a material stack including the semiconductor channel and the gate stack structure in the field effect transistor in the second example structure when the voltage applied to the gate electrode is a positive voltage that turns on the field effect transistor, according to the second embodiment of the present disclosure. Fig. 18A is a band diagram of a comparative exemplary material stack formed from the material stack in Fig. 17A with the addition of an interfacial silicon oxide layer when the voltage applied to the gate electrode is zero. Fig. 18B is a band diagram of the comparative exemplary material stack in Fig. 18A when the voltage applied to the gate electrode is a positive voltage, which turns on the field effect transistor. Fig. 19 is a first flowchart illustrating steps for forming the first exemplary structure of the present disclosure according to an embodiment of the present disclosure. Fig. 20 is a second flowchart illustrating steps for forming the second exemplary structure of the present disclosure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0005] The present disclosure is generally directed to semiconductor devices, and more particularly to ferroelectric field effect transistors (FeFETs) having a misalignment layer between a conduction band of a semiconductor channel and a charge trapping band of a ferroelectric dielectric gate layer, and a method of forming the same.

[0006] With reference to Fig. 1A and Fig. 1B illustrates a first exemplary structure according to a first embodiment of the present disclosure, including a semiconductor substrate 8 including a semiconductor material layer 10. The semiconductor substrate 8 may be a bulk semiconductor substrate in which the semiconductor material layer 10 extends from a front surface to a back surface, or it may be a semiconductor-on-insulator (SOI) substrate including a buried insulating layer (not shown) underlying the semiconductor material layer 10 and a handle substrate (not shown) underlying the buried insulating layer. The semiconductor substrate 8 may, for example, be a commercially available single-crystalline bulk semiconductor substrate or a commercially available semiconductor-on-insulator substrate.

[0007] The semiconductor material layer 10 may contain a single-crystalline semiconductor material or a polycrystalline semiconductor material. In one embodiment, the entirety of the semiconductor material layer 10 may contain a single-crystalline semiconductor material, such as single-crystalline silicon. The semiconductor material of the semiconductor material layer 10 may have a doping of a first conductivity type, which may be a p-type or an n-type. The atomic concentration of dopants of the first conductivity type in the semiconductor material layer 10 may be in a range of 1.0 × 10 14 / cm 3 up to 3.0 × 10 17 / cm 3 , although smaller and larger atomic concentrations may also be used. In one embodiment, the semiconductor material layer 10 may consist essentially of silicon and dopants of the first conductivity type.

[0008] Shallow trench isolation structures 12 can be formed in an upper portion of the semiconductor material layer 10. Shallow trenches can be formed, for example, with a depth in a range of 50 nm to 500 nm through the upper surface of the semiconductor material layer 10 by applying and patterning a photoresist layer over the upper surface of the semiconductor material layer 10 and by transferring the pattern in the photoresist layer into the upper portion of the semiconductor material layer 10 using an anisotropic etching process. The photoresist layer can then be removed, for example, by ashing. A dielectric material can be applied in the shallow trenches, and excess portions of the dielectric can be removed from above the horizontal plane containing the upper surface of the semiconductor material layer 10 using a planarization process, such as a chemical mechanical polishing (CMP) process.The remaining portions of the dielectric material filling the shallow trenches comprise the shallow trench isolation structures 12. The shallow trench isolation structures 12 may laterally surround device regions, one of which is shown in . Fig. 1A and Fig. 1B. In one embodiment, each device region may be laterally surrounded by a shallow trench isolation structure 12. While the present disclosure is explained using a single device region, it should be understood that multiple device regions may be laterally surrounded by a respective shallow trench isolation structure 12, which may be formed in the first example structure.

[0009] With reference to Fig. 2A and Fig. 2B, the upper surface of the semiconductor material layer 10 may be cleaned to remove contaminants. For example, RCA cleaning may be performed to remove organic contaminants, particles, surface oxides, and ionic contaminants from the upper surface of the semiconductor material layer 10. Wet etching or vapor etching using dilute hydrofluoric acid or hydrofluoric acid vapor may be performed to provide an oxide-free surface as the upper surface of the semiconductor material layer 10. Normal exposure to air for a duration of more than 10 minutes generally forms a native oxide layer, which is a surface oxide of the semiconductor material of the semiconductor material layer 10. For example, if the semiconductor material layer 10 includes single-crystalline silicon, a surface silicon oxide layer may be formed on the upper surface of the semiconductor material layer 10.The surface silicon oxide layer is referred to herein as an interfacial silicon oxide layer 51 and has an effective thickness in a range of 0.1 nm to 0.8 nm. As used herein, the effective thickness of a material layer is the sum of all volumes of the material layer divided by the area of ​​the material layer. The effective thickness of the interfacial silicon oxide layer 51 may be less than the thickness of a monolayer of silicon oxide (which is about 0.3 nm). In this case, the interfacial silicon oxide layer 51 may be formed as multiple discrete sections or as a continuous layer with multiple holes therethrough. Alternatively, the effective thickness of the interfacial silicon oxide layer 51 may be greater than the thickness of a monolayer of silicon oxide. In this case, the interfacial silicon oxide layer 51 may be formed as a continuous material layer without a hole therethrough.

[0010] The thickness of the interfacial silicon oxide layer 51 generally increases with the length of exposure to air. If the oxygen content in the ambient air is higher than normal or if the ambient temperature is above room temperature (i.e., 20 degrees Celsius), the thickness of the interfacial silicon oxide layer 51 may increase. The thickness of the interfacial silicon oxide layer 51 tends to saturate after long exposure to air.

[0011] A metal oxide dielectric layer can be formed directly on the interfacial silicon oxide layer 51 by directly depositing a metal oxide dielectric material or by depositing a metal and subsequently oxidizing the metal. Depositing the metal oxide dielectric material can be performed by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process (i.e., a sputtering process). Depositing a metal can be performed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD), or an atomic layer deposition (ALD) process. Oxidation of the metal can be performed by a plasma oxidation process or a thermal oxidation process at an elevated temperature, which can range from 300 degrees Celsius to 600 degrees Celsius.

[0012] According to one embodiment of the present disclosure, the metal oxide dielectric layer includes a metal oxide dielectric material that can shift the band structure of a ferroelectric material to be subsequently deposited thereon. As such, the metal oxide dielectric material includes a material that is different from the ferroelectric material to be subsequently deposited. A ferroelectric material generally includes a charge-trapping band, which is an energy band between the valence band and the conduction band of the ferroelectric material. The charge-trapping band may be caused by interfacial charge traps inherent in the ferroelectric material.The dielectric material of the metal oxide dielectric layer may be selected to shift the charge-trapping band of the ferroelectric material that may subsequently be formed and to misalign the charge-trapping band of the ferroelectric material with the minority carrier electronic band of the semiconductor material of the semiconductor material layer 10. As such, the metal oxide dielectric layer is referred to herein as a charge-trapping band misalignment layer 52.

[0013] The charge trapping band misalignment layer 52 may be formed directly on the interfacial silicon oxide layer 51. In one embodiment, the dielectric metal oxide may comprise and / or consist essentially of an oxide material comprising at least one elemental metal selected from Be, Mg, Ca, Sr, Ba, Al, Ga, Sc, Y, Ti, V, Cr, Mn, Zr, Nb, Mo, Ta, W, and lanthanide elements. Other suitable materials may be within the contemplated scope of the disclosure. In one embodiment, the dielectric material may comprise and / or consist essentially of an oxide material comprising a single elemental metal selected from Be, Mg, Ca, Sr, Ba, Al, Ga, Sc, Y, Ti, V, Cr, Mn, Zr, Nb, Mo, Ta, W, and lanthanide elements.In one embodiment, the dielectric metal oxide may comprise and / or consist essentially of an oxide material selected from Be, Mg, Ca, Sr, Ba, Al, Ga, Sc, Y, Ti, V, Cr, Mn, Zr, Nb, Mo, Ta, W, and lattice elements. The charge-trapping band misalignment layer 52 may have an effective thickness in a range of 0.1 nm to 0.5 nm. The dielectric material of the charge-trapping band misalignment layer 52 induces shifting of the charge-trapping band of the ferroelectric material to be subsequently formed relative to a band structure of the semiconductor material upon application of an external electric field.

[0014] A ferroelectric dielectric material may subsequently be deposited directly on the charge trapping band misalignment layer 52 to form a ferroelectric material layer used as a component layer of a gate dielectric of a field-effect transistor. As such, the deposited ferroelectric material layer is referred to herein as a ferroelectric gate dielectric layer 53. The ferroelectric dielectric material of the ferroelectric dielectric layer 53 may be Pb(Zr x Ti 1-x )O3, where x is a range from 0 to 1 (i.e. lead zirconate titanate (PZT)), PbZrO3 (PZ), PbTiO3 (PT), HfO2 (i.e. hafnium oxide), ZrO2 (i.e. zirconium oxide)), Hf x Zr 1-xO2, where x is between 0 and 1 (i.e., hafnium zirconium oxide), NH4H2PO4 (ADP), KH2PO4 (KDP), LiNbO3 (LN), LiTaO3 (LT), BaTiO3 (BT), (Pb,La)TiO3 (PLT), and (Pb,La)(Zr,Ti)O3, and doped variants thereof, may be selected, but are not limited to these. Other suitable materials may be within the contemplated scope of the disclosure. The ferroelectric dielectric gate layer 53 may be deposited, for example, by a physical vapor deposition (PVF) process from a sputtering target. The thickness of the ferroelectric dielectric gate layer 53 may range from 3 nm to 20 nm, such as from 4.5 nm to 10 nm, although smaller or larger thicknesses may also be used.The ferroelectric dielectric gate layer 53 may be thick enough to avoid dielectric breakdown during operation of a field effect transistor and may be thin enough to apply a sufficiently strong electric field to a semiconductor channel formed on the surface of the semiconductor material layer 10.

[0015] The ferroelectric dielectric gate layer 53 may have a charge-trapping band containing electronic states created by interfacial trapping of the ferroelectric dielectric material. The dielectric material of the charge-trapping band misalignment layer 52 shifts a band structure of the ferroelectric dielectric material of the ferroelectric dielectric gate layer 53. Accordingly, the charge-trapping band of the ferroelectric dielectric material may be shifted by the dielectric material of the charge-trapping band misalignment layer 52 relative to a comparative example structure in which the charge-trapping band misalignment layer 52 is omitted.The charge trapping band of the ferroelectric dielectric material of the ferroelectric dielectric gate layer 53 can be shifted from the minority charge carrier electronic band of the semiconductor material of the semiconductor material layer 10 along a direction that increases the energy separation between the Fermi level in the semiconductor material layer 10 and the charge trapping band of the ferroelectric dielectric material of the ferroelectric dielectric gate layer 53 during operation of a field effect transistor.

[0016] A gate electrode material layer 54L may then be deposited over the ferroelectric dielectric gate layer 53. The gate electrode material layer 54L may include at least one conductive material. The gate electrode material layer 54L may include, for example, a metal, an intermetallic alloy, a metal semiconductor alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and / or a doped semiconductor material containing p-type or n-type dopants with an average atomic concentration in a range of 5.0 × 10 19 / cm 3 up to 2.0 × 10 21 / cm 3The gate electrode material layer 54L may be comprised of a single conductive material or a stack of multiple conductive materials. The bottommost material in the gate electrode material layer 54L may be selected to provide a suitable work function for the gate electrodes to be subsequently formed by patterning the gate electrode material layer 54L. The gate electrode material layer 54L may be formed by chemical vapor deposition, physical vapor deposition, vacuum evaporation, and / or atomic layer deposition. The thickness of the gate electrode material layer 54L may range from 50 nm to 300 nm, although smaller and larger thicknesses may also be used.

[0017] A gate cap dielectric layer 58L may be formed over the gate electrode material layer 54L. The gate cap dielectric layer 58L includes a diffusion barrier material, such as silicon nitride. Other suitable materials are within the contemplated scope of the disclosure. The thickness of the gate cap dielectric layer 58L may range from 20 nm to 60 nm, although smaller and larger thicknesses may also be used.

[0018] With reference to Fig. 3A and 3B, a photoresist layer (not shown) may be applied over the gate electrode material layer 54L and lithographically patterned to form line structures extending across respective ones of the device regions. An anisotropic etch process (such as a reactive ion etch process) may be performed to transfer the pattern in the photoresist layer through the layer stack of the gate cap dielectric layer 58L, the gate electrode material layer 54L, the ferroelectric gate dielectric layer 53, the charge-trapping band misalignment layer 52, and the interfacial silicon oxide layer 51. The semiconductor material layer 10 and the shallow trench isolation structures 12 may be used as etch stop structures.

[0019] Remaining portions of the layer stack of gate cap dielectric layer 58L, gate electrode material layer 54L, ferroelectric gate dielectric layer 53, charge-trapping band misalignment layer 52, and interfacial silicon oxide layer 51 comprise gate stack structures (51, 52, 53, 54, 58). Each gate stack structure (51, 52, 53, 54, 58) may include, from bottom to top, an interfacial silicon oxide layer 51, a charge-trapping band misalignment layer 52, a ferroelectric gate dielectric layer 53, a gate electrode 54, and a gate cap dielectric 58. The interface silicon oxide layer 51 in each gate stack structure (51, 52, 53, 53, 58) may be a patterned portion of the interface silicon oxide layer 51 as formed in the processing steps in Fig. 2A and Fig. 2B. The charge trapping band misalignment layer 52 in each gate stack structure (51, 52, 53, 54, 58) may be a patterned portion of the charge trapping band misalignment layer 52 as formed in the processing steps in Fig. 2A and Fig. 2B. The ferroelectric dielectric gate layer 53 in each gate stack structure (51, 52, 53, 54, 48) may be a patterned portion of the ferroelectric dielectric gate layer 53 as formed in the processing steps in Fig. 2A and Fig. 2B. The gate electrode 54 in each gate stack structure (51, 52, 53, 54, 58) may be a patterned portion of the gate electrode material layer 54L, as formed in the processing steps in Fig. 2A and Fig. 2B. The dielectric gate cap 58 in each gate stack structure (51, 52, 53, 54, 58) may be a patterned portion of the dielectric gate cap layer 58L as formed in the processing steps in Fig. 2A and Fig. 2B is formed.

[0020] The sidewalls of each gate stack structure (51, 52, 53, 54, 58) may vertically coincide with sidewalls of the patterned photoresist layer. In other words, the sidewalls of each gate stack structure (51, 52, 53, 54, 58) may be located within the same vertical planes as the sidewalls of a respective overlying, patterned portion of the photoresist layer. In one embodiment, the sidewalls of the interfacial silicon oxide layer 51, the sidewalls of the charge-trapping band misalignment layer 52, the sidewalls of the ferroelectric dielectric gate layer 53, and the sidewalls of the gate electrode 54 in each gate stack structure (51, 52, 53, 54, 58) may vertically coincide with one another. The photoresist layer may then be removed, for example, by ashing.

[0021] With reference to Fig. 4A and Fig. 4B, an extension ion implantation process may be performed to implant dopants of a second conductivity type into unmasked surface portions of the semiconductor material layer 10. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The implanted surface portions of the semiconductor material layer 10 may be converted into doped semiconductor regions with a doping of the second conductivity type. A source extension region 32E and a drain extension region 38E may be formed in each device region for forming a field-effect transistor by converting the surface portions of the semiconductor material layer 10 into doped semiconductor material portions with a doping of the second conductivity type.The average atomic concentration of dopants of the second conductivity type in the source extension regions 32E and the drain extension regions 38E can be in a range of 1.0 × 10. 19 / cm 3 up to 1.0 × 10 21 / cm 3, although smaller and larger dopant concentrations may also be used. The depth of the source extension regions 32E and the drain extension regions 38E may be in a range of 10 nm to 100 nm, although smaller and larger depths may also be used. Each surface portion of the semiconductor material layer 10 underlying a gate stack structure (51, 52, 53, 54, 58) and located between an adjacent pair of a source extension region 32E and a drain extension region 38E may include a semiconductor channel 35. Each semiconductor channel 35 extends between a source extension region 32E and a drain extension region 38E and may include a dopant of the first conductivity type. Optionally, a halo implantation can be performed to implant dopants of the first conductivity type into regions underlying the gate stack structures (51, 52, 53, 54, 58).

[0022] At least one dielectric material, such as silicon nitride and / or silicon oxide, may be conformally deposited over the gate stack structures (51, 52, 53, 54, 58), the source extension regions 32E, the drain extension regions 38E, and the shallow trench isolation structures 12. The at least one dielectric material may be anisotropically etched (e.g., by a reactive ion etching process) to remove horizontal portions. Each remaining vertical portion laterally surrounding a respective gate stack structure (51, 52, 53, 54, 58) includes a gate spacer 56 containing the at least one dielectric material.Although only a single gate spacer 56 is illustrated for a gate stack structure (51, 52, 53, 54, 58), embodiments are also expressly contemplated herein in which multiple gate spacers are formed on a gate stack structure (51, 52, 53, 54, 58) by sequentially depositing and anisotropic etching multiple dielectric materials. In one embodiment, a gate spacer 56 may laterally surround a gate stack structure (51, 52, 53, 54, 58) and be topologically homeomorphic to a torus, i.e., it may be continuously deformed into a torus without forming a new opening or destroying an existing opening. The width of each gate spacer 56 at the base portion (i.e., the lateral distance between an inner sidewall and an outer sidewall) may range from 20 nm to 100 nm, although smaller and larger widths may also be used.

[0023] With reference to Fig. 5A and Fig. 5B, dopants of the second conductivity type may be implanted into unmasked portions of the source extension regions 32E, the drain extension regions 38E, and underlying regions of the semiconductor material layer 10. Implanted portions of the source extension regions 32E, the drain extension regions 38E, and the semiconductor material layer 10 form deep source regions 32D and deep drain regions 38D. The average atomic concentration of dopants of the second conductivity type in the deep source regions 32D and the deep drain regions 38D may be in a range of 5.0 × 10 19 / cm 3 up to 2.0 × 10 21 / cm 3, although smaller and larger dopant concentrations may also be used. The average atomic concentration of dopants of the second conductivity type in the deep source regions 32D and the deep drain regions 38D is higher than the average atomic concentration of dopants of the second conductivity type in the remaining portions of the source extension regions 32E and the drain extension regions 38E. The depth of the deep source regions 32D and the deep drain regions 38D may be in a range of 40 nm to 300 nm, although smaller and larger depths may also be used. The depth of the deep source regions 32D and the deep drain regions 38D may be greater than the depth of the remaining portions of the source extension regions 32E and the drain extension regions 38E. A deep source region 32D and a deep drain region 38D may be formed within each device region.Each combination of a source extension region 32E and a deep source region 32D forms a source region 32. Each combination of a drain extension region 38E and a deep drain region 38D forms a drain region 38. Generally, a source region 32 and a drain region 38 can be formed in the semiconductor material of the semiconductor material layer 10 within each device region, which is laterally surrounded by a shallow trench isolation structure 12. A semiconductor channel 35 extends between the source region 32 and the drain region 38 under a layer stack of a gate stack structure (51, 52, 53, 54, 58).

[0024] With reference to Fig. 6A and Fig. 6B, a dielectric material may be deposited over the gate stack structures (51, 52, 53, 54, 58), the source regions 32, the drain regions 38, and the shallow trench isolation structures 12. The dielectric material may include a planarizable dielectric material, such as undoped silicate glass or a doped silicate glass, or a self-planarizing dielectric material, such as flowable oxide (FOX). The dielectric material may be deposited by a chemical vapor deposition process (such as a plasma-enhanced chemical vapor deposition process) or by spin coating. The top surface of the dielectric material may be planarized during or after the deposition process. A dielectric material layer is formed with a planar (i.e., horizontal) top surface, through which contact over structures will later be formed.As such, the dielectric material layer is referred to herein as a contact level dielectric layer 70. The top surface of the contact level dielectric layer 70 may be planar and located above the top surface of the dielectric gate cap 58. The vertical distance between the top surface of the contact level dielectric layer 70 and the top surfaces of the dielectric gate caps 58 may range from 30 nm to 400 nm, although smaller and larger thicknesses may also be used.

[0025] A photoresist layer (not shown) may be applied over the dielectric layer at contact level 70 and may be lithographically patterned to form discrete openings therethrough. The openings in the photoresist layer may be formed over the source regions 32, the drain regions 38, and the gate electrodes 54. An anisotropic etch process may be performed to form via cavities (72, 75, 78) through the dielectric layer at contact level 70.The via cavities (72, 75, 78) include source via cavities 72 extending from the top surface of the contact level dielectric layer 70 to a top surface of a respective one of the source regions 32, drain via cavities 78 extending from the top surface of the contact level dielectric layer 70 to a top surface of a respective one of the drain regions 38, and gate via cavities 75 extending from the top surface of the contact level dielectric layer 70 to a top surface of a respective one of the gate electrodes 54.

[0026] With reference to Fig. 7A and Fig. 7B, a metal capable of forming a metal semiconductor alloy may be deposited into the via cavities (72, 75, 78) via a conformal or non-conformal deposition process. If the semiconductor material layer 10 comprises and / or consists essentially of doped silicon, the metal may be a material capable of forming a metal silicide. The metal may, for example, comprise nickel, titanium, tungsten, molybdenum, platinum, or another metal capable of forming a metal silicide. An annealing process at an elevated temperature may be performed to induce formation of a metal silicide material. The elevated temperature may range from 500 degrees Celsius to 750 degrees Celsius. Unreacted portions of the metal may be removed by a wet etching process that etches the metal selectively to the metal silicide material.Remaining portions of the metal silicide material include source-side metal semiconductor alloy regions 42 contacting a respective source region 32, drain-side metal semiconductor alloy regions 48 contacting a respective drain region 38, and gate-side metal semiconductor alloy regions 45 contacting a respective gate electrode 54 (if the topmost material of the gate electrodes 54 includes silicon prior to the annealing process).

[0027] A metallic liner comprising diffusion barrier material may be applied to peripheral portions of the remaining volumes of the via cavities (72, 75, 78). The metallic liner contains a conductive metallic nitride material (such as TiN, TaN, or WN) and / or a metallic carbide material (such as TiC, TaC, or WC). The thickness of the metallic liner may range from 3 nm to 15 nm, although smaller and larger thicknesses may also be used.

[0028] A metallic fill material, such as Cu, W, Mo, Co, Ru, and / or another elemental metal, or an intermetallic alloy may be deposited in remaining volumes of the via cavities (72, 75, 78). Portions of the metallic fill material and metallic liner located above the horizontal plane, including the top surface of the dielectric layer at contact level 70, may be removed by a planarization process. Each combination of a remaining portion of the metallic fill material and metallic liner filling a respective one of the via cavities (72, 75, 78) forms a via structure (82, 88, 85).The via structures (82, 88, 85) include source via structures 82 contacting a respective source-side metal semiconductor alloy region 42, drain via structures 88 contacting a respective drain-side metal semiconductor alloy region 48, and gate via structures 85 contacting a respective gate-side metal semiconductor alloy region 45 or a respective gate electrode 54 (if no gate-side metal semiconductor alloy regions 45 are formed). Each source via structure 82 includes a source-side metallic liner 82L and a source-side metallic fill material portion 82F. Each drain via structure 88 includes a drain-side metallic liner 88L and a drain-side metallic fill material portion 88F.Each gate via structure 85 includes a gate-side metallic liner 85L and a gate-side metallic fill material portion 85F. The first exemplary structure includes a ferroelectric field-effect transistor including a charge-trapping band misalignment layer 52 as a component of a gate dielectric (51, 52, 53).

[0029] In one embodiment, the ferroelectric field effect transistor can be Fig. 7A and Fig. 7B to form a ferroelectric memory device. In the first exemplary structure, additional devices, such as field-effect transistors for a gate bias circuit and a sensing circuit, may be formed simultaneously with the formation of the field-effect transistor shown in Fig. 2A to 7B. Interconnect level dielectric material layers and metal interconnect structures may be formed over the contact level dielectric layer 70 to provide electrical connections between the various nodes of the Fig. 7A and Fig. 7B, the gate bias circuit and the sampling circuit. Fig. Figure 7C illustrates a circuit diagram of a ferroelectric memory device incorporating the first exemplary structure of the Fig. 7A and Fig. 7B. The ferroelectric field-effect transistor contains a surface portion of the semiconductor material of the semiconductor material layer 10 as a semiconductor channel 35.

[0030] A ferroelectric memory device according to an embodiment of the present disclosure includes the Fig. 7A and Fig. 7B, a gate bias circuit 120 configured to provide an on-state and an off-state for the ferroelectric field-effect transistor by applying an on-voltage and an off-voltage, respectively, and a sensing circuit 140 configured to measure a direction of electrical polarization in the ferroelectric dielectric gate layer 53 by measuring a magnitude of the electrical current between the source region 32 and the drain region 38 while a gate sensing voltage is applied to the gate electrode 54. In general, the gate electrode 54 may be located on the ferroelectric dielectric gate layer 53 and may be configured to provide an on-state and an off-state for the ferroelectric field-effect transistor by applying an on-voltage and an off-voltage, respectively, from the gate bias circuit 120.In an illustrative example, the on-voltage may have a magnitude in a range of 0.5 V to 5 V and the off-voltage may have a magnitude in a range of 0 V to 0.3 V.

[0031] The ferroelectric material of the ferroelectric dielectric gate layer 53 may have a charge-trapping band containing electronic states generated by interfacial trapping of the ferroelectric material. The charge-trapping band misalignment layer 52 contains a dielectric material that induces a shift in the charge-trapping band of the ferroelectric material relative to a band structure of the semiconductor material of the semiconductor material layer 10 that is present in the absence of an external electric field and upon application of an external electric field.

[0032] With reference to Fig. 8A, Fig. 8B, Fig. 9A and Fig. Figure 9B shows band diagrams for two material stacks under two different electrical bias conditions. Fig. 8A is a band diagram of a material stack including the semiconductor channel 35 and the gate stack structure (51, 52, 53, 54, 58) without the dielectric gate cap 58 in the field effect transistor in the first exemplary structure in Fig. 7A and Fig. 7B when the voltage applied to the gate electrode 54 (relative to the semiconductor channel 35) is zero (ie, an off-voltage). Fig. Figure 8B is a band diagram of the material stack in Fig. 8A when the voltage applied to the gate electrode 54 is a positive voltage (ie, an on-voltage) that turns on the field effect transistor. Fig. 9A is a band diagram of a comparative exemplary material stack formed from the material stack in Fig. 8A by removing a charge-trapping band misalignment layer when the voltage applied to the gate electrode 54 is zero. In other words, the comparative exemplary material stack consists, from one side to the other, of a semiconductor channel 35, an interfacial silicon oxide layer 51, a ferroelectric dielectric gate layer 53, and a gate electrode 54. Fig. 9B is a band diagram of the comparative exemplary material stack in Fig. 9A, when the voltage applied to the gate electrode is a positive voltage (i.e., the on-voltage), which turns on the field-effect transistor. The on-voltage and the off-voltage can be provided, for example, by the gate bias circuit 120.

[0033] The various band diagrams illustrate the valence band 35V of the semiconductor channel 35, the conduction band 35C of the semiconductor channel 35, the valence band 51V of the interfacial silicon oxide layer 51, the conduction band 51C of the interfacial silicon oxide layer 51, the valence band 52V of the charge trapping band misalignment layer 52, the conduction band 52C of the charge trapping band misalignment layer 52, the valence band 53V of the ferroelectric dielectric gate layer 53, the conduction band 53C of the ferroelectric dielectric gate layer 53, the charge trapping band 53T of the ferroelectric dielectric gate layer 53, and the Fermi level 54F within the gate electrode 54 for each electrical bias condition for the combination of a semiconductor channel 35 and a gate stack of the first exemplary structure and for the combination of a semiconductor channel and the comparative exemplary material stack without a charge trapping band misalignment layer.

[0034] Fig. Figure 9B illustrates that the charge trapping band 53T of the ferroelectric dielectric gate layer 53 is at the same energy level as the Fermi level for the combination of the semiconductor channel and the comparative exemplary material stack without a charge trapping band misalignment layer when a ferroelectric field-effect transistor is turned on. In contrast, Figure 9B illustrates Fig. 8B shows that the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 is offset from the Fermi level for the combination of the semiconductor channel 35 and the gate stack structure (51, 52, 53, 54, 58) without the gate dielectric cap 58 of the present disclosure when the ferroelectric field-effect transistor of the first exemplary structure is turned on. Electron trapping in the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 during operation of the ferroelectric field-effect transistor of the first exemplary structure is avoided by offsetting the energy level of the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 from the Fermi level during the on-state of the ferroelectric field-effect transistor of the present disclosure.

[0035] The slope of the conduction band 52C and the valence band 52V of the charge-trapping misalignment layer 52 can be positive or negative depending on the magnitude of the internal electric field generated by the dipole moments of the charge-trapping misalignment layer material. In general, the charge-trapping misalignment layer 52 can include a metal oxide dielectric material having a dipole moment aligned with the direction of the external electric field generated by an applied voltage bias across the semiconductor channel 34 and the gate electrode 54. The dipole moment generates an internal electric field that is antiparallel to the external electric field. The magnitude of the internal electric field can be greater than or less than the magnitude of the external electric field.In one embodiment, the slope of the conduction band 52C and the valence band 52V of the charge trapping band misalignment layer 52 may be along the opposite direction of the slopes of various bands in adjacent material layers, as shown in FIG. Fig. 9B. The opposing slope of the energy bands (52C, 52V) within the charge-trapping band misalignment layer 52 may cause the energy level of the charge-trapping band 53T of the ferroelectric gate dielectric layer 53 to shift upward, away from the Fermi level, thereby providing a larger energy gap between electrons tunneling through the ferroelectric gate dielectric layer 53 and the energy level of the charge-trapping band 53T of the ferroelectric gate dielectric layer 53. In another embodiment, the slope of the conduction band 52C and the valence band 52V of the charge-trapping band misalignment layer 52 may be along the direction of the slopes of various bands in adjacent material layers. The presence of the charge-trapping band misalignment layer 52 may be smaller than the energy gap in the band structure of the comparative example structure shown in Fig. 9D, in which no charge trapping band misalignment layer is present, induce a larger energy gap between electrons tunneling through the ferroelectric gate dielectric layer 53 and the charge trapping band energy level 53T of the ferroelectric gate dielectric layer 53.

[0036] In general, the material of the charge-trapping band misalignment layer 52 can be selected such that the energy level of the charge-trapping band 53T is offset from the Fermi level during the on-state. The Fermi level can be closer to the minority carrier energy level of the semiconductor channel 35 during the on-state. The minority carrier energy level can be the valence band level if the minority carriers are holes, and the conduction band level if the minority carriers are electrons. In one embodiment, the material of the charge-trapping band misalignment layer 52 is selected such that the energy level of the charge-trapping band 53T is offset from the minority carrier energy level of the semiconductor channel 35 during the on-state.

[0037] With reference to Fig. 10A and Fig. 10B, a second exemplary structure according to a second embodiment of the present disclosure can be derived from the first exemplary structure shown in Fig. 2A and Fig. 2B, by modifying the composition of the semiconductor material layer 10 and by omitting the formation of the interfacial silicon oxide layer 51 and the charge trapping band misalignment layer 52. In the second exemplary structure, a semiconductor material layer 110 containing germanium may be used instead of the semiconductor material layer 10 of the first embodiment. In one embodiment, the semiconductor material layer 110 includes single-crystal germanium containing germanium atoms with an atomic concentration greater than 90% and / or greater than 95% and / or greater than 98% and / or greater than 99% and / or greater than 99.9% and / or greater than 99.99% and / or greater than 99.999%. The semiconductor material layer 110 may have a doping of the first conductivity type, which may be a p-type or an n-type.In one embodiment, the atomic concentration of dopants of the first conductivity type in the semiconductor material layer 110 is in a range of 1.0 × 10. 14 / cm 3 up to 3.0 × 10 17 / cm 3 , although smaller and larger atomic concentrations can also be used.

[0038] Thus, the semiconductor substrate 8 may include a doped germanium material portion with a doping of the first conductivity type. The doped germanium material portion may be a single-crystalline doped semiconductor material portion, as embodied in the semiconductor material layer 110. The semiconductor material layer 110 may be provided as a bulk germanium substrate (such as a germanium wafer) or may be provided as a top semiconductor layer overlying an insulating layer in a semiconductor-on-insulator (SOI) substrate. Alternatively, the semiconductor material layer 110 may be formed in a host substrate with a larger lateral dimension than the semiconductor material layer 100.In this case, the semiconductor material layer 110 may be attached to the host substrate by semiconductor-semiconductor bonding (for example, by a silicon-germanium alloy layer formed by annealing an interface region between the semiconductor material layer 110 and a silicon substrate) or by semiconductor-oxide bonding (for example, by a silicon oxide layer or a silicon-germanium oxide layer).

[0039] The shallow trench isolation structures 12 can be formed by performing the processing steps in Fig. 2A and Fig. 2B. In one embodiment, the silicon nitride liner (not shown) may be formed at the outer periphery of each shallow trench isolation structure 12 to avoid exposing the germanium material in the semiconductor material layer 110 to the silicon oxide material in the shallow trench isolation structures 12.

[0040] The upper surface of the semiconductor material layer 110 may be cleaned to remove contaminants. The final step of the cleaning process may include a cleaning step that removes any surface oxide materials from the upper surface of the semiconductor material layer 110. For example, an alkaline solution that dissolves germanium oxide may be used to remove surface germanium oxide from the upper surface of the semiconductor material layer 110, which is a doped germanium layer. The cleaned semiconductor substrate 8 may be placed in an inert environment, such as a transport capsule with nitrogen ambient gas, to minimize oxygen exposure and to prevent the formation of germanium oxide on the surface of the semiconductor material layer 110. The semiconductor substrate 8 may be loaded into a process chamber through a vacuum loadlock to prevent the formation of germanium oxide on the upper surface of the semiconductor material layer 110.

[0041] According to one embodiment of the present disclosure, a ferroelectric dielectric material may be deposited directly onto the top surface of the semiconductor material layer 110 (which may be a single-crystalline doped germanium layer) to form a ferroelectric material layer without an interfacial oxide layer between the semiconductor material layer 110 and the ferroelectric material layer. Exposure of the top surface of the semiconductor material layer 110 to an oxygen environment (such as air) may be avoided or minimized during transport of the second example structure from a surface cleaning tool to the process chamber for depositing the ferroelectric material layer.

[0042] The ferroelectric material layer can then be used as a component layer of a gate dielectric of a field-effect transistor. As such, the deposited ferroelectric material layer is referred to herein as a ferroelectric gate dielectric layer 53. The ferroelectric dielectric material of the ferroelectric gate dielectric layer 53 in the first exemplary structure can be any of the materials that can be used for the ferroelectric gate dielectric layer 53. The thickness of the ferroelectric gate dielectric layer 53 can be in the same range as in the first embodiment, for example, in a range of 3 nm to 20 nm.

[0043] The ferroelectric dielectric gate layer 53 may have a charge trapping band containing electronic states created by interfacial trapping of the ferroelectric dielectric material. Eliminating any interfacial oxide material at the interface between the semiconductor material layer 110 and the ferroelectric dielectric gate layer 53 has the effect of shifting the band structure of the ferroelectric dielectric material of the ferroelectric dielectric gate layer 53 relative to a comparative example structure in which an interfacial oxide layer is present at the interface between the semiconductor material layer 110 and the ferroelectric dielectric gate layer.The charge trapping band of the ferroelectric dielectric material of the ferroelectric dielectric gate layer 53 can be shifted from the minority charge carrier electronic band of the semiconductor material of the semiconductor material layer 10 along a direction that increases the energy separation between the Fermi level in the semiconductor material layer 10 and the charge trapping band of the ferroelectric dielectric material of the ferroelectric dielectric gate layer 53 during operation of a field effect transistor.

[0044] A gate electrode material layer 54L may then be deposited over the ferroelectric dielectric gate layer 53. The gate electrode material layer 54L may include at least one conductive material. The gate electrode material layer 54L may include, for example, a metal, an intermetallic alloy, a metal semiconductor alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and / or a doped semiconductor material containing p-type or n-type dopants with an average atomic concentration in a range of 5.0 × 10 19 / cm 3 up to 2.0 × 10 21 / cm 3The gate electrode material layer 54L may be comprised of a single conductive material or a stack of multiple conductive materials. The bottommost material in the gate electrode material layer 54L may be selected to provide a suitable work function for the gate electrodes to be subsequently formed by patterning the gate electrode material layer 54L. The gate electrode material layer 54L may be formed by chemical vapor deposition, physical vapor deposition, vacuum evaporation, and / or atomic layer deposition. The thickness of the gate electrode material layer 54L may range from 50 nm to 300 nm, although smaller and larger thicknesses may also be used.

[0045] A gate cap dielectric layer 58L may be formed over the gate electrode material layer 54L. The gate cap dielectric layer 58L includes a diffusion barrier material, such as silicon nitride. The thickness of the gate cap dielectric layer 58L may range from 20 nm to 60 nm, although smaller and larger thicknesses may also be used.

[0046] With reference to Fig. 11A and Fig. 11B, a photoresist layer (not shown) may be applied over the gate electrode material layer 54L and lithographically patterned to form line structures extending across respective ones of the device regions. An anisotropic etch process (such as a reactive ion etch process) may be performed to transfer the pattern in the photoresist layer through the layer stack of the gate cap dielectric layer 58L, the gate electrode material layer 54L, and the ferroelectric gate dielectric layer. The semiconductor material layer 110 and the shallow trench isolation structures 12 may be used as etch stop structures.

[0047] Remaining portions of the layer stack of the dielectric gate cap layer 58L, the gate electrode material layer 54L, and the ferroelectric dielectric gate layer 53 comprise gate stack structures (53, 54, 58). Each gate stack structure (53, 54, 58) may include, from bottom to top, a ferroelectric dielectric gate layer 53, a gate electrode 54, and a dielectric gate cap 58. The ferroelectric dielectric gate layer 53 in each gate stack structure (53, 54, 58) is a patterned portion of the ferroelectric dielectric gate layer 53, as in the processing steps in Fig. 10A and Fig. 10B. The gate electrode 54 in each gate stack structure (53, 54, 58) may be a patterned portion of the gate electrode material layer 54L, as in the processing steps in Fig. 10A and Fig. 10B. The dielectric gate cap 58 in each gate stack structure (53, 54, 58) may be a patterned portion of the dielectric gate cap layer 58L as formed in the processing steps in Fig. 10A and Fig. 10B were formed.

[0048] The sidewalls of each gate stack structure (53, 54, 58) may vertically coincide with sidewalls of the patterned photoresist layer. In other words, the sidewalls of each gate stack structure (53, 54, 58) may be located within the same vertical planes as the sidewalls of a respective overlying, patterned portion of the photoresist layer. In one embodiment, the sidewalls of the ferroelectric dielectric gate layer 53 and the sidewalls of the gate electrode 54 within each gate stack structure (53, 54, 58) may vertically coincide with each other. The photoresist layer may then be removed, for example, by ashing.

[0049] With reference to Fig. 12A and Fig. 12B, an extension ion implantation process may be performed to implant dopants of a second conductivity type into unmasked surface portions of the semiconductor material layer 110. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The implanted surface portions of the semiconductor material layer 110 are converted into doped semiconductor regions with a doping of the second conductivity type. A source extension region 132A and a drain extension region 138E may be formed in each device region for forming a field-effect transistor by converting the surface portions of the semiconductor material layers 110 into doped semiconductor material portions with a doping of the second conductivity type.The average atomic concentration of dopants of the second conductivity type in the source extension regions 132E and the drain extension regions 138E may be in a range of 1.0 × 10. 19 / cm 3 up to 1.0 × 10 21 / cm 3, although smaller and larger dopant concentrations may also be used. The depth of the source extension regions 132E and the drain extension regions 138E may be in a range of 10 nm to 100 nm, although smaller and larger depths may also be used. Each surface portion of the semiconductor material layer 110 underlying a gate stack structure (53, 54, 58) and located between an adjacent pair of a source extension region 132E and a drain extension region 138E comprises a semiconductor channel 135. Each semiconductor channel 135 extends between a source extension region 132E and a drain extension region 138E and comprises a dopant of the first conductivity type. In an alternative embodiment, a halo implantation may be performed to implant dopants of the first conductivity type into regions underlying the gate stack structures (53, 54, 58).

[0050] At least one dielectric material, such as silicon nitride and / or silicon oxide, may be conformally deposited over the gate stack structures (53, 54, 58), the source extension regions 132E, the drain extension regions 138E, and the shallow trench isolation structures 12. The at least one dielectric material may be anisotropically etched (e.g., by a reactive ion etching process) to remove horizontal portions. Each remaining vertical portion laterally surrounding a respective gate stack structure (53, 54, 58) includes a gate spacer 56 containing the at least one dielectric material.Although only a single gate spacer 56 is illustrated for a gate stack structure (53, 54, 58), embodiments are also expressly contemplated herein in which multiple gate spacers are formed on a gate stack structure (53, 54, 58) by sequentially depositing and anisotropic etching multiple dielectric materials. In one embodiment, a gate spacer 56 may laterally surround a gate stack structure (53, 54, 58) and may be topologically homeomorphic to a torus. The width of each gate spacer 56 at the base portion (i.e., the lateral distance between an inner sidewall and an outer sidewall) may range from 20 nm to 100 nm, although smaller and larger widths may also be used.

[0051] With reference to Fig. 13A and Fig. 13B, dopants of the second conductivity type may be implanted into unmasked portions of the source extension regions 132E, the drain extension regions 138E, and underlying regions of the semiconductor material layer 110. Implanted portions of the source extension regions 132E, the drain extension regions 138E, and the semiconductor material layer 110 form deep source regions 132D and deep drain regions 138D. The average atomic concentration of dopants of the second conductivity type in the deep source regions 132D and the deep drain regions 138D may be in a range of 5.0 × 10 19 / cm 3 up to 2.0 × 10 21 / cm 3, although smaller and larger dopant concentrations may also be used. The average atomic concentration of dopants of the second conductivity type in the deep source regions 132D and the deep drain regions 138D is higher than the average atomic concentration of dopants of the second conductivity type in the remaining portions of the source extension regions 132E and the drain extension regions 138E. The depth of the deep source regions 132D and the deep drain regions 138D may range from 40 nm to 300 nm, although smaller and larger depths may also be used. The depth of the deep source regions 132D and the deep drain regions 138D may be greater than the depth of the remaining portions of the source extension regions 132E and the drain extension regions 138E.A deep source region 132D and a deep drain region 138D can be formed within each device region. Any combination of a source extension region 132E and a deep source region 132D forms a source region 132. Any combination of a drain extension region 138E and a deep drain region 138D forms a drain region 138. Generally, a source region 132 and a drain region 138 can be formed in the semiconductor material of the semiconductor material layer 110 within each device region, which is laterally surrounded by a shallow trench isolation structure 12. A semiconductor channel 135 extends between the source region 132 and the drain region 138 under a layer stack of a gate stack structure (53, 54, 58).

[0052] With reference to Fig. 14A and Fig. 14B, raised source regions 34 and raised drain regions 36 may be grown from the physically exposed areas of source regions 32 and drain regions 38. In general, germanium is prone to pitting during a wet cleaning process and is prone to the formation of germanium oxide, which is a water-soluble material. Thus, avoiding direct exposure of germanium to a wet etchant or an oxide material is advantageous for the purpose of preserving device properties for a germanium-containing device. In one embodiment, a selective epitaxial process may be performed to grow a silicon-germanium alloy from each physically exposed semiconductor area. A selective epitaxial process is a semiconductor deposition method in which a semiconductor precursor and an etching gas are simultaneously or alternately flowed into a process chamber.Semiconductor surfaces provide a shorter incubation time than dielectric surfaces, and deposition rates of semiconductor material on semiconductor surfaces are higher than deposition rates of semiconductor material on insulating surfaces. The etching gas flow rate is selected such that net deposition of semiconductor material occurs on semiconductor surfaces and net deposition of semiconductor material does not occur on insulating surfaces in the selective epitaxy process.

[0053] Each raised source region 34 may be formed on the top surface of a respective source region 132, and each raised drain region 36 may be formed on the top surface of a respective drain region 138. The raised source regions 34 and the raised drain regions 36 may include a silicon-germanium alloy doped with the second conductivity type. The atomic concentration of silicon in the silicon-germanium alloy may be uniform, or it may decrease with distance from the source regions 132 and the drain regions 138. The average atomic fraction of silicon in the silicon-germanium alloy of the raised source regions 34 and the raised drain regions 36 may range from 25% to 95%. The atomic fraction of silicon atoms at the topmost portions of the raised source regions 34 and the raised drain regions 36 may range from 70% to 99.9%.The second conductivity type dopants in the raised source regions 34 and the raised drain regions 36 can be provided in-situ during the selective epitaxial growth process, or they can be provided by an ion implantation process after deposition of an undoped silicon-germanium alloy material. The atomic concentration of the second conductivity type dopants in the raised source regions 34 and the raised drain regions 36 can be in a range of 5.0 x 10 19 / cm 3 up to 2.0 x 10 21 / cm 3 although smaller or larger atomic concentrations can also be used.

[0054] With reference to Fig. 15A and Fig. 15B, a dielectric material may be deposited over the gate stack structures (58, 54, 58), the raised source regions 34, the drain regions 36, and the shallow trench isolation structures 12. The dielectric material may include a planarizable dielectric material, such as undoped silicate glass or a doped silicate glass, or a self-planarizing dielectric material, such as flowable oxide (FOX). The dielectric material may be deposited by a chemical vapor deposition process (such as a plasma-enhanced chemical vapor deposition process) or by spin coating. The top surface of the dielectric material may be planarized during or after the deposition process. A dielectric material layer having a planar (i.e., horizontal) top surface is formed, through which via structures will later be formed.As such, the dielectric material layer is referred to herein as a contact-level dielectric layer 70. The top surface of the contact-level dielectric layer 70 may be planar and located above the top surface of the dielectric gate cap 58. The vertical distance between the top surface of the contact-level dielectric layer 70 and the top surfaces of the dielectric gate caps 58 may range from 30 nm to 400 nm, although smaller and larger thicknesses may also be used.

[0055] A photoresist layer (not shown) may be applied over the dielectric layer at contact level 70 and may be lithographically patterned to form discrete openings therethrough. The openings in the photoresist layer may be formed over the raised source regions 34, the raised drain regions 36, and the gate electrodes 54. An anisotropic etch process may be performed to form via cavities (72, 75, 78) through the dielectric layer at contact level 70.The via cavities (72, 75, 78) include source via cavities 72 extending from the top surface of the contact level dielectric layer 70 to a top surface of a respective one of the raised source regions 34, drain via cavities 78 extending from the top surface of the contact level dielectric layer 70 to a top surface of a respective one of the raised drain regions 36, and gate via cavities 75 extending from the top surface of the contact level dielectric layer 70 to a top surface of a respective one of the gate electrodes 54.

[0056] With reference to Fig. 16A and Fig. 16B, a metal capable of forming a metal-semiconductor alloy may be deposited into the via cavities (72, 75, 78) via a conformal or non-conformal deposition process. When the raised source regions 34 and the raised drain regions 36 comprise and / or consist essentially of a doped silicon-germanium alloy, the metal may be a material capable of forming a metal-germanium silicide. The metal may, for example, comprise nickel, titanium, tungsten, molybdenum, platinum, or another metal capable of forming a metal-germanium silicide. Other suitable materials are within the contemplated scope of the disclosure.An elevated temperature annealing process may be performed to induce formation of a metal germanium silicide material over the raised source regions 34 and the raised drain regions 36, and to induce formation of a metal silicide material over the gate electrodes 54 (if the topmost gate electrode material includes silicon). The elevated temperature may range from 500 degrees Celsius to 750 degrees Celsius. Unreacted portions of the metal may be removed by a wet etching process that etches the metal selectively to the metal silicide material.Remaining portions of the metal germanium silicide material include source-side metal semiconductor alloy regions 142 contacting a respective raised source region 34 or a respective source region 132, drain-side metal semiconductor alloy regions 148 contacting a respective raised drain region 36 or a respective drain region 138, and gate-side metal semiconductor alloy regions 145 contacting a respective gate electrode 54.

[0057] A metallic liner comprising diffusion barrier material may be applied to peripheral portions of the remaining volumes of the via cavities (72, 75, 78). The metallic liner contains a conductive metallic nitride material (such as TiN, TaN, or WN) and / or a metallic carbide material (such as TiC, TaC, or WC). The thickness of the metallic liner may range from 3 nm to 15 nm, although smaller and larger thicknesses may also be used.

[0058] A metallic fill material, such as Cu, W, Mo, Co, Ru, and / or another elemental metal, or an intermetallic alloy may be deposited in remaining volumes of the via cavities (72, 75, 78). Other suitable materials are within the contemplated scope of the disclosure. Portions of the metallic fill material and metallic liner located above the horizontal plane, including the top surface of the dielectric layer at contact level 70, may be removed by a planarization process. Any combination of a remaining portion of the metallic fill material and metallic liner filling a respective one of the via cavities (72, 75, 78) forms a via structure (82, 88, 85).The via structures (82, 88, 85) may include source via structures 82 contacting a respective source-side metal semiconductor alloy region 142, drain via structures 88 contacting a respective drain-side metal semiconductor alloy region 148, and gate via structures 85 contacting a respective gate-side metal semiconductor alloy region 145 or a respective gate electrode 54 (in the case that no gate-side metal semiconductor alloy regions 145 are formed). Each source via structure 82 includes a source-side metallic liner 82L and a source-side metallic fill material portion 82F. Each drain via structure 88 includes a drain-side metallic liner 88L and a drain-side metallic fill material portion 88F.Each gate via structure 85 includes a gate-side metallic liner 85L and a gate-side metallic fill material portion 85F.

[0059] In the second exemplary structure, the semiconductor channel 135 comprises doped germanium, which includes germanium atoms with an atomic concentration of more than 99% and contains dopants of the first conductivity type with an atomic concentration of less than 1%. The ferroelectric dielectric gate layer 53 is formed directly on a top surface of the doped germanium material portion without an interface material layer between the doped germanium material portion and the ferroelectric dielectric gate layer 53. Thus, the ferroelectric dielectric gate layer 53 is in direct contact with a surface of the semiconductor channel 135 without an interface material layer therebetween.

[0060] In one embodiment, the ferroelectric field effect transistor can be Fig. 16A and Fig. 16B to form a ferroelectric memory device. In the first exemplary structure, additional devices, such as field-effect transistors for a gate bias circuit and a sensing circuit, may be formed simultaneously with the formation of the field-effect transistor shown in Fig. 10A to 16B. Interconnect level dielectric material layers and metal interconnect structures may be formed over the contact level dielectric layer 70 to provide electrical connections between the various nodes of the Fig. 16A and Fig. 16B, the gate bias circuit, and the sampling circuit. Fig. 16C illustrates a circuit diagram of a ferroelectric memory device incorporating the second exemplary structure of the Fig. 16A and Fig. 16B. The ferroelectric field-effect transistor includes a surface portion of the semiconductor material of the semiconductor material layer 110 as a semiconductor channel 135.

[0061] A ferroelectric memory device according to an embodiment of the present invention includes the Fig. 16A and Fig. 16B, a gate bias circuit 120 configured to provide an on-state and an off-state for the ferroelectric field-effect transistor by applying an on-voltage and an off-voltage, respectively, and a sensing circuit 140 configured to measure a direction of electrical polarization in the ferroelectric dielectric gate layer 53 by measuring a magnitude of the electrical current between the source region 132 and the drain region 138 while a gate sensing voltage is applied to the gate electrode 54. In general, the gate electrode 54 may be located on the ferroelectric dielectric gate layer 53 and may be configured to provide an on-state and an off-state for the ferroelectric field-effect transistor by applying an on-voltage and an off-voltage, respectively, from the gate bias circuit 120.In an illustrative example, the on-voltage may have a magnitude in a range of 0.5 V to 5 V and the off-voltage may have a magnitude in a range of 0 V to 0.3 V.

[0062] The ferroelectric material of the ferroelectric dielectric gate layer 53 may have a charge-trapping band containing electronic states generated by interfacial trapping of the ferroelectric material. The level of the charge-trapping band of the ferroelectric material is shifted relative to a band structure of the semiconductor material of the semiconductor material layer 110 present in the absence of an interfacial material layer between the semiconductor material layer 110 and the ferroelectric dielectric gate layer 53, which band structure is present in the absence of an external electric field and when an external electric field is applied.

[0063] With reference to Fig. 17A, Fig. 17B, Fig. 18A and Fig. Figure 18B shows band diagrams for two material stacks under two different electrical bias conditions. Fig. 17A is a band diagram of a material stack including the semiconductor channel 135 and the gate stack structure (53, 54, 58) without the dielectric gate cap 58 in the field effect transistor in the second exemplary structure in Fig. 16A and Fig. 16B when the voltage applied to the gate electrode 54 (relative to the semiconductor channel 35) is zero (ie, an off-voltage). Fig. 17B is a band diagram of the material stack in Fig. 17A when the voltage applied to the gate electrode 54 is a positive voltage (ie, an on-voltage) that turns on the field effect transistor. Fig. 18A is a band diagram of a comparative exemplary material stack formed from the material stack in Fig. 17A by introducing an interfacial germanium oxide layer when the voltage applied to the gate electrode 54 is zero. In other words, the comparative exemplary material stack consists, from one side to the other, of a semiconductor channel 135, an interfacial germanium oxide layer, a ferroelectric dielectric gate layer 53, and a gate electrode 54. Fig. 18B is a band diagram of the comparative exemplary material stack in Fig. 18A when the voltage applied to the gate electrode is a positive voltage (i.e., the on-voltage), which turns on the field-effect transistor. The on-voltage and the off-voltage can be provided, for example, by the gate bias circuit 120.

[0064] The various band diagrams illustrate the valence band 135V of the semiconductor channel 135, the conduction band 135C of the semiconductor channel 135, the valence band 151V of the interfacial germanium oxide layer, the conduction band 151C of the interfacial germanium oxide layer 51, the valence band 53V of the ferroelectric dielectric gate layer 53, the conduction band 53C of the ferroelectric dielectric gate layer 53, the charge trapping band 53T of the ferroelectric dielectric layer 53, and the Fermi level 54F within the gate electrode 54 for each electrical bias condition for the combination of a semiconductor channel 135 and a gate stack of the second example structure and for the combination of a semiconductor channel and the comparative example material stack with an interfacial germanium oxide layer.

[0065] Fig. Figure 18B illustrates that the charge trapping band 53T of the ferroelectric dielectric gate layer 53 is at the same energy level as the Fermi level for the combination of the semiconductor channel and the comparative example material stack with an interfacial germanium oxide layer when a ferroelectric field-effect transistor is turned on. In contrast, Fig. 17B shows that the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 is offset from the Fermi level for the combination of the semiconductor channel 135 and the gate stack structure (53, 54, 58) without the gate dielectric cap 58 of the present disclosure when the ferroelectric field-effect transistor of the second exemplary structure is turned on. Electron trapping in the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 during operation of the ferroelectric field-effect transistor of the second exemplary structure is avoided by offsetting the energy level of the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 from the Fermi level during the on-state of the ferroelectric field-effect transistor of the present disclosure.

[0066] In general, the energy level of the charge-trapping band 53T is offset from the Fermi level during the on-state. The Fermi level may be closer to the minority carrier energy level of the semiconductor channel 135 during the on-state. The minority carrier energy level may be the valence band level if the minority carriers are holes, and the conduction band level if the minority carriers are electrons. In one embodiment, the energy level of the charge-trapping band 53T is offset from the minority carrier energy level of the semiconductor channel 35 during the on-state.

[0067] With reference to Fig. 19 illustrates a first flowchart of steps for forming the first exemplary structure of the present disclosure. In step 1910, a semiconductor substrate 8 comprising a semiconductor material doped with a first conductivity type is provided. In step 1920, a layer stack (51, 52, 53, 54, 58) is formed over the semiconductor substrate 8. The layer stack (51, 52, 53, 54, 58) includes, from bottom to top, a charge trapping band misalignment layer 52 comprising a metal oxide dielectric material, a ferroelectric gate dielectric layer 53 comprising a ferroelectric material, and a gate electrode. Referring to step 1930, a source region 32 and a drain region 38 are formed in the semiconductor material. A semiconductor channel 35 extends between the source region 32 and the drain region 38 under the layer stack (51, 52, 53, 54, 58).

[0068] With reference to Fig.20 illustrates a second flowchart of steps for forming the second exemplary structure of the present disclosure. In step 2010, a semiconductor substrate 8 is provided, comprising a doped germanium material portion with a doping of a first conductivity type. In step 2020, a ferroelectric dielectric layer 53 containing a ferroelectric material is formed over the doped germanium material. In step 2030, a gate electrode 54 is formed over the ferroelectric dielectric gate layer 53. In step 2040, a source region 132 and a drain region 138 are formed in the semiconductor substrate 8. A semiconductor channel 135, comprising the doped germanium material portion, extends between the source region 132 and the drain region 138 beneath the ferroelectric dielectric gate layer 53.

[0069] With reference to all the drawings and according to various embodiments of the present disclosure, a ferroelectric field effect transistor is provided, comprising: a semiconductor substrate 8 comprising a semiconductor channel (35 or 135) extending between a source region (32 or 132) and a drain region (38 or 138) and doped with a first conductivity type; a ferroelectric dielectric gate layer 53 located over the semiconductor channel (35 or 135) and containing a ferroelectric material with a charge trapping band 53T comprising electronic states generated by interfacial traps of the ferroelectric material; and a gate electrode 53 located on the ferroelectric dielectric gate layer 53 and configured to establish an on-state and an off-state for the ferroelectric field effect transistor by applying an on-voltage and an off-state, respectively.an off-voltage from a gate bias circuit 120, wherein an energy level of the charge trapping band during the on-state is offset from an energy level of an energy band of the minority charge carriers of the semiconductor channel (35 or 135).

[0070] In another embodiment, a method of forming a semiconductor structure is disclosed, the method comprising the acts of: providing a semiconductor substrate 8 comprising a semiconductor material 10 doped with a first conductivity type; forming a layer stack comprising, from bottom to top, a charge trapping band misalignment layer 52 comprising a metal oxide dielectric material, a ferroelectric gate dielectric layer 53 comprising a ferroelectric material, and a gate electrode 54 over the semiconductor substrate 8; and forming a source region 32 and a drain region 38 in the semiconductor material 10, wherein a semiconductor channel 35 extends between the source region 32 and the drain region 38 beneath the layer stack.

[0071] In another embodiment, a method of forming a semiconductor structure is disclosed, the method comprising the acts of: providing a semiconductor substrate 8 comprising a semiconductor material layer 110 (which may be a single-crystalline doped germanium layer with a doping of a first conductivity type); forming a ferroelectric dielectric gate layer 53 containing a ferroelectric material over the semiconductor material layer 110 (which may be a single-crystalline doped germanium layer with a doping of a first conductivity type); forming a gate electrode 54 over the ferroelectric dielectric gate layer;and forming a source region 132 and a drain region 138 in the semiconductor substrate 8, wherein a semiconductor channel 135 comprising the doped germanium material portion extends between the source region 132 and the drain region 138 under the ferroelectric dielectric gate layer 53;

[0072] The various embodiments of the present disclosure provide an energy level offset between the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 of a ferroelectric field-effect transistor and the Fermi level during operation of the ferroelectric field-effect transistor. Because charge carriers (such as electrons) must traverse energy levels different from the energy levels of the charge-trapping band 53T of the ferroelectric dielectric gate layer 53, charge trapping in the ferroelectric dielectric gate layer 53 can be avoided. Residual polarization of the ferroelectric dielectric gate layer 53 does not decrease during use of the ferroelectric field-effect transistor because charge trapping in the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 is avoided.Furthermore, the saturation polarization of the ferroelectric dielectric gate layer 53 does not decrease during use of the ferroelectric field-effect transistor because charge trapping in the charge-trapping band 53T of the ferroelectric dielectric gate layer 53 is avoided. Thus, the ferroelectric field-effect transistors of the present disclosure can provide a longer lifetime than prior art field-effect transistors that cause charge trapping in the charge-trapping band of a ferroelectric dielectric gate layer.

Claims

[1] Ferroelectric field-effect transistor, comprising: a semiconductor substrate (10) comprising a semiconductor channel (35) extending between a source region (32) and a drain region (38) and having a doping of a first conductivity type; a ferroelectric dielectric gate layer (53) disposed over the semiconductor channel (35) and containing a ferroelectric material having a charge trapping band (53T) containing electronic states generated by interfacial trapping of the ferroelectric material; and a gate electrode (54) disposed on the ferroelectric dielectric gate layer (53) and configured to provide an on-state and an off-state for the ferroelectric field-effect transistor by applying an on-voltage and an off-voltage, respectively, from a gate bias circuit (120), wherein an energy level (53T) of the charge trapping band during the on-state is offset from an energy level of an energy band (35V, 35C) of minority charge carriers of the semiconductor channel (35). [2] The ferroelectric field effect transistor of claim 1, further comprising a charge trapping band misalignment layer (52) disposed between the ferroelectric dielectric gate layer (53) and the semiconductor channel (35), and including a dielectric material that induces shifting of the charge trapping band (53T) of the ferroelectric material relative to a band structure of the semiconductor channel (35). [3] A ferroelectric field effect transistor according to claim 2, wherein the charge trapping band misalignment layer (52) comprises a dielectric metal oxide having an effective thickness in a range of 0.1 nm to 0.5 nm. [4] A ferroelectric field effect transistor according to claim 3, wherein the dielectric metal oxide comprises an oxide material of at least one elemental metal selected from Be, Mg, Ca, Sr, Ba, Al, Ga, Sc, Y, Ti, V, Cr, Mn, Zr, Nb, Mo, Ta, W and lanthanide elements. [5] Ferroelectric field effect transistor according to one of the preceding claims 2 to 4, wherein: the semiconductor channel (35) comprises silicon; and the ferroelectric field effect transistor comprises an interfacial silicon oxide layer disposed between the semiconductor channel (35) and the charge trapping band misalignment layer (52) and comprising silicon oxide and having an effective thickness in a range of 0.1 nm to 0.8 nm. [6] A ferroelectric field effect transistor according to claim 5, wherein sidewalls of the interface silicon oxide layer, sidewalls of the charge trapping band misalignment layer (52), sidewalls of the ferroelectric dielectric gate layer (53) and the sidewalls of the gate electrode (54) vertically coincide with each other. [7] A ferroelectric field effect transistor according to any preceding claim, wherein the semiconductor channel (35) comprises germanium and the ferroelectric dielectric gate layer (53) is in direct contact with a surface of the semiconductor channel (35) without an interface material layer therebetween. [8] A ferroelectric field effect transistor according to claim 7, wherein the semiconductor channel (35) comprises doped germanium containing germanium atoms in an atomic concentration of greater than 99% and containing dopants of the first conductivity type with an atomic concentration of less than 1%. [9] A ferroelectric field effect transistor according to any preceding claim, wherein the ferroelectric dielectric gate layer (53) comprises a material selected from the group consisting of Pb(Zr x Ti 1-x )O3, where x is in a range from 0 to 1, PbZrO3, PbTiO3, HfO2, ZrO2, Hf x Zr 1-x O2, where x is between 0 and 1, NH4H2PO4, KH2PO4, LiNbO3, LiTaO3, BaTiO3, (Pb,La)TiO3 and (Pb,La)(Zr,Ti)O3 doped variants thereof, and has a thickness in a range of 3 nm to 20 nm. [10] A ferroelectric field effect transistor according to any preceding claim, wherein the gate electrode (54) comprises at least one of a metal, an intermetallic alloy, a metal-semiconductor alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and a doped semiconductor material comprising p-type dopants or n-type dopants having an average atomic concentration in a range of 5.0 × 10 19 / cm 3 up to 2.0 × 10 21 / cm 3 contains. [11] Ferroelectric field effect transistor according to one of the preceding claims, wherein: the on-voltage has a magnitude in a range of 0.5 V to 5 V; and the off-voltage has a magnitude in a range from 0 V to 0.3 V. [12] A ferroelectric memory device comprising: the ferroelectric field-effect transistor according to one of the preceding claims 1 to 11; and a sensing circuit (140) configured to measure a direction of electrical polarization in the ferroelectric dielectric gate layer (53) by measuring a magnitude of the electrical current between the source region (32) and the drain region (38) while a sensing gate voltage is applied to the gate electrode (54). [13] A method of forming a semiconductor structure, comprising: Providing a semiconductor substrate (10) comprising a semiconductor material doped with a first conductivity type; Forming a layer stack comprising, from bottom to top, a charge trapping band misalignment layer (52) containing a metal oxide dielectric material, a ferroelectric gate dielectric layer (53) containing a ferroelectric material, and a gate electrode (54) over the semiconductor substrate (10); and Forming a source region (32) and a drain region (38) in the semiconductor material, wherein a semiconductor channel (35) extends between the source region (32) and the drain region (38) under the layer stack. [14] The method of claim 13, wherein: the semiconductor material comprises silicon; and the method comprises forming an interfacial silicon oxide layer having an effective thickness in a range of 0.1 nm to 0.8 nm directly on an upper surface of the semiconductor channel (35), wherein the charge trapping band misalignment layer (52) is formed directly on the interfacial silicon oxide layer. [15] A method according to claim 13 or 14, wherein: the charge trapping band misalignment layer (52) has an effective thickness in a range of 0.1 nm to 0.5 nm; and the dielectric metal oxide material comprises an oxide material of at least one elemental metal selected from Be, Mg, Ca, Sr, Ba, Al, Ga, Sc, Y, Ti, V, Cr, Mn, Zr, Nb, Mo, Ta, W and lanthanide elements. [16] A method according to any one of the preceding claims 13 to 15, wherein: the ferroelectric material has a charge trapping band (53T) containing electronic states generated by interface traps of the ferroelectric material; the charge trapping band misalignment layer (52) contains a dielectric material that induces shifting of the charge trapping band (53T) of the ferroelectric material relative to a band structure of the semiconductor channel (35); the semiconductor structure comprises a ferroelectric field-effect transistor containing a surface portion of the semiconductor material as a semiconductor channel; the method further comprises providing a gate bias circuit (120) configured to provide an on-state and an off-state for the ferroelectric field-effect transistor by applying an on-voltage and an off-voltage, respectively; an energy level (53T) of the charge trapping band is shifted from an energy level (35V, 35C) of minority charge carriers of the semiconductor channel (35) during the on-state. [17] A method of forming a semiconductor structure, comprising: Providing a semiconductor substrate (110) comprising a doped germanium material portion having a doping of a first conductivity type; Forming a ferroelectric dielectric gate layer (53) containing a ferroelectric material over the doped germanium material, the ferroelectric material having a charge trapping band (53T) containing electronic states generated by interfacial trapping of the ferroelectric material; Forming a gate electrode (54) over the ferroelectric dielectric gate layer (53); and Forming a source region (132) and a drain region (138) in the semiconductor substrate (110), wherein a semiconductor channel (135) comprising the doped germanium material portion extends between the source region (132) and the drain region (138) under the ferroelectric dielectric gate layer (53), wherein an energy level (53T) of the charge trapping band is offset from a Fermi level (54F) of the gate electrode (54) during an on-state of the semiconductor structure. [18] The method of claim 17, wherein the ferroelectric gate dielectric layer (53) is formed directly on a top surface of the doped germanium material portion without an interface material layer between the doped germanium material portion and the ferroelectric gate dielectric layer (53). [19] The method of claim 18, wherein the semiconductor channel (135) comprises doped germanium containing germanium atoms at an atomic concentration greater than 99% and containing dopants of the first conductivity type at an atomic concentration of less than 1%. [20] A method according to any one of the preceding claims 17 to 19, wherein the ferroelectric dielectric gate layer (53) comprises a material selected from Pb(Zr x Ti 1-x )O3, where x is in a range from 0 to 1, PbZrO3, PbTiO3, HfO2, ZrO2, Hf x Zr 1-xO2, where x is between 0 and 1, NH4H2PO4, KH2PO4, LiNbO3, LiTaO3, BaTiO3, (Pb,La)TiO3 and (Pb,La)(Zr,Ti)O3 and doped variants thereof, and has a thickness in a range of 3 nm to 20 nm.

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