CIRCUIT AND METHOD FOR OPERATION OF A CIRCUIT

Abstract

Circuit comprising: a first inverter (110) connected to an input terminal (N0), wherein the input terminal (N0) receives an input signal (SIN) that changes in a first voltage domain from a negative supply level (VSS) to a first positive supply level (VDDH); a second inverter (120) connected between the first inverter (110) and an output terminal (N2), wherein the second inverter (120) generates an output signal (SOUT) that changes in a second voltage domain from the negative supply level (VSS) to a second positive supply level (VDDM);and a first feedback loop (141), wherein the first inverter (110) comprises: a first PMOS transistor (MP1) biased with a first input tracking signal (INH) generated from the input signal (SIN), wherein the first input tracking signal (INH) changes in a third voltage domain from a reference level (VDDL) to the first positive supply level (VDDH), the reference level (VDDL) being higher than the negative supply level (VSS); a first NMOS transistor (MN1) biased with a second input tracking signal (INL) generated from the input signal (SIN), wherein the second input tracking signal (INL) changes in the second voltage domain;and a third PMOS transistor (MP3), wherein a source terminal of the third PMOS transistor (MP3) is connected to a drain terminal of the first PMOS transistor (MP1), a gate terminal of the third PMOS transistor (MP3) is biased to the reference level (VDDL), and a drain terminal of the third PMOS transistor (MP3) is connected to a first node (N1), and wherein the first feedback loop (141) comprises: a fifth NMOS transistor (MN5), wherein a drain terminal of the fifth NMOS transistor (MN5) is connected to the first node (N1), and a gate terminal of the fifth NMOS transistor (MN5) is connected to the second positive supply level (VDDM);and a sixth NMOS transistor (MN6), wherein a drain terminal of the sixth NMOS transistor (MN6) is connected to a source terminal of the fifth NMOS transistor (MN5), a gate terminal of the sixth NMOS transistor (MN6) is connected to the output terminal (N2), and a source terminal of the sixth NMOS transistor (MN6) is connected to the negative supply level (VSS).

Description

Cross-reference to related registration

[0001] The present application claims priority over the preliminary US patent application filed on July 8, 2019, with file number 62 / 871.587 , which is included by reference. background

[0002] With the advent of submicrometer technology, the dimensions of core components in an IC chip are becoming increasingly smaller, leading to higher speeds and lower costs. Simultaneously, the operating voltages of these core components must also be reduced to accommodate the smaller dimensions, such as thinner oxides and smaller spacing. However, at the PCB level, signals to and from the core components at interfaces still travel at conventionally high voltages for interoperability with other chips and to maintain signal integrity. For example, core components in an IC chip might have an internal operating voltage of 1.0 V, and it can still be coupled to other components at a 2.5 V level. In such an IC chip, its input buffer must convert an external signal with a larger voltage range into an internal signal with a smaller voltage range. List of characters

[0003] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 is a circuit diagram showing an input buffer circuit according to various embodiments of the present invention. Fig. 2 is a signal waveform that takes an input signal into the input buffer circuit and an output signal that is fed from the in Fig. The input buffer circuit shown in 1 is generated according to various embodiments of the present invention. Fig. Figure 3A is a signal relationship diagram showing a relationship between the input signal and a first input tracking signal according to various embodiments of the present invention. Fig. Figure 3B is a signal relationship diagram showing a relationship between the input signal and a second input tracking signal according to various embodiments of the present invention. Fig. 4A is a signal waveform showing a relationship between the input signal and the first input tracking signal according to various embodiments of the present invention. Fig. 4B is a signal waveform showing a relationship between the input signal and the second input tracking signal according to various embodiments of the present invention. Fig. 4C is a signal waveform that shows a relationship between the input signal and a first inverted signal according to various embodiments of the present invention. Fig. 4D is a signal waveform that shows a relationship between the input signal and a second inverted signal according to various embodiments of the present invention. Fig. 5A is a circuit diagram that shows another structure of the tracking-high circuit of Fig. 1 shows. Fig. 5B is a circuit diagram that shows another structure of the tracking-high circuit of Fig. 1 shows. Fig. Figure 6 is a circuit diagram showing an input buffer circuit according to various embodiments of the present invention. Fig. 7 is a signal waveform that takes an input signal SIN into the input buffer circuit and an output signal that is taken from the input buffer circuit by Fig. 6 is produced according to various embodiments of the present invention. Fig. Figure 8 is a circuit diagram showing an input buffer circuit according to various embodiments of the present invention. Fig. 9 is a signal waveform that takes the input signal SIN into the input buffer circuit and an output signal that is taken from the input buffer circuit. Fig. 8 is generated according to various embodiments of the present invention. Fig. Figure 10 is a circuit diagram showing an input buffer circuit according to various embodiments of the present invention. Fig. Figure 11 is a flowchart of a method according to various embodiments of the present invention. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] The terms used in this patent description generally have their usual meanings in the relevant field and in the specific context in which each term is used. The use of examples in this patent description, including examples of terms discussed herein, is for illustrative purposes only and in no way limits the scope of protection or the meaning of the description or any explained term. Likewise, the present invention is not limited to various embodiments set forth in this patent description.

[0006] It is understood that the terms "first," "second," etc., may be used here to describe different elements, but these elements are not intended to be limited by these terms. These terms merely serve to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without altering the scope of protection of the embodiments. The term "and / or" used here encompasses all combinations of one or more of the listed associated elements.

[0007] The terms used here “indicates”, “includes”, “has”, “contains” and the like are to be understood as open, i.e. they mean “the” but are not limited to that.

[0008] Throughout the patent description, references to "one embodiment" or "some embodiments" mean that a specific element, structure, implementation, or feature described in connection with one or more embodiments is part of at least one embodiment of the present invention. Therefore, the use of the phrases "in one embodiment" or "in some embodiments" at various points in the description does not necessarily always refer to one and the same embodiment. Furthermore, the specific elements, structures, implementations, or features may be appropriately combined in one or more embodiments.

[0009] Fig. 1 is a circuit diagram showing an input buffer circuit 100aaccording to various embodiments of the present invention. In some embodiments, the input buffer circuit 100a between an input port No and an output port N2 switched. The input buffer circuit 100a is configured so that, based on an input signal SIN at the input terminal No, it outputs a signal SOUT at the output terminal N2 generated.

[0010] In Fig. 2 is a signal waveform that feeds the input signal SIN into the input buffer circuit. 100a and the output signal SOUT, which is from the in Fig. 1 shown input buffer circuit 100a is generated according to various embodiments of the present invention. For better understanding, in Fig. 2 similar elements as in the embodiments of Fig. 1 with the same reference numbers.

[0011] Fig. Figure 2 shows a simulation result of the output signal SOUT in response to the voltage level of the input signal SIN rising from a negative supply level VSS to a first positive supply level VDDH and then falling from the first positive supply level VDDH back to the negative supply level VSS. As exemplified in Fig. As shown in section 2, this is the input buffer circuit. 100a The generated output signal SOUT is set to logic "1" or to a high level if the input signal SIN is higher than a threshold voltage Vt, and this is from the input buffer circuit. 100a The generated output signal SOUT is at logic "o" or at the L level when the input signal SIN is lower than the threshold voltage Vt. In other words, the output signal SOUT has the same logic level as the input signal SIN.

[0012] As exemplified in Fig. 1 and in Fig. As shown in Figure 2, the input signal SIN and the output signal SOUT operate in different voltage domains. In some embodiments, the input signal SIN is a signal from an external circuit or an interface circuit (not shown in the figures) on an IC chip, and the input signal SIN changes in a first voltage domain with a larger voltage difference window from a negative supply level VSS to a first positive supply level VDDH. For example, the input signal SIN changes from approximately 0 V to approximately 1.8 V.In some embodiments, the output signal SOUT is a signal sent to core components (not shown in the figures) in an IC chip, where the output signal SOUT changes in a second voltage domain with a narrower voltage difference window from the negative supply level VSS to the second positive supply level VDDM, which is lower than the first positive supply level VDDH. For example, the output signal SOUT changes from approximately 0 V to approximately 1.2 V.

[0013] In some embodiments, the core components are implemented with smaller dimensions, such as thinner oxides and smaller distances, making them susceptible to overdrive voltage and requiring operation within a narrower voltage difference window. In some embodiments, the input buffer circuit... 100aconfigured to convert the input signal SIN, which changes in the first voltage domain, into the output signal SOUT, which changes in the second voltage domain, in order to protect the core components that are driven by the output signal SOUT.

[0014] As exemplified in Fig. As shown in 1, the input buffer circuit 100a a first inverter 110 , a second inverter 120 , a tracking-high circuit 131 , a tracking-low circuit 132 and another tracking-low setting 134 on. In some embodiments, the first inverter 110 configured to generate a first inverted signal INB1 in response to the input signal SIN, and the second inverter 120 is configured to generate the output signal SOUT in response to the first inverted signal INB1.

[0015] As exemplified in Fig. The one shown in step 1 is the tracking-high circuit. 131 configured to convert the input signal SIN into a first input tracking signal INH. Additionally, it is configured to Fig. Reference is made to Figure 3A, which is a signal relationship diagram showing a relationship between the input signal SIN and the first input tracking signal INH according to various embodiments of the present invention. For better understanding, in Fig. 3A similar elements to those in the embodiments of Fig. 1 and Fig. 2 with the same reference numbers. As in Fig. As shown in 3A, the tracking-high circuit is duplicated. 131 The input signal SIN becomes the first input tracking signal INH when the input signal SIN is above a reference level VDDL. As in Fig. As shown in 3A, the tracking-high circuit is maintained. 131The first input tracking signal INH is set to the reference level VDDL when the input signal SIN is lower than the reference level VDDL. In other words, in response to the input signal SIN changing in the first voltage domain (from VSS to VDDH), the tracking-high circuit generates 131 the first input tracking signal INH, which changes in a third voltage domain (from VDDL to VDDH).

[0016] In some embodiments, the reference level VDDL is a voltage level between the negative supply level VSS and the second positive supply level VDDM. In some embodiments, the reference level VDDL can be configured to be equal to the first positive supply level VDDH minus the second positive supply level VDDM. For example, the reference level VDDL is configured to be approximately 0.6 V when the first positive supply level VDDH is approximately 1.8 V and the second positive supply level VDDM is approximately 1.2 V.

[0017] As exemplified in Fig. Figure 1 shows the tracking-low circuit. 132 configured to convert the input signal SIN into a second input tracking signal INL. Additionally, it is configured to Fig. Reference is made to Figure 3B, which is a signal relationship diagram showing a relationship between the input signal SIN and the second input tracking signal INL according to various embodiments of the present invention. For better understanding, in Fig. 3B similar elements as in the embodiments of Fig. 3A is designated with the same reference numbers. As in Fig. As shown in 3B, the tracking-low circuit is duplicated. 132 The input signal SIN becomes the second input tracking signal INL when the input signal SIN is below the second positive supply level VDDM. As shown in Fig. As shown in 3B, the tracking-low circuit is in place. 132The second input tracking signal INL is set to the second positive supply level VDDM when the input signal SIN is higher than the second positive supply level VDDM. In other words, in response to the change in the input signal SIN in the first voltage domain (from VSS to VDDH), the tracking-low circuit generates 132 the second input tracking signal INL, which changes in the second voltage domain (from VSS to VDDM).

[0018] As exemplified in Fig. As shown in 1, in some embodiments the first inverter 110 five transistors are connected in series between the first positive supply level VDDH and the negative supply level VSS. In the Fig. In the embodiments shown in 1, the first inverter has 110 three PMOS transistors MP1 to MP3 and two NMOS transistors MN1 and MN2.

[0019] As exemplified in Fig. As shown in Figure 1, in some embodiments, a source terminal of the PMOS transistor MP2 is connected to the first positive supply level VDDH. A gate terminal of the PMOS transistor MP2 is biased to the reference level VDDL. Since the reference level VDDL is lower than the first positive supply level VDDH, the PMOS transistor MP2 is normally switched on. A drain terminal of the PMOS transistor MP2 is connected to a source terminal of the PMOS transistor MP1. A source terminal of the PMOS transistor MP1 is connected to the drain terminal of the PMOS transistor MP2. A gate terminal of the PMOS transistor MP1 is biased to the first input tracking signal INH, which changes in the third voltage domain. A drain terminal of the PMOS transistor MP1 is connected to a source terminal of the PMOS transistor MP3. A gate terminal of the PMOS transistor MP3 is biased to the reference level VDDL.A drain terminal of the PMOS transistor MP3 is connected to a first node. N1 tied together.

[0020] The PMOS transistors MP1 to MP3 are configured to output a voltage level of the first inverted signal INB1 at the first node. N1 (i.e., the output node of the first inverter) 110 ) in response to an initial input tracking signal INH goes high.

[0021] Now let's move on to the Fig. 4A to Fig. 4D. Fig. 4A is a signal waveform showing a relationship between the input signal SIN and the first input tracking signal INH according to various embodiments of the present invention. Fig. 4B is a signal waveform showing a relationship between the input signal SIN and the second input tracking signal INL according to various embodiments of the present invention. Fig. 4C is a signal waveform showing a relationship between the input signal SIN and the first inverted signal INB1 according to various embodiments of the present invention. Fig. 4D is a signal waveform that shows a relationship between the input signal SIN and a second inverted signal INB2 according to various embodiments of the present invention. For better understanding, the following are shown in the Fig. 4A to Fig. 4D-like elements as in the embodiments of Fig. 1 and Fig. 2 with the same reference numbers.

[0022] As in the Fig. 4A and Fig. As shown in Figure 4C, when the input signal SIN is lower than the threshold voltage Vt, the first input tracking signal INH is correspondingly lower than the threshold voltage Vt and it turns on the PMOS transistor MP1. Accordingly, the PMOS transistor MP3 is also turned on (MP2 is also turned on), so that the inverted signal INB1 is brought to the first positive supply level VDDH (high).

[0023] It should be noted that the terminals of PMOS transistors MP1 to MP3 operate in the third voltage domain (from VDDL to VDDH). The third voltage difference window (VDDH - VDDL) of the third voltage domain is smaller than the first voltage difference window (VDDH - VSS) of the first voltage domain. For example, if VDDH = 1.8 V, VDDL = 0.6 V, and VSS = 0 V, the third voltage difference window of 1.2 V is smaller than the first voltage difference window of 1.8 V. Since, in this case, the terminals of PMOS transistors MP1 to MP3 operate in the third voltage domain, the PMOS transistors MP1 to MP3 can be used in the first inverter. 110with smaller dimensioned transistors with a relatively lower voltage tolerance (compared to transistors that operate in the first voltage domain with a larger voltage difference window), and the smaller dimensioned PMOS transistors MP1 to MP3 can operate with lower leakage currents and lower energy consumption.

[0024] As exemplified in Fig. Figure 1 shows a drain terminal of the NMOS transistor MN2 with the first node N1 connected. A gate terminal of the NMOS transistor MN2 is biased to the positive supply level VDDM. A source terminal of the NMOS transistor MN2 is connected to a drain terminal of the NMOS transistor. N1 connected. A gate terminal of the NMOS transistor. N1 is biased with the second input tracking signal INL, which is provided by the second tracking-low circuit. 132generated from the input signal. A source terminal of the NMOS transistor. N1 is coupled to the negative supply level VSS.

[0025] The NMOS transistors MN1 and MN2 are configured to adjust the voltage level of the first inverted signal INB1 at the first node. N1 In response to a second input tracking signal, bring INL to low.

[0026] As in the Fig. 4A and Fig. As shown in Figure 4C, if the input signal SIN is higher than the threshold voltage Vt, the second input tracking signal INL is correspondingly higher than the threshold voltage Vt and it switches on the NMOS transistor MN1. Consequently, the NMOS transistor MN2 is also switched on, so that the inverted signal INB1 is brought to the negative supply level VSS (low).

[0027] It should be noted that the terminals of the NMOS transistors MN1 and MN2 operate in the second voltage domain (from VSS to VDDM). A second voltage difference window (VDDM - VSS) of the second voltage domain is smaller than the first voltage difference window (VDDH - VSS) of the first voltage domain. For example, if VDDH = 1.8 V, VDDM = 1.2 V, and VSS = 0 V, the second voltage difference window of 1.2 V is smaller than the first voltage difference window of 1.8 V. In some embodiments, the second voltage difference window (VDDM - VSS) can be essentially the same as the third voltage difference window (VDDH - VDDL), as explained above. Since, in this case, the terminals of the NMOS transistors MN1 and MN2 operate in the second voltage domain, the NMOS transistors MN1 and MN2 can be used in the first inverter. 110with smaller dimensioned transistors with a relatively lower voltage tolerance (compared to transistors that operate in the first voltage domain with a larger voltage difference window), and the smaller dimensioned NMOS transistors MN1 and MN2 can operate with lower leakage currents and lower power consumption.

[0028] In some examples, if the pull-up transistors (e.g., MP1 to MP3) and the pull-down transistors (e.g., MN1 and MN2) are driven by the same input tracking signal, such as the second input tracking signal INL, which changes in the second voltage domain (from VSS to VDDM), the bias voltages for the pull-up transistors (e.g., MP1 to MP3) and the pull-down transistors (e.g., MN1 and MN2) are shifted to a lower voltage range (from VSS to VDDM). Shifting these bias voltages to the lower voltage range is not ideal, as it is desirable to keep the threshold voltage Vt of the input buffer circuit lower. 100aThe voltage difference is approximately an average level between VSS and VDDH of the input signal SIN. To compensate for the bias shift to the lower voltage range and maintain the threshold voltage Vt, the pull-up transistors (e.g., MP1 to MP3) must have larger dimensions than the pull-down transistors (e.g., MN1 and MN2) so that the pull-up transistors (e.g., MP1 to MP3) can operate within a wider voltage difference window from VSS to VDDH. In some embodiments, the ratio between the pull-up transistor size (MP1 to MP3) and the pull-down transistor size (e.g., MN1 and MN2) can reach 50:1 to 100:1. Implementing the PMOS and NMOS transistors on a circuit layout with such a large size difference is challenging. In other words, the first inverter can have a reasonable size ratio between PMOS transistors and NMOS transistors.

[0029] As exemplified in Fig. As shown in Figure 1, the first input tracking signal INH for the pull-up transistors (e.g., MP1 to MP3) and the second input tracking signal INL for the pull-down transistors (e.g., MN1 and MN2) cover the entire voltage range (from VSS to VDDH) of the input signal SIN, since the pull-up transistors (e.g., MP1 to MP3) and the pull-down transistors (e.g., MN1 and MN2) are driven by different input tracking signals INH and INL. In some embodiments, the input buffer circuit requires 100a from Fig. 1. To compensate for the bias shift, the sizes of the pull-up transistors (e.g., MP1 to MP3) can be similar to those of the pull-down transistors (e.g., MN1 and MN2). In some embodiments, the ratio between the size of a pull-up transistor (MP1 to MP3) and a size of a pull-down transistor (e.g., MN1 and MN2) can be 1:1, 2:1, or 3:2. It is simpler to implement the PMOS transistors and the NMOS transistors on a circuit layout with similar sizes.

[0030] It should be noted that the aforementioned voltage values ​​of the input signal SIN (from approximately 0 V to approximately 1.8 V) and the output signal SOUT (from approximately 0 V to approximately 1.2 V) are for illustrative purposes only. The invention is not limited thereto. In some embodiments, the second positive supply level VDDM can be equal to or greater than half of the first positive supply level VDDH. For example, if the first positive supply level VDDH is set to 3.6 V, the second positive supply level VDDM can be equal to or greater than 1.8 V. If the second positive supply level VDDM is less than half of the first positive supply level VDDH, the first input tracking signal INH and the second input tracking signal INL may not cover the entire voltage range (from VSS to VDDH) of the input signal SIN.

[0031] As in the Fig. 1 and Fig. As shown in 4C, the first inverted signal INB1 can be obtained at the first node. N1 The PMOS transistors MP1 to MP3 can be brought to the first positive supply level VDDH (high), or the NMOS transistors MN1 and MN2 can be brought to the negative supply level VSS (low), so that the first inverted signal INB1 changes in the first voltage domain.

[0032] As in the Fig. 1, Fig. 4C and Fig. As shown in Figure 4D, the first inverted signal INB1 is from the tracking-low circuit. 134 The signal is converted into the second inverted signal INB2, which changes in the second voltage domain. This is the behavior of the tracking-low circuit. 134 is the same as the aforementioned tracking-low setting 132Similarly, the relationship between the first inverted signal INB1 and the second inverted signal INB2 is similar to the relationship between the input signal SIN and the second input tracking signal INL, which is described in Fig. 3B is shown. As in the Fig. 4C and Fig. The 4D shown duplicates the tracking-high circuit. 131 The first inverted signal INB1 is higher than the second inverted signal INB2 if the first inverted signal INB1 is below the second positive supply level VDDM. As in the Fig. 4C and Fig. 4D is shown, the tracking-high circuit is maintained. 131 The second inverted signal, INB2, is at the second positive supply level, VDDM, when the first inverted signal, INB1, is higher than the second positive supply level, VDDM. In other words, corresponding to the first inverted signal, INB1, changing in the first voltage domain (from VSS to VDDH), the tracking-high circuit generates131 the second inverted signal INB2, which changes in the second voltage domain (from VSS to VDDM).

[0033] As in the Fig. 1, Fig. 2 and Fig. As shown in 4D, this is the second inverter. 120 configured so that it converts the second inverted signal INB2 in the second voltage domain into the output signal SOUT (which is in Fig. (as shown in Figure 2) is also inverted in the second voltage domain. In some embodiments, the second inverter is 120 configured to invert signals in the same voltage domain, so that the second inverter 120 can be implemented with a CMOS inverter.

[0034] In the embodiments described in Fig. As shown in 1, the tracking-high circuit is indicated. 131Two PMOS transistors, MP4 and MP5, are connected. A source terminal of PMOS transistor MP4 is connected to the gate terminal of PMOS transistor MP1. A gate terminal of PMOS transistor MP4 is connected to input terminal No. A drain terminal of PMOS transistor MP4 is connected to the reference level VDDL. A source terminal of PMOS transistor MP5 is connected to the gate terminal of PMOS transistor MP1. A gate terminal of PMOS transistor MP5 is connected to the reference level VDDL. A drain terminal of PMOS transistor MP5 is connected to input terminal No. When the input signal SIN is high, PMOS transistor MP4 is turned off and PMOS transistor MP5 is turned on to duplicate the input signal SIN as the first input tracking signal INH. When the input signal SIN is low, the PMOS transistor MP4 is turned on and it brings the first input tracking signal INH to the reference level VDDL (low).

[0035] In the Fig. In the embodiments shown in 1, the tracking-low circuit features 132 Two NMOS transistors, MN3 and MN4, are connected. One source terminal of NMOS transistor MN3 is connected to the second positive supply level, VDDM. One gate terminal of NMOS transistor MN3 is connected to the input terminal, No. One drain terminal of NMOS transistor MN3 is connected to the gate terminal of NMOS transistor MN4. N1 connected. One source terminal of the NMOS transistor MN4 is connected to the gate terminal of the NMOS transistor. N1The gate terminal of NMOS transistor MN4 is connected to the second positive supply level VDDM. A drain terminal of NMOS transistor MN4 is connected to an input terminal No. When the input signal SIN is low, NMOS transistor MN3 is turned off and NMOS transistor MN4 is turned on to duplicate the input signal SIN as the second tracking signal INL. When the input signal SIN is high, NMOS transistor MN3 is turned on and maintains the second tracking signal INL at the second positive supply level VDDM. In some embodiments, the structure of the tracking-low circuit is 134 the structure of the tracking-low circuit 132 similar.

[0036] It should be noted that the tracking-high circuit 131 and the tracking-low circuits 132 and 134 not on the in Fig. The structures shown in section 1 are limited. Now let's turn to the Fig. 5A and Fig. 5B. Fig. 5A is a circuit diagram that shows another structure of the tracking-high circuit. 131 from Fig. 1 shows. Fig. 5B is a circuit diagram that shows another structure of the tracking-high circuit. 131 from Fig. 1 shows. For better understanding, the following are included: Fig. 5A and Fig. 5B similar elements to those in the embodiments of Fig. 1 with the same reference numbers.

[0037] In the embodiments described in Fig. The 5A shown indicates the tracking-high circuit. 131 a PMOS transistor MP4a and a resistor R1 The source terminal of the PMOS transistor MP4a is connected to the gate terminal of the PMOS transistor MP1 (see figure). Fig. 1) connected to output the first input tracking signal INH. One gate terminal of the PMOS transistor MP4a is connected to the input terminal No (see Fig. 1) Connected to receive the input signal SIN. One drain terminal of the PMOS transistor MP4 is connected to the reference level VDDL. A first terminal of the resistor R1 is connected to the first positive supply level VDDH. A second connection of a resistor. R2 is connected to the gate terminal of the PMOS transistor MP1 (see Fig. 1) connected to output the first input tracking signal INH. The structure of the tracking-high circuit. 131 from Fig. 5A generates the first input tracking signal INH in response to the input signal SIN, which is in Fig. The relationship shown in 3A is similar.

[0038] In the embodiments described in Fig. As shown in 5B, the tracking-low circuit is activated. 132an NMOS transistor MN3a and a resistor R2 The source terminal of the NMOS transistor MN3a is connected to the gate terminal of the NMOS transistor. N1 (see Fig. 1) connected to output the second input tracking signal INL. One gate terminal of the NMOS transistor MN3a is connected to the input terminal No (see Fig. 1) Connected to receive the input signal SIN. One drain terminal of the NMOS transistor MN3a is connected to the second positive supply level VDDM. One terminal of the resistor R2 is connected to the gate terminal of the NMOS transistor N1 (see Fig. 1) connected to output the second input tracking signal INL. A second connection of the resistor R2 is associated with the negative supply level VSS. The structure of the tracking-low circuit 132 from Fig. 5B generates the second input tracking signal INL in response to the input signal SIN, which is in Fig. The relationship shown in 3A is similar.

[0039] In other words, the tracking-high circuit 131 and the tracking-low circuits 132 and 134 are not on the in Fig. The structures shown in section 1 are limited. Any equivalent circuit capable of generating a tracking signal corresponding to the input signal (see the relevant relationships in the [reference]) can be used. Fig. 3A and Fig. 3B), in the input buffer circuit 100a be used.

[0040] In some embodiments, the Fig. 1. Input buffer circuit shown 100aCascaded PMOS and NMOS transistors are used, with each PMOS and NMOS transistor biased with gate signals in suitable voltage domains, allowing the PMOS and NMOS transistors to be manufactured in small sizes with a lower standby leakage current. Furthermore, the first inverter can 110 in the input buffer circuit 100a have a reasonable size ratio between PMOS transistors and NMOS transistors. As in Fig. As shown in 2, the on-time of the output signal SOUT, which is from the input buffer circuit, is 100a in response to the input signal SIN, approximately 50%. Since the first inverter 110 Being able to detect the entire voltage range of the input signal SIN, the on-time of the input buffer circuit can be determined. 100aThe generated output signal SOUT under different process / voltage / temperature (PVT) conditions is closer to approximately 50% (e.g., approximately 40% to approximately 60%) than in the case where the first inverter 110 The input buffer circuit is biased with a partial voltage range of the input signal SIN. In the above embodiments, the input buffer circuit modifies... 100a the level of the output signal SOUT in response to the input signal SIN in relation to the threshold voltage.

[0041] In some other embodiments, the input buffer circuit can have a Schmitt trigger function which can have different threshold voltages, one for the input signal SIN from low to high, and another for the input signal SIN from high to low.

[0042] Now let's move on to... Fig. 6. Fig. 6 is a circuit diagram that shows an input buffer circuit 100baccording to various embodiments of the present invention. In some embodiments, the input buffer circuit 100b between an input port No and an output port N2 switched. The input buffer circuit 100b is configured so that, based on an input signal SIN at the input terminal No, it outputs a signal SOUT at the output terminal N2 generated. For better understanding, in Fig. 6 similar elements as in the embodiments in the Fig. 1 and Fig. 5B is designated with the same reference numbers.

[0043] In comparison to the input buffer circuit 100a from Fig. 1 indicates the input buffer circuit 100b from Fig. 6. A feedback loop continues. 141 on, which between the output port N2 and the first knot N1 is switched. The feedback loop 141It includes NMOS transistors MN5 and MN6. One drain terminal of the NMOS transistor MN5 is connected to the first node. N1 connected. A gate terminal of the NMOS transistor MN5 is connected to the second positive supply level VDDM. A drain terminal of the NMOS transistor MN6 is connected to a source terminal of the NMOS transistor MN5. A gate terminal of the NMOS transistor MN6 is connected to the output terminal. N2 connected. One source terminal of the NMOS transistor MN6 is connected to the negative supply level VSS. In the embodiments described in Fig. Figure 6 shows the feedback loop. 141 another pull-down path relative to the first node N1 in addition to the NMOS transistors MN1 and MN2 in the first inverter 110 .

[0044] Now let's move on to... Fig. 7. Fig. 7 is a signal waveform that feeds the input signal SIN into the input buffer circuit. 100band the output signal SOUT, which is from the input buffer circuit 100b from Fig. Figure 6 is generated according to various embodiments of the present invention. For better understanding, the following are shown in Fig. 7 similar elements as in the embodiments of Fig. 6 with the same reference numbers.

[0045] As in the Fig. 6 and Fig. As shown in Figure 7, during a transition of the input signal SIN from logic "1" to logic "0", e.g., from the first positive supply level VDDH to the negative supply level VSS, the input signal SIN is initially at the first positive supply level VDDH (logic "1"), the first inverted signal INB1 is initially at the negative supply level VSS (logic "0"), and the output signal SOUT is initially at the second positive supply level VDDM (logic "1"). The NMOS transistors MN1 and MN2 in the first inverter 110are switched on to receive the first inverted signal INB1 at the first node N1 to bring it low. Additionally, the output signal SOUT is fed back to the NMOS transistor MN6 in the feedback loop. 141 to switch on. Therefore, the NMOS transistors MN5 and MN6 are also switched on to regulate the voltage level at the first node. N1 to bring it down to low.

[0046] Since there are two pull-down paths (MN1 and MN2 as well as MN5 and MN6) versus only one pull-up path (MP1 to MP3) during the gradual transition of the input signal SIN from the first positive supply level VDDH to the negative supply level VSS, the first inverted signal INB1 and the output signal SOUT flip later than the original threshold voltage Vt. As in Fig. As shown in Figure 7, the output signal SOUT jumps from the second positive supply level VDDM to the negative supply level VSS when the input signal SIN reaches a low threshold voltage Vt-. In this case, the input buffer circuit 100b a Schmitt trigger function which has a threshold voltage Vt relative to the input signal SIN from logic “o” to logic “1” and another threshold voltage Vt- relative to the input signal SIN from logic “1” to logic “o”.

[0047] In other words, the feedback loop 141 in the input buffer circuit 100b is used to reduce the low threshold voltage Vt- of the input buffer circuit 100b Used when the input signal SIN changes from logical "1" to logical "0".

[0048] In some further embodiments, the input buffer circuit can have a Schmitt trigger function on both sides of a threshold voltage when the input signal SIN changes from logic "1" to logic "0", and also when the input signal SIN changes from logic "0" to logic "1". Let's now turn to Fig. 8. Fig. 8 is a circuit diagram that shows an input buffer circuit 100c according to various embodiments of the present invention. In some embodiments, the input buffer circuit 100c between an input port No and an output port N2 switched. The input buffer circuit 100c is configured so that, based on an input signal SIN at the input terminal No, it outputs a signal SOUT at the output terminal N2 generated. For better understanding, in Fig. 8 similar elements as in the embodiments in the Fig. 1 and Fig. 6 with the same reference numbers.

[0049] In comparison to the input buffer circuit 100b from Fig. 6 indicates the input buffer circuit 100c from Fig. 8 also a tracking-high circuit 133, a third inverter 150 and another feedback loop 142 (those from the feedback loop 141 (is different) on. In some embodiments, structures of the tracking-high circuit are present. 133 those of the tracking-high circuit 131 similarly, those referring to Fig. 1 or Fig. 5A has been discussed, and the behavior of the tracking-high circuit 133 is that of the tracking-high circuit 131 similarly, which refers to the Fig. 3A and Fig. 4A has been discussed. Therefore, the structures and behavior of the tracking-high circuit need to be considered. 133This does not need to be explained again. The tracking-high circuit 133 is used to convert the first inverted signal INB1, which changes in the first voltage domain, into a third inverted signal INBH, which changes in the third voltage domain. The third inverted signal INBH is then used by the third inverter. 150 The signal is converted into a high output signal OUTH, which changes in the third voltage domain. The high output signal OUTH is then used for the feedback loop. 142 feedback.

[0050] As in Fig. As shown in Figure 8, the feedback loop 142 PMOS transistors MP6 and MP7 are used. One source terminal of PMOS transistor MP6 is connected to the first positive supply level VDDH. One gate terminal of PMOS transistor MP6 is connected to the third inverter. 150connected. A source terminal of PMOS transistor MP7 is connected to a drain terminal of PMOS transistor MP6. A gate terminal of PMOS transistor MP7 is connected to the reference level VDDL. A drain terminal of PMOS transistor MP7 is connected to the first node N1 tied together.

[0051] In the embodiments described in Fig. Figure 8 shows the feedback loop. 141 another pull-up path in relation to the first node N1 in addition to the PMOS transistors MP1 to MP3 in the first inverter 110 .

[0052] Now let's move on to... Fig. 9. Fig. 9 is a signal waveform that feeds the input signal SIN into the input buffer circuit. 100c and the output signal SOUT, which is from the input buffer circuit 100c from Fig. Figure 8 is generated according to various embodiments of the present invention. For better understanding, the following are shown in Fig. 9 similar elements as in the embodiments of Fig. 8 with the same reference numbers.

[0053] As in the Fig. 8 and Fig. As shown in Figure 9, during a transition of the input signal SIN from logic "0" to logic "1", e.g., from the negative supply level VSS to the first positive supply level VDDH, the input signal SIN is initially at the negative supply level VSS (logic "0"), the first inverted signal INB1 is initially at the first positive supply level VDDH (logic "1"), and the output signal SOUT is initially at the negative supply level VSS (logic "0"). The PMOS transistors MP1 to MP3 in the first inverter 110 are switched on to receive the first inverted signal INB1 at the first node N1 to bring it high. Additionally, the high output signal OUTH is fed back to control the PMOS transistor MP6 in the feedback loop. 142to switch on. Therefore, the PMOS transistors MP6 and MP7 are also switched on to regulate the voltage level at the first node. N1 to bring it to a high.

[0054] Since there are two pull-down paths (MP1 to MP3 and MP6 and MP7) during the gradual transition of the input signal SIN from the negative supply level VSS to the first positive supply level VDDH, the first inverted signal INB1 and the output signal SOUT flip later than the original threshold voltage Vt. As shown in Fig. As shown in Figure 7, the output signal SOUT jumps from the second positive supply level VDDM to the negative supply level VSS when the input signal SIN reaches a high threshold voltage Vt+. In this case, the input buffer circuit 100cA Schmitt trigger function that has a high threshold voltage Vt+ relative to the input signal SIN from logic "0" to logic "1" and a low threshold voltage Vt- relative to the input signal SIN from logic "1" to logic "0". The high threshold voltage Vt+ is higher than the threshold voltage Vt, and the low threshold voltage Vt- is lower than the threshold voltage Vt.

[0055] In other words, the feedback loop 141 in the input buffer circuit 100b is used to reduce the low threshold voltage Vt- of the input buffer circuit 100b This is used when the input signal SIN changes from logic "1" to logic "0". The input buffer circuit also has... 100c a Schmitt trigger function on both sides of the threshold voltage when the input signal SIN changes from logic "1" to logic "0", and also when the input signal SIN changes from logic "0" to logic "1".

[0056] Now let's move on to... Fig. 10. Fig. 10 is a circuit diagram that shows an input buffer circuit 100d according to various embodiments of the present invention. In some embodiments, the input buffer circuit 100d between an input port No and an output port N2 switched. The input buffer circuit 100d is configured so that, based on an input signal SIN at the input terminal No, it outputs a signal SOUT at the output terminal N2 generated. For better understanding, in Fig. 10 similar elements as in the embodiments of the Fig. 1 to Fig. 9 with the same reference numbers.

[0057] In some embodiments, the input buffer circuit 100d from Fig. 10. Furthermore, an input activation function is provided, which is controlled by an activation signal. When the activation signal is high or logic "1", the input buffer circuit is activated. 100d The circuit is activated to generate the output signal SOUT in response to the input signal SIN. Conversely, if the activation signal is low or logic "0", the input buffer circuit is deactivated. 100d It is deactivated and does not respond to the SIN input signal.

[0058] In comparison to the input buffer circuit 100b from Fig. 6 indicates the input buffer circuit 100d from Fig. 10 also a PMOS transistor MP8, an NMOS transistor MN7, another NMOS transistor MN8 and an AND logic gate 142 on. Furthermore, the second inverter 120 in the input buffer circuit 100d implemented with a NOR logic inverter. The second inverter 120performs a NOR operation between the second inverted signal INB2, which changes in the second voltage domain, and an inverted activation signal IEB, which changes in the second voltage domain.

[0059] A source terminal of PMOS transistor MP8 is connected to the first positive supply level VDDH. A gate terminal of PMOS transistor MP8 is coupled to a first activation signal IEH in the third voltage domain. A drain terminal of PMOS transistor MP8 is connected to the source terminal of PMOS transistor MP3.

[0060] A source terminal of the NMOS transistor MN7 is connected to the negative supply level VSS. A gate terminal of the NMOS transistor MN7 is coupled to a second activation signal IE, which changes in the second voltage domain. A drain terminal of the NMOS transistor MN7 is connected to the source terminal of the NMOS transistor MN1.

[0061] One source terminal of the NMOS transistor MN8 is connected to the negative supply level VSS. One gate terminal of the NMOS transistor MN8 is connected to the AND logic gate. 142 connected. A drain terminal of the NMOS transistor MN8 is connected to the source terminal of the NMOS transistor MN6.

[0062] The AND logic gate 142 is configured to perform a logical AND operation between the second activation signal IE, which changes in the second voltage domain, and a Schmitt trigger activation signal ST, which changes in the second voltage domain.

[0063] When the input activation function and the Schmitt trigger function are enabled, the first activation signal IEH and the second activation signal IE are configured to be logic "1"; the inverted activation signal IEB is configured to be logic "0"; and the Schmitt trigger activation signal ST is logic "1". The PMOS transistor MP8 is turned off. The NMOS transistors MN7 and MN8 are turned on. The input buffer circuit 100d is activated using the Schmitt trigger function.

[0064] When the input activation function is enabled and the Schmitt trigger function is disabled, the first activation signal IEH and the second activation signal IE are configured to be logic "1"; the inverted activation signal IEB is configured to be logic "0"; and the Schmitt trigger activation signal ST is logic "0". The PMOS transistor MP8 is turned off. The NMOS transistor MN7 is turned on, and the NMOS transistor MN8 is turned off. The input buffer circuit 100d It is activated without the Schmitt trigger function.

[0065] When the input activation function is disabled, the first activation signal IEH and the second activation signal IE are configured to be logic "0"; and the inverted activation signal IEB is configured to be logic "1". The PMOS transistor MP8 is turned on. The NMOS transistor MN7 is turned off. The input buffer circuit 100d will be deactivated.

[0066] In some embodiments, the second activation signal IE, the inverted activation signal IEB, and the Schmitt trigger activation signal ST change in the second voltage domain, and the first activation signal IEH changes in the third voltage domain, so that the transistors in the input buffer circuit 100d can be operated within suitable voltage change windows.

[0067] In the embodiments described in Fig. The input buffer circuit is shown in 10. 100d, how the input activation function is integrated into the Fig. 6 shown input buffer circuit 100b is integrated. In some other embodiments, the input activation function can be integrated into the Fig. 10 shown input buffer circuit 100d also in the input buffer circuit 100a from Fig. 1 or into the input buffer circuit 100c from Fig. 8 will be integrated.

[0068] Fig. 11 is a flowchart of a procedure 200 according to various embodiments of the present invention. In some embodiments, the method can 200 from Fig. 11 for the input buffer circuits 100a until 100d are used, which have been discussed in the preceding embodiments, which are described in Fig. 1, Fig. 6, Fig. 8 and / or Fig. 10 are shown. For better understanding, in Fig. 11 similar elements to those in the embodiments of Fig. 1 to Fig. 10 with the same reference numbers. For the sake of brevity, the procedure 200 in the following paragraphs together with the embodiments of the in Fig. 1 shown input buffer circuit 100a and related embodiments of the Fig. 2 to Fig. 5B is discussed. It should be noted that the procedure 200 also in other embodiments of the input buffer circuits 100b until 100d , which in Fig. 6, Fig. 8 or Fig. 10 are shown, which can be used.

[0069] In some embodiments, the process 200 from Fig. 11 to generate the output signal SOUT, which changes in the second voltage domain, e.g. from VSS to VDDM, corresponding to the input signal SIN, which changes in the first voltage domain, e.g. from VSS to VDDH, wherein on Fig. 2. Reference is made to this.

[0070] As exemplified in the Fig. 1, Fig. 4A and Fig. As shown in Figure 11, in response to the change in the input signal SIN in the first voltage domain, e.g. from VSS to VDDH, a step is taken. S211 from the tracking-high circuit 131 performed to generate the first input tracking signal INH, which changes in the third voltage domain, e.g. from VDDL to VDDH.

[0071] As exemplified in the Fig. 1, Fig. 4B and Fig. As shown in Figure 11, in response to the change in the input signal SIN in the first voltage domain, e.g. from VSS to VDDH, a step is taken. S212 from the tracking-low circuit 132 performed to generate the second input tracking signal INL, which changes in the second voltage domain, e.g. from VSS to VDDM.

[0072] In some embodiments, the first voltage domain has a wider voltage difference window, ranging from a negative supply level VSS to a first positive supply level VDDH. For example, the first voltage domain covers a range of approximately 0 V to approximately 1.8 V. In some embodiments, the second voltage domain has a narrower voltage difference window, ranging from a negative supply level VSS to a second positive supply level VDDM. For example, the second voltage domain covers a range of approximately 0 V to approximately 1.2 V. In some embodiments, the third voltage domain has a further narrower voltage difference window, ranging from the reference level VDDL to the first positive supply level VDDH. For example, the third voltage domain covers a range of approximately 0.6 V to approximately 1.8 V. It should be noted that the aforementioned voltage values ​​are for illustrative purposes only.

[0073] As exemplified in the Fig. 1 and Fig. As shown in 11, a step will be taken. S221 This was done to bias a pull-up transistor (e.g., the PMOS transistor MP1) with the first input tracking signal INH. As exemplified in the Fig. 1 and Fig. As shown in 11, a step will be taken. S222 performed to bias a pull-down transistor (e.g. the NMOS transistor MN1) with the second input tracking signal INL.

[0074] As exemplified in the Fig. 1, Fig. 4C and Fig. As shown in 11, a step will be taken. S230 carried out to convert the first inverted signal INB1, which changes in the first voltage domain, using the pull-up transistor and the pull-down transistor in the first inverter. 110 to produce.

[0075] As exemplified in the Fig. 1, Fig. 4D and Fig. As shown in 11, a step will be taken. S240performed to convert the first inverted signal INB1 to the tracking-low circuit 134 to convert into the second inverted signal INB2, which changes in the second voltage domain.

[0076] As exemplified in the Fig. 1, Fig. 2, Fig. 4D and Fig. As shown in 11, a step will be taken. S250 performed to convert the second inverted signal INB2 to the second inverter 120 to invert the output signal SOUT, which changes in the second voltage domain. In some embodiments, the output signal SOUT is a signal sent to core components (not shown in the figures) in an IC chip.

[0077] In some embodiments, a circuit comprises a first inverter and a second inverter. The first inverter is connected to an input terminal. The input terminal receives an input signal that changes in a first voltage domain from a negative supply level to a first positive supply level. The second inverter is connected between the first inverter and an output terminal. The second inverter generates an output signal that changes in a second voltage domain from the negative supply level to a second positive supply level. The first inverter comprises a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased with a first input tracking signal derived from the input signal. The first input tracking signal changes in a third voltage domain from a reference level to the first positive supply level.The reference level is higher than the negative supply level. The first NMOS transistor is biased with a second input tracking signal, which is generated from the input signal. The second input tracking signal changes in the second voltage domain.

[0078] In some embodiments, a first stress difference window of the first stress domain is larger than a second stress difference window of the second stress domain. The first stress difference window is larger than a third stress difference window of the third stress domain. In some embodiments, the second stress difference window is essentially equal to the third stress difference window.

[0079] In some embodiments, the first inverter includes a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor. A source terminal of the second PMOS transistor is connected to the first positive supply level. A gate terminal of the second PMOS transistor is biased to the reference level. A drain terminal of the second PMOS transistor is connected to a source terminal of the first PMOS transistor. A source terminal of the third PMOS transistor is connected to a drain terminal of the first PMOS transistor. A gate terminal of the third PMOS transistor is biased to the reference level. A drain terminal of the third PMOS transistor is connected to a first node. A drain terminal of the second NMOS transistor is also connected to the first node. A gate terminal of the second NMOS transistor is biased to the second positive supply level.A source terminal of the second NMOS transistor is connected to a drain terminal of the first NMOS transistor. A source terminal of the first NMOS transistor is connected to the negative supply level. The first inverter is configured to generate a first inverted signal, changing in the first voltage domain, at the first node.

[0080] In some embodiments, the circuit further includes a first tracking-high circuit, a first tracking-low circuit, and a second tracking-low circuit. The first tracking-high circuit is connected between the input terminal and a gate terminal of the first PMOS transistor. The first tracking-high circuit is configured to convert the input signal into the first tracking signal. The first tracking-low circuit is connected between the input terminal and a gate terminal of the first NMOS transistor. The first tracking-low circuit is configured to convert the input signal into the second tracking signal. The second tracking-low circuit is connected between the first nodes and the second inverter. The second tracking-low circuit is configured to convert the first inverted signal into a second inverted signal that changes in the second voltage domain.The second inverter is configured to invert the second inverted signal into the output signal.

[0081] In some embodiments, the first tracking-high circuit includes a fourth PMOS transistor and a fifth PMOS transistor. A source terminal of the fourth PMOS transistor is connected to the gate terminal of the first PMOS transistor. A gate terminal of the fourth PMOS transistor is connected to the input terminal. A drain terminal of the fourth PMOS transistor is connected to the reference level. A source terminal of the fifth PMOS transistor is connected to the gate terminal of the first PMOS transistor. A gate terminal of the fifth PMOS transistor is connected to the reference level. A drain terminal of the fifth PMOS transistor is connected to the input terminal. The first tracking-low circuit includes a third NMOS transistor and a fourth NMOS transistor. A source terminal of the third NMOS transistor is connected to the second positive supply level.A gate terminal of the third NMOS transistor is connected to the input terminal. A drain terminal of the third NMOS transistor is connected to the gate terminal of the first NMOS transistor. A source terminal of the fourth NMOS transistor is connected to the gate terminal of the first NMOS transistor. A gate terminal of the fourth NMOS transistor is connected to the second positive supply level. A drain terminal of the fourth NMOS transistor is connected to the input terminal.

[0082] In some embodiments, the first tracking-high circuit includes a fourth PMOS transistor and a first resistor. A source terminal of the fourth PMOS transistor is connected to the gate terminal of the first PMOS transistor. A gate terminal of the fourth PMOS transistor is connected to the input terminal. A drain terminal of the fourth PMOS transistor is connected to the reference level. A first terminal of the first resistor is connected to the first positive supply level. A second terminal of the first resistor is connected to the gate terminal of the first PMOS transistor. The first tracking-low circuit includes a third NMOS transistor and a second resistor. A source terminal of the third NMOS transistor is connected to the gate terminal of the first NMOS transistor. A gate terminal of the third NMOS transistor is connected to the input terminal.One drain terminal of the third NMOS transistor is connected to the second positive supply level. One terminal of the second resistor is connected to the gate terminal of the first NMOS transistor. The other terminal of the second resistor is connected to the negative supply level.

[0083] In some embodiments, the circuit further includes a first feedback loop. The first feedback loop comprises a fifth NMOS transistor and a sixth NMOS transistor. A drain terminal of the fifth NMOS transistor is connected to the first node. A gate terminal of the fifth NMOS transistor is connected to the second positive supply level. A drain terminal of the sixth NMOS transistor is connected to a source terminal of the fifth NMOS transistor. A gate terminal of the sixth NMOS transistor is connected to the output terminal. A source terminal of the sixth NMOS transistor is connected to the negative supply level.

[0084] In some embodiments, the circuit further includes a third inverter, a second tracking-high circuit, and a second feedback loop. The second tracking-high circuit is connected between the first nodes and the third inverter. The second tracking-high circuit is configured to invert the first inverted signal into a third inverted signal that changes in the third voltage domain. The second feedback loop includes a sixth PMOS transistor and a seventh PMOS transistor. A source terminal of the sixth PMOS transistor is connected to the first positive supply level. A gate terminal of the sixth PMOS transistor is connected to the third inverter. A source terminal of the seventh PMOS transistor is connected to a drain terminal of the sixth PMOS transistor. A gate terminal of the seventh PMOS transistor is connected to the reference level.A drain terminal of the seventh PMOS transistor is connected to the first node.

[0085] In some embodiments, the circuit further includes an eighth PMOS transistor and a seventh NMOS transistor. A source terminal of the eighth PMOS transistor is connected to the first positive supply level. A gate terminal of the eighth PMOS transistor is coupled to a first activation signal in the third voltage domain. A drain terminal of the eighth PMOS transistor is connected to the source terminal of the third PMOS transistor. A source terminal of the seventh PMOS transistor is connected to the negative supply level. A gate terminal of the seventh NMOS transistor is coupled to a second activation signal in the second voltage domain. A drain terminal of the seventh NMOS transistor is connected to the source terminal of the first NMOS transistor.

[0086] In some embodiments, the reference level is essentially equal to the first positive supply level minus the second positive supply level.

[0087] In some embodiments, a circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The first PMOS transistor is biased with a first input tracking signal generated from the input signal. The input signal changes in a first voltage domain from a negative supply level to a first positive supply level. The first input tracking signal changes in a third voltage domain from a reference level to the first positive supply level. The reference level is higher than the negative supply level. A source terminal of the second PMOS transistor is connected to the first positive supply level. A gate terminal of the second PMOS transistor is biased to the reference level.A drain terminal of the second PMOS transistor is connected to a source terminal of the first PMOS transistor. A source terminal of the third PMOS transistor is connected to a drain terminal of the first PMOS transistor. A gate terminal of the third PMOS transistor is biased to the reference level. A drain terminal of the third PMOS transistor is connected to a first node. The first NMOS transistor is biased to a second input tracking signal, which is generated from the input signal. The second input tracking signal changes in a second voltage domain from the negative supply level to a second positive supply level. A source terminal of the first NMOS transistor is connected to the negative supply level. A drain terminal of the second NMOS transistor is connected to the first node.A gate terminal of the second NMOS transistor is biased to the second positive supply level. A source terminal of the second NMOS transistor is connected to a drain terminal of the first NMOS transistor. A first inverted signal, changing in the first voltage domain, is generated at the first node.

[0088] In some embodiments, a first stress difference window of the first stress domain is larger than a second stress difference window of the second stress domain. The first stress difference window is larger than a third stress difference window of the third stress domain. In some embodiments, the second stress difference window is essentially equal to the third stress difference window.

[0089] In some embodiments, the circuit further includes a first tracking-high circuit and a first tracking-low circuit. The first tracking-high circuit is connected between the input terminal and a gate terminal of the first PMOS transistor. The first tracking-high circuit is configured to convert the input signal into the first tracking signal. The first tracking-low circuit is connected between the input terminal and a gate terminal of the first NMOS transistor. The first tracking-low circuit is configured to convert the input signal into the second tracking signal.

[0090] In some embodiments, the circuit further includes a second tracking-low circuit connected to the first node. This second tracking-low circuit is configured to convert the first inverted signal into a second inverted signal that varies in the second voltage domain. In some embodiments, the circuit further includes an inverter connected between the second tracking-low circuit and an output terminal. The inverter generates an output signal corresponding to the second inverted signal, which also varies in the second voltage domain.

[0091] In some embodiments, a method comprises the following steps: based on an input signal that changes in a first voltage domain from a negative supply level to a first positive supply level, generating a first input tracking signal that changes in a third voltage domain from a reference level to the first positive supply level; based on the input signal, generating a second input tracking signal that changes in a second voltage domain from a reference level to the first positive supply level; biasing a pull-up transistor with the first input tracking signal; and biasing a pull-down transistor with the second input tracking signal.

[0092] In some embodiments, a first stress difference window of the first stress domain is larger than a second stress difference window of the second stress domain, and the first stress difference window is larger than a third stress difference window of the third stress domain. In some embodiments, the second stress difference window is essentially equal to the third stress difference window.

[0093] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. It should be clear to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent designs do not deviate from the fundamental concept and scope of protection of the present invention and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present invention.

Claims

[1] Circuit with: a first inverter connected to an input terminal, the input terminal receiving an input signal that changes in a first voltage domain from a negative supply level to a first positive supply level; and a second inverter connected between the first inverter and an output terminal, wherein the second inverter generates an output signal that changes in a second voltage domain from the negative supply level to a second positive supply level, wherein the first inverter has the following: a first PMOS transistor that is biased with a first input tracking signal generated from the input signal, wherein the first input tracking signal changes in a third voltage domain from a reference level to the first positive supply level, where the reference level is higher than the negative supply level, and a first NMOS transistor which is biased with a second input tracking signal generated from the input signal, the second input tracking signal changing in the second voltage domain. [2] Circuit according to claim 1, wherein a first voltage difference window of the first voltage domain is larger than a second voltage difference window of the second voltage domain and the first voltage difference window is larger than a third voltage difference window of the third voltage domain. [3] Circuit according to claim 2, wherein the second voltage difference window is substantially the same as the third voltage difference window. [4] Circuit according to any one of the preceding claims, wherein the first inverter further comprises: a second PMOS transistor, wherein a source terminal of the second PMOS transistor is connected to the first positive supply level, a gate terminal of the second PMOS transistor is biased to the reference level, and a drain terminal of the second PMOS transistor is connected to a source terminal of the first PMOS transistor; a third PMOS transistor, wherein a source terminal of the third PMOS transistor is connected to a drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor is biased to the reference level, and a drain terminal of the third PMOS transistor is connected to a first node; and a second NMOS transistor, wherein a drain terminal of the second NMOS transistor is connected to the first node, a gate terminal of the second NMOS transistor is biased to the second positive supply level, and a source terminal of the second NMOS transistor is connected to a drain terminal of the first NMOS transistor, where a source terminal of the first NMOS transistor is connected to the negative supply level, and The first inverter is configured to generate a first inverted signal at the first node, which changes in the first voltage domain. [5] Circuit according to claim 4, further comprising: a first tracking-high circuit connected between the input terminal and a gate terminal of the first PMOS transistor, wherein the first tracking-high circuit is configured to convert the input signal into the first input tracking signal; a first tracking-low circuit connected between the input terminal and a gate terminal of the first NMOS transistor, wherein the first tracking-low circuit is configured to convert the input signal into the second input tracking signal; and a second tracking-low circuit connected between the first nodes and the second inverter, wherein the second tracking-low circuit is configured to convert the first inverted signal into a second inverted signal that changes in the second voltage domain, wherein the second inverter is configured to invert the second inverted signal into the output signal. [6] Circuit according to claim 5, wherein the first tracking-high circuit comprises: a fourth PMOS transistor, wherein a source terminal of the fourth PMOS transistor is connected to the gate terminal of the first PMOS transistor, a gate terminal of the fourth PMOS transistor is connected to the input terminal, and a drain terminal of the fourth PMOS transistor is connected to the reference level, and a fifth PMOS transistor, wherein a source terminal of the fifth PMOS transistor is connected to the gate terminal of the first PMOS transistor, a gate terminal of the fifth PMOS transistor is connected to the reference level, and a drain terminal of the fifth PMOS transistor is connected to the input terminal, and the first tracking-low circuit has the following: a third NMOS transistor, wherein a source terminal of the third NMOS transistor is connected to the second positive supply level, a gate terminal of the third NMOS transistor is connected to the input terminal, and a drain terminal of the third NMOS transistor is connected to the gate terminal of the first NMOS transistor, and a fourth NMOS transistor, wherein a source terminal of the fourth NMOS transistor is connected to the gate terminal of the first NMOS transistor, a gate terminal of the fourth NMOS transistor is connected to the second positive supply level, and a drain terminal of the fourth NMOS transistor is connected to the input terminal. [7] Circuit according to claim 5, wherein the first tracking-high circuit comprises: a fourth PMOS transistor, wherein a source terminal of the fourth PMOS transistor is connected to the gate terminal of the first PMOS transistor, a gate terminal of the fourth PMOS transistor is connected to the input terminal, and a drain terminal of the fourth PMOS transistor is connected to the reference level, and and a first resistor, wherein a first terminal of the first resistor is connected to the first positive supply level and a second terminal of the first resistor is connected to the gate terminal of the first PMOS transistor, and the first tracking-low circuit has the following: a third NMOS transistor, wherein a source terminal of the third NMOS transistor is connected to the gate terminal of the first NMOS transistor, a gate terminal of the third NMOS transistor is connected to the input terminal, and a drain terminal of the third NMOS transistor is connected to the second positive supply level, and a second resistor, wherein a first terminal of the second resistor is connected to the gate terminal of the first NMOS transistor and a second terminal of the second resistor is connected to the negative supply level. [8] Circuit according to any one of claims 5 to 7, further comprising a first feedback loop, wherein the first feedback loop comprises: a fifth NMOS transistor, wherein a drain terminal of the fifth NMOS transistor is connected to the first node and a gate terminal of the fifth NMOS transistor is connected to the second positive supply level; and a sixth NMOS transistor, wherein a drain terminal of the sixth NMOS transistor is connected to a source terminal of the fifth NMOS transistor, a gate terminal of the sixth NMOS transistor is connected to the output terminal, and a source terminal of the sixth NMOS transistor is connected to the negative supply level. [9] Circuit according to any one of claims 5 to 8, further comprising: a third inverter; a second tracking-high circuit connected between the first nodes and the third inverter, wherein the second tracking-high circuit is configured to invert the first inverted signal into a third inverted signal that changes in the third voltage domain; and a second feedback loop, wherein the second feedback loop comprises the following: a sixth PMOS transistor, wherein a source terminal of the sixth PMOS transistor is connected to the first positive supply level and a gate terminal of the sixth PMOS transistor is connected to the third inverter, and a seventh PMOS transistor, wherein a source terminal of the seventh PMOS transistor is connected to a drain terminal of the sixth PMOS transistor, a gate terminal of the seventh PMOS transistor is connected to the reference level, and a drain terminal of the seventh PMOS transistor is connected to the first node. [10] Circuit according to any one of claims 4 to 9, further comprising: an eighth PMOS transistor, wherein a source terminal of the eighth PMOS transistor is connected to the first positive supply level, a gate terminal of the eighth PMOS transistor is coupled to a first activation signal in the third voltage domain, and a drain terminal of the eighth PMOS transistor is connected to the source terminal of the third PMOS transistor; and a seventh NMOS transistor, wherein a source terminal of the seventh PMOS transistor is connected to the negative supply level, a gate terminal of the seventh NMOS transistor is coupled to a second activation signal in the second voltage domain, and a drain terminal of the seventh NMOS transistor is connected to the source terminal of the first NMOS transistor. [11] Circuit according to one of the preceding claims, wherein the reference level is essentially equal to the first positive supply level minus the second positive supply level. [12] Circuit with: a first PMOS transistor that is biased with a first input tracking signal generated from the input signal, wherein the input signal changes in a first voltage domain from a negative supply level to a first positive supply level, the first input tracking signal changes in a third voltage domain from a reference level to the first positive supply level, and the reference level is higher than the negative supply level; a second PMOS transistor, wherein a source terminal of the second PMOS transistor is connected to the first positive supply level, a gate terminal of the second PMOS transistor is biased to the reference level, and a drain terminal of the second PMOS transistor is connected to a source terminal of the first PMOS transistor; a third PMOS transistor, wherein a source terminal of the third PMOS transistor is connected to a drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor is biased to the reference level, and a drain terminal of the third PMOS transistor is connected to a first node; a first NMOS transistor which is biased with a second input tracking signal generated from the input signal, wherein the second input tracking signal changes in a second voltage domain from the negative supply level to a second positive supply level, and a source terminal of the first NMOS transistor is connected to the negative supply level; and a second NMOS transistor, wherein a drain terminal of the second NMOS transistor is connected to the first node, a gate terminal of the second NMOS transistor is biased to the second positive supply level, and a source terminal of the second NMOS transistor is connected to a drain terminal of the first NMOS transistor, generating a first inverted signal that changes in the first voltage domain at the first node. [13] Circuit according to claim 12, wherein a first voltage difference window of the first voltage domain is larger than a second voltage difference window of the second voltage domain and the first voltage difference window is larger than a third voltage difference window of the third voltage domain [14] Circuit according to claim 13, wherein the second voltage difference window is substantially the same as the third voltage difference window. [15] Circuit according to any one of claims 12 to 14, further comprising: a first tracking-high circuit connected between the input terminal and a gate terminal of the first PMOS transistor, wherein the first tracking-high circuit is configured to convert the input signal into the first input tracking signal; and a first tracking-low circuit connected between the input terminal and a gate terminal of the first NMOS transistor, wherein the first tracking-low circuit is configured to convert the input signal into the second input tracking signal. [16] Circuit according to any one of claims 12 to 15, further comprising a second tracking-low circuit connected to the first node, wherein the second tracking-low circuit is configured to convert the first inverted signal into a second inverted signal which changes in the second voltage domain. [17] Circuit according to claim 16, further comprising an inverter connected between the second tracking-low circuit and an output terminal, wherein the inverter generates an output signal corresponding to the second inverted signal which changes in the second voltage domain. [18] Procedure with the following steps: Based on an input signal that changes in a first voltage domain from a negative supply level to a first positive supply level, generating a first input tracking signal that changes in a third voltage domain from a reference level to the first positive supply level; Based on the input signal, a second input tracking signal is generated, which changes in a second voltage domain from a reference level to the first positive supply level; Biasing a pull-up transistor with the first input tracking signal; and Pre-biasing a pull-down transistor with the second input tracking signal. [19] Method according to claim 18, wherein a first stress difference window of the first stress domain is larger than a second stress difference window of the second stress domain and the first stress difference window is larger than a third stress difference window of the third stress domain. [20] Method according to claim 19, wherein the second stress difference window is essentially the same as the third stress difference window.