DEVICE AND OPTIMIZATION OF A TRANSISTOR GATE PROFILE

Abstract

Device comprising: several fin structures (120), each projecting vertically upwards from a substrate (110) and each extending in a first direction (X) in a top view; and a gate structure (300, 600, 1300) arranged above the fin structures (120), wherein the gate structure (300, 600, 1300) extends in a second direction (Y) in the top view, wherein the second direction (Y) is different from the first direction (X); wherein the fin structures (120) have a fin spacing (210) which is equal to the sum of a dimension (230) of one of the fin structures (120) in the second direction and a distance (220) between an adjacent pair of fin structures (120) in the second direction (Y); wherein an end segment (300A, 600A, 1300A) of the gate structure (300, 600, 1300) extends in the second direction (Y) beyond an edge of a nearest fin structure of the fin structures (120); and wherein the end segment (300A, 600A, 1300A) has a tapered profile in plan view, wherein a dimension (320) of the end segment (300A, 600A, 1300A) decreases continuously and gradually as the end segment (300A, 600A, 1300A) extends further in the second direction (Y) beyond the fin structures (120).

Description

TECHNICAL BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest device (or line) that can be produced by a manufacturing process) has decreased. This downsizing process generally offers advantages by increasing production efficiency and reducing associated costs. However, this downsizing has also increased the complexity of IC processing and manufacturing.

[0002] For example, manufacturing processes used to define transistor gate structures can generate residues or unwanted byproducts. As device sizes become smaller, the risk of electrical shorting from such residues or byproducts can also increase, which can lead to lower yields or degraded device performance.

[0003] Therefore, the conventional methods for forming gate structures, although generally adequate, were not satisfactory in all aspects.

[0004] US 2016 / 0379928 A1 discloses a device having a plurality of fin structures extending in a first direction and a gate structure extending over the plurality of fin structures in a second direction. The gate structure has portions that protrude beyond the fin structures and have a rounded end.

[0005] US 2008 / 0001176 A1 discloses an array of nanofin structures extending in a first direction, in which a gate structure extends over the nanofin structures in a second direction and protrudes from the nanofin structures. SUMMARY OF THE INVENTION

[0006] The present invention relates to a device according to claim 1, a method according to claim 7 and a method according to claim 14. Advantageous embodiments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of explanation. Fig. 1A is a perspective view of an IC device in the form of a FinFET according to various non-claimed embodiments. Fig. 1B is a planar top view of an IC device in the form of a FinFET according to various non-claimed embodiments. Fig. 1C is a perspective view of an IC device in the form of an ATM device according to various claimed embodiments. Fig. 2-18 are plan views of various embodiments of IC devices after various stages of fabrication. Fig. 19-20 are flowcharts illustrating methods of manufacturing a semiconductor device according to various non-claimed embodiments. Fig. 21A and Fig. 21B shows the top view profiles of various structures on a lithography mask and the corresponding structures on the wafer. DETAILED DESCRIPTION

[0008] The following invention offers many different embodiments or examples of implementing various features of the invention. To simplify the present invention, specific examples of components and arrangements are described below. These are, of course, only examples. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated throughout the various examples of the present invention.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed herein.

[0009] Furthermore, the present invention may repeat reference numerals in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed herein. Furthermore, the formation of a feature on, in conjunction with, and / or coupled to another feature in the present invention that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed sandwiching the features between them such that the features may not be in direct contact. Furthermore, spatially relative terms such as "below," "above," "horizontal," "vertical," "over," "on," "below," "below," "above," etc., as well as derivatives thereof (e.g., "horizontal," "upward," "downward," etc.)) is used to facilitate the present invention of the relationship of one feature to another feature. The spatially relative terms are intended to cover various orientations of the device including the features. Furthermore, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to include numbers that are within a reasonable range inclusive of the described number, e.g., within + / - 10% of the described number or other values ​​as understood by those skilled in the art. For example, the term "about 5 nm" encompasses the dimensional range from 4.5 nm to 5.5 nm.

[0010] The present invention relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar (flat) FETs, three-dimensional fin-line FETs (FinFETs), or gate-all-around (GAA) devices. One aspect of the present invention is the formation of a dipole layer directly on an interface layer in a gate structure and the subsequent use of multiple interface layer patterning processes to create different threshold voltages for different devices. This improves flexibility in tuning the threshold voltage and reduces gate resistance compared to conventional devices, as discussed in more detail below.

[0011] Fig. 1A and Fig. 1B show a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) 90. The IC device 90 may be an intermediate device manufactured during processing of an IC or a portion thereof and may include static random access memory (SRAM) and / or other logic circuitry, passive components such as resistors, capacitors, and inductors, and active devices such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS), bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. The present invention is not limited to any particular number of devices or device regions, or to any particular device configurations, unless otherwise stated. Although, for example,While the IC device 90, as shown, is a three-dimensional FinFET device, the concepts of the present invention may also apply to planar FET devices or GAA devices.

[0012] According to Fig. 1A, the IC device 90 includes a substrate 110. The substrate 110 may include an elemental semiconductor (single-element semiconductor) such as silicon, germanium, and / or other suitable materials; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 may be a single-layer material with a uniform composition. Alternatively, the substrate 110 may include multiple layers of material with similar or different compositions suitable for fabricating IC devices. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer.In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain regions, may be formed in or on the substrate 110. The doped regions may be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron, depending on design requirements. The doped regions may be formed directly on the substrate 110, in a p-well structure, in an n-well structure, in a dual-well structure, or by means of a raised structure. Doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0013] Three-dimensional active regions 120 are formed on the substrate 110. The active regions 120 are elongated, fin-like structures that protrude upward from the substrate 110. As such, the active regions 120 may be referred to interchangeably as fins 120 or fin structures 120 hereinafter. The fin structures 120 may be fabricated by suitable processes, including photolithography and etching processes. The photolithographic process may include forming a photoresist layer over the substrate 110, exposing the photoresist to a structure, performing post-exposure bake processes, and developing the photoresist into a masking element (not shown) including the resist. The masking element is then used to etch recesses into the substrate 110, leaving the fin structures 120 on the substrate 110.The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed using double or multiple patterning processes. Generally, double or multiple patterning processes combine photolithography and self-aligned processes and enable the creation of structures that, for example, have smaller pitches than those otherwise obtained with a single, direct photolithography process. For example, a layer may be formed over a substrate and patterned using a photolithography process. Using a self-aligned process, spacers are formed laterally / along the patterned layer. The layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin structures 120.

[0014] The IC device 90 further includes source / drain features 122 formed over the fins 120. The source / drain features 122 may include epitaxial layers grown epitaxially on the fin structures 120.

[0015] The IC device 90 further includes isolation structures 130 formed on the substrate 110. The isolation structures 130 electrically separate various components of the IC device 90 from each other. The isolation structures 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable materials. In some embodiments, the isolation structures 130 may include shallow trench isolation (STI) features. In one embodiment, the isolation structures 130 are formed by etching trenches in the substrate 110 during the formation of the fin structures 120. The trenches may then be filled with an insulating material described above, followed by a chemical mechanical planarization (CMP) process.Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures may also be implemented as isolation structures 130. Alternatively, isolation structures 130 may have a multi-layer structure, e.g., with one or more thermal oxide liner layers.

[0016] The IC device 90 also includes gate structures 140 formed over and engaging the fins 120 on three sides in a channel region of each fin 120. The gate structures 140 may be dummy gate structures (e.g., having an oxide gate dielectric and a polysilicon gate electrode) or may be HKMG structures having a high-k gate dielectric and a metal gate electrode, with the HKMG structures formed by replacing the dummy gate structures. Although not illustrated herein, the gate structure 140 may include additional material layers, such as an interface layer over the fins 120, a cap layer, other suitable layers, or combinations thereof.

[0017] With reference to Fig. 1B, a plurality of fins 120 are longitudinally aligned along the X-direction, and a plurality of gate structures 140 are longitudinally aligned along the Y-direction, i.e., generally perpendicular to the fins 120. In many embodiments, the IC device 90 includes additional features such as gate spacers disposed along the sidewalls of the gate structures 140, hard mask layer(s) disposed over the gate structures 140, and numerous other features.

[0018] It should be understood that the various aspects of the present invention discussed below may also apply to multi-channel devices such as gate-all-around (GAA) devices. Fig. Figure 1C illustrates a three-dimensional perspective view of an exemplary ATM device 150. For consistency and clarity, similar devices are shown in Fig. 1C and Fig. 1A-1B are labeled with the same reference numerals. For example, the fin structures 120 protrude vertically upward from the substrate 110 in the Z direction. The isolation structures 130 provide electrical isolation between the fin structures 120. The gate structure 140 lies over the fin structures 120 and over the isolation structures 130. A mask 155 is disposed over the gate structure 140, and the gate spacers 160 are disposed on the sidewalls of the gate structure 140. A cap layer 165 is formed over the fin structures 120 to protect the fin structures 120 from oxidation during the formation of the isolation structures 130. A plurality of nanostructures 170 are disposed over each of the fin structures 120. The nanostructures 170 may comprise nanosheets, nanotubes, nanowires, or another type of nanostructure extending horizontally in the X direction.Portions of the nanostructures 170 beneath the gate structure 140 may serve as channels for the GAA device 150. Dielectric internal spacers 175 may be disposed between the nanostructures 170. Although not shown for simplicity, each of the nanostructures 170 may further be circumferentially wrapped with a gate dielectric layer. In the depicted embodiment, the portions of the nanostructures 170 outside the gate structure 140 may serve as source / drain features of the GAA device 150. However, in some embodiments, continuous source / drain features may be epitaxially grown over portions of the fin structures 120 outside the gate structure 140. Separately, conductive source / drain contacts 180 may be formed over the source / drain features to provide electrical connection thereto.An interlayer dielectric (ILD) 185 is formed over the isolation structures 130 and around the gate structure 140 and the source / drain contacts 180.

[0019] Further details regarding the fabrication of GAA devices are provided in U.S. Patent No. 10,164,012, entitled "Semiconductor Device and Manufacturing Method thereof," issued December 25, 2018, and U.S. Patent No. 10,361,278, entitled "Method of Manufacturing a Semiconductor Device and a Semiconductor Device," issued July 23, 2019, and U.S. Patent No. 9,887,269, entitled "Multi-Gate Device and Method of Fabrication Thereof," issued February 6, 2018, the disclosures of which are hereby incorporated by reference in their entireties. To the extent that the present invention relates to a fin structure or FinFET devices, these explanations may also apply to GAA devices.

[0020] Fig. 2-13 show schematic, fragmentary plan views of various sections of IC devices at various stages of fabrication. For example, Fig. 2-13 schematic, fragmentary top views of IC devices 200A, 200B, 200C, 200D, and 200E. In some embodiments, IC devices 200A, 200B, 200C, 200D, and 200E may be fabricated on the same wafer (or IC die), but they may be fabricated using different processes. For the sake of consistency and clarity, similar components used in Fig. 2-13 and 1A-1B are provided with the same reference numerals.

[0021] With reference to Fig. 2, the IC device 200A includes a plurality of active regions, for example, the fin structures 120 described above with reference to Fig. 1A-1B. The fin structures 120 each extend in the X direction and are separated from each other in the Y direction. The fin structures 120 have a spacing that is measured in the Y direction and can be a sum of a distance 220 between two adjacent fin structures 120 and a width 230 of one of the fin structures 120 in the Y direction. In other words, the spacing 210 = distance 220 + width 230.

[0022] The IC device 200A has gate structures 240 which, in plan view, are Fig. 2 over the fin structures 120. It is to be understood that the gate structures 240 are formed over the fin structures 120 and partially wrapped around them in a cross-sectional view or in a three-dimensional view, e.g., in a similar manner as the gate structures 140 are formed over the fin structures 120 in Fig. 1A. In some embodiments, the gate structures 240 comprise dummy gate structures and may be interchangeably referred to as such below. For example, in some embodiments, the dummy gate structures 240 may comprise a dummy polysilicon gate electrode and possibly a dummy silicon oxide gate dielectric. In the dummy gate structures 240, the dummy polysilicon gate electrode (and the dummy silicon oxide gate dielectric, if present) is removed in a gate replacement process and replaced with high-k metal gate (HKMG) structures comprising a metal gate electrode and a high-k gate dielectric. The HKMG structures may substantially adopt or inherit (adopt) the top-view shape or profile of the dummy gate structures 240.

[0023] It is to be understood that in Fig. 2, only a portion of each of the dummy gate structures 240 is shown for reasons of space. For example, each dummy gate structure 240 may include an elongated body segment joined by two opposing end segments 240A. In some embodiments, the end segment 240A may be the portion of the dummy gate structure 240 that extends beyond the edge of the outermost fin structure 120. For example, the end segment 240A may have an outermost tip 250 in the Y direction that is spaced a distance 255 from the nearest fin structure 120. In some embodiments, the distance 255 is less than about three times the inter-pitch 210 of the fin structures 120. In some embodiments, the distance 255 is about 0.5 times to about 3 times the inter-pitch 210.

[0024] It should be noted that only one of such end segments 240A is depicted together with a portion of the body segment. The other end segment (e.g., opposite end segment 240A in the Y direction) and the remainder of the body segment are shown in Fig. 2 omitted for reasons of space.

[0025] As in Fig. 2, the end segment 240A may have an outwardly protruding, contoured profile (e.g., convexly curved in both the X and Y directions). This may be an unintended result of lithography effects. More specifically, the dummy gate structures 240 may be formed by depositing a dummy gate layer (e.g., a polysilicon layer) over a substrate (including over the fin structures 120), defining a mask pattern (e.g., a photoresist pattern and / or a hard mask pattern) over the dummy gate layer, and etching the dummy gate layer while the mask pattern serves as an etch mask. The shape or profile of the mask pattern is defined by a mask pattern of a lithography mask. Portions of the dummy gate layer below the mask pattern are protected from etching while the exposed portions of the dummy gate layer are etched away.The remaining sections of the dummy gate layer form the dummy gate structures 240.

[0026] In many cases, the mask pattern on the lithography mask can have a rectangular or polygonal profile. In older technology generations, where device sizes are significantly larger, the dummy gate structure can often inherit (adopt) the shape and / or profile of the top view of the mask pattern on the lithography mask, thus exhibiting a profile resembling a rectangle or polygon. However, as device sizes become increasingly smaller, optical effects of the photolithography process can distort the profile of the structures formed on a wafer. For example, the mask pattern (formed over the dummy gate layer) corresponding to the mask pattern on the lithography mask may not maintain the rectangular / polygonal profile and instead be formed to have outwardly protruding contours at the end segments.Therefore, the end segments 240A of the dummy gate structure 240 may also have the outwardly protruding contours as shown in FIG. Fig. 2 shown.

[0027] It should be noted that the outwardly projecting contour profile is not required for the end segments 240A. In some cases, the end segments 240A may each have a profile that, in plan view, resembles a rectangle, but with slightly curved edges (e.g., at the corners), as shown in Fig. 3 shown.

[0028] With reference back to Fig. 2, due to imperfections in the lithography process, a residue or by-product 260 may be formed around the end segments 240A and even portions of the body segment of the dummy gate structure 240. More specifically, the etching process discussed above for etching the dummy gate layer (with the mask structure serving as an etch mask) may use gases containing fluorine (F), chlorine (Cl), and / or bromine (Br). These gases may react with the polysilicon material of the dummy gate layer to produce the residue or by-product 260, which may contain polysilicon and / or elements of the gases. For example, in some cases, the residue or by-product 260 may contain SiF4 or Si2OCl6.

[0029] Portions of the residue or byproduct 260 may be dispersed as particles 270 around the dummy gate structures 240. Typically, the manufacturing tools used to fabricate the IC device 200A may employ suction or fan mechanisms to remove the residue or byproduct 260 and the particles 270. Removal of the residue or byproduct 260 is not too difficult because, at this stage of fabrication, they are typically not surrounded by densely packed structures. However, removal of the particles 270 may become more difficult, particularly when the particles 270 are trapped between adjacent fin structures 120 (which may resemble two adjacent, vertically protruding walls around the particles 270).For example, the vertically protruding fin structures 120 may interfere with the suction forces used to remove the particles 270, which may result in incomplete removal of the particles 270.

[0030] The incomplete removal of particles 270 could lead to electrical short-circuiting problems. In the subsequent gate replacement process, the dummy gate structures 240 are replaced, for example, with HKMG structures. Since the remaining particles 270 and the dummy gate structures 240 have similar material compositions (e.g., both contain polysilicon), the remaining particles 270 may also be replaced with HKMG structures, even if unintentionally. In effect, unwanted "extra" HKMG structures would be formed at locations corresponding to the remaining particles 270. These "extra" HKMG structures could short-circuit components of the IC device 200A.For example, if the remaining particles 270 are located between the fin structures 120 and / or overlap a location of a conductive source / drain contact to be formed (typically between the adjacent dummy gate structures 240), the "extra" HKMG structures corresponding to the remaining particles 270 may cause undesirable electrical shorts between the HKMG structures and the conductive source / drain contacts. Such electrical shorts may degrade device performance, such as voltage breakdown (also referred to as breakdown voltage) VBD, and lead to lower yields.

[0031] It is assumed that such electrical short circuits are not too concerning for certain structures. For example, the particles 270 may be easier to remove for devices with larger distances between adjacent gate structures, and even the unremoved particles 270 may still be sufficiently far away from sensitive structures such as the fin structures 120 and / or the source / drain contacts. Thus, the undesired electrical short circuit may not occur even if the "extra" HKMG structures are present. As another example, the particles 270 would be much easier to remove if the IC device 200A is implemented with planar (flat) structures instead of fin structures, since there may not be any vertically standing walls (e.g., corresponding to the vertically protruding fin structures 120) around the particles 270.Therefore, in planar devices, particles 270 may not yet be present at the time of the gate replacement process. Therefore, no "extra" HKMG gate structures would be formed for the planar devices, and thus, unwanted electrical short circuits would not occur.

[0032] However, since the electrical short circuit discussed above could be a problem for IC devices with closer pitches (e.g., higher structure density) and / or FinFET devices (including multi-channel GAA devices), the present invention attempts to optimize the shape and / or profile of the gate structures to minimize the risks of electrical short circuit. Fig. For example, Figure 4 is a schematic, fragmentary top view of an IC device 200B showing an optimized dummy gate shape profile according to one embodiment. For the sake of consistency and clarity, similar devices shown in Fig. 2-4 are provided with the same reference numerals.

[0033] With reference to Fig. 4, the IC device 200B includes the fin structures 120 and a plurality of dummy gate structures 300 formed over and partially wrapped around the fin structures 120, similar to Fig. 1A. The dummy gate structures 300 have end segments 300A that extend in the Y direction beyond the edge of the outermost fin structure 120. In contrast to the end segments 240A of the dummy gate structures 240 in Fig. 2, the end segments 300A in Fig. 4 has a profile that tapers inward (is conical) in plan view. For example, the end segment 300A may have a tip 310 that defines a point of the end segment 300A that is farthest from the fin structure 120. The end segment 300A may further have a dimension 320 (measured in the X direction) that varies as a function of the position within the end segment 300A or as a function of the distance from the nearest fin structure 120. The body 300B of the dummy gate structure 300 has a dimension (measured in the X direction) that remains relatively constant regardless of the position within the body.

[0034] In the embodiment as in Fig. 4, dimension 320 gradually shrinks with increasing distance from fin structure 120 (i.e., as end segment 300A extends further beyond fin structures 120). For example, dimension 320 may have a first value at a first location closer to fin structure 120. Dimension 320 may have a second value that is smaller than the first value at a second point farther from fin structure 120 than the first location. In some embodiments, the tapered (conical) profile of end segment 300A is curved and substantially smooth; i.e., dimension 320 may continuously and gradually decrease as distance from fin structure 120 increases. In other embodiments, the tapered profile of the end segment 300A may not be completely smooth, so that it may have some flat or jagged edges (e.g., when the decrease in dimension 320 is not continuous).For example, the end segment 300A may be formed similar to a triangle or similar to a polygon in plan view, as long as the portion farther from the fin structures 120 is narrower in the X direction than the portion closer to the fin structures.

[0035] In some embodiments, the tapered profile of the end segment 300A may further manifest itself in the end segment 300A being, on average, narrower than a body 300B of the dummy gate structure 300. For example, the end segment 300A may have a first average width (measured in the X-direction), which may be an average of all the different dimensions 320 at different locations of the end segment 300A. Further, the body 300B may have a second average width (measured in the X-direction), which may be an average of all the different dimensions 330 at different locations of the body 300B. Because the end segment 300A is tapered, the first average width of the end segment 300A is substantially less than the second average width of the body 300B.In some embodiments, the ratio between the first average width and the second average width ranges between about 0.5 and about 0.78. This ratio range is not randomly chosen, but is specifically configured to ensure that the curvature or taper of the end segment 300A is sufficient to substantially completely remove the particles 270 while ensuring that the end segment 300A is not too narrow to adversely affect the functionality of the gate.

[0036] The inwardly tapered profile of the end segment 300A helps to mitigate the problems caused by the particles 270. For example, even if particles 270 are formed, they can be more easily removed from the IC device 200B during a cleaning process performed after patterning the dummy gate structures 300. This is because the inwardly tapered profile of the end segments 300A effectively creates a larger and freer surface area for the particles 270. This reduces the likelihood of the particles 270 becoming trapped (e.g., between the adjacent dummy gate structures 300 or between the fin structures 120). Therefore, the particles 270 generated during the fabrication of the IC device 200B can be more easily vacuumed or otherwise removed, thereby avoiding potential problems caused by the presence of the remaining particles 270, as discussed above with reference to Fig. 2. In some embodiments, the tapered profile of the end segment 300A allows for the removal of all particles 270 (and byproduct 260) during the cleaning process.

[0037] Fig. 5 is a schematic, fragmentary top view of an IC device 200C incorporating an optimized dummy gate shape profile according to embodiments not claimed. For the purpose of consistency and clarity, similar devices shown in Fig. 2-5 are marked with the same reference numerals. With reference to Fig. 5, the IC device 200C includes the fin structures 120 and a plurality of dummy gate structures 350 formed over and partially wrapped around the fin structures 120, similar to that described with reference to FIG. Fig. 1A described.

[0038] The dummy gate structures 350 have end segments 350A that protrude in the Y direction beyond the outermost fin structure 120. Although the end segments 350A have an outwardly protruding shape (e.g., similar to the end segments 240A in Fig. 2), it is possible that in other embodiments they may have a rectangular profile (e.g. similar to the end segments 240A in Fig. 3) or an inwardly tapered profile (e.g. similar to the end segments 300A in Fig. 4). However, in contrast to the end segments 240A and / or 300A, the end segment 350A extends much further beyond the nearest fin structure 120. In other words, the end segment 350A is stretched or extends (elongated, elongated) further in the Y-direction than the end segments 240A. For example, the outermost tip 310 of the end segment 350A is spaced a distance 360 ​​from the edge of the nearest fin structure 120. In some embodiments, the distance 360 ​​is at least 4 times as long as the intermediate distance 210 of the fin structures 120. In some embodiments, the distance 360 ​​is between about 4 times and about 8 times the intermediate distance 210. In comparison, the distance 255 (see Fig. 2) the dummy gate structure 240 is less than about 3 times as long as the intermediate pitch 210. This range of values ​​is not randomly chosen, but is specifically configured such that the pitch 360 is sufficiently long to ensure that the particles 270 (if any are generated) are far enough away from the fin structures 120 so that they can be easily removed according to the various aspects of the present invention. Furthermore, this range of values ​​ensures that the pitch 360 is not too long as to consume an undesirably large amount of chip area / space. In other words, this range of values ​​is optimized in the sense that the removal of the unwanted particles 270 is facilitated without unduly sacrificing valuable chip area.

[0039] The fact that the end segment 350A is further stretched or extended further helps to mitigate the problems explained above that are caused by the particles 270. For example, even if particles 270 are formed, the particles 270 are less likely to be formed near the fin structures 120 due to the now greater distance 360 ​​from the fin structures 120. This allows the particles 270 to be removed more easily because the particles 270 are not in a region that is as densely populated (e.g., near the fin structures 120) compared to the particles in Fig. 2. Furthermore, even if some particles 270 are not removed and are converted into the HKMG-containing structures in the subsequent manufacturing steps, the probability of an electrical short circuit with the fin structures 120 and / or with the conductive source / drain contacts is still low, since there is a greater separation between the HKMG-containing structures and the fin structures 120 and / or the conductive source / drain contacts.

[0040] It is to be understood that in some embodiments, the features of the embodiment in Fig. 4 (e.g. an inwardly tapered profile for the end segment of the gate) and the embodiment in Fig. 5 (e.g. a longer end segment of the gate) can be combined to realize the dummy gate structures. Fig. For example, Figure 6 shows a schematic, fragmentary top view of an IC device 200D showing an optimized dummy gate shape profile according to an embodiment incorporating elements of the embodiments in Fig. 4 and Fig. 5. For the sake of uniformity and clarity, similar devices are Fig. 2-6 are provided with the same reference numerals.

[0041] With reference to Fig. 6, the IC device 200D includes the fin structures 120 and a plurality of dummy gate structures 400 formed over and partially wrapped around the fin structures 120, similar to that described above with reference to Fig. 1A. The dummy gate structures 400 have end segments 400A, each having an inwardly tapered profile, similar to the Fig. 4. For example, the dimension 420 of the end segment 400A decreases the closer it is to the tip 410 of the end segment 400A (e.g., as the end segment 400A extends further beyond the next fin structure 120). Furthermore, the end segment 400A is also elongated or stretched, similar to the embodiment shown in Fig. 5. For example, a distance 430 between the tip 410 and the edge of the nearest fin structure 120 is at least four times the inter-pitch distance 210 of the fin structures 120. Due to these unique physical properties, the particles 270 are easier to remove during cleaning, and the remaining particles 270 (and the resulting HKMG-containing structures) are less likely to subsequently cause electrical shorting problems.

[0042] Fig. Figure 7 shows a schematic, fragmentary top view of an IC device 200E, illustrating an optimized dummy gate shape profile according to embodiments not claimed. For the sake of consistency and clarity, similar components are shown in Fig. 2-7 are provided with the same reference numerals. In Fig. 7, the IC device 200E includes the fin structures 120 and a plurality of dummy gate structures 450 formed over and partially wrapped around the fin structures 120, similar to that described above with reference to Fig. 1A. However, the dummy gate structures 450 lack the end segments of the dummy gate structures 240, 300, 350, and 400. In other words, the dummy gate structures 450 are each formed as a continuous dummy gate structure extending in the Y direction over the length of the die (e.g., a die of a wafer), and not as individual gate structures like the dummy gate structures 240, 300, 350, and 400. For reasons of space, Fig. 7 may show only a portion of each of the continuous dummy gate structures 450 in the Y direction, it being understood that the continuous dummy gate structures 450 may each extend beyond what is shown in Fig. 7 is shown.

[0043] After the formation of the HKMG structures, a dielectric structure 470 (also referred to as a cut metal gate or CMG feature) may be formed to replace the dummy gate structures 450 in order to divide the HKMG structures into individual HKMG gate structures. Thus, the dummy gate structures do not have end segments similar to end segments 240A, 300A, 350A, or 400A, which reduces the likelihood of the formation of the particles 270. Even if the particles 270 are formed, they are still further away from the fin structures 120 and are easier to remove, thereby mitigating the electrical short-circuit problems discussed above. It should be understood that at this stage of manufacturing, the dielectric structures 470 are as in Fig. 7 shown are not yet formed, and it is shown in Fig. 7 merely indicates the locations where the continuous gate structures can be "cut." Therefore, the edges / boundaries of the dielectric structure 470 are shown here as dashed lines.

[0044] The Fig. 8-13 show schematic, fragmentary top views of IC devices 200A, 200B, 200C, 200D, and 200E at a subsequent manufacturing stage, e.g., after a gate replacement process has been performed to replace the above-discussed dummy gate structures with HKMG structures. For example, an interlayer dielectric (ILD) may be formed around the above-discussed dummy gate structures. The dummy gate structures may be removed by etching processes, leaving openings (trenches) in the ILD. These openings or trenches are then filled with the metal gate electrodes of the HKMG structures. If the dummy gate structures in some embodiments include a dummy gate dielectric layer (e.g., a silicon oxide gate dielectric), then in some embodiments the dummy gate dielectric layer is also replaced by a high-k gate dielectric layer as part of the KHMG structures.

[0045] With reference to Fig. 8-9, the HKMG structures 540 are formed to replace the dummy gate structures 240. The HKMG structures 540 substantially adopt the shape or profile of the dummy gate structures 240 in a top view. For example, the HKMG structures 540 may have end segments 540A that protrude outward in the X and / or Y directions, and the distance 555 between a tip 550 of the end segment 540A may be less than about three times the inter-pitch distance 210 of the fin structures 120. In other words, the end segments 540A of the HKMG structures 540 are not inwardly tapered and are not elongated in the Y direction.

[0046] A conductive source / drain contact 500 may be formed between the HKMG structures 540. The conductive source / drain contact 500 establishes an electrical connection with the source / drain features listed below. If the particles 270 discussed above were not removed and subsequently transformed into the HKMG-containing structures, such as structures 570, they could cause an electrical short circuit with the conductive source / drain contacts 500, which may result in poor device performance or device defects, e.g., breakdown voltage (VBD).

[0047] With reference to Fig. 10, the HKMG structures 600 are now formed to replace the dummy gate structures 300. The HKMG structures 600 essentially adopt (inherit) the shape or profile of the dummy gate structures 300 in a top view. Thus, the HKMG structures 600 may have end segments 600A that taper inwardly like the end segments 300A. For example, the end segment 600A may have a dimension 620 (measured in the X direction) that decreases the closer it is to the tip 610 of the end segment 600A (e.g., the further the end segment 600A protrudes beyond the edge of the nearest fin structure 120), while a dimension 630 of the body segment 600B remains relatively constant throughout the body.As explained above, the removal of the end segment 600A helps to remove the particles 270 during the cleaning performed after the definition of the dummy gate structures 300 and reduces the likelihood of an electrical short circuit caused by HKMG-containing structures corresponding to the particles 270 remaining after cleaning. Therefore, the likelihood of an electrical short circuit with the conductive source / drain contact 500 is lower. In some embodiments, at the time of the gate replacement process, no remaining particles 270 are trapped between the fin structures 120, which means that no unwanted HKMG-containing structures form between the fin structures 120 that could be electrically shorted to the conductive source / drain contact 500.

[0048] With reference to Fig. 11, the HKMG structures 650 are now formed to replace the dummy gate structures 350. The HKMG structures 650 substantially inherit the shape or profile of the dummy gate structures 350 in a top view. As such, the HKMG structures 650 may have end segments 650A that are stretched or extended in the Y direction. For example, a tip 610 of the end segment 650A and an edge of the nearest fin structure 120 are separated by a distance 660. The distance 660 has a similar value to the distance 360. In some embodiments, the distance 660 is at least 4 times as long as the inter-pitch 210 of the fin structures 120. For example, the distance 660 may be between about 4 times and about 8 times as long as the inter-pitch 210.As explained above, the extension of the end segment 650A helps to remove the particles 270 during the cleaning performed after the definition of the dummy gate structures 350, as well as to reduce the likelihood of an electrical short circuit caused by HKMG-containing structures corresponding to the particles 270 remaining after cleaning. Therefore, the likelihood of an electrical short circuit with the conductive source / drain contact 500 is lower.

[0049] With reference to Fig. 12, the HKMG structures 700 are now formed to replace the dummy gate structures 400. The HKMG structures 700 essentially inherit the shape or profile of the dummy gate structures 400 in a top view. Thus, the HKMG structures 700 may include end segments 700A, each having an inwardly tapered profile and stretched or elongated in the Y direction. For example, a dimension 720 (measured in the X direction) of the end segment 7004 decreases the closer it is to the tip 710 of the end segment 7004. Furthermore, the distance 730 between the tip 610 and the nearest fin structure 120 is at least 4 times as long as the intermediate distance 210 of the fin structures 120. For example, the distance 730 may be between about 4 times and about 8 times as long as the intermediate distance 210.As explained above, the inwardly tapered profile and extension of the end segment 700A contributes to the removal of the particles 270 during the cleaning performed after the definition of the dummy gate structures 400, as well as to reducing the likelihood of an electrical short circuit caused by HKMG-containing structures corresponding to the particles 270 remaining after cleaning. Therefore, the likelihood of an electrical short circuit with the conductive source / drain contact 500 is lower.

[0050] With reference to Fig. 13, the HKMG structures 750 are now formed to replace the dummy gate structures 450. The HKMG structures 750 essentially adopt (inherit) the shape or profile of the dummy gate structures 450 in a plan view. Thus, the HKMG structures 750 may lack the end segments similar to the end segments 540A, 600A, 650A, or 700A, since the HKMG structures 750 can be formed as continuous structures extending in the Y direction across the length of the tool. Due to space constraints, Fig. 13, only a portion of the HKMG structures 750 may be shown, and it is to be understood that the HKMG structures 750 may each extend beyond what is shown in Fig. 13. The above-discussed dielectric structures 470 (e.g., CMG features) are formed to divide each of the continuous HKMG structures 750 into separate gate structures 750A and 750B. As discussed above, such a process generates fewer particles 270, makes potentially generated particles 270 easier to remove, and / or also reduces the likelihood of an electrical short circuit between the conductive source / drain contact 500 and any HKMG-containing structures formed corresponding to the particles 270.

[0051] Fig. 14 is a schematic, fragmentary top view of the HKMG structures 540 and 600A, illustrating the difference between their curvatures. For example, the end segment 540A of the HKMG structure 540 has an outwardly protruding profile that can be measured at least in part by an angle 800. The angle 800 can be defined by a substantially straight (e.g., substantially Y-direction) edge 810 of the HKMG structure 540 and a tangent 820 taken as a tangent along the outwardly curved portion of the end segment 540A. The angle 800 is greater than 0. In some embodiments, the angle 800 ranges between about 1 degree and about 30 degrees.

[0052] In comparison, the end segment 600A of the HKMG structure 600 has an inwardly tapered profile that can be measured at least in part by an angle 850. The angle 850 can be defined by a substantially straight (e.g., substantially Y-direction) edge 860 of the HKMG structure 600 and a tangent 870 taken as a tangent along the inwardly tapered portion of the end segment 600A. The angle 850 is less than 0. In some embodiments, the angle 850 ranges between about -1 degree and about -30 degrees. The said range of values ​​is not chosen randomly, but is specifically configured to ensure that the end segment 600A is sufficiently tapered to allow easy removal of the unwanted particles 270, while ensuring that the end segment 600A is not excessively thin or excessively tapered, such that the functionality of the gate would be impaired.It is understood that the end segment 700A of the HKMG structure 700 may also have such an angle 850 with similar ranges of values.

[0053] Fig. 15 is a schematic, fragmentary top view of the HKMG structure 540 and another HKMG structure 900 formed according to an embodiment of the present invention. In the HKMG structure 540, a distance 880 separates the edge 810 from its outermost protruding point of the end segment 540A. The distance 880 is greater than 0. In some embodiments, the distance 880 ranges between about 1 nm and about 20 nm. In comparison, the HKMG structure 900 may have an end segment 900A that is overall thinner in the X direction than the body of the HKMG structure 900. The end segment 900A further includes a concave portion 910 that curves inward. For example, the end segment 900A curves inward most at a point 920.Due to such an inward curvature, a distance 930 separates the point 920 and an edge 940 of the HKMG structure 900, with the edge 940 extending substantially straight in the Y direction. The distance 930 is between approximately 1 nm and approximately 30 nm.

[0054] It is to be understood that the Fig. 14-15 show the top view profiles of the various HKMG structures actually formed on a wafer, but they may also correspond (e.g., resemble) the top view profiles of mask structures on a lithography mask. For example, the mask structure on a lithography mask used to define the HKMG structure 600 may also have the shape / profile similar to that shown in Fig. 14. Some minor differences between the shape / profile of the HKMG structures and the mask structures on the lithography mask may be that the mask structures may be thinner (e.g., in the X-direction) and / or longer (e.g., in the Y-direction) than the corresponding HKMG structures. In addition, the end portions of the structures on the lithography mask may be modified (e.g., by adding OPC-supporting functions) to achieve a desired shape / profile for the structures formed on the actual wafer. In this context, Fig. 21A and Fig. 21B shows several examples of the relationship between different structures on the lithography mask and their corresponding structures on the wafer. Fig. For example, Figure 21A illustrates how a rectangular structure on a lithography mask can form a structure with rounded end portions on a wafer. Fig. Figure 21B illustrates how a rectangular main structure with smaller auxiliary features at its end portions can form a structure with more tapered end portions (e.g., tapered according to aspects of the present invention) on the wafer. Thus, one can see how the structures can be configured, manipulated, or otherwise adapted on a lithography mask to achieve the gate structures with the specific profiles (e.g., tapered and / or extended end portions) according to embodiments of the present invention.

[0055] According to some aspects of the present invention, gate structures with different shapes or profiles may be fabricated on the same wafer. For example, a schematic, fragmentary plan view of various portions of a wafer 1000 is shown in Fig. 16. The wafer 1000 may have regions, for example, regions 1000A and 1000B. Active regions, such as fin structures, may be formed in both region 1000A and region 1000B. For example, a plurality of fin structures 1010 may be formed in wafer region 1000A, while a plurality of fin structures 1110 may be formed in wafer region 1000B. The fin structures 1010 and 1110 may be similar to the fin structures 120 discussed above, e.g., they may be formed as semiconductor-containing structures that protrude vertically upward from a substrate. The fin structures 1010 and 1110 each extend in the X-direction and have widths 1020 and 1120 measured in the Y-direction. In some embodiments, widths 1020 and 1120 may be substantially the same. In other embodiments, widths 1020 and 1120 may have different values.It should be understood that due to space constraints only a subset of the fin structures 1010 and 1110 is shown in . Fig. 16 is shown.

[0056] The wafer region 1000A and the wafer region 1000B have different structure densities. For example, a distance 1030 separates adjacent pairs of fin structures 1010, while a distance 1130 separates adjacent pairs of fin structures 1110. As shown in Fig. As shown in Figure 16, pitch 1030 is substantially greater than pitch 1130. In some embodiments, the ratio between pitch 1030 and pitch 1130 is in a range between about 1.6 and about 2.0. Due at least in part to the different pitches 1030 and 1130, wafer regions 1000A and 1000B may also have substantially different fin pitches 1040 and 1140. In some embodiments, the ratio between fin pitch 1040 and fin pitch 1140 is in a range between about 1.8 and about 2.3.

[0057] The differences in feature densities between wafer regions 1000A and 1000B may be due to design or manufacturing requirements. For example, certain types of IC devices may require a higher feature density (e.g., more densely packed fin structures), while other types of IC devices may require a lower feature density (e.g., more widely spaced fin structures).

[0058] Due to the different structure densities, gate structures with different end segment profiles may be implemented in wafer region 1000A and wafer region 1000B. Specifically, a gate structure 1200 may be implemented in wafer region 1000A, while a gate structure 1300 may be implemented in wafer region 1000B. Gate structures 1200 and 1300 may each extend in the Y direction and may be wrapped around fin structures 1010 and 1110. In some embodiments, gate structures 1200 and 1300 may be HKMG structures.

[0059] The lower fin structure density in the wafer region 1000A means that the unwanted particles 270 are more likely to be generated. More specifically, the etching may stop during the etching of the dummy gate layer to define the dummy gate structures when the underlying fin structures 1010 are reached. The lower fin structure density in the wafer region 1000A means that a larger amount of the dummy gate layer material must be etched away, thereby increasing the probability that the particles 270 are generated. Therefore, the gate structure 1200 may be similar to the HKMG structure 600 in Fig. 10 or the HKMG structure 650 in Fig. 11 or the HKMG structure 700 in Fig. 12 (e.g., as a combination of the HKMG structures 600 and 650). In other words, the gate structure 1200 may be implemented such that the end segments 1200A are tapered inward or that the end segments 1200A are spaced apart by a distance 1060 that is at least four times as long as the inter-fin distance 1040 (it should be noted that Fig. 16 is not to scale), protrude beyond the outermost fin structure 1010. Here again, the fact that the end segment 1200A has an inwardly tapered profile and / or is elongated in the Y direction allows the unwanted particles 270 to be generated further away from the fin structures 1010, whereby they can be more easily removed during a cleaning process (e.g., by suction forces).

[0060] On the other hand, the greater structure density in the wafer region 1000B means that the unwanted particles 270 are less likely to be generated, since the greater presence of the fin structures 1110 under the dummy gate layer means that not as much of the dummy gate layer material needs to be etched away. Therefore, the gate structures 1300 do not need to be optimized in a similar manner as the gate structure 1200. In the illustrated embodiment, the gate structure 1300 may be designed similarly to the HKMG structure 540 in Fig. 8. For example, the gate structure 1300 may have end segments 1300A formed similarly to the end segment 540A in Fig. 8 or Fig. 9, which may have an outwardly protruding profile or a rectangular profile with rounded corners. The end segment 1300A also does not need to be elongated in the same way as the end segment 1200A. For example, the end segment 1300A may protrude beyond the outermost fin structure 1110 in the Y direction by a distance 1160, wherein the ratio between the distance 1160 and the inter-fin distance 1140 may be less than about 3. In some embodiments, the distance 1060 is also substantially larger than the distance 1160. For example, a ratio between the distance 1060 and the distance 1160 may range between about 2.0 and about 4.0. Again, the difference in value between the distance 1060 and the distance 1160 is not a random result, but is due to the profile of the gate structure 1200 being specifically configured according to aspects of the present invention.

[0061] Fig. Figure 17 shows a schematic, fragmentary top view of various portions of wafer 1000 according to some other aspects of the present invention. For the purpose of consistency and clarity, similar components are shown in Fig. 16-17 are provided with the same reference numerals. For example, Fig. 17 also shows the wafer region 1000A in which the gate structure 1200 is formed according to the present invention. As explained above, the gate structure 1200 has an optimized profile in that the end segment 1200A is tapered and extended in the Y direction.

[0062] Fig. 17 further shows a wafer region 1000C having a plurality of active regions 1410. Note that wafer region 100C may or may not be on the same wafer or on the same die as wafer region 100A. In some embodiments, active regions 1410 are non-fin structures. For example, active regions 1410 may be the active regions for planar devices. In other words, active regions 1410 may comprise semiconductor regions (portions of which may be doped) embedded in a substrate and not protruding vertically from the substrate. As explained above, planar devices may not have the problems associated with particles 270 because there are no vertically protruding fin structures to capture particles 270. Therefore, it is not necessary to optimize the profile of gate structure 1500 formed over active regions 1410.For example, the gate structure 1500 may have end segments 1500A formed similarly to the end segment 13004 in . Fig. 16 (or similar to the end segment 540A, as in Fig. 8 or Fig. 9), which may have an outwardly projecting profile or a rectangular profile with rounded corners.

[0063] The end segment 1500A also does not need to be as elongated as the end segment 1200A. For example, the end segment 1500A may extend beyond the edge of an outermost active region 1410 by a distance 1460, where the distance 1460 is less than three times the distance 1440 of the active regions 1410, where the distance 1440 is equal to the sum of a dimension 1420 of the active region 1410 and a distance 1430 between an adjacent pair of the active regions 1410. In other words, for planar devices (e.g., devices that do not have the vertically protruding fin structures), the probability of the unwanted particles 270 being trapped is much lower, i.e., they would not have become a problem even at the gate ends. The problems associated with the unwanted particles 270 are those that only occur in connection with FinFETs (including gate-all-around devices).Therefore, it would not have been obvious for planar devices to implement gate structures with tapered or extended end portions like the present invention, as this would have been unnecessary for planar devices.

[0064] Another aspect of the present invention is the revision of an IC layout plan to optimize the shape or profile of the gate structures. In this context, modern semiconductor manufacturing may employ a foundry that receives an original IC layout plan from a colorless IC design house, wherein the colorless IC design house generated the original IC layout plan. The original IC layout plan typically includes structures formed as rectangles, squares, or other polygons with substantially straight edges and 90-degree corners. These structures may be modified by the foundry to facilitate manufacturing. For example, OPC (optical proximity correction) structures may be added to the original IC layout plan to achieve the desired shapes and / or sizes of the device structure.According to various aspects of the present invention, the gate structures in the original IC layout plan may be optimized to have tapered end segments and may be elongated or stretched.

[0065] As an example of such a modification of the original IC layout plan, Fig. 18, which shows top views of a portion of an original IC layout plan 1600A and the corresponding revised IC layout plan 1600B. The original IC layout plan 1600A includes multiple active areas, e.g., fin structure features 1610, each extending in the X direction. The fin structure features 1610 each have a dimension 1620 measured in the Y direction, and a pitch 1630 separates the adjacent fin structure features 1610. A fin pitch 1640 of the fin structure features 1610 is equal to a sum of the dimension 1620 and the pitch 1630.

[0066] A gate structure 1700 overlaps the fin structure structures 1610 in plan view and extends in the Y direction. The gate structure structure 1700 has end segments 17004, each extending in the Y direction by a distance 1660 beyond the boundaries of the outermost fin structure structures 1610. As shown in Fig. As shown in Figure 18, the fin structure structures 1610 and the gate structure structure 1700 may each be formed as a rectangle. When such an IC layout plan is transferred to a lithography mask, the resulting gate structure structure on an actually manufactured wafer may, as explained above, have outwardly protruding end segments, e.g., in a similar manner to the end segment 540A (see Fig. 15). As explained above, this may be undesirable because the particles 270 may be generated that may be too close to the fin structures corresponding to the fin structure structures 1610, which may subsequently lead to electrical short circuits.

[0067] The present invention solves this problem by generating the revised IC layout plan 1600B based on the original IC layout plan 1600A. The revised IC layout plan 1600B may or may not modify the fin structure structures 1610, but the gate structure structure 1700 is revised into a gate structure structure 1800. In some embodiments, the gate structure structure 1800 may be generated such that the end segments 1800A are tapered inward, e.g., similar to the gate structure 1200 described above (see Fig. 16-17).

[0068] In some embodiments, in addition to (or instead of) tapering end segments 1800A, gate structure structure 1800 is further stretched or elongated in the Y direction. For example, according to the revised IC layout plan, gate structure structure 1800 extends beyond outermost fin structure 1610 by a distance 1860, where distance 1860 is substantially greater than distance 1660, while gate structure structure 1700 according to the original IC layout plan extends beyond outermost fin structure 1610 by a distance 1660. In some embodiments, distance 1860 is stretched to be at least 4 times as long as interfin distance 1640. In some embodiments, the ratio between distance 1860 and distance 1660 ranges between about 2.0 and about 4.0.The said value range is not chosen randomly, but is specifically configured so that the gate structure fabricated according to the revised IC layout plan is sufficiently long to ensure that the unwanted particles 270 (if generated) are far enough away from the fabricated fin structures so that they can be easily removed, while the chip area(s) is not excessively sacrificed by the extension of the gate structures.

[0069] Fig. 19 is a flowchart illustrating a method 2000 for fabricating a semiconductor device according to embodiments of the present invention. The method 2000 includes a step 2010 of forming a plurality of first active regions on a wafer, each extending horizontally in a first direction. The first active regions include first fin structures, each protruding vertically upward above a substrate.

[0070] The method 2000 includes a step 2020 of depositing a dummy gate layer over the first fin structures.

[0071] The method 2000 includes a step 2030 of patterning the dummy gate layer into at least a first dummy gate structure through an etching process using an etchant. The etching process creates an etch byproduct comprising elements of the dummy gate layer and the etchant. The first dummy gate structure extends horizontally in a second direction that is different from the first direction.

[0072] The method 2000 includes a step 2040 of performing a cleaning process to remove the etching byproduct. No etching byproduct remains between the first fin structures after the cleaning process.

[0073] The method 2000 includes a step 2050 of replacing the first dummy gate structure with a metal-containing gate structure. The metal-containing gate structure essentially assumes the shape of the first dummy gate structure in a top view.

[0074] In some embodiments, patterning the dummy gate layer comprises forming a first end segment of the first dummy gate structure that extends beyond the first fin structures by a first distance, wherein the first distance is at least four times as long as a pitch of the first fin structures.

[0075] It should be understood that the method 2000 may include further steps performed before, during, or after steps 2010-2050. For example, the method 2000 may include a step of forming a plurality of second active regions on the wafer, each extending in the first direction. The method 2000 may further include a step of forming a second dummy gate structure over the second active regions. The second dummy gate structure extends in the second direction and includes a second end segment that extends beyond the second active regions in a plan view. The second end segment is formed differently in a plan view than the first end segment. In some embodiments, patterning the dummy gate layer includes tapering an end segment of the first dummy gate structure. In some embodiments, the second end segment is shorter in the second direction than the first end segment.In some embodiments, the second end segment is less tapered in plan view than the first end segment. In some embodiments, forming the second active regions comprises forming a plurality of second fin structures having a lower feature density than the first fin structures. In some embodiments, forming the second active regions comprises forming non-fin structures as the second active regions. Other steps may include forming vias, contacts, or metal layers, etc.

[0076] Fig.20 is a flowchart illustrating a method 2100 for facilitating the fabrication of a semiconductor device according to embodiments of the present invention. The method 2100 includes a step 2110 of obtaining a layout plan for an integrated circuit (IC). The IC layout plan includes a plurality of fin structures each extending in a first direction and a gate structure extending in a second direction different from the first direction. The gate structure overlaps the fin structures in a top view. The method 2100 includes a step 2120 of at least partially revising the IC layout plan by: extending an end segment of the gate structure in the second direction that extends beyond the fin structures; or reducing the end segment of the gate structure in the first direction.The method 2100 includes a step 2130 of facilitating the fabrication of a semiconductor device using the revised IC layout plan. For example, a lithography mask may be fabricated according to the revised IC layout plan, and semiconductor devices may be fabricated using the lithography mask.

[0077] In some embodiments, the extending is performed such that the distance between an outermost tip of the gate structure and a nearest fin structure is at least 4 times as long as an inter-pitch of the fin structures.

[0078] In some embodiments, reducing the size includes reducing a first portion of the end segment to a greater extent than a second portion of the end segment. The first portion is located farther from the fin structures than the second portion.

[0079] In some embodiments, revising the IC layout plan includes lengthening and shrinking the end segment of the gate structure.

[0080] It should be understood that method 2100 may include additional steps performed before, during, or after steps 2110-2130. For example, method 2100 may include steps for performing design rule checks on the IC layout plan, adding optical proximity correction (OPC) features to the IC layout plan, and / or performing other revisions to the IC layout plan, etc.

[0081] The advanced lithography process, method, and materials discussed above can be used in many applications, including fin field-effect transistors (FinFETs). For example, the fins can be patterned to create a relatively smaller spacing between features, for which the above invention is well-suited. Furthermore, spacers, also called mandrels, used in the fabrication of FinFET fins can be processed according to the above invention.

[0082] It should further be understood that the various aspects of the present invention discussed above are applicable to multi-channel devices such as gate-all-around (GAA) devices. Additional details regarding the fabrication of GAA devices are disclosed in U.S. Patent No. 10,164,012, entitled "Semiconductor Device and Manufacturing Method thereof," issued December 25, 2018, and U.S. Patent No. 10,361,278, entitled "Method of Manufacturing a Semiconductor Device and a Semiconductor Device," issued July 23, 2019, the inventions of each of which are incorporated herein by reference in their entirety. To the extent that the present invention relates to a fin structure or FinFET devices, these explanations may also be applicable to GAA devices.

[0083] In summary, the present invention optimizes a profile of the gate of a transistor by inwardly tapering the end segment of the gate and / or by extending the gate. Optimizing the gate profile may provide advantages over conventional devices. However, it should be understood that not all advantages are explained herein, different embodiments may provide different advantages, and no particular advantage is required for any embodiment. One advantage is that the present invention improves device performance and / or yield. For example, etch residues or byproducts may be generated during patterning of the dummy gate structures. A portion of the etch residues or byproduct (e.g., particles) may be trapped by the vertically protruding fin structures and difficult to remove during cleaning.If such residues or byproducts are still present at the time of replacing the dummy gates with high-k metal gates (HKMGs), the residues or byproducts may also be converted into HKMG-containing structures. These HKMG-containing structures may come into contact with IC device elements such as source / drain contacts, which may lead to electrical short circuits. In this case, by tapering the end segment of the gate or by extending the gate, any generated etch residue or byproduct can be further away from the fin structures, facilitating their removal during cleaning. And even if a portion of the residue or byproduct still remains after cleaning, the fact that they are further away from the fin structures (and also from the source / drain contacts to be formed) will reduce the risk of an electrical short circuit. Thus, device performance (e.g.,Voltage breakdown (VBD) and yield are improved. A further advantage is a larger etch window. For example, etching is performed during the definition of the dummy gate structures, and this etch window is now larger (e.g., can be performed over a longer period of time or is more flexible with regard to the etchant) because it is more likely that etch residues or by-products will be removed, and that remaining etch residues or by-products are less likely to cause electrical short circuits. Further advantages may be compatibility with existing manufacturing processes as well as simple and cost-effective implementation.

[0088] The invention is defined by the main claim and the independent claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Device comprising: a plurality of fin structures (120) each projecting vertically upward from a substrate (110) and each extending in a first direction (X) in a plan view; and a gate structure (300, 600, 1300) disposed over the fin structures (120), the gate structure (300, 600, 1300) extending in a second direction (Y) in plan view, the second direction (Y) being different from the first direction (X); wherein the fin structures (120) have a fin-to-fin spacing (210) equal to a sum of a dimension (230) of one of the fin structures (120) in the second direction and a spacing (220) between an adjacent pair of the fin structures (120) in the second direction (Y); wherein an end segment (300A, 600A, 1300A) of the gate structure (300, 600, 1300) extends in the second direction (Y) beyond an edge of a nearest fin structure of the fin structures (120); and wherein the end segment (300A, 600A, 1300A) has a tapered profile in plan view, wherein a dimension (320) of the end segment (300A, 600A, 1300A) continuously and gradually decreases as the end segment (300A, 600A, 1300A) extends further in the second direction (Y) beyond the fin structures (120). [2] Device according to claim 1, wherein the plurality of fin structures (120) are first fin structures (1110) having a first structure density; wherein the gate structure (1300) is a first gate structure (1300); wherein the device further comprises a plurality of second fin structures (1010) having a second structure density lower than the first structure density, and a second gate structure (1200) disposed over the second fin structures (1010); and an end segment (1200A) of the second gate structure (1200) has a different profile in plan view than the end segment (1300AA) of the first gate structure (1300). [3] The device of claim 2, wherein the end segment (1200A) of the second gate structure (1200) is longer than the end segment (1300A) of the first gate structure (1300). [4] The device of claim 2 or 3, wherein the end segment (1200A) of the second gate structure (1200) is at least four times as long in the second direction (Y) as the inter-fin pitch (1040) of the second fin structure (1010). [5] The device of claim 1, wherein the gate structure (300) comprises a body (300B) having a dimension (330) that remains constant in the first direction (X). [6] The device of claim 5, wherein the end segment (300A) has a first average width in the first direction (X) that is an average of all different dimensions (320) at different locations of the end segment (300A), and wherein the body (300B) has a second average width in the first direction (X) that is an average of all different dimensions (330) at different locations of the body (300B), wherein a ratio of the first average width to the second average width is between 0.5 and 0.

78. [7] Procedure comprising: Forming (2010) a plurality of first active regions on a wafer, each extending horizontally in a first direction (X), the first active regions having first fin structures (120) each projecting vertically upwards above a substrate (110); Depositing (2020) a dummy gate layer over the first fin structures (120); Structuring (2030) the dummy gate layer into at least one first dummy gate structure (300) by an etching process using an etchant, wherein the etching process produces an etching by-product (260) containing elements of the dummy gate layer and the etchant, and wherein an end segment (300A) of the first dummy gate structure (300) extends horizontally in a second direction (Y) beyond an edge of a nearest fin structure of the first fin structures (120), wherein the second direction (Y) is different from the first direction (X), wherein the end segment (300A) has a tapered profile in plan view, wherein a dimension (320) of the end segment (300A) continuously and gradually decreases as the end segment (300A) extends further in the second direction (Y) beyond the fin structures (120); Performing (2040) a cleaning process to remove the etching by-product (260), wherein no etching by-product (260) remains between the first fin structures (120) after the cleaning process is performed; and replacing (2050) the first dummy gate structure (300) with a metal-containing gate structure (600), wherein the metal-containing gate structure (600) substantially assumes a shape of the first dummy gate structure (300) in a plan view. [8] The method of claim 7, further comprising: Forming a plurality of second active regions on the wafer, each extending in the first direction (X); and Forming a second dummy gate structure (350; 400; 600; 900) over the second active regions, wherein the second dummy gate structure (350; 400; 600; 900) extends in the second direction (Y) and has a second end segment (350A; 400A; 600A; 900A) extending beyond the second active regions in plan view, and wherein the second end segment (350A; 400A; 600A; 900A) is formed differently in plan view than the first end segment (300A). [9] The method of claim 8, wherein patterning the dummy gate layer comprises: Tapering an end segment (300A) of the first dummy gate structure (300). [10] The method of claim 9, wherein the second end segment is shorter in the second direction than the first end segment. [11] A method according to claim 9 or 10, wherein the second end segment is less tapered in plan view than the first end segment. [12] The method of any one of claims 9 to 11, wherein forming the second active regions comprises: Forming a plurality of second fin structures (120) which have a lower structure density than the first fin structures (120). [13] A method according to any one of claims 9 to 12, wherein forming the second active regions comprises: Formation of non-fin structures as the second active regions. [14] Procedure comprising: Receiving (2110) a layout plan for an integrated circuit (IC), the IC layout plan comprising a plurality of fin structures (120) each extending in a first direction and a gate structure (300, 600) extending in a second direction (Y) different from the first direction (X), the gate structure (300, 600) overlapping the fin structures (120) in a plan view; and revising (2120) the IC layout plan at least in part by: Reducing the end segment (300A, 600A) of the gate structure (300, 600) in the first direction (X) such that the end segment (300A, 600A) has a tapered profile in plan view, wherein a dimension (320) of the end segment (300A, 600A) continuously and gradually decreases as the end segment (300A, 600A) extends further in the second direction (Y) beyond the fin structures (120). [15] The method of claim 14, wherein revising (2120) the IC layout plan further comprises: Extending an end segment (300A, 600A) of the gate structure (300, 600) in the second direction (Y) that extends beyond the fin structures (120).

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