Device with gate isolation area between gate stacks and method for their manufacture

Abstract

Method comprising: fabricating an active channel region in the form of a semiconductor fin (24'); fabricating a dummy channel region in the form of a dummy fin (25'); fabricating a first dielectric gate layer (32) over the active channel region (24'); fabricating a second dielectric gate layer (32) over the dummy channel region (25'), wherein the first dielectric gate layer (32) and the second dielectric gate layer (32) are deposited in a common deposition process; removing the second dielectric gate layer (32) from the dummy channel region (25'); fabricating a gate isolation region (52) over and in contact with the dummy channel region (25'); and manufacturing a first gate stack (158A) and a second gate stack (158B), wherein the first gate stack (158A) is arranged on the active channel area (24') and the gate isolation area (52) separates the first gate stack (158A) from the second gate stack (158B),wherein the first gate stack (158A) and the second gate stack (158B) comprise a first high-k dielectric (54) and a second high-k dielectric (54), respectively, wherein the first high-k dielectric (54) and the second high-k dielectric (54) each have a side wall portion that is in physical contact with the dummy channel region (25') and the gate isolation region (52), forming a first gate spacer (38) and a second gate spacer (38), wherein the gate isolation region (52), the first gate stack (158A) and the second gate stack (158B) are each located between and in contact with the first gate spacer (38) and the second gate spacer (38), wherein the gate isolation region (52) is formed after the first and the second gate spacer (38), and the first and the second high-k dielectric (54) is produced after the gate insulation region (52) has been manufactured.

Description

BackgroundMetal oxide semiconductor (MOS) devices are basic devices in integrated circuits. A MOS device may have a gate electrode made of polysilicon doped with p- or n-type dopants by means of doping processes such as ion implantation or thermal diffusion. A work function of a gate electrode may be adjusted to the band edge of silicon. For an n-type metal oxide semiconductor (NMOS) device, the work function may be adjusted to be close to the conduction band of silicon. For a p-type metal oxide semiconductor (PMOS) device, the work function may be adjusted to be close to the valence band of silicon. The work function of the polysilicon gate electrode may be adjusted by selecting suitable dopants.MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, also known as a polysilicon depletion effect. The polysilicon depletion effect occurs when the applied electric fields clear carriers from gate regions in the vicinity of gate dielectrics, thus creating depletion layers. In an n-doped polysilicon layer, the depletion layer has ionized non-mobile donor sites, while in a p-doped polysilicon layer, the depletion layer has ionized non-mobile acceptor sites. The depletion effect leads to an increase in the effective gate dielectric thickness, which makes it difficult for an inversion layer to be formed at the surface of the semiconductor.The problem of polysilicon depletion can be solved by fabricating metal gate electrodes, wherein the metal gates used in NMOS and PMOS devices may also have band-edge work functions. Accordingly, the resulting metal gates have a plurality of layers to meet the requirements of the NMOS and PMOS devices.The formation of metal gates typically includes: forming dummy gate dielectrics and dummy gate electrodes; removing the dummy gate dielectrics and dummy gate electrodes to form trenches; depositing high-k dielectric layers and metal layers into the trenches; and performing a chemical mechanical polishing (CMP) process to remove excess portions of the high-k dielectric layers and the metal layers. The remaining portions of the metal layers form metal gates.US 2020 / 0 105 613 A1 describes methods for scaling semiconductor devices having fins and a plurality of gate structures isolated from one another. In particular, US 2020 / 0 105 613 A1 discloses a method of forming a semiconductor device comprising: forming a first fin and a second fin projecting beyond a substrate; forming isolation regions on opposite sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, the recess extending into the metal gate from a top surface of the metal gate distal to the substrate, the recess having a top portion distal to the substrate and a bottom, the top portion having a first width and the bottom portion having a second width greater than the first width, the first width and the second width being measured along a longitudinal direction of the metal gate.U.S. Pat. No. 2019) / 0 189 804 A1 and U.S. Pat. No. 2017 / 0 125 411 A1 propose introducing separating elements into an insulation layer which is arranged between adjacent fins. In U.S. Pat. No. 2020 / 0 091 311 A1, dielectric fins with different dielectric layers are arranged between semiconductor fins.US 2019 / 0 067 417 A1 describes methods in which fin structures are formed in trenches of a dielectric.US 2011 / 0 159 678 A1 describes scaling methods for planar transistors.The invention is defined in the claims.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1-4, 5A, 5B, 6, 7A-1, 7A-2, 7B, 8A, 8B, 9A-1, 9A-2, and 9B show perspective and cross-sectional views of intermediate stages in the fabrication of fin field effect transistors (FinFETs), in accordance with some embodiments.FIGS. 10-13, 14-17, 18-21, and 22-25 show intermediate stages of various embodiments in the fabrication of dummy dielectric fins, in accordance with some embodiments.FIGS. 26-30, 31-35, and 36-40 show intermediate stages of various embodiments in the selective formation and removal of dummy gate dielectrics and in the formation of gate isolation regions, in accordance with some embodiments.FIGS. 41-44, 45-48, and 49-50 show intermediate stages of various embodiments in the selective fabrication and removal of dummy gate dielectrics, in accordance with some embodiments.FIGS. 51-53, 54-56, and 57-59 show intermediate stages of various embodiments in the selective fabrication and removal of dummy gate dielectrics, in accordance with some embodiments.FIGS. 60 and 61 show cross-sectional views of some portions of structures in accordance with some embodiments. FIG. 62 shows a cross-sectional view of a dummy fin and a gate isolation region, in accordance with some embodiments. FIG. 63 illustrates a process flow for forming transistors with selective removal of the dummy gate dielectrics prior to forming the gate isolation regions, in accordance with some embodiments.Detailed DescriptionThe following description provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. For example, in the description below, the formation of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein interpreted accordingly.In some embodiments, pre-removing dummy gate dielectrics from dummy dielectric fins and subsequently forming gate isolation regions and forming corresponding fin field effect transistors (FinFETs) are performed. Embodiments discussed herein are intended to provide examples to enable manufacture or use of the subject matter of the present invention, and those of ordinary skill in the art will readily appreciate modifications that may be made without departing from the intended scope of other embodiments. In all illustrations and illustrative embodiments, similar reference numerals are used to designate similar elements. Although method embodiments may be discussed as embodiments performed in a particular order, other method embodiments may be performed in any logical order.FIGS. 1-4, 5A, 5B, 6, 7A-1, 7A-2, 7B, 8A, 8B, 9A-1, 9A-2, and 9B show perspective and cross-sectional views of intermediate stages in the fabrication of FinFETs, gate isolation regions, and dummy dielectric fins, in accordance with some embodiments of the present invention. The corresponding steps are also schematically indicated in the process flow 300 shown in FIG. 63.FIG. 1 shows a perspective view of an initial structure. The initial structure comprises a wafer 10 which in turn comprises a substrate 20. The substrate 20 may be a semiconductor substrate that may be a silicon substrate, a silicon germanium substrate, or a substrate made of other semiconductor materials. The substrate 20 may be doped with a p- or an n-dopant. Isolation regions 22, such as shallow trench isolation (STI) regions, are formed to extend into the substrate 20 from a top surface of the substrate 20. The corresponding step is indicated as a step 302 in the process flow 300 shown in FIG. 63. The portions of the substrate 20 between adjacent STI regions 22 are referred to as semiconductor strips 24. In some embodiments of the present invention, the semiconductor strips 24 are portions of the original substrate 20, and thus the material of the semiconductor strips 24 is the same as that of the substrate 20. Accordingly, the semiconductor strips 24 are made of a different semiconductor material than that of the substrate 20. In some embodiments, the semiconductor strips 24 are made of Si, SiP, SiC, SiPC, SiGe, SiGeB, or Ge, or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like.The STI regions 22 may include an oxide liner (not individually shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The oxide film may also be a deposited silicon oxide film formed by, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDP-CVD), chemical vapor deposition (CVD), or the like. The STI regions 22 may also include a dielectric material over the oxide liner, where the dielectric material may be deposited by flowable CVD (FCVD), spin-on, or the like.FIG. 2 shows the formation of dummy dielectric strips 25 and the recessing of the STI regions 22, and the upper parts of the semiconductor strips 24 and the dummy dielectric strips 25 project above the upper sides of the STI regions 22, resulting in projecting (semiconductor) semiconductor regions 24' and a projecting (dielectric) dummy fin 25', respectively. The corresponding step is indicated as a step 304 in the process flow 300 shown in FIG. 63. The protruding fins 24' and the dummy protruding fin 25' may also be referred to as active channel regions 24' and a dummy channel region 25', respectively. The details for the formation of dummy dielectric strip 25 and dummy fin 25' will be described in more detail in the embodiments shown in Figures 10-13, 14-16, 18-21, and 22-25, discussed in later sections. In some embodiments of the present invention, the material of the dummy strip 25 is a silicon-based dielectric material, such as SiN, SiON, SiOCN, SiC, SiOC, SiO 2 or the like. In alternative embodiments of the present invention, the material of dummy strip 25 is a metal-based dielectric material (an oxide or nitride) such as TaN, TaO, HfO, or the like. The bottom surface of the dummy dielectric strip 25 may be higher than, at the same height as, and lower than the top surfaces of the STI regions 22, and may be at the same height as, or higher than, the bottom surfaces of the STI regions 22. The dummy fin 25' may have a single-layer structure or a multi-layer structure including a plurality of layers made of different materials.In some embodiments, the recessing of the STI regions 22 to form the protruding semiconductor fins 24' and the dummy dielectric fin 25' may be performed with a dry etch process using, for example, HF 3 and NH 3 as etch gases. In alternative embodiments, the recessing of the STI regions 22 is performed using a wet etching process. As the etching chemical, for example, an HF solution can be used.In the embodiments discussed above, the fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, such as dual-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes that can produce patterns having, for example, pitch spacings that are less than those that can otherwise be achieved with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers, or mandrels, may then be used to pattern the fins.In FIG. 3, dummy gate stacks 30 are formed on the top and side walls of protruding fins 24' and dummy fin 25'. The formation of dummy gate stacks 30 may include selectively forming gate dielectrics 32 on some of protruding fins 24' and dummy fins 25' as set forth in more detail in later paragraphs. The corresponding step is indicated as a step 306 in the process flow 300 shown in FIG. 63. Dummy fins 25' are therefore alternatively referred to as dummy channels. Dummy gate electrodes 34 are formed over dummy gate dielectrics 32. The corresponding step is indicated as a step 308 in the process flow 300 shown in FIG. 63. As will be discussed in more detail in the embodiments shown in FIGS. 26-40, dummy gate dielectrics 32 may be selectively removed from dummy fins 25' (see FIG. 7B ). However, gate dielectrics 32, which may be dummy gate dielectrics or real gate dielectrics in different device areas, remain on the protruding fins 24'. Accordingly, dummy gate electrodes 34 are formed on gate dielectrics 32 on protruding fins 24', while dummy gate electrodes 34 are in physical contact with dummy fins 25' on dummy fins 25'.Returning to Figure 3. The gate dielectrics 32 may be or include silicon oxide, silicon nitride, or the like. Depending on the fabrication process, the gate dielectrics 32 may or may not have horizontal portions on the STI regions 22. Dummy gate electrodes 34 may be formed using polysilicon or amorphous silicon, for example, but other materials may also be used. The dummy gate stacks 30 may also each include a hard mask layer 36 (or a plurality of hard mask layers 36) over the dummy gate electrode 34. The hard mask layers 36 may be made of silicon nitride, silicon oxide, silicon carbonitride, or multilayers thereof. Dummy gate stacks 30 may pass over only one or more of protruding fins 24', dummy fins 25' and STI regions 22. Dummy gate stacks 30 also have longitudinal directions that are perpendicular to longitudinal directions of protruding fins 24'.As also shown in FIG. 3, gate spacers 38 are then formed on the sidewalls of the dummy gate stacks 30. The corresponding step is indicated as a step 310 in the process flow 300 shown in FIG. 63. In some embodiments of the present invention, the gate spacers 38 are made of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.In some embodiments of the present invention, an etching process is performed to etch the portions of the protruding fins 24' not covered by the dummy gate stack 30 and the gate spacers 38 to form the structure shown in FIG. 4. The corresponding step is indicated as a step 312 in the process flow 300 shown in FIG. 63. The recessing may be anisotropic such that the portions of the fins 24' directly under the dummy gate stacks 30 are protected and not etched. The tops of the recessed semiconductor strips 24 may be lower than tops 22A of the STI regions 22 in some embodiments. The gaps left by the etched portions of the protruding fins 24' are referred to as recesses 40. In the etching process, the dummy dielectric fin 25' is not etched. The protruding fins 24' may be etched with, for example, a mixture of NF 3 and NH 3, a mixture of HF and NH 3, or the like.Then, epitaxial regions (source / drain regions) 42 are formed by selectively growing a semiconductor material from the recesses 40, thereby forming the structure shown in FIG. 5A. The corresponding step is indicated as a step 314 in the process flow 300 shown in FIG. 63. In some embodiments, the epitaxy regions 42 include silicon germanium, silicon, silicon carbon, or the like. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p- or an n-type dopant may be doped in situ during epitaxy. For example, when the resulting FinFET is a p-type FinFET, SiB, silicon germanium boron (SiGeB), GeB, or the like may be grown. On the other hand, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown. In alternative embodiments of the present invention, epitaxial regions 42 are formed from a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AltPS, or GaP, a combination thereof, or the like. After the epitaxy regions 42 completely fill the recesses 40, the epitaxy regions 42 may begin to expand horizontally and slopes may be formed.FIG. 5B illustrates the formation of source / drain cladding regions 42 in accordance with alternative embodiments of the present invention. In these embodiments, protruding fins 24' shown in FIG. 4 are not recessed, but epitaxial regions 41 are grown on protruding fins 24'. Depending on whether the resulting FinFET is a p- or an n-type FinFET, the material of the epitaxy regions 41 may be similar to the epitaxial semiconductor material 42 shown in FIG. 5A. Thus, the source / drain regions 42 include the protruding fins 24' and the epitaxial region 41.FIG. 6 shows a perspective illustration of the structure after formation of a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48, which step is indicated as a step 316 in the process flow 300 shown in FIG. 63. The CESL 46 may be made of silicon nitride, silicon carbonitride, or the like. The CESL 46 may be formed using a conformal deposition process such as ALD or CVD. The ILD 48 may be a dielectric material deposited by, for example, FCVD, spin coating, CVD, or other deposition method. The ILD 48 may also be made of or include an oxygen-containing dielectric material, which may be silicon oxide-based, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (bond pads), or the like. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to level tops of the ILD 48, dummy gate stacks 30, and gate spacers 38. In some embodiments of the present invention, the planarization process ends on the tops of the hard masks 36. In alternative embodiments, the hard masks 36 are also removed during the planarization process, and the planarization process ends on the tops of the dummy gate electrodes 34.FIGS. 7A-1 and 7A-2 show a device area 100 and 200, respectively, in wafer 10 (and in the same die) and the structure fabricated therein. In some embodiments, device portion 100 includes, among other things, a core device portion (sometimes referred to as a logic device portion), and device portion 200 includes, among other things, an input / output (I / O) device portion. Thus, in some embodiments, the FinFETs fabricated in device region 100 and device region 200 may be a core FinFET and an I / O FinFET, respectively.To distinguish the structural elements in the device area 100 from the structural elements in the device area 200, the structural elements in the device area 100 may be represented using the reference numerals of the corresponding structural elements in FIG. 6 plus the number 100, and the structural elements in the device area 200 may be represented using the reference numerals of the corresponding structural elements in FIG. 6 plus the number 200. For example, source / drain regions 142 and 242 in FIGS. 7A-1 and 7A-2, respectively, correspond to source / drain region 42 of FIG. 6. The respective structural elements in the device region 100 and the device region 200 may be manufactured in common processes.In FIGS. 7A-1 and 7A-2, a dummy gate cutting process is performed by etching dummy gate stacks 130 and 230 to create openings 150 and 250, respectively, also collectively referred to as openings 50. The corresponding step is indicated as a step 318 in the process flow 300 shown in FIG. 63. The dummy gate stacks 130 and 230 are thus each cut into discrete parts. To perform the dummy gate cutting process, an etch mask (not shown), which may be a photoresist, may be formed and patterned and then used to etch the dummy gate stacks 130 and 230.FIG. 7B is a sectional view obtained from a portion 7B- 7B shown in each of FIGS. 7A- 1 and 7A- 2. In the dummy gate cutting process, the dummy gate stacks 30 are etched in anisotropic etching processes until the dummy dielectric fin 25' is exposed. This removes a portion of the dummy gate stack 30. Thus, a long dummy gate stack 30 is cut into two discrete parts 30A and 30B that are separated from each other. Each discrete portion 30A and 30B of dummy gate stack 30 may pass over one, two, or more protruding fins 24' to produce an in-fin FinFET or a multi-fin FinFET. After etching the dummy gate stacks 30, the etch mask may be removed in a stripping process, for example.Then, the openings 50 are filled with one or more dielectric regions to form gate isolation regions 152 and 252 (collectively referred to as gate isolation regions 52) shown in FIGS. 8A and 8B. Gate isolation regions 152 and 252 are formed in device regions 100 and 200, respectively, and are individually shown in FIGS. 9A-1 and 9A-2, respectively. The corresponding step is indicated as a step 320 in the process flow 300 shown in FIG. 63. The fabrication process includes depositing one or more dielectric materials and performing a planarization process, such as a CMP. The deposition process may be performed using a method selected from the group consisting of atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), gravure chemical vapor deposition (LPCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other suitable deposition methods. The gate isolation regions 152 and 252 may have a single-layer structure made of a homogeneous dielectric material or a multi-layer structure including a plurality of layers made of different materials. The dielectric materials may include, but are not limited to, oxide-based dielectric materials, nitride-based dielectric materials, oxynitride-based dielectric materials, oxide carbide-based dielectric materials, carbide-based dielectric materials, etc.As set forth above, the gate dielectric 32 has been removed from the dummy fin 25'. Accordingly, the gate isolation regions 52 physically contact the dummy fin 25'. On the other hand, the protruding fins 24' still have the gate dielectrics 32 thereon.Then, the dummy gate stacks 30A and 30B are etched, and the hard masks 36 and the dummy gate electrodes 34 are removed. In device region 100, gate dielectric 32 is removed (and thus was a dummy gate dielectric) and is replaced with a core gate oxide, while in region 102, gate dielectric 32 is not removed during this process and is exposed after the removal of dummy gate electrodes 34 shown in FIGS. 29, 34, and 39, which will be discussed in more detail in later paragraphs.Replacement gate stacks 158 and 258 (collectively referred to as 58) are then formed in device regions 100 and 200, respectively. The corresponding step is indicated as a step 322 in the process flow 300 shown in FIG. 63. The resulting structure is shown in Figs. 9A-1, 9A-2 and 9B. The gate stacks 158 and 258 include high-k dielectrics 154 and 254 (collectively referred to as 54) and replacement gate electrodes 156 and 256 (collectively referred to as 56). The high-k dielectrics 54 may be made of hafnium oxide, zirconium oxide, lanthanum oxide, or the like. The gate electrodes 56 may have a composite structure including a plurality of layers made of TiN, TaN, TiAl, TaAlC, Co, Al, or the like. The respective metals and structure are selected such that the resulting replacement gate electrodes 156 and 256 have suitable work functions. Thus, FinFETs 160A and 160B are formed in the device region 100 as shown in FIGS. 9A-1 and 9A-2. In addition, FinFETs 260A and 260B are formed in the device region 200 as shown in FIGS. 9A-2 and 9B.The previous figures show a short process flow for forming dummy fins 25' and corresponding FinFETs. Details of some processes that have been briefly addressed in the previous figures are presented and discussed in later figures and paragraphs.FIGS. 10-13, 14-17, 18-21, and 22-25 show the details of the formation of dummy strips 25 and dummy fins 25' in accordance with some embodiments. The processes shown in these figures may correspond to the processes shown in FIGS. 1 and 2. It should be understood that FIGS. 10-25 only show the features in a region 11 of FIG. 2, and the features underlying them, such as STI regions 22 and substrate 20, are not shown. These structural elements can be identified with reference to FIGS. 1 and 2.FIGS. 10 to 13 show the production of the dummy strips 25 by deposition and structuring. In FIG. 10, semiconductor stripes 24 are formed by etching the substrate 20, and trenches 13 are formed between the semiconductor stripes 24. The structure shown in FIG. 10 is formed prior to the formation of the STI regions 22 shown in FIG. 1. Then, in FIG. 11, a dielectric layer 25 is formed by deposition, and then a planarization process for planarizing the top surface thereof is performed. The material for the dielectric region 25 has been discussed above with reference to FIG. 2. The dielectric layer 25 is patterned to form a dummy dielectric strip 25, as shown in FIG. 12. Prior to the patterning process, an etch back process may be performed to lower the top of the dielectric region 25. In a later process, the STI regions 22 are formed to fill the trenches 13 and then recessed to form protruding fins 24' and dummy fins 25'. It should be understood that the order of the processes shown in FIGS. 14-17 differs slightly from the order of the processes shown in FIGS. 1 and 2 in terms of whether the STI regions 22 are first formed or whether the dummy dielectric strip 25 is first formed.FIGS. 14-17 illustrate the formation of dummy strips 25 and dummy fin 25' in accordance with alternative embodiments in which semiconductor strip 24 is etched and then refilled. FIGS. 14 and 15 show the process for manufacturing the structure shown in FIG. 1. In Figure 14, the substrate 20 is etched to form the semiconductor strips 24, forming trenches 13 between the semiconductor strips 24. Then, the trenches 13 are filled to form the STI regions 22. FIG. 16 illustrates the recessing of the semiconductor stripe 24 to create a trench 15 between adjacent STI regions 22. In a subsequent process, a dielectric material is filled into trench 15 to form dummy stripe 25, and STI regions 22 are subsequently recessed to form protruding fins 24' and dummy fin 25'.FIGS. 18-21 show the formation of dummy strips 25 in accordance with alternative embodiments, where the formation process includes conformal deposition of STI regions 22 and a dielectric fill process. FIG. 18 shows the production of semiconductor strips 24 and trenches 13 comprising etching a semiconductor substrate 20 for producing the semiconductor strips 24, wherein the trenches 13 are produced between adjacent semiconductor strips 24. In Fig. 19, a dielectric material is deposited. The dielectric material is the same material used to form the STI regions 22, and is therefore referred to as a dielectric material 22. In some embodiments, the dielectric material 22 is deposited using a conformal deposition process such as ALD, CVD, or the like, such that surfaces of the dielectric material 22 follow the topology of the protruding fins 24'. This creates a trench 15 in the dielectric material 22, and in FIG. 20, the dummy stripe 25 is formed in the STI region 22, which includes a deposition process, a planarization process, and an etch-back process. Dummy stripe 25 and STI regions 22 are made of different dielectric materials. FIG. 21 shows etching back of dummy strip 25 and recessing of STI regions 22 to form protruding fins 24' and dummy fin 25'. In the resulting structure, the dummy stripe 25 is formed directly on a part of the STI region 22.FIGS. 22-25 illustrate the formation of dummy strips 25 and dummy fin 25' in accordance with alternative embodiments in which the dielectric layer is etched and filled to form STI region 22. FIG. 22 shows the production of semiconductor strips 24 and trenches 13 comprising etching the semiconductor substrate 20 to produce the semiconductor strips 24, wherein the trenches 13 are produced between the semiconductor strips 24. The process is substantially the same as that shown in FIG. 10. In Fig. 23, a dielectric material is deposited. The dielectric material is the same material used to form the STI regions 22, and is therefore referred to as dielectric material 22. Then, a trench 15 is formed by etching the dielectric material 22, as shown in FIG. 24. Then, a dummy stripe 25 (FIG. 25 ) is formed in the trench 15. The formation of the dummy strip 25 may include a deposition process, a planarization process, and an etch back process. Dummy stripe 25 and STI regions 22 are made of different dielectric materials. Then, the dielectric material 22 is etched back to form the STI regions 22, as shown. In these embodiments, dummy stripe 25 is formed directly over a portion of STI region 22.FIGS. 26-30, 31-35 and 36-40 illustrate several different embodiments including dummy gate formation and replacement of dummy gates with replacement gates, and formation of gate isolation regions 52 on a dummy fin 25'. The processes shown in Figs. 26 to 40 correspond to the processes shown in Figs. 3 and 4, 5A, 5B, 6, 7A-1, 7A-2, 7B, 8A, 8B, 9A-1, 9A-2 and 9B. In each of Figs. 26 to 30, 31 to 35 and 36 to 40 and in subsequent figures, four portions and the corresponding sectional views are shown. The cross-sectional views are obtained from regions 100-channel, 200-channel, 100-non-iso and 100-iso. The cross-section 100 channel is obtained from the channel in the device area 100 shown in FIGS. 9A-1. The cross section 200 channel is obtained from the channel in the device area 200 shown in FIGS. 9A-2. The cross-section 100-non-iso is obtained from a portion of the device region 100 that passes through the dummy fin 25' but not through the gate isolation region 52, as shown in FIGS. 9A-1. The cross-section 100-iso passes through the gate isolation region 52 as shown in FIGS. 9A-1.FIGS. 26-30 show cross-sectional views of a manufacturing process, in accordance with some embodiments. In Figure 26, protruding fins 24' and dummy fins 25' are formed. The structure also corresponds to the structure shown in FIG. 2. Then, in FIG. 27, dummy gate dielectrics 32 are selectively formed on protruding fins 24' but not on dummy fins 25'. This process corresponds to the process shown in FIG. 3. The processes for manufacturing the structure shown in FIG. 27 will be explained in detail in the embodiments shown in FIGS. 41 to 44. As a material for the dummy gate dielectric 32, silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials may be used.FIG. 28 illustrates the formation of a dummy gate electrode 34, which may be formed of or include polysilicon, amorphous silicon, or other types of materials. This process also corresponds to the process shown in FIG. 3. It should be appreciated that in cross-sections 100-channel and 200-channel, dummy gate electrodes 34 are separated from corresponding protruding fins 24' by gate dielectrics 32, while in cross-sections 100-non-iso and 100-iso dummy gate electrode 34 is in physical contact with dummy fin 25'. As also shown in FIG. 28, a gate isolation region 52 is then formed to contact the underlying dummy fin 25'. This process corresponds to the processes shown in FIGS. 7A-1, 7A-2, 7B, 8A and 8B.Figure 29 illustrates the removal of dummy gate electrodes 34. As also shown in Figure 29, dummy gate dielectric 32 (132) (see Figure 28) is then removed from device region 100, and a gate dielectric 132' is formed, shown in cross-section 100 channel. The gate dielectric 232 in the cross-section 200 channel remains. Therefore, the gate dielectric 232 is used as the real gate dielectric of the corresponding FinFET. The details of the process shown in Fig. 29 are set forth in the embodiments shown in Figs. 51 to 53.FIG. 30 illustrates the fabrication of high-k dielectrics 154 and 254 and replacement gate electrodes 156 and 256 forming replacement gate stacks 158 and 258. This process corresponds to the process shown in Figs. 9A-1, 9A-2 and 9B. As shown in cross-section 100-iso of FIG. 30, dummy fin 25' contacts overlying gate isolation region 52 to completely separate replacement gate stack 158A from replacement gate stack 158B. However, if dummy gate dielectric 32 is not removed from dummy fin 25' before gate isolation region 52 is formed, dummy gate dielectric 32 is removed in the process shown in FIG. 29, and a gap is formed between dummy fin 25' and gate isolation region 52 above it. The material for the replacement gate electrode 56 may be filled into the gap, resulting in a creepage path between the gate stacks 158A and 158B. In some embodiments of the present invention, the dummy gate dielectric is selectively removed from the dummy fin 25' prior to forming the gate isolation region, thereby eliminating the creepage path.FIGS. 31-35 show cross-sectional views of the manufacturing process according to alternative embodiments. These embodiments are similar to the embodiments shown in Figures 26-30, except that a gate dielectric layer is present in the 100 non-iso (Figure 34). In Figure 31, protruding fins 24' and dummy fins 25' are formed. As shown in FIG. 32, dummy gate dielectrics 32 are subsequently formed. In contrast to the embodiment shown in FIG. 27, the dummy gate dielectric 32 remains on the portion of the dummy fin 25' in the cross-section 100 non-iso. The details of the production of the structure of Fig. 32 are set forth in the processes shown in Figs. 45 to 48. FIG. 33 illustrates the formation of dummy gate electrodes 34. In addition, the dummy gate dielectric 132 is removed from the device region 100 (cross-section 100 channel) and is replaced with a replacement dielectric layer 132' by, for example, deposition, natural oxidation, or the like. Meanwhile, a gate dielectric 132" is formed on the dummy fin 25' and in the cross section 100 non-iso. The details of the fabrication of the structure of Fig. 34 are set forth in the processes shown in Figs. 54 to 56. FIG. 35 illustrates the fabrication of replacement gates 58.FIGS. 36-40 are sectional views of the fabrication process in accordance with alternative embodiments. These embodiments are similar to the embodiments shown in Figures 26-30, except that dummy gate dielectrics 32 are formed by oxidizing surface portions of protruding fins 24'. In Figure 36, protruding fins 24' and dummy fins 25' are formed. Next, as shown in FIG. 37, the dummy gate dielectrics 32 are formed. The details of manufacturing the structure of FIG. 37 are set forth in the processes shown in FIGS. 49 and 50. FIG. 38 illustrates the formation of dummy gate electrodes 34. In addition, the dummy gate dielectric 132 is removed from the device region 100 (cross-section 100 channel) and is replaced with a replacement dielectric layer 132' by, for example, deposition, natural oxidation, or the like. The details of the production of the structure of Fig. 39 are set forth in the processes shown in Figs. 57 to 59. FIG. 40 illustrates the fabrication of the replacement gates 58.Figures 41-44 show the processes for forming and then selectively removing gate dielectrics. The method can be adapted to produce the structure shown in Fig. 27. Fig. 41 shows the initial structure also shown in Fig. 26. Then, as shown in FIG. 42, the dummy gate dielectrics 32 are formed in the device regions 100 and 200, and therefore, cover all parts of the protruding fins 24' and the dummy fins 25' in the cross sections 100-channel, 200-channel, 100-non-iso, and 100-iso. In FIG. 43, an etch mask 66, which may be made of a photoresist, is formed to cover channel portions of the dummy gate dielectrics 32, which channel portions in turn cover the protruding fins 24' in the device regions 100 and 200, while the portions of the dummy gate dielectrics 32 covering the dummy fins 25' remain exposed by the etch mask 66. Then, the exposed portions of the dummy gate dielectrics 32 on the dummy fins 25' are removed. Subsequently, the etching mask 66 is also removed, and the resulting structure is shown in FIG. 44.Figures 45-48 illustrate the processes for forming and then selectively removing the gate dielectrics. The method can be adapted to form the structure shown in FIG. 32. Fig. 45 shows the initial structure also shown in Fig. 31. Then, as shown in FIG. 46, the dummy gate dielectrics 32 are formed in the device regions 100 and 200, and therefore, cover all parts of the protruding fins 24' and the dummy fins 25' in the cross sections (regions) 100-channel, 200-channel, 100-non-iso, and 100-iso. In FIG. 47, an etch mask 66, which may be made of a photoresist, is formed to cover channel portions of the dummy gate dielectrics 32, which channel portions in turn cover the protruding fins 24' in the device regions 100 and 200. The portion of dummy gate dielectrics 32 in cross-section 100-non-iso is also covered, while the portion of dummy gate dielectric 32 covering dummy fins 25' in cross-section 100-iso remains exposed by etch mask 66. Then, the exposed portions of the dummy gate dielectrics 32 are removed. Subsequently, the etching mask 66 is also removed, and the resulting structure is shown in FIG. 48.The processes shown in Figs. 41 to 48 require additional photolithography processes. However, a thickness of the resultant gate dielectrics 32 may be set to desired values.FIGS. 49 and 50 show processes for selectively forming gate dielectrics in accordance with some embodiments. The method can be adapted to produce the structure shown in Fig. 37. Fig. 49 shows the initial structure also shown in Fig. 36. Then, as shown in FIG. 50, dummy gate dielectrics 32 are formed on the protruding fins 24', and the exposed surface layer (made of, for example, Si, SiGe, or the like) of each of the protruding fins 24' is converted into a dielectric layer 32 comprising silicon oxide (SiO 2), SiN, SiCN, or the like. The surface layers of dummy fins 25' remain dielectric, and therefore the surface layer is not individually illustrated, although elements such as oxygen, nitrogen, carbon, and / or the like may be added to the surface layers. The conversion can be achieved by thermal oxidation, thermal nitration, chemical oxidation or the like. The thermal oxidation may be performed using, for example, O 2, SO 2, CO 2, CO, or similar process gases, or combinations thereof. The thermal nitration may be performed using N 2, NH 3 or similar process gases or combinations thereof. The resulting gate dielectric 32 may have a thickness of about 0.3 nm (3 Å) to about 5 nm (50 Å). The processes shown in Figs. 49 and 50 have the advantage that photolithographic steps are omitted. However, the thickness of the resulting dummy gate dielectric 32 is limited.Figures 51-53, 54-56, and 57-59 show some processes for selectively replacing the gate dielectric in device region 100 (e.g., the core region) while gate dielectric 232 remains in device region 200 (e.g., the I / O region) as the real gate dielectric.Figures 51-53 show an embodiment in which no gate dielectric is formed on dummy fins 25'. The method can be adapted to produce the structure shown in Fig. 29. FIG. 51 may correspond to the structure shown in FIG. 28, except that the dummy gate electrodes 34 shown in FIG. 28 have been removed. As shown in FIG. 52, an etch mask 68, which may be a photoresist, is then formed and patterned to cover the device region 200 (cross-section 200 channel), while leaving the device region 100 (comprising the portions appearing in the cross-sections 100 channel, 100 non-iso, and 100 iso) exposed. Then, the dummy gate dielectric 132 is removed and is replaced with a gate dielectric 132', also shown in FIG. 52. The gate dielectric 132' may be a native oxide or may be formed using a deposition or oxidation process. The thickness may be about 0.3 nm (3 Å) to about 10 nm (100 Å). Subsequently, the etching mask 68 is removed, and the resulting structure is shown in FIG. 53.Figures 54-56 show an embodiment in which a thin gate dielectric is formed on the portion of dummy fin 25' in cross section 100-non-iso, but not on the portion of dummy fin 25' in cross section 100-iso. The method can be adapted to produce the structure shown in Fig. 34. FIG. 54 may correspond to the structure shown in FIG. 33, except that the dummy gate electrodes 34 shown in FIG. 33 have been removed. Then, as shown in FIG. 55, an etching mask 68 is formed and patterned to cover the device region 200 (cross section 200 channel), while the device region 100 (including the parts appearing in the cross sections 100 channel, 100 non-iso, and 100 iso) remains exposed. Then, as shown in Fig. 54, the dummy gate dielectric 132 is removed and is replaced with a gate dielectric 132' also shown in Fig. 55. In addition, a gate dielectric 132" is formed in the 100 non-iso cross section. The manufacturing process may be performed with a deposition process. The gate dielectrics 132' and 132" may be made of or include silicon oxide, silicon nitride, or the like. Subsequently, the etching mask 68 is removed, and the resulting structure is shown in FIG. 56.FIGS. 57 to 59 show an embodiment similar to the embodiment shown in FIGS. 51 to 53 except that the dummy gate dielectrics 32 are formed by oxidation, nitriding, or the like. The method can be adapted to form the structure shown in Fig. 39. FIG. 57 may correspond to the structure shown in FIG. 38 except that the dummy gate electrodes 34 shown in FIG. 38 have been removed. Then, as shown in Fig. 58, an etching mask 68 is formed. Subsequently, as shown in Figure 57, the dummy gate dielectric 132 is removed and replaced with a gate dielectric 132', also shown in Figure 58. Then, the etching mask 68 is removed, and the resultant structure is shown in Fig. 59.FIG. 60 shows cross sections of gate structures, the cross sections being obtained from the structure shown in FIGS. 9A-1, 9A-2, and 9B, and also shown in FIGS. 30 and 40. Sidewall thicknesses of dielectric layers 132', 232, 132" (if present) and 132"' (if present) are designated CDS1, CDS2, CDS3 and CDS4, respectively. Top thicknesses of dielectric layers 132', 232, 132" (if present) and 132"' (if present) are designated CDT1, CDT2, CDT3, and CDT4, respectively.In some embodiments, there are relationships CDS1>CDS3and CDS1>CDS4. In addition, there may be relationships CDT1>CDT3, CTD3=CDT4, CDS1<CDS2, and CDT1<CDT2. Ratios of CDS2 / CDS1and CDT2 / CDT1may be greater than about 2 and may be about 5 to about 10. The thicknesses CDT3, CDT4, CDS3, and CDS4 may be zero (if the respective dielectric layers 132" and / or 132"' are absent) or may be equal to the thickness of the native oxide (about 0.3 nm (3 Å), namely, 0.2 nm (2 Å) to about 0.4 nm (4 Å)).FIG. 61 shows cross sections of gate structures, the cross sections being obtained from the structure shown in FIGS. 9A-1, 9A-2, and 9B, and also shown in FIG. 35. In some embodiments, the thickness CDS 1 is equal to or nearly equal to the thickness CDS 3, and a relationship of CDS 3>CDS 4 may exist. The thickness CDT 1 is equal to or nearly equal to the thickness CDT 3, and relationships CDT 1<CDT 2 and CDT 3>CDT 4 may exist. In addition, relationships CDS 1<CDS 2 and CDT 1<CDT 2 may exist. Ratios of CDS2 / CDS1and CDT2 / CDT1may be greater than about 2 and may be about 5 to about 10. In FIGS. 61 and 62, the thicknesses CDS 1, CDT 1, CDS 3, CDT 3, CDS 4, and CDT 4 may be about 0.3 nm (3 Å) (in a native oxide) to about 10 nm (100 Å), respectively. CDS2 and CDT2 may each be about 1 nm (10 Å) to about 10 nm (100 Å).FIG. 62 shows a cross-sectional view of the gate isolation region 152 and the dummy fin 125', in accordance with some embodiments. By the fabrication process of the present invention, due to the selective removal of the dummy gate dielectric 32 performed prior to the formation of the gate isolation region 152, a central surface portion of the dummy fin 25' may be recessed deeper than opposing portions. The gate isolation region 152 correspondingly extends into the recess in the dummy fin 125'. Also, lower corners 53 of the gate isolation region 152 have right angles (90°).The embodiments of the present invention have several advantages. Removing the dummy gate dielectrics from the dummy fins prior to forming gate isolation regions does not create gaps between the dummy fins and the overlying gate isolation regions. If gaps are formed between the gate isolation regions and the dummy fins located thereunder by the removal of the dummy gate dielectrics, these can be filled with the materials of the replacement gate electrodes. This creates a leak between the replacement gate electrodes on the opposing sides of the corresponding gate isolation region and the dummy fins. Thus, embodiments of the present invention eliminate the risk of leakage.

Claims

A method comprising: forming an active channel region in the form of a semiconductor fin (24'); forming a dummy channel region in the form of a dummy fin (25'); forming a first gate dielectric layer (32) over the active channel region (24'); forming a second gate dielectric layer (32) over the dummy channel region (25'), wherein the first gate dielectric layer (32) and the second gate dielectric layer (32) are deposited in a common deposition process; removing the second gate dielectric layer (32) from the dummy channel region (25'); forming a gate isolation region (52) over and in contact with the dummy channel region (25'); and forming a first gate stack (158A) and a second gate stack (158B), wherein the first gate stack (158A) is disposed on the active channel region (24'), and the gate isolation region (52) separates the first gate stack (158A) from the second gate stack (158B), the first gate stack (158A) and the second gate stack (158B) comprising a first high-k dielectric (54) and a second high-k dielectric (54), respectively, the first high-k dielectric (54) and the second high-k dielectric (54) each having a sidewall portion in physical contact with the dummy channel region (25') and the gate isolation region (52), forming a first gate spacer (38) and a second gate spacer (38), the gate isolation region (52), the first gate stack (158A) and the second gate stack (158B) are each interposed between and in contact with the first gate spacer (38) and the second gate spacer (38), wherein the gate isolation region (52) is formed after the first and second gate spacers (38), and the first and second high-k dielectric materials (54) are formed after the formation of the gate isolation region (52).The method of claim 1, further comprising: after removing the second gate dielectric layer (32), forming a dummy gate electrode (34) over the dummy channel region (25'); and patterning the dummy gate electrode (34) to form an opening (50), wherein the gate isolation region (52) is formed in the opening (50).The method of claim 2, further comprising removing the dummy gate electrode (34) after forming the gate isolation region (52).The method of any preceding claim, further comprising: removing the first gate dielectric layer (32) from the active channel region (24'); and forming a replacement gate dielectric layer (32') on the active channel region (24').The method of any preceding claim, wherein the dummy channel region (25') comprises: a first portion, the second gate dielectric layer (32) being removed from the first portion; and a second portion, the second gate dielectric layer (32) remaining on the second portion at a time after being removed from the first portion.The method of claim 5, wherein the first portion is between the first gate stack (158A) and the second gate stack (158B), and the method further comprises forming a first source / drain region (42) and a second source / drain region (42) on opposite sides of the second portion.A device comprising: a dummy fin (25') having a first portion and a second portion, the dummy fin (25') comprising a dielectric material; a gate isolation region (52) over and in contact with the dummy fin (25'); a first gate stack (158A) and a second gate stack (158B) on opposite sides of and in contact with the first portion of the dummy fin (25'), the first gate stack (158A) and the second gate stack (158B) including a first high-k dielectric (54) and a second high-k dielectric (54), respectively, the first high-k dielectric (54) and the second high-k dielectric (54) each having a sidewall portion in physical contact with the dummy fin (25') and the gate isolation region (52); a contact etch stop layer (46) on opposite sidewalls and a top surface of the second portion of the dummy fin (25'); and an interlayer dielectric (48) over the contact etch stop layer (46), wherein the sidewall portions of the first and second high-k dielectric (54) are on sidewalls of the dummy fin (25') and the gate isolation region, respectively, and the gate isolation region (52) extends into a recess in the dummy fin (25').The apparatus of claim 7, wherein the first gate stack (158A) and the second gate stack (158B) are portions of a first fin field effect transistor, FinFET, and a second FinFET, respectively.The device of claim 8, wherein the first FinFET has a first gate dielectric (132') with a first silicon oxide layer, and the device further comprises a third FinFET comprising: a protruding semiconductor fin (24'); and a second gate dielectric (132') over and in contact with the protruding semiconductor fin (24'), wherein the second gate dielectric (132') has a second silicon oxide layer thicker than the first silicon oxide layer.The device of any of claims 7 to 9, wherein the dummy fin (25') and the gate isolation region (52) are made of different materials.The device of any of claims 7 to 10, wherein the gate isolation region (52) extends laterally beyond edges of the dummy fin (25'), and the gate isolation region (52) has lower corners (53) at right angles.An apparatus comprising: a semiconductor substrate (20); isolation regions (22) extending into the semiconductor substrate (20); a first protruding semiconductor fin (24') and a second protruding semiconductor fin (24') parallel to each other and protruding beyond the isolation regions (22); a dummy fin (25') between the first protruding semiconductor fin (24') and the second protruding semiconductor fin (24'); a first gate stack (158A) and a second gate stack (158B) extending on top and side walls of the first protruding semiconductor fin (24') and the second protruding semiconductor fin (24'), respectively; and a gate isolation region (52) between the first gate stack (158A) and the second gate stack (158B), the gate isolation region (52) being disposed over and in contact with the dummy fin (25'), the first gate stack (158A) and the second gate stack (158B) including a first high-k dielectric (54) and a second high-k dielectric (54), respectively, the first high-k dielectric (54) and the second high-k dielectric (54) each having a sidewall portion in physical contact with the dummy fin (25') and the gate isolation region (52); wherein the sidewall portions of the first and second high-k dielectric (54) are on sidewalls of the dummy fin (25') and the gate isolation region (52), respectively, and the gate isolation region (52) extends into a recess in the dummy fin (25').The device of claim 12, further comprising a first gate spacer (38) and a second gate spacer (38), wherein the gate isolation region (52), the first gate stack (158A), and the second gate stack (158B) are respectively disposed between and in contact with the first gate spacer (38) and the second gate spacer (38).The device of claim 12 or 13, further comprising: a contact etch stop layer (46) contacting opposite sidewalls of the dummy fin (25'); and an interlayer dielectric (48) over the contact etch stop layer (46).

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