METHOD FOR FILTERING REFERENCE VOLTAGE NOISE

Abstract

Circuit comprising: a converter (200) that receives an input voltage (Vin) at an input terminal and compares the input voltage with a reference voltage (Vref1) received at a reference terminal (REF) from a reference voltage circuit (210); a resistor (410) connected at a first end (REF_IN) to the reference voltage circuit and at a second end to the reference terminal of the converter; and a reference gain tuning circuit with a memory (430) that stores a scale factor (scale_fac) with a value chosen to compensate for a gain error caused by a voltage drop across the resistor when the reference voltage (Vref) is applied to the first end of the resistor, and with a multiplier (440) that multiplies an output signal (Dout) of the converter by the scale factor.

Description

AREA OF REVELATION This document relates to a device for filtering external reference noise for any circuit having a constant reference load current, and in particular to a reference voltage noise filter for analog-to-digital converters or digital-to-analog converters, wherein the reference current is a constant load. BACKGROUND Analog-to-digital converters (ADCs), and in particular continuous-time sigma-delta modulators (CTSDMs), are gaining popularity due to their energy-efficient operation, making them well-suited for high-speed and high-performance systems. In a CTSDM, a time-varying analog input signal is typically converted into a digital data stream that represents the input signal in the frequency band of interest with high fidelity. This digital data stream then undergoes digital post-processing (typically decimation) to produce the final digital code stream, which represents the analog input signal in the digital domain with high fidelity. However, one solution employed by CTSDMs is the use of a current-to-digital-to-analog converter (DAC) in a feedback path, which can suffer from input-dependent reference errors. Although techniques such as quadruple switching have been used to address such errors, CTSDMs, as well as other ADCs and DACs, are also susceptible to external reference noise. For example, the values ​​of external components such as reference voltages can drift with temperature and over time, adversely affecting performance. US 7,554,072 B2 relates to a system, a method, and an apparatus for amplifying the signal of a photodiode. The exemplary system may include a photodiode with an amplifier. The amplifier may have an inverting amplifier input, a non-inverting amplifier input, and an amplifier output. A photodiode of the system may have a photodiode anode electrically connected to the inverting amplifier input and a photodiode cathode electrically connected to the non-inverting amplifier input. A gain resistor of the system may couple the inverting amplifier input to the amplifier output. The system may further include a fixed voltage reference electrically connected to the photodiode cathode and the non-inverting amplifier output. SUMMARY OF THE REVELATION This document describes a reference voltage noise filter for any circuit, such as an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC), where the reference load current is a constant load and the circuit uses external components whose values ​​can vary with temperature, over time, and the like. While the implementation shown in example implementations is for an ADC, it is welcome that the techniques described here can be extended to any circuit that receives a substantially constant current from a reference voltage source. In example implementations, a circuit is created that includes a converter (e.g., an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC)) that receives an input voltage at an input terminal and compares the input voltage to a reference voltage received at a reference terminal from a reference voltage circuit. A resistor is connected at one end to the reference voltage circuit and at the other end to the converter's reference terminal. The circuit may also include a reference capacitor terminal connected to the other end of the resistor. The reference capacitor terminal connects the other end of the resistor to a capacitor to form a filter that filters an output signal from the reference voltage circuit. A reference gain tuning circuit compensates for the voltage drop across the resistor using a scaling factor chosen to offset any gain error caused by this voltage drop. A multiplier within the reference gain tuning circuit multiplies the converter's output signal by this scaling factor. In further example implementations, a circuit is created that includes at least two converters (e.g., continuous-time sigma / delta analog-to-digital converters) which receive input reference voltages at corresponding input terminals and compare these input voltages with a reference voltage received at corresponding reference terminals by a reference voltage circuit. A resistor is connected at one end to the reference voltage circuit and at the other end to the reference terminals of the respective converters. A reference gain tuning circuit is created that stores a scaling factor chosen to compensate for a gain error caused by a voltage drop across the resistor and multiplies the corresponding output signals of the converters by this scaling factor. In example implementations, the reference gain tuning circuit includes a digital memory in which the scaling factor is stored. The scaling factor has a value calculated during a calibration process of the circuit to compensate for a voltage drop across the resistor when the reference voltage is applied to the first end of the resistor with all converters switched on. The reference gain tuning circuit may further include a multiplier that multiplies the corresponding output signals of the converters by the scaling factor and by a second scaling factor with a value of L / M, where M is the total number of converters and L is the total number of converters switched on.The multiplier can also multiply corresponding output signals of the converters with additional scaling factors to compensate for output voltage differences between corresponding ADCs if the ADCs are not of the same type. In example implementations, the resistor is located on the same semiconductor chip as the one or more converters and the reference gain tuning circuit. Optionally, the reference voltage circuit can be located on the same semiconductor chip. The resistor can be made of the same material as the converter to reduce gain drift with temperature. In further example embodiments, a circuit is created that includes a converter (e.g., an ADC or a DAC) which receives an input voltage at an input terminal and compares the input voltage to a reference voltage received at a reference terminal from a reference voltage circuit. A resistor is connected at one end to the reference voltage circuit and at the other end to the reference terminal of the converter. A reference gain tuning element compensates for an output signal of the converter to match a gain error caused by a voltage drop across the resistor, using a scaling factor chosen to compensate for the gain error caused by the voltage drop across the resistor.In example implementations, the reference gain tuning device includes a digital memory containing the scaling factor, which is calculated during a circuit calibration process to compensate for a voltage drop across the resistor when the reference voltage is applied to the first end of the resistor, and a multiplier that multiplies the converter's output signal by the scaling factor. In other example implementations, the reference gain tuning device includes a field-programmable gate array (FPGA) or a controller algorithm designed to adjust the converter's output signal to compensate for the drop across the resistor. Example embodiments further include a method comprising receiving an input voltage at an input terminal of a circuit, comparing the input voltage with a reference voltage received at a reference terminal of the circuit from a reference voltage circuit, and compensating for a gain error due to a voltage drop across a resistor connected at a first end to the reference voltage circuit and at a second end to the reference terminal of the circuit by multiplying an output signal of the circuit by a scaling factor chosen to compensate for a gain error caused by a voltage drop across the resistor. In further exemplary embodiments, the input voltage is received at the input terminals of at least two converters. In such a case, the method includes balancing the corresponding output signals of the converters by multiplying the corresponding output signals by a second scaling factor having a value of L / M, where M is the total number of converters and L is the total number of converters switched on. The method may further include multiplying the corresponding output signals of the converters by additional scaling factors to compensate for output voltage differences between corresponding converters if the converters are not of the same type.In example implementations, the circuit and the resistor are located on the same semiconductor chip, and the scaling factor is determined by performing a background calibration and / or by measuring a voltage drop across the resistor when the semiconductor chip is switched on during a calibration process. This section is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide a complete or exhaustive explanation of the invention. A detailed description is included to provide further information about the present patent application. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which are not necessarily drawn to scale, similar numerical symbols may describe similar components in different views. Similar numerical symbols with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example but not as limiting consideration, various embodiments discussed in this document; they show: Fig. 1 the transfer function of an example 3-bit analog-to-digital converter (example 3-bit ADC). Fig. 2 an ADC connected to a reference voltage and incorporating a passive filter for noise reduction. Fig. 3 an ADC connected to a reference voltage and incorporating a passive filter and a buffer for reducing gain error and input signal-dependent error.Figure 4 shows an ADC where the resistance of the passive filter is placed on the chip containing the ADC, according to example implementations. Figure 5 shows a multi-channel ADC with an on-chip resistor for the passive filter, implementing digital reference error correction, according to example implementations. Figure 6 shows a flowchart of a method for compensating for a voltage drop across a resistor of the passive filter in example implementations. DETAILED DESCRIPTION The following description, with reference to Figures 1 to 6, sufficiently illustrates certain embodiments to enable those skilled in the art to implement them. Further embodiments may include structural, logical, procedural, and other modifications. Sections and features of some embodiments may be included in or substituted for other embodiments. Embodiments set forth in the claims include all available equivalents of those claims. The exemplary embodiments are presented for illustrative purposes only and are not intended to limit or restrict the scope of the disclosure or of the claims presented herein. The following disclosure will describe a reference voltage noise filter for any circuit, such as an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC), where the reference load current is a constant load and the circuit uses external components whose values ​​can vary with temperature, over time, and the like. While the implementation shown in example implementation forms is for an ADC, it is welcome that the techniques described here can be extended to any circuit that receives a constant reference load current. An ADC samples an analog input signal and digitizes it to provide a digital output signal according to the following general equation: Where: Vin = input voltage level; Vref = reference voltage of the ADC, N = number of bits and Doutideai = ideal digital output signal. For a 3-bit ADC, the transfer function would ideally look like transfer function 100 shown in Fig. 1, where the digital output codes follow the analog input voltage 110 linearly. However, as shown by equation (1), the ideal digital output signal Doutideal is a function of Vref, which generally includes chip-external components interacting with the chip-internal ADC. Accordingly, any error in Vref causes a corresponding error in the digital output signal. For example, noise in Vref causes a degradation of the signal-to-noise ratio (SNR) of the ADC. Furthermore, any errors in the value of Vref can cause a gain error and a linearity error, which limits the maximum range of the ADC. To reduce the noise of Vref, a passive filter can be used, as shown in Fig. 2, which depicts an ADC 200 receiving a reference voltage Vref from the reference voltage 210 via a passive filter 220 containing resistor R222 and capacitor C224. In this configuration, when the filter output signal Vref1 is directly connected to the reference input REF of the ADC 200, as shown in Fig. 2, the current ladc through resistor R222 causes a voltage drop defined by the following equation: In this case: This leads to an amplification error in the ADC output signal, which is proportional to the voltage drop across resistor R 222. Furthermore, the gain error will also depend on the number of ADCs connected to the reference voltage Vref. For example, if 'M' ADCs are connected to the reference voltage Vref, the value of Vref1 can be defined by the following equation: Additionally, the ADC and resistor R will drift with temperature and over time. Since resistor R222 is located outside the ADC, these two drifts cannot cancel each other out. As a result, a gain drift with temperature will be present. Furthermore, as mentioned above, in some configurations the ladc can be input signal-dependently, which causes Vref1 to also have a signal-dependent error. In such a case, the current of the reference voltage 210, which is input to the ADC (Iadc), can be defined as Ierrorvin, further causing a signal-dependent error of the reference voltage as follows: The value of Ierrorvin therefore leads to a linearity error. To address these gain and linearity errors, a buffer 300 can be inserted after the passive filter 220, as shown in Fig. 3. In general, the buffer 300 is designed to essentially prevent the signal source from being affected by currents or voltages that the load may generate. Thus, in Fig. 3, the buffer 300 prevents an impermissible load on the reference voltage 210 by the ADC 200 and disrupts its operation. An ideal buffer 300 is perfectly linear, regardless of its signal amplitudes. US Patent No. 9,065,477 B2 describes a linear and DC-correct feedback DAC for a continuous-time sigma / delta ADC (CTSD-ADC) that ensures the DC-DC is independent of the input signal. The circuitry described in US 9,065,477 B2 ensures that the reference input impedance is resistive and that the current through the reference input is constant, allowing a direct connection of the reference voltage circuit to the ADC without a buffer. Noise from the reference voltage circuit can be filtered using an external RC filter. The disclosed circuit minimizes nonlinearity due to input-dependent switching activity by continuously using different parallel switches to provide one of the states during a duty cycle, with each switch being activated for approximately half the duty cycle. Activating different switches during a duty cycle to provide the same state can reduce the nonlinear nature of the DAC element in the CTSD-ADC due to input-dependent switching activity. The nonlinear nature of the DAC element can be reduced because the output current does not depend on a single switching resistor being in use throughout the entire duty cycle. Instead, the output current depends on the average of several switching resistors. Furthermore, because the number of switches that are active can be constant in each duty cycle, each charge injection through the switches can be code-independent.As a result, the reference current is essentially constant and the reference voltage does not exhibit the error shown in equation (6). Thus, the configuration in US 9 065 477 B2 can be used to eliminate linearity errors in the reference current. As a result, the buffer 300 does not need to be used, and the output signal of the passive filter 220 can be applied directly to the ADC 200, simplifying the connection to the reference voltage 210 as shown in Fig. 2. Furthermore, eliminating the buffer saves energy, the area required for the buffer, and the additional noise it introduces. However, the gain error in the ADC 200, shown in equation (2), is still present due to the drop across resistor R 222 of the passive filter 220. Furthermore, resistor R 222 can cause gain drift with temperature, since it is located outside the ADC 200 chip. This problem is further addressed by the embodiments described below with reference to Figures 4 and 5. The following embodiments address the gain drift of resistor R222 by relocating resistor R222 from the passive filter 220 to the chip containing the ADC 200 and digitally correcting the voltage drop across the resistor to ensure gain error-free operation and guarantee the entire input range of the ADC 200 regardless of the number of ADCs switched on or off. For example, Fig. 4 shows an example embodiment where resistor R222 of the configuration shown in Fig. 2 is relocated to the chip 400. As shown, resistor R'410 on the chip 400 is positioned between the REF_IN terminal, which is connected to the external reference voltage 210, and the REF_CAP terminal, which is connected to the external capacitor C'420.In this configuration, the user selects a capacitor C' 420 for connection to the REF_CAP pin of chip 400 during setup, based on the required filtering. Since this value can vary, resistor 410 and capacitor 420 are separated by an apostrophe to indicate that they do not need to have the same values ​​as the corresponding external components in Figures 2-3 above. Furthermore, the chip's internal resistor R' 410 and the ADC can be designed to drift in the same direction to cancel out any gain drift with temperature and time. In one example embodiment, R' can have a value of 20 ohms and is made of the same material as the chip's internal ADCs 200 to follow all changes with respect to temperature and time. Additionally, in other example embodiments, capacitor 420 can also be located on the chip.In exemplary embodiments, the Chip 400 can be a semiconductor configured to incorporate one or more converter circuits as described herein. To obtain a correct digital output signal with reference to Vref as in equation (1), a scaling factor is introduced, which has a value determined during a calibration process during manufacturing. The calibration process can be performed in-chip using circuitry to measure the voltage drop when the chip is powered on, during background calibration, or whenever calibration is initiated. In particular, equation (1) is modified as follows: When equation (2) and equation (7) are combined, the resulting equation is: Equation (2) shows that Vref1 is a function of ladc and R, which are process-dependent and can therefore differ from device to device. Thus, for each device, Vref and Vref1 are measured during production, and the scale_fac is calculated and stored in a digital memory 430 on the chip 400 to be multiplied by the ADC output signal by the digital multiplier 440, as shown in Fig. 4. This procedure is called reference gain adjustment, and in the embodiment of Fig. 4, the scale_fac from the digital memory 430 and the digital multiplier 440 provide a means for performing the reference gain adjustment. In example embodiments, the digital memory 430 can be a 20-bit backup register storage element. In the case of a multi-channel ADC on a single chip, Vref1 can change based on the number of ADCs that are switched on and off. In this case, an additional scaling factor is needed to account for the number of ADCs that are switched on. Fig. 5 shows a multi-channel ADC in chip 500, which has a single in-chip resistor R' 410 that, together with the external capacitor C' 420, forms a passive filter. In the embodiment of Fig. 5, chip 500M has identical ADCs 200A, 200B, ..., 200M, which are connected to the same reference voltage 210 via the REF_IN terminal and resistor R' 410, and to the external capacitor C' 420 via the REF_CAP terminal. In example embodiments, the ADCs 200A, 200B, ..., 200M can be ADCs of the type described in US 9,065,477 B2, mentioned above. When all ADCs 200A, 200B, ..., 200M are turned on, equation (4) is modified as follows: If only 'L' from M ADCs 200A, 200B, ..., 200M are switched on, then: From equations (1), (3) and (10) the correct digital output signal can be obtained with reference to Vref as in equation (1) by introducing a second scaling factor such that: where: and: For multiple ADCs, the scale_fac1 is calculated with all ADCs switched on and stored in memory 510 during manufacturing, as in the embodiment shown in Fig. 4. Then, based on the number of ADCs switched on, the scale_fac2 is digitally scaled by a digital multiplier 520 using equation (12). In one example embodiment, the scale_fac2 can be stored in a lookup table 530. For example, in an implementation of the Chip 500 with four ADCs, the reference input REF_IN receives approximately 3k / 6k ohm impedance for each ADC channel in a high-power and a low-power mode, respectively. In such an implementation, the scale_fac2 can be stored in a lookup table 530 as follows: scale_fac2 = 1 when all 4 ADCs are turned on; scale_fac2 = 0.75 when 3 ADCs are turned on; scale_fac2 = 0.5 when 2 ADCs are turned on; and scale_fac2 = 0.25 when 1 ADC is turned on. During operation, the appropriate value for scale_fac2 is selected from lookup table 530 based on the number of ADCs that are switched on, while scale_fac1 is multiplied from memory 510 by the corresponding ADC output signals using the digital multiplier 520 to apply a reference gain adjustment as shown in the embodiment of Fig. 4. It is also advantageous that additional scaling factors can be multiplied by ADC output signals to compensate for output voltage differences between corresponding ADCs in configurations where the ADCs are not all of the same type or on the same chip 500. Such additional scaling factors can be stored in memory 510, in lookup table 530, or in a separate memory element. Thus, Figures 4 and 5 illustrate implementations of a reference voltage noise filter that can be used with ADCs such as a continuous-time sigma / delta ADC (CTSD ADC) and DACs to essentially eliminate noise with minimal external components. The embodiments of Figures 4 and 5 exhibit no channel-dependent gain error and support the full input range. However, it is welcome that the techniques described with reference to Figures 4 and 5 can be extended to any circuit requiring a reference voltage with a constant load current. Furthermore, the embodiments of Figures 4 and 5 are described with reference to an on-chip implementation.It is further welcomed that the techniques can be extended to any system-level implementation and that the resistor can be implemented externally when controlled by a reference gain tuning device such as a field-programmable gate array (FPGA) or a controller algorithm designed to adjust the output signal of one or more converters to compensate for the drop across the resistor. It is also welcomed that the reference voltage 210 can be implemented in-chip in certain configurations, further minimizing voltage errors due to temperature and gain drift. Fig. 6 shows a flowchart of a method for compensating a voltage drop across a resistor of the passive filter at the output of the reference voltage 210 in exemplary embodiments. As shown, the method involves receiving an input voltage at an input terminal of a converter in 600, where the converter in exemplary embodiments can be an ADC or a DAC. In 610, the input voltage of the converter is compared with a reference voltage received at a reference terminal of the converter by a reference voltage circuit.The gain error due to the voltage drop across a resistor connected at one end to the reference voltage circuit and at the other end to the reference terminal of the converter is compensated in 620 by multiplying an output signal of the converter by a scaling factor chosen to compensate for a gain error caused by a voltage drop across the resistor. The procedure further determines in 630 whether multiple (M) converters are present. If so, the input voltage at the input terminals of the corresponding converters is received, and the corresponding output signals of the converters are balanced in 640 by multiplying the corresponding output signals by a second scaling factor having a value of L / M, where M is the total number of converters and L is the number of the total number of converters that are switched on. The procedure also includes in 650 a check whether the converters are of different types. If so, the output voltages of the converters are further balanced in 660 by multiplying corresponding output signals of the converters by additional scaling factors to compensate for output voltage differences between the corresponding converters. The process then ends in 670. The detailed description above includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate certain embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples." All publications, patents, and patent documents referenced in this document are incorporated herein by reference in their entirety, as if they were individually incorporated herein by reference. In the event of inconsistent usage between this document and the documents incorporated herein by reference, the usage in the one or more incorporated references shall be considered supplementary to that in this document; for irreconcilable inconsistencies, the usage in this document shall prevail. In this document, the terms "a" or "an" are used, as is customary in patent documents, to include one or more than one, irrespective of any other instances or uses of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive or such that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise specified. In the appended claims, the terms "contain" and "in which" are used as the plain-text equivalents of the corresponding terms "include" and "whereby". Furthermore, in the following claims, the terms "contain" and "include" are unlimited, i.e., a system, device, article, or process that includes, or includes, the following:Elements included in a claim in addition to those listed under such a term are still considered to fall within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as designations and are not intended to impose numerical limitations on their subject matter. Method examples described herein may be at least partially machine-implemented or computer-implemented. The description given above is intended to be illustrative and not limiting. For example, the examples described above (or one or more of their aspects) may be used in combination with one another. Further embodiments may be used, for example, by a person skilled in the art after reviewing the description given above. The abstract is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it is not used to interpret or limit the scope or meaning of the claims. Furthermore, in the detailed description given above, various features are grouped together to streamline the disclosure. This should not be interpreted as implying that an unclaimed disclosed feature is essential to a claim.Rather, the subject matter of the invention may consist of fewer than all features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, each claim being independent as a separate embodiment. The scope of the invention shall be determined by reference to the attached claims together with the full scope of correspondences to which such claims entitle the holder. In one respect, a reference voltage noise filter is created that essentially eliminates noise with minimal external components for any circuit where the reference load current is a constant load and the circuit uses external components with values ​​that can vary with temperature, over time, and the like. Drift in a reference voltage output signal due to fluctuations in the resistance of the external filter is minimized by placing the external resistor on the chip containing the circuit. The voltage drop across the resistor is digitally compensated by a scaling factor determined during calibration. If more than one converter is included on the chip, further adjustment of the converter output signals is made based on the number of converters that are enabled or disabled.Furthermore, an error in the output signal of converters due to a mismatch between the converters is digitally compensated for by an additional scaling factor.

Claims

Circuit comprising: a converter (200) that receives an input voltage (Vin) at an input terminal and compares the input voltage with a reference voltage (Vref1) received at a reference terminal (REF) from a reference voltage circuit (210); a resistor (410) connected at a first end (REF_IN) to the reference voltage circuit and at a second end to the reference terminal of the converter; and a reference gain tuning circuit with a memory (430) that stores a scale factor (scale_fac) with a value chosen to compensate for a gain error caused by a voltage drop across the resistor when the reference voltage (Vref) is applied to the first end of the resistor, and with a multiplier (440) that multiplies an output signal (Dout) of the converter by the scale factor. Circuit according to claim 1, wherein the converter (200), the resistor and the reference gain tuning circuit are all located on the same semiconductor chip (400). Circuit according to claim 2, wherein the reference voltage circuit is located on the same semiconductor chip. Circuit according to one of the preceding claims, further comprising a reference capacitor terminal (REF_CAP) connected to the second end of the resistor, wherein the reference capacitor terminal connects the second end of the resistor to a capacitor (420) to form a filter that filters an output signal of the reference voltage circuit. Circuit according to one of the preceding claims, wherein the converter (200) comprises an analog-to-digital converter. Circuit according to one of the preceding claims, wherein the memory comprises a digital memory and the scale factor (scale_fac) has a value calculated during a calibration process of the circuit to compensate for the voltage drop across the resistor when the reference voltage (Vref) is applied to the first end of the resistor. Circuit according to one of the preceding claims, wherein the resistor is made of the same type of material as the converter (200). Circuit according to claim 1, wherein the converter (200) is one of at least two converters (200A, 200B) which receive input voltages (Vin) at corresponding input terminals and compare the input voltages with the reference voltage (Vref1) received at corresponding reference terminals (REF) from the reference voltage circuit (210), wherein the resistor (410) at the second end is connected to the reference terminals of the corresponding converters and the multiplier (520) multiplies corresponding output signals (Dout) of the converters by the scaling factor (scale_fac1). Circuit according to claim 8, wherein the multiplier (520) multiplies corresponding output signals of the converters (200A, 200B) by the scaling factor (scale_fac1) and by a second scaling factor (scale_fac2, 530) which has a value of L / M, where M is a total number of converters and L is a number of the total number of converters that are switched on. Circuit according to claim 9, wherein the multiplier (520) further multiplies corresponding output signals (Dout) of the converters (200A, 200B) with additional scaling factors to compensate for output voltage differences between corresponding converters when the converters are not of the same type (650). Circuit according to one of claims 8 to 10, wherein the scaling factor (scale_fac1) has a value that was calculated during a calibration process of the circuit to compensate for a voltage drop across the resistor when the reference voltage (Vref) is applied to the first end of the resistor when all converters (200A, 200B) are switched on. Circuit according to one of claims 8 to 11, wherein the converters (200A, 200B), the resistor and the reference gain tuning circuit are all located on the same semiconductor chip (500). Circuit according to one of claims 8 to 12, further comprising a reference capacitor terminal (REF_CAP) connected to the second end of the resistor, wherein the reference capacitor terminal connects the second end of the resistor to a capacitor (420) to form a filter that filters an output signal of the reference voltage circuit. Circuit comprising: a converter (200) that receives an input voltage (Vin) at an input terminal and compares the input voltage with a reference voltage (Vref1) received at a reference terminal (REF) from a reference voltage circuit (210); a resistor (410) connected at a first end (REF_IN) to the reference voltage circuit and at a second end to the reference terminal of the converter; and reference gain tuning means for compensating an output signal (Dout) of the converter to adapt to a gain error caused by a voltage drop across the resistor by multiplying the output signal of the converter by a scaling factor (scale_fac) whose value was chosen to compensate for the gain error caused by the voltage drop across the resistor when the reference voltage (Vref) is applied to the first end of the resistor. Circuit according to claim 14, wherein the reference gain tuning means comprises a digital memory (430) in which the scale factor (scale_fac) is stored, wherein the scale factor has a value that was calculated during a calibration process of the circuit to compensate for the voltage drop across the resistor when the reference voltage (Vref) is applied to the first end of the resistor, and a multiplier (440) that multiplies the output signal (Dout) of the converter (200) by the scale factor. Circuit according to claim 14, wherein the reference gain tuning means comprises a field-programmable gate array (FPGA) or a controller algorithm designed to adjust the output signal of the converter (200) to compensate for the drop across the resistor. A method comprising: Receiving (600) an input voltage (Vin) at an input terminal of a circuit; Comparing (610) the input voltage with a reference voltage (Vref1) received at a reference terminal (REF) of the circuit by a reference voltage circuit (210); and Compensating (620) for a gain error due to a voltage drop across a resistor (410) connected at a first end (REF_IN) to the reference voltage circuit and at a second end to the reference terminal of the circuit by multiplying an output signal (Dout) of the circuit by a scaling factor (scale_fac) whose value was chosen to compensate for the gain error caused by the voltage drop across the resistor when the reference voltage (Vref) is applied to the first end of the resistor. The method of claim 17, wherein the input voltage (Vin) is received at input terminals of at least two converters (200A, 200B), further comprising a balancing (640) of corresponding output signals (Dout) of the converters by multiplying the corresponding output signals by a second scaling factor (scale_fac2) having a value of L / M, wherein M is a total number of converters and L is a number of the total number of converters that are switched on. The method of claim 18, further comprising multiplying (660) corresponding output signals (Dout) of the converters (200A, 200B) with additional scaling factors to compensate for output voltage differences between corresponding converters when the converters are not of the same type (650). Method according to one of claims 17 to 19, wherein the circuit and the resistor are arranged on the same semiconductor chip (400, 500), which further comprises determining the scale factor (scale_fac) by performing a background calibration and / or by measuring a voltage drop across the resistor when the semiconductor chip is switched on during a calibration process.

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