Structure and method for transistors having rear-side power rails

Abstract

Semiconductor structure (100, 300) comprising: a substrate (102) having a front (102FS) and a back (102BS); multiple gate stacks (112) formed on the front (102FS) of the substrate (102) and arranged on an active region (106) of the substrate (102); a shallow trench insulating element (STI element, 104) adjacent to an active region (106), wherein the active region (106) is an active fin region (106) projecting over an upper surface of the STI element (104), with edge gate stacks (112a, 112d) of the multiple gate stacks (112) each extending along a direction (Y) from the fin elements (106) to the STI elements (104) arranged in the substrate (102) and being connected to the STI elements (104) and the fin elements (106); a first source / drain element (108, 110) formed at the active region (106) and located at an edge of the gate stack (112);a rear busbar (118) formed on the rear side (102BS) of the substrate (102); and a rear contact element (120) formed between the rear busbar (118) and the first source / drain element (108, 110) and electrically connecting the rear busbar (118) to the first source / drain element (108, 110), the rear contact element (120) further comprising a first silicide layer (152) arranged on the rear side (102BS) of the substrate (102).

Description

PRIORITY DATA

[0001] This application claims priority over provisional US application 62 / 954,532 entitled “Structure and Method for Transistors with Backside Power Rails”, filed on December 29, 2019, and incorporated herein by reference in its entirety. BACKGROUND

[0002] Integrated circuits have evolved to advanced technologies with smaller feature sizes, such as 7 nm, 5 nm, and 3 nm. In these advanced technologies, gate spacing is constantly shrinking, leading to contact-to-gate bridging issues. Furthermore, three-dimensional transistors with active fin regions are often desired to improve device performance. These three-dimensional field-effect transistors (FETs) formed on active fin regions are also known as FinFETs. FinFETs require narrow fin widths for short-channel control, resulting in smaller source / drain regions than those of planar FETs. This reduces alignment margins and causes problems with further shrinking of component spacing and increased packing density. Along with downscaling of component sizes, current paths are formed on the back side of the substrate.Existing rear-side power rails still face several challenges, including routing resistance, alignment margins, layout flexibility, and packing density. Therefore, there is a need for a finned transistor and power rail structure and methodology to address concerns regarding improved circuit performance and reliability. List of characters

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It is emphasized that, according to standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A is a top view of a semiconductor structure built according to some embodiments. Fig. 1B, Fig. 1C, Fig. 1D, Fig. 1E and Fig. Figure 1F shows cross-sectional views of the semiconductor structure built according to some embodiments. Fig. 2 is a flowchart of a process that produces the semiconductor structure from Fig. 1A to Fig. 1F represents, which is constructed according to various aspects of this disclosure, in some embodiments. Fig. 3, Fig. 4, Fig. 5A, Fig. 6A, Fig. 6C, Fig. 7, Fig. 8, Fig. 9, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 and Fig. Figure 19 shows cross-sectional views of a semiconductor structure at various stages of fabrication, built according to several embodiments. Fig. 5B and Fig. Figure 6B shows top views of a semiconductor structure at various stages of fabrication, built according to several embodiments. Fig. 10A and Fig. Figure 10B shows cross-sectional views of a gate stack of the semiconductor structure at various stages of fabrication, built according to several embodiments. DETAILED DESCRIPTION

[0004] It is understood that the following disclosure provides many different embodiments, or examples, for the implementation of various features of different embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be understood as limiting. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.Furthermore, the formation of a first element or a second element in the following description may include embodiments in which the first and the second element are formed in direct contact, and it may also include embodiments in which further elements can be formed between the first and the second element, so that the first and the second element do not have to be in direct contact.

[0005] This disclosure provides a semiconductor structure with backside busbars and the method for its fabrication. In particular, the semiconductor structure comprises a backside contact element located on the back side of the substrate and positioned between the active regions and the backside busbars. The backside contact elements electrically connect the backside busbars to the active regions, such as by connecting the backside busbar to a source element of a transistor. The semiconductor structure also comprises an interconnect structure formed on the front side of the substrate. The interconnect structure further comprises a frontside contact element that electrically connects to the field-effect transistors, such as by grounding to and connecting to a drain element of a transistor.In these embodiments, the front and back contact elements both include silicides to reduce contact resistance. Such a semiconductor structure comprises backside power rails and an interconnect structure on the frontside for collective routing of power lines, such that the drain elements are connected to the corresponding power lines through the interconnect structure and the source elements are connected to the corresponding power lines through the backside power rails.

[0006] Fig. 1A is a top view of a semiconductor structure 100 , which is built according to several designs. Fig. 1B, Fig. 1C, Fig. 1D, Fig. 1E and Fig. 1F are cross-sectional views of the semiconductor structure 100 along the dashed lines AA', BB', CC', DD' and EE', which are constructed according to some embodiments. The semiconductor structure 100can contain one or more standard cells 101 include, each of which has one or more field-effect transistors.

[0007] The semiconductor structure 100 includes a substrate 102 , active regions 106 and shallow trench insulation elements (STI elements) 104 The active regions are isolated from each other. In this embodiment, the active regions are 106 active fin regions located above the STI elements 104 are extruded. In some embodiments, the active regions can be 106 Alternatively, they can be planar active regions or active regions with multiple channels that are vertically stacked (also known as a gate-all-around (GAA) structure). The semiconductor structure 100 also includes Sources (also referred to as Source Elements) 108, Drains (also referred to as Drain Elements) 110 and Gate Stacks 112 , which are located in the active regions 106are arranged. The source elements 108 and the drain elements 110 alternate with respective gate stacks 112 from, to form various field-effect transistors (FETs). In this embodiment, the active regions have 106 an elongated shape aligned along the first direction (X-direction), and the gate stacks 112 They have an elongated shape that is aligned along the second direction (Y-direction), which is orthogonal to the first direction.

[0008] The semiconductor structure 100 also includes an interconnect structure 114 , located at the front of the substrate 102 is formed. The interconnect structure 114 includes various contact elements 116 Through-hole components and metal traces for connecting FETs and other devices in functional circuits. The interconnect structure 114comprises several metal layers, each containing several metal conductors and vias to connect the metal conductors in the adjacent metal layers, such as metal conductors 126 in the first metal layer and through-hole components 128 , which the metal pipes 126 connect to the front contact elements. In this embodiment, the contact elements 116 also as front contact elements, which are located on the front sides of the substrate 102 are formed, referred to as such. In particular, a subset of the front-side contact elements is present. 116 at the drain elements 110 .

[0009] The semiconductor structure 100 includes rear busbars 118 and backside contact elements 120 , which are located on the back of the substrate 102BS 102 are formed. The backside contact elements 120 are between the active regions 106and the rear busbars 118 In this embodiment, the rear busbars are electrically connected. 118 with the active regions 106 , such as connecting rear busbars 118 with source elements 108 . Thus, both the rear busbars at the rear and the interconnect structure at the front collectively contribute to the routing of power lines, such as the drain elements being connected to the corresponding power lines through the interconnect structure and the source elements being connected to the corresponding power lines through the rear busbars.

[0010] In these embodiments, the front contact elements comprise 116 and the rear contact elements 120Silicide and bulk metal on silicide to reduce contact resistance. Silicide comprises titanium silicon (TiSi), nickel silicon (NiSi), tantalum silicon (TaSi), cobalt silicon (CoSi), or a combination thereof. In this embodiment, a silicide layer is 144 on the drain element 110 formed from the front and between the drain element 110 and the front contact element 116 used; and a silicide layer 152 is on the source element 108 formed from the back and placed between the source element 108 and the back contact element 120 used, as in Fig. 1B is illustrated.

[0011] The semiconductor structure 100 It also includes a dielectric layer 122 a first dielectric and a backside intermediate dielectric layer (IMAGE layer) 124 a second dielectric located on the back of the substrate102 The first and second dielectrics differ in composition to provide etch selectivity. For example, the first dielectric comprises silicon nitride, silicon carbon nitride, SiOCN, silicon oxide, SiOC, or combinations thereof. The second dielectric comprises one of the above dielectrics but is chosen differently in composition to provide etch selectivity.

[0012] Fig. 2 is a flowchart of a process 200 for the production of the semiconductor structure 100 according to some embodiments. The method 200 includes various operations 202 until 232 for forming the semiconductor structure 100 in Fig. 1A to Fig. 1F. In particular, the procedure includes 200 the formation of FETs (and other devices) and the interconnect structure 114 at the front of the substrate102 and the formation of rear busbars 118 and rear contact elements 120 on the back of the substrate 102 , where power lines are collectively routed through the rear busbars 118 on the back and the interconnect structure 114 at the front of the substrate 102 be routed.

[0013] In particular, the procedure includes 200 an operation 220 to thin the substrate 102 from the back. The operation 220 It can include grinding, chemical-mechanical polishing (CMP), and etching, such as wet etching, in a combination to make the thinning process efficient. To properly interrupt the thinning process, the substrate includes 102an embedded layer, such as a silicon germanium layer or a doped silicon germanium layer, to provide etch selectivity during a thinning process, so that the thinning process of the operation 220 can stop correctly. In this embodiment, the substrate 102 A silicon substrate. A silicon-germanium layer is epitaxially built up on the silicon surface, and then a silicon layer is epitaxially built up on the doped silicon-germanium surface. The silicon-germanium acts as an etch stop layer during the etching process. In other embodiments, the etch stop layer can be a semiconductor material other than silicon, such as a compound semiconductor material, a silicon layer doped with other elements for improved etch selectivity, or another doped or undoped semiconductor layer such as silicon carbide.

[0014] Fig. 3 to Fig. Figure 18 shows top or cross-sectional views of a semiconductor structure (or workpiece) at various stages of fabrication. The semiconductor structure 300 is an example of semiconductor structure 100 or an alternative structure built according to some embodiments. The semiconductor structure 300 It includes field-effect transistors (FETs), interconnect structure, and rear power rails. The semiconductor structure 300 (and therefore also the semiconductor structure) 100 ) and the procedure 200 , which manufactures the same, are listed below collectively with reference to Fig. 1 to Fig. 18 described.

[0015] With reference to Fig. 2 and Fig. The procedure begins on day 3. 200 with block 202 by taking up a workpiece (or a semiconductor structure) 300, which is a semiconductor substrate 102 exhibits the semiconductor substrate. 102includes silicon. In some other embodiments, the substrate includes 102 Germanium, silicon germanium, or other suitable semiconductor materials. The substrate 102 Alternatively, it can consist of another suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide, or gallium indium phosphide. The semiconductor substrate 102 It also includes various doped regions such as n-wells and p-wells. In one embodiment, the semiconductor substrate comprises 102 an epitaxial (or epi) semiconductor layer. In another embodiment, the semiconductor substrate comprises 102A concealed dielectric layer for insulation, formed using a suitable technology, such as a technology known as implanted oxygen separation (SIMOX). In some embodiments, the substrate can 102 be a semiconductor on an insulator, such as silicon on an insulator (SOI). In particular, the substrate comprises 102 a semiconductor layer 102A , which serves as an etch stop layer (ESL) for the subsequent fabrication associated with the backside current rails. The semiconductor layer 102A is in the semiconductor substrate 102 embedded, but comprises a different semiconductor composition to provide etch selectivity during the backside process. For example, the semiconductor layer is 102AA silicon-germanium layer (SixGey layer) is used, while the bulk substrate is a silicon substrate. The etch selectivity can be determined by the concentration of germanium in the silicon-germanium layer. 102A The germanium concentration (atomic fraction) in the silicon germanium layer can range between 30% and 90%. The semiconductor layer 102A The solution can be undoped or doped with a suitable dopant (such as boron, phosphorus, carbon, or combinations thereof) to further improve etch selectivity. For example, an etching solution of NH4OH, H2O2, and H2O can be used to selectively etch silicon germanium relative to silicon with substantial etch selectivity.

[0016] The semiconductor layer 102A can be formed by epitaxial construction, such as by epitaxial construction of a silicon germanium layer 102A on a silicon substrate and then epitaxial build-up of a silicon layer102B on the silicon germanium layer 102A In some embodiments, the semiconductor layer has 102A a thickness in the range between 10 nm and 20 nm, while the silicon layer 102B has a thickness in the range between 70 nm and 100 nm.

[0017] With reference to Fig. 2 and Fig. 4 carries out the procedure 200 with an operation 204 by forming insulation elements, such as shallow trench insulation elements (STI elements) 104 on the semiconductor substrate 102 , resulting in active regions 106 are defined as being separated and insulated from each other by the insulating elements. In Fig. Figure 4 and some of the following figures show the embedded semiconductor layer. 102A Not illustrated for the sake of simplicity. However, it goes without saying that the semiconductor layer 102A as part of the semiconductor substrate 102 is available.

[0018] In some embodiments, the STI elements 104 formed by a process that includes etching to create trenches, filling the trenches with dielectric, and polishing to remove excess dielectric and planarize the top surface. One or more processes are applied to the semiconductor substrate. 102 This is achieved through soft or hard mask openings formed by lithographic texturing and etching. The formation of the STI elements 104 further described below according to some embodiments.

[0019] In this example, a hard mask is applied to the substrate. 102The hard mask layers are deposited and structured by a lithography process. They comprise a dielectric such as semiconductor oxide, semiconductor nitride, semiconductor oxynitride, and / or semiconductor carbide, and in an exemplary embodiment, the hard mask layer comprises a silicon oxide film and a silicon nitride film. The hard mask layer can be formed by thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), or other suitable deposition processes.

[0020] A photoresist layer is formed on the hard mask layer. An example resist layer comprises a photosensitive material that causes the layer to undergo a change in properties when exposed to light, such as ultraviolet (UV) light, deep UV light (DUV light), or extreme UV light (EUV light). This change in properties can be used to selectively remove exposed or unexposed portions of the resist layer during a development process. This process of forming a structured resist layer is also known as a lithographic process (or lithographic structuring process). An example lithographic process includes spin-on coating of a resist layer, soft firing of the resist layer, mask alignment, exposure, post-exposure firing, development of the resist layer, rinsing, and drying (e.g., hard firing).Alternatively, a lithography process can be implemented or replaced by other methods, such as maskless photolithography, electron beam writing, and ion beam writing.

[0021] After structuring the resist, an etching process is applied to the semiconductor structure. 300 The process is carried out to open the hard mask layer, thereby transferring the structure from the resist layer to the hard mask layer. The remaining resist layer can be removed after the hard mask layer has been structured. The etching process for structuring the hard mask layer can involve wet etching, dry etching, or a combination of both. The etching process may include multiple etching steps. For example, the silicon oxide film in the hard mask layer may be etched by a dilute hydrofluoric acid solution, and the silicon nitride film in the hard mask layer may be etched by a phosphoric acid solution.

[0022] Then another etching process can follow to separate the sections of the substrate. 102 to etch areas not covered by the structured hard mask layer to create trenches in the semiconductor substrate 102 to form. The structured hard mask layer is used as an etching mask during the etching process to expose the substrate. 102to structure the substrate. The etching process can include any suitable etching technique, such as dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching (RIE)). In some embodiments, the etching process includes multiple etching steps with different etching chemicals, designed to etch the substrate to form the trenches with a specific trench profile for improved device performance and structuring density. In some examples, the semiconductor material of the substrate can be etched by a dry etching process using a fluorine-based etchant. In particular, the etching process applied to the substrate is controlled such that the substrate 102 is partially etched.

[0023] One or more dielectrics are filled into the trenches to hold the STI elements. 104to form. Suitable filling dielectrics include semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, fluorinated silica glass (FSG), low k-value dielectrics, and / or combinations thereof. In various exemplary embodiments, the dielectric is deposited using a high-density post-processing (HDP) CVD process, a subatmospheric active vapor deposition (SACVD) process, a high aspect ratio regeneration (HARP) process, a flowable fluid vapor deposition (FCVD), and / or a spin-on process.

[0024] The deposition of the dielectric can be achieved through a chemical-mechanical polishing / planarization process (CMP process) to remove the excess dielectric and the top surface of the semiconductor structure. 300to planarize. The CMP process can use the hard mask layers as a polish stop layer to prevent polishing of the semiconductor surface. The hard mask can be removed by the CMP process or alternatively by an etching process.

[0025] With reference to Fig. 5A and Fig. 5B can perform the procedure 200 by forming the fin structure with multiple active fin regions (or fin elements) 106 with an operation 206 continue. Fig. 5A and Fig. 5B are a cross-sectional view or a top view of the semiconductor structure. 300 The operation 206 includes cutting out the STI elements 104 , so that the active regions 106 from the STI elements 104They are extruded, so they are referred to as active fin regions. The cutting process uses one or more etching steps (such as dry etching, wet etching, or combinations thereof) to selectively re-etch the STI elements. 104 For example, hydrofluoric acid can be used in a wet etching process for the selective etching of STI elements. 104 to be applied when the STI elements 104 Silicon oxide elements are present. Examples of active fin regions. 106 They are located at a distance from each other in the second direction (Y-direction). The active fin regions 106 It has an elongated shape that is aligned along the first direction (X-direction).

[0026] Doping trials can take place at this stage or before the operation 206 on the active Finnish regions 106 can be used to create differently doped wells in the semiconductor substrate 102to form structures such as n-wells and p-wells. Differently doped wells can be formed by ion implantation or diffusion.

[0027] With reference to Fig. 6A, Fig. 6B and Fig. 6C is running the procedure 200 by forming different gate stacks 107 in the active Finnish regions 106 with an operation 208 on. Fig. 6B is a top view; Fig. 6A is a sectional view along the dashed line AA'; and Fig. 6C is a sectional view along the dashed line BB' of the semiconductor structure. 300 In this embodiment, the gate stacks comprise 107 exemplary gate stacks 107a , 107b , 1070 and 107d , as in Fig. 6B illustrates. The following Fig. 7 to Fig. 19 are all sectional views of the semiconductor structure 300 along the dashed line BB' from Fig. 6B, however, in later stages of production.

[0028] The Gate Stacks 107 They have elongated shapes and are aligned in the second direction (Y-direction). Each of the gate stacks 107 is across several active Finnish regions 106 extends. In particular, a gate stack 107 (such as gate stacks) 107a or 107d) at the ends (or edges) of the active fin regions 106 arranged so that this gate stack is partially located at the active fin region 106 is partly due to the STI element 104 This edge configuration is designed to reduce the border effect, increase the uniformity of the device, and improve overall device performance.

[0029] In this embodiment, the gate stacks 107 Stacks of dummy gates, which are to be replaced by metal gates in later manufacturing steps. 107Each gate can comprise a gate dielectric layer and a gate electrode. The gate dielectric layer comprises a dielectric, such as silicon oxide, and the gate electrode can comprise polysilicon. Forming the gate stack 107 This includes the deposition of the gate materials (in this example comprising polysilicon); and the structuring of the gate materials by a lithography process and etching. A gate hard mask layer can be formed on the gate material layer and is used as an etching mask in the formation of the gate stack. The gate hard mask layer can comprise any suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, other suitable materials, and / or combinations thereof. In one embodiment, the gate hard mask comprises multiple films, such as silicon oxide and silicon nitride. In some embodiments, the structuring process for forming the gate stack includes 107the formation of a structured resist layer through the lithography process; etching the hard mask layer using the structured resist layer as an etching mask; and etching the gate materials to form the gate stack. 107 using the structured hard mask as an etching mask.

[0030] One or more gate sidewall elements (or gate spacers) 113 are attached to the sidewalls of the gate stack. 107 formed. The gate spacers 113 These can be used to space the subsequently formed source / drain elements, to design or modify the source / drain structural profile, and / or to provide insulation between the gate electrode and the source / drain elements. The gate spacer 113can include any suitable dielectric, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, other suitable dielectrics, and / or combinations thereof. The gate spacers 113 They can have multiple films, such as dual films (e.g., a silicon oxide film and a silicon nitride film) or three films (a silicon oxide film, a silicon nitride film, and a silicon oxide film). Forming the gate spacer 113 This includes deposition and anisotropic etching, such as dry etching.

[0031] With reference to Fig. 7 in a section view the process 200 by creating various source elements 108 and drain elements 110 on respective fin FETs (FinFETs) with an operation 210 continued. The source elements 108 and the drain elements 110Field-effect transistors can include lightly doped drain elements (LDD elements) and heavily doped source and drain (S / D) elements. For example, every field-effect transistor includes a source element. 108 and a drain element 110 , which are on the respective fin element 106 are formed and between which the gate stack lies. A channel is in the fin element. 106 formed within a section that lies below the gate stack and is located between the source element 108 and the drain element 110 extends.

[0032] The source / drain elements 108 and 110 They can exhibit an elevated source / drain structure and can be formed by selective epitaxial growth for a stress effect, resulting in improved carrier mobility and device performance. The gate stacks 107 and gate spacers 113 restrict the source / drain elements 108 and 110on the source / drain regions. In some embodiments, the source / drain elements are 108 and 110 formed by one or more epitaxial processes, whereby Si elements, SiGe elements, SiC elements and / or other suitable semiconductor elements are deposited in a crystalline state on the fin elements. 106 are formed. Alternatively, an etching process is performed to excise the source / drain regions prior to epitaxial assembly. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) or ultra-high vacuum CVD (UHV CVD)), molecular beam epitaxy, and / or other suitable processes). The epitaxial process may involve gaseous and / or liquid precursors that are compatible with the composition of the fin elements. 106 interact.

[0033] The source / drain elements 108 and 110Source / drain elements can be doped during the epitaxy process by introducing doping species, including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the source / drain elements are not doped in place, an implantation process is performed to introduce the appropriate dopant into the source / drain elements. 108 and 110 to introduce. In an exemplary embodiment, the source / drain elements comprise 108 and 110 in an nFET Si or SiC doped with phosphorus, while the source / drain elements 108 and 110 in a pFET comprising SiGe or Ge doped with boron. In some other embodiments, the source / drain elements comprise 108 and 110More than one semiconductor material layer. For example, a silicon-germanium layer is epitaxially built up on the substrate within the source / drain regions, and a silicon layer is epitaxially built up on the silicon-germanium layer. In another example, a semiconductor layer (silicon-germanium or silicon) is epitaxially built up, with multiple films having different dopant concentrations on the substrate within the source / drain regions. One or more annealing processes can then be performed to activate the source / drain elements. Suitable annealing processes include rapid thermal annealing (RTA), laser annealing, other suitable annealing techniques, or combinations thereof.

[0034] With reference to Fig. 8 carries out the procedure 200 with an operation 212 further, in which an intermediate dielectric layer (ILD layer) 130(also called front-side ILD layer or FILD layer to separate it from the IMAGE) 124 to distinguish) on the substrate 102 is formed to include the source / drain elements 108 and 110 to cover the front. The ILD 130 surround the gate stacks 107 and the gate spacers 113 , so that the gate stacks 107 They can be removed, and replacement gates can be formed in the resulting cavities (also called gate trenches). Accordingly, in such embodiments, the gate stacks 107 after the formation of the ILD layer 130 removed. The ILD layer 130 can also be part of an interconnect structure 114 be the electrically different devices of the semiconductor structure 300 connects. In such embodiments, the ILD layer acts 130 as an insulator that connects and isolates the conductive traces. The ILD layer 130The ILD layer can comprise any suitable dielectric, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, other suitable dielectrics, or combinations thereof. In some embodiments, forming the ILD layer includes... 130 the deposition of CMP to provide a planarized top surface.

[0035] With reference to Fig. 9 carries out the procedure 200 with an operation 214 to the gate replacement. The Dummygate stacks 107 are created by gate stacks 112 , which have a dielectric with a high k-value, and replace metal, and are therefore also called high-k metal gates.

[0036] The Gate Stacks 112 are in the active Finnish regions 106They are configured to form various field-effect transistors (FETs) and are therefore also called FinFETs. In some examples, the field-effect transistors include n-type and p-type transistors. In other examples, these field-effect transistors are configured to form one or more static random-access memory (SRAM) cells, logic gate cells, or a structure that includes both. Each SRAM cell includes two cross-coupled inverters configured for data storage. Furthermore, the gate stacks 112 configured to increase structural uniformity and improve manufacturing quality. For example, as noted above, the gate stack includes 112 the edge gate stacks 112a and 112d , each extending along the Y-direction from the fin elements 106 to the STI elements 104 extend and at the STI elements 104 and the fin elements 106 land.

[0037] As in Fig. As illustrated in Figure 9, the active Finnish regions extend 106 from one end 138A to another end 138B along the Y-direction. The gate replacement process can include etching, deposition, and polishing. This example shows sample dummy gate stacks for illustration. 107a , 107b , 1070 and 107d removed, resulting in gate trenches. In some embodiments, the dummy gate stacks 107 removed by an etching process, such as wet etching, to remove the gate stacks 107 to selectively remove the dummy gate. The etching process may involve multiple etching steps to remove the dummy gate if more materials are present. Then, the gate materials, such as the high k-value dielectric and the metal, are deposited in the gate grooves to complete the gate stack. 112 to form, such as the exemplary gate stacks 112a , 112b , 112cand 112d A CMP process is also implemented to remove excess gate materials from the semiconductor structure. 300 to polish and remove. The structure and formation of the gate stacks 112 are furthermore, with reference to Fig. 10A and Fig. 10B described. Fig. 10A and Fig. Figure 10B illustrates sectional views of an exemplary gate stack. 112 according to various designs.

[0038] The Gate Stack 112 (such as 112b) is on the substrate 102 formed above the canal region of the active Finnish region 106 lies. The gate stack 112 is formed in the gate trenches by a suitable process, such as a process that includes deposition and CMP. However, it is understood that the gate stack 112 may have a different suitable gate structure and may be formed by a different suitable method.

[0039] The Gate Stack 112 comprises a gate dielectric layer (or gate dielectric element) 132 and a gate electrode 134 , which are located at the gate dielectric layer 132 is arranged. In this embodiment, the gate dielectric layer comprises 132 a dielectric with a high k-value and the gate electrode 134 comprises metal or a metal alloy. In some examples, the gate dielectric layer 132 and the gate electrode 134 Each comprise a number of intermediate layers.

[0040] The high k-value dielectric can comprise metal oxides, metal nitrides such as LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃ (STO), BaTiO₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO₃ (BST), Al₂O₃, Si₃N₄, oxynitrides (SiON), or other suitable dielectrics. The gate electrode 134The material may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, or suitable materials. In some embodiments, different metal materials are used for nFET and pFET devices with respective output functions.

[0041] The gate dielectric layer 132The device may further comprise an interface layer inserted between the high k-value dielectric layer and the active fin region. The interface layer may comprise silicon oxide, silicon nitride, silicon oxynitride, and / or another suitable material. The interface layer is deposited by a suitable process, such as ALD, CVD, ozone oxidation, etc. The high k-value dielectric layer is deposited on the interface layer (if the interface layer is present) by a suitable technique, such as ALD, CVD, metal-organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof, and / or other suitable techniques. In some embodiments, the gate dielectric layer 132 during the operation 208 , which the gate stack 107 forms, on the active Finnish region 106 formed. In this case, the gate dielectric layer is 132 as in Fig. 10A is illustrated in the shape. In some other embodiments, the gate dielectric layer is 132 in the process with high k-value, the gate dielectric layer is formed last. 132 during the operation 214 in the gate groove. In this case, the gate dielectric layer 132 as in Fig. 10B illustrates a U-shape.

[0042] The gate electrode 134 It can comprise several conductive materials. In some embodiments, the gate electrode comprised 134 a covering layer 134-1 , a blockage layer 134-2 , an exit working metal layer 134-3 , another blockage layer 134-4 and a filler metal layer 134-5 To promote the embodiments, the covering layer includes 134-1 comprises titanium nitride, tantalum nitride, or another suitable material, formed by a suitable deposition technique such as ALD. The blocking layer 134-2This includes titanium nitride, tantalum nitride, or another suitable material formed by an appropriate deposition technique such as ALD. In some examples, the block layers may be absent, or only one may be present in the gate electrode.

[0043] The exit metal layer 134-3 It comprises a conductive layer of metal or metal alloy with a suitable work function, thus improving the performance of the corresponding FET in the device. The work function metal layer (WF metal layer) 134-3 The WF metal differs for a pFET and an nFET, and is referred to as an n-WF metal and a p-WF metal, respectively. The choice of WF metal depends on the FET that is to be formed on the active region. For example, the semiconductor structure includes 300A first active region is defined for an nFET and another for a pFET, and accordingly, the n-WF metal and the p-WF metal are formed in their respective gate stacks. Specifically, an n-WF metal is a metal that exhibits a first work function, thus reducing the threshold voltage of the associated nFET. The n-WF metal has a work function close to the silicon conductivity band energy (Ec), or lower, which facilitates electron escape. For example, the n-WF metal has a work function of approximately 4.2 eV or less. A p-WF metal is a metal that exhibits a second work function, thus reducing the threshold voltage of the associated pFET. The p-type work function metal is close to the silicon valence band energy (Ev) or higher, and represents a strong electron bonding energy to the nuclei. For example, the p-type work function metal has a work function of approximately 5.2 eV or more.In some embodiments, the n-WF metal comprises tantalum (Ta). In other embodiments, the n-WF metal comprises titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or combinations thereof. In other embodiments, the n-metal comprises Ta, TiAl, TiAlN, tungsten nitride (WN), or combinations thereof. The n-WF metal may comprise various metal-based films as a stack for optimized device performance and processing compatibility. In some embodiments, the p-WF metal comprises titanium nitride (TiN) or tantalum nitride (TaN). In other embodiments, the p-metal comprises TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), or combinations thereof. The p-WF metal may comprise various metal-based films as a stack for optimized device performance and processing compatibility. The exit work metal is deposited by a suitable technique, such as PVD or ALD.

[0044] The blockage layer 134-4It comprises titanium nitride, tantalum nitride, or another suitable material formed by a suitable deposition technique such as ALD. In various embodiments, the filler metal layer comprises 134-5 Aluminum, tungsten, or another suitable metal. The filler metal layer 134-5 is separated using a suitable technique, such as PVD or plating.

[0045] Referring back to Fig. 9 can the procedure 200 may also include surgery to create a hard mask 136 on the gate stack 112 to form the gate stack 112 to protect against loss during subsequent processing. The formation of the hard mask. 136 includes cutting out the gate stack 112 by selective etching; deposition (such as CVD) of a hard mask; and CMP according to this example. The hard mask 136It may comprise a suitable material that differs from the dielectric of the ILD layers to achieve etch selectivity during the etching process in order to form contact orifices. In some embodiments, the hard mask comprises 136 Silicon nitride, for example, is a hard mask. 136 formed from silicon nitride (SiN) by CVD using chemicals including hexachlorosilane (HCD or Si2C16), dichlorosilane (DCS or SiH2Cl2), bis(tertiary butylamino)silane (BTBAS or C8H22N2Si) and disilane (DS or Si2H6).

[0046] Fig. 11 to Fig. 13 are cross-sectional views of the semiconductor structure 300 in various manufacturing stages, constructed according to several embodiments. The process 200 is undergoing surgery 216 by forming an interconnect structure 114to connect FETs and various other devices to form an integrated circuit, as in Fig. 11 to Fig. 13 is illustrated and furthermore in Fig. 1A to Fig. 1F is illustrated. The interconnect structure 114 is formed on the front side of the workpiece. The semiconductor structure 300 It also includes busbars and other conductive elements formed on the back of the workpiece and collectively connected to the interconnect structure. 114 function to connect the various devices into a functionally integrated circuit.

[0047] The interconnect structure 114 It comprises multi-layered metal conductors to provide horizontal electrical routing and contact / via elements to provide vertical routing. Various metal conductors, contact elements, and via elements are used in the interconnect structure.114 are formed using a suitable technique, such as a damascening process. In particular, the interconnect structure includes 114 one or more elements 116 , which end up on transistors and / or other devices, such as a drain element 110 of a FET. The operation 216 may involve several steps to create one or more contact elements 116 to form, as described in detail below.

[0048] Another ILD layer 140 the ILD layer 130 It is similar in composition and formation, and is formed on the workpiece as in Fig. Figure 11 illustrates the formation of the ILD layer. 140 In some embodiments, it may include deposition and CMP. The ILD layer 140 is furthermore structured, with one or more contact holes (or openings) 142 to form it through a lithography process and etching. A hard mask can be used to create the ILD layer.140 to structure. The etching process etches through the ILD layers. 140 and 130 . to one or more drain elements 110 are disclosed, as in Fig. 12 illustrated. In various structuring processes, which are described above in the procedure 200 As described, each structuring process can be implemented through double structuring or multiple structuring. In some embodiments, a silicide layer is used. 144 on the drain element 110 formed to reduce contact resistance, as in Fig. 12 is illustrated. The silicide layer 144 It includes silicon and metals, such as titanium silicide, tantalum silicide, nickel silicide, or cobalt silicide. The silicide layer 144can be formed by a process known as a self-aligned silicide process (or salicide process), which includes metal deposition, annealing to react the metal with silicon, and etching to remove the unreacted metal.

[0049] One or more contact elements 116 are in the contact hole (the contact holes) 142 formed, as in Fig. 13 illustrated. The contact hole 142 It is filled with one or more conductive materials, such as Ti, TiN, TaN, Co, W, Al, Cu, or a combination thereof. Forming the contact element 116 This involves the deposition of one or more conductive materials and CMPs, as illustrated by some examples. The deposition can be implemented using a suitable deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), plating, CVD, or another suitable method.

[0050] As noted above, the operation includes 216 including the formation of other conductive elements, such as vias. 128 , which are attached to the contact element 116 land, the via-connection elements 146 , which are located at the gate electrodes 134 land, and the metal pipes 126 in the first metal layer, the interconnect structure 114 , as in Fig. 13 or Fig. 1C is illustrated. Furthermore, other detailed structures such as semiconductor layers are shown. 102A and 102B in Fig. 13 illustrated.

[0051] The procedure 200 This also includes other operations, such as surgery. 218 to perform various processes at the rear end of the conductor, which includes: forming a passivation layer, forming a redistribution layer (RDL), forming capacitors in the passivation layer, and forming bonding pads (in Fig. 13 (not shown). Then the workpiece 300 for the subsequent operations on the back of the workpiece, as in Fig. 14 to Fig. 19 illustrated. Fig. 14 to Fig. 19 are cross-sectional views of the semiconductor structure 300 along the active Finnish region 106 , such as along the dashed line BB' of Fig. 6B, however, in later stages of production.

[0052] With reference to Fig. 14 are proceeding with the procedures 200 with an operation 220 further, to remove the semiconductor substrate of the workpiece 300to thin from the back side so that the active regions are exposed using suitable methods, such as polishing, etching, or combinations thereof. In some embodiments, the polishing process may include a CMP process. In some embodiments for improved throughput, the polishing process includes a grinding process with a higher polishing rate and then a CMP process with a higher polish quality. In this embodiment, the semiconductor substrate comprises 102 an embedded semiconductor layer 102A , which serves as a stop layer, such as a polishing stop layer or, alternatively, an etching stop layer. If the embedded semiconductor layer 102A Serving as a polishing stop layer, the CMP process stops at the embedded semiconductor layer. 102A . If the embedded semiconductor layer 102ASince it acts as an etch stop layer, a further etching process is applied after the CMP process to further etch the semiconductor substrate. 102 to cut out until it reaches the embedded semiconductor layer 102A stops. In this embodiment, in which the semiconductor substrate 102 a silicon substrate, while the embedded semiconductor layer 102A In a silicon-germanium layer, the etching process comprises the application of an etchant for the selective removal of silicon relative to silicon-germanium. To further the embodiment, the etching process includes cryogenic deep reactive ion etching (DRIE) with SF6 and O2 for the selective etching of silicon relative to silicon-germanium. Subsequently, a further etching process is applied to remove the embedded semiconductor layer. 102A to remove it. For example, a dry etching process can be used to selectively remove the embedded semiconductor layer. 102Ato remove SiGe using an etchant containing HBr, O2, and N2. In another example, a wet etching process is used to selectively remove the embedded semiconductor layer. 102A SiGe using a solution of NH4OH, H2O2 and H2O.

[0053] With reference to Fig. 15 carries out the procedure 200 by forming an insulating layer 122 on the back of the workpiece 300 with an operation 222 on. The insulating layer 122 is a dielectric layer and can comprise silicon oxide, silicon nitride, silicon oxynitride, a low k-value dielectric, another suitable dielectric, or combinations thereof. The insulating layer 122 It can be formed by a suitable deposition technique, such as CVD, ALD, or flowable CVD (FCVD), and can be followed by a CMP process. In some embodiments, the insulating layer comprises122 a thickness in the range between 10 nm and 30 nm.

[0054] With reference to Fig. 16 is proceeding with the procedure 200 with an operation 224 to access one or more contact holes (or backside contact holes) 150 in the insulation layer 122 to form it using a process that includes lithography and etching. The process for forming the backside contact hole. 150 is similar to the procedure for forming the front-side contact hole 142 In this embodiment, the backside contact holes 150 on source elements 108 aligned, with the source elements 108 within the corresponding backside contact holes 150 are exposed. In particular, the lithography process forms a structured resist with an opening that is located at the source element. 108is aligned. The etching process transfers the opening to the insulating layer. 122 , to expose the source element. In some embodiments, the etching process further includes etching onto the semiconductor substrate. 102 , such as etching the lower section of the active fin region to expose the source element 108 .

[0055] With reference to Fig. 17 carries out the procedure 200 with an operation 226 to one or more contact elements (also called backside contact elements) 120 in the contact hole 150 to form. In this embodiment, a silicide layer is formed. 152 on the source element 108 Formed to reduce contact resistance. The silicide layer 152 It includes silicon and metals, such as titanium silicide, tantalum silicide, nickel silicide, or cobalt silicide. The silicide layer 152In terms of composition and formation, it is similar to the silicide layer. 144 The silicide layer 152 However, it forms on the back of the workpiece. In particular, the silicide layer... 152 on the lower surface of the source element 108 formed, while the silicide layer 144 on the upper surface of the drain element 110 is educated.

[0056] The contact hole 150 It is filled with one or more conductive materials, such as Ti, TiN, TaN, Co, W, Al, Cu, or a combination thereof. Forming the backside contact element. 120 This involves the deposition of one or more conductive materials and CMPs, as illustrated in some examples. The deposition can be implemented using a suitable deposition technique, such as CVD, ALD, plating, or another suitable method. The resulting backside contact element 120has a thickness similar to that of the insulation layer 122 is, for example, in a range between 10 nm and 30 nm.

[0057] With reference to Fig. 18 carries out the procedure 200 with an operation 228 further to add another dielectric layer or a backside ILD layer (image layer) 124 to form structures similar in composition and formation to the ILD layer 130 is. The formation of the image layer. 124 In some embodiments, it may include deposition and CMP.

[0058] Still referring to Fig. 18 carries out the procedure 200 with an operation 230 away, to the BILD layer 124 to structure in order to create one or more trenches through the lithography process and etching 154 to form. A hard mask can be used to create the image layer. 124to structure the image. An etching process is used to cut through the image layers. 124 to etch until the backside contact element 120 has been disclosed.

[0059] With reference to Fig. 19 continues the procedure 200 with an operation 232 to proceed to one or more rear power rails (BPR) 118 in the trenches 154 the BILD layer 124 to form. The BPR 118 It comprises one or more conductive materials, such as Ti, TiN, TaN, Co, W, Al, Cu, or a combination thereof. The formation of the BPR 118 This includes the deposition of one or more conductive materials and CMP according to some embodiments. The deposition can be implemented by a suitable deposition technique, such as PVD, ALD, plating, CVD, another suitable method, or a combination thereof. In particular, the BPR 118 designed and configured, via the rear contact element120 to be electrically connected to the FET, such as by connecting it to the source element 108 of the FET in this embodiment. Other manufacturing steps can be implemented before, during, and after the operations of the process.

[0060] This disclosure provides a semiconductor structure comprising backside busbars formed on the rear side of the substrate and a method for fabricating the same according to various embodiments. Such a formed semiconductor structure comprises backside busbars on the rear side and an interconnect structure on the front side for the collective routing of power lines, such that the drain elements are connected to the corresponding power lines through the interconnect structure and the source elements are connected to the corresponding power lines through the backside busbars. In particular, the semiconductor structure comprises backside contact elements located at the rear side of the source elements and electrically connecting the backside busbars to the source elements; and frontside contact elements located at the drain elements and electrically connecting to the conductive elements of the upper layer (e.g.,The interconnect structure is connected to metal traces. Furthermore, both the front and back contact elements incorporate silicide layers to further reduce contact resistance. The disclosed structure reduces routing resistance, increases alignment margins, enhances layout flexibility, and improves packing density. The disclosed structure provides greater flexibility for circuit design layout and a wider IC fabrication process window, making it suitable for advanced technology nodes.

[0061] The disclosed structure can be used in various applications where FinFETs are integrated for improved performance. For example, the FinFETs can be used with multi-fin devices to form random-access memory (SRAM) cells. In other examples, the disclosed structure can be integrated into various integrated circuits, such as logic circuits, dynamic random-access memory (DRAM), flash memory, or imaging sensors.

[0062] In an example, this disclosure provides a semiconductor structure according to some embodiments. The semiconductor structure comprises a substrate having a front and a back side; a gate stack formed at the front of the substrate and located at an active region of the substrate; a first source / drain element formed at the active region and located at an edge of the gate stack; a back-side busbar formed at the back of the substrate; and a back-side contact element inserted between the back-side busbar and the first source / drain element, electrically connecting the back-side busbar to the first source / drain element.

[0063] Another aspect of this disclosure relates to a semiconductor structure. The semiconductor structure comprises a substrate having a front and a back side; an active fin region projecting from the front side of the substrate; a gate stack located on the active fin region; a source element and a drain element formed on the active region, with the gate stack situated between them; a front contact element located on the drain element on the front side of the substrate; a back bus bar formed on the back side of the substrate; and a back contact element inserted between the back bus bar and the source element, the back contact element electrically connecting the back bus bar to the source element.

[0064] Another aspect of this disclosure relates to a method for forming an integrated circuit structure. The method comprises taking up a substrate having a front face and a back face; forming a shallow trench insulating element (STI element) in the front face of the substrate, thereby forming an active fin region surrounded by the STI element; forming a gate stack at the active fin regions; forming a source element and a drain element at the active fin regions, the gate stack extending from the source element to the drain element; forming an interconnect structure at the gate stack, the source element, and the drain element from the front, the interconnect structure comprising a front-side contact element that contacts the drain element;Thinning the substrate from the back surface so that the source element is exposed with an exposed surface; forming a backside contact element located at the exposed surface of the source element; and forming a backside busbar located at the backside contact element.

[0065] The above has outlined elements of various embodiments. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments introduced herein. They should also understand that such corresponding designs do not deviate from the spirit and scope of this disclosure and that they can make various changes, substitutions, and modifications to it without deviating from the spirit and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62 / 954532

[0001]

Claims

[1] Semiconductor structure, comprising: a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source / drain element formed at the active region and disposed at an edge of the gate stack; a backside bus bar formed on the backside of the substrate; and a backside contact element formed between the backside bus bar and the first source / drain element and electrically connecting the backside bus bar to the first source / drain element, whereby the backside contact element further comprises a first silicide layer arranged on the backside of the substrate. [2] The semiconductor structure of claim 1, wherein the first silicide layer of the backside contact element directly contacts a bottom surface of the first source / drain element. [3] The semiconductor structure of claim 1 or 2, wherein the backside contact element further extends into the first source / drain element with a raised contact area. [4] Semiconductor structure according to one of the preceding claims, further comprising: a second source / drain element formed at the active region; and an interconnect structure formed on the gate stack and the first and second source / drain elements, the interconnect structure further comprising a front-side contact element directly contacting the second source / drain element. [5] The semiconductor structure of claim 4, wherein the front side contact element comprises a second silicide layer in direct contact with a top surface of the second source / drain element. [6] The semiconductor structure of claim 5, wherein the second silicide layer of the front side contact element is disposed on the front side of the substrate and directly contacts the upper surface of the second source / drain element. [7] The semiconductor structure of any preceding claim, further comprising a shallow trench isolation (STI) element adjacent to an active region, wherein the active region is an active fin region extruded over a top surface of the STI element. [8] The semiconductor structure of claim 7, further comprising a first dielectric layer disposed on the active fin region at the rear side; and a second dielectric layer disposed on the first dielectric layer, wherein the backside contact element is embedded in the first dielectric layer, and the backside busbar is embedded in the second dielectric layer. [9] The semiconductor structure of claim 8, wherein the first and second dielectric layers have different compositions. [10] The semiconductor structure of claim 8 or 9, wherein the first dielectric layer directly contacts the STI element. [11] Semiconductor structure, comprising: a substrate having a front side and a back side; an active fin region protruding from the front of the substrate; a gate stack arranged at the active fin region; a source element and a drain element formed at the active region and between which the gate stack lies; a front contact element adjacent to the drain element on the front side of the substrate; a backside bus bar formed on the backside of the substrate; and a backside contact element inserted between the backside bus bar and the source element, the backside contact element electrically connecting the backside bus bar to the source element, the backside contact element having a first silicide layer arranged on the backside and in direct contact with the source element, and the front side contact element has a second silicide layer arranged on the front side and in direct contact with the drain element. [12] The semiconductor structure of claim 11, wherein the first silicide layer directly contacts a lower surface of the source element; and the second silicide layer directly contacts an upper surface of the drain element. [13] Semiconductor structure of claim 11 or 12, wherein the backside contact element further extends into the source element; and the frontside contact element further extends into the drain element. [14] Semiconductor structure according to one of claims 11 to 13, further comprising a first dielectric layer disposed on the active fin region and the STI element on the backside of the substrate; and a second dielectric layer disposed on the first dielectric layer, wherein the backside contact element is embedded in the first dielectric layer, the backside busbar is embedded in the second dielectric layer, and the first and second dielectric layers differ in composition. [15] The semiconductor structure of any one of the preceding claims 11 to 14, further comprising a shallow trench isolation (STI) element adjacent to an active fin region, wherein the active fin region is extruded over a top surface of the STI element. [16] A method of forming an integrated circuit structure, comprising: Obtaining a substrate comprising a front side and a back side; Forming a shallow trench isolation (STI) element in the front surface of the substrate, thereby defining an active fin region surrounded by the STI element; Forming a gate stack at the active fin regions; Forming a source element and a drain element at the active fin regions, wherein the gate stack extends from the source element to the drain element; Forming an interconnect structure on the gate stack, the source element and the drain element from the front surface, the interconnect structure comprising a front side contact element contacting the drain element; Thinning the substrate from the back surface so that the source element is exposed with an exposed surface; Forming a backside contact element located on the exposed surface of the source element; and Forming a rear busbar that lies on the rear contact element. [17] The method of claim 16, wherein forming the backside contact element comprises forming a first silicide layer in direct contact with the source element; and forming the interconnect structure comprises forming a second silicide layer in direct contact with the drain element. [18] The method of claim 16 or 17, wherein forming the back contact element comprises Depositing a dielectric layer of a first dielectric on the substrate comprising the exposed surface of the source element; Structuring the dielectric layer to form a contact opening; Forming the first silicide layer on the source element exposed within the contact opening; and Filling a first conductive material in the contact opening to form the back contact element. [19] The method of claim 18, wherein forming the backside contact element comprises depositing a backside interlayer dielectric (BILD) layer of a second dielectric on the dielectric layer, the second dielectric different from the first dielectric in composition; Patterning the BILD layer to form a trench for exposing the backside contact element; and Depositing a second conductive material in the trench to form the backside busbar. [20] The method of any one of claims 16 to 19, wherein receiving the substrate comprises forming a silicon germanium layer on a semiconductor surface; and epitaxially growing a silicon layer on the silicon germanium; and thinning the substrate comprises polishing the silicon layer; selectively etching the silicon layer; and selectively etching the silicon germanium layer.