METHOD FOR THEIR MANUFACTURING

Abstract

Method for manufacturing a semiconductor device (50) comprising the following steps: Etching a first trench (106) in a multilayer stack (104), wherein the multilayer stack (104) comprises alternating dielectric layers (104A) and sacrificial layers (104B); Widening the first trench (106) to create the first side wall recesses (110); Deposition of a first conductive material (112A) to fill the first trench (106); after the separation of the first conductive material (112A) etching of a second trench (120) in the multilayer stack (104); Widening the second trench (120) to create second side wall recesses (124); Deposition of a second conductive material (112B) to fill the second trench (120); and Etching of the first conductive material (112A) and the second conductive material (112B).

Description

background

[0001] Semiconductor memory is used in integrated circuits for electronic applications such as radios, televisions, mobile phones, and personal computers. Semiconductor memory is divided into two main categories: volatile and non-volatile. Volatile memory is random-access memory (RAM), which can be further subdivided into static random-access memory (SRAM) and dynamic random-access memory (DRAM). SRAM and DRAM are both volatile because they lose the information they store when they are not powered.

[0002] In contrast, non-volatile memory can retain data. One type of non-volatile semiconductor memory is ferroelectric random-access memory (FeRAM or FRAM). Advantages of FeRAM include its high read / write speed and small size.

[0003] US 2011 / 0 199 804 A1 discloses a method for manufacturing a multilayer memory cell with active patterns that serve as current paths for electrical connection to two different memory areas formed at the same level, thereby enabling the memory cell to have an increased number of bits per unit area. US 9 570 464 B1 discloses a method for manufacturing a multilayer memory cell that incorporates a metal nitride film between the gate and the memory film. The metal nitride film provides improved adhesion between the gate and the memory film. US 2018 / 0 130 823 A1 and US 2020 / 0 119 047 A1 disclose methods for manufacturing multilayer memory cells that incorporate ferroelectric layers.

[0004] DE 10 2020 130 890 A1 discloses a method for forming a three-dimensional storage device, comprising: forming a layer stack over a substrate, wherein the layer stack has alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines; lining the sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines and source lines extending vertically through the third dielectric material; removing sections of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along the sidewalls of the openings;and filling the openings with a fourth dielectric material.;

[0005] US 2015 / 0243674A1 discloses: A plurality of layers of a first conductive material are etched to define a first plurality of stacks of conductive strips between a first plurality of trenches, wherein each stack has a width greater than twice a target width. A first storage layer is formed on the side faces of the conductive strips in the first plurality of trenches, and a first layer of a second conductive material is formed over the first storage layer. The first plurality of stacks is etched to define a second plurality of stacks of conductive strips between a second plurality of trenches, wherein each stack has a width equal to the target width.A second storage layer is formed on the side surfaces of the conductive strips in the second multitude of trenches, and a second layer of the second conductive material is formed above the second storage layer. Brief description of the drawings

[0006] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 is a block diagram of a random access memory according to some embodiments. The Fig. 2A and Fig. Figure 2B shows different representations of a storage matrix according to some embodiments. The Fig. 3A to 13D are different representations of intermediate stages in the production of a storage matrix according to some embodiments. The Fig. 14A and Fig. Figures 14B are different representations of a storage matrix according to some further embodiments. The Fig. 15A and Fig. Figure 15B shows various representations of a storage matrix according to some further embodiments. The Fig. 16A and Fig. Figure 16B shows various representations of a storage matrix according to some further embodiments. The Fig. 17A and Fig. Figure 17B shows various representations of a storage matrix according to some further embodiments. The Fig. 18A and Fig. Figures 18B are various representations of a storage matrix according to some further embodiments. The Fig. Figures 19A to 20B are different representations of intermediate stages in the production of a storage matrix according to some further embodiments. Detailed description

[0007] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0009] According to various embodiments, word lines for a memory matrix are manufactured using a multi-structuring process, wherein initial parts of the word lines and a first subset of transistors for the memory matrix are manufactured in a first structuring process, and subsequently, second parts of the word lines and a second subset of transistors for the memory matrix are manufactured in a second structuring process. This improves the aspect ratio of the columns of the memory matrix while preventing twisting or breakage of structural elements during manufacturing.

[0010] Fig. Figure 1 is a block diagram of a random-access memory 50 according to some embodiments. The random-access memory 50 comprises a memory matrix 52, a row decoder 54, and a column decoder 56. The memory matrix 52, the row decoder 54, and the column decoder 56 may each be part of the same semiconductor die or they may be part of different semiconductor dies. For example, the memory matrix 52 may be part of a first semiconductor die, while the row decoder 54 and the column decoder 56 may be part of a second semiconductor die.

[0011] The memory matrix 52 comprises memory cells 58, word lines 62, and bit lines 64. The memory cells 58 are arranged in rows and columns. The word lines 62 and the bit lines 64 are electrically connected to the memory cells 58. The word lines 62 are conductive lines that extend along the rows of the memory cells 58. The bit lines 64 are conductive lines that extend along the columns of the memory cells 58.

[0012] The row decoder 54 can be, for example, a static CMOS decoder (CMOS: complementary metal oxide semiconductor), a pseudo-NMOS decoder, or the like. During operation, the row decoder 54 selects the desired memory cells 58 in a row of the memory matrix 52 by activating the word line 62 for that row. The column decoder 56 can be, for example, a static CMOS decoder, a pseudo-NMOS decoder, or the like, and can include write drivers, read amplifiers, combinations thereof, or the like. During operation, the column decoder 56 selects bit lines 64 for the desired memory cells 58 from the columns of the memory matrix 52 in the selected row and reads data from or writes data to the selected memory cells 58 using the bit lines 64.

[0013] The Fig. 2A and Fig. 2B are different representations of a storage matrix 52 according to some embodiments. Fig. 2A is a circuit diagram of the memory matrix 52. Fig. 2B is a three-dimensional representation of a part of the memory matrix 52.

[0014] The memory matrix 52 is: a flash memory matrix, such as a NOR flash memory matrix; a high-speed memory matrix, such as a DRAM or an SRAM; a non-volatile memory, such as a reactive random-access memory (RRAM) or a magnetoresistive random-access memory (MRAM); or the like. The memory cells 58 are each a flash memory cell comprising a thin-film transistor (TFT) 68. A gate of each TFT 68 is electrically connected to a respective word line 62, a first source / drain region of each TFT 68 is electrically connected to a respective bit line 64, and a second source / drain region of each TFT 68 is electrically connected to a respective source line 66 (which are electrically grounded).The memory cells 58 in the same row of the memory matrix 52 use a common word line 62, while the memory cells in the same column of the memory matrix 52 use a common bit line 64 and a common source line 66.

[0015] The storage matrix 52 has several conductive lines (e.g., the word lines 62), with dielectric layers 72 arranged between adjacent word lines 62. The word lines 62 extend in a first direction D1, which is parallel to a main surface of an underlying substrate (which is in Fig. 2B is not shown, but will be shown later with reference to the Fig. (3A to 21B are discussed in more detail). The word lines 62 can have a step-like arrangement, such that lower word lines 62 are longer than upper word lines 62 and extend laterally beyond the endpoints of the upper word lines 62. For example, in Fig. Figure 2B shows several stacked layers of word lines 62, with the uppermost word lines 62A being the shortest and the lowermost word lines 62B being the longest. The respective lengths of the word lines 62 increase in a direction extending towards the substrate below. In this way, a portion of each word line 62 can be accessed from an area above the storage matrix 52, allowing conductive contacts to be established with an exposed portion of each word line 62.

[0016] The memory matrix 52 further comprises several conductive lines, such as bit lines 64 and source lines 66. The bit lines 64 and the source lines 66 extend in a second direction D2, which is perpendicular to the first direction D1 and the main surface of the underlying substrate. A dielectric layer 74 is arranged between adjacent bit lines 64 and source lines 66 and insulates them. The boundaries of each memory cell 58 are defined by pairs of bit lines 64 and source lines 66 together with a crossing word line 62. A dielectric pin 76 is arranged between adjacent pairs of bit lines 64 and source lines 66 and insulates them. Fig. 2A and Fig. Figure 2B shows a specific placement of the bit lines 64 in relation to the source lines 66, but it should be understood that the placement of the bit lines 64 and the source lines 66 can be rotated in other embodiments.

[0017] The memory matrix 52 further comprises ferroelectric strips 84 and semiconductor strips 82. The ferroelectric strips 84 are in contact with the word lines 62. The semiconductor strips 82 are arranged between the ferroelectric strips 84 and the dielectric layer 74.

[0018] The semiconductor strips 82 provide channel areas for the TFTs 68 of the memory cells 58. For example, if a corresponding voltage, which is higher than a respective threshold voltage (V), is applied... th) of a corresponding TFT 68, is applied by means of a corresponding word line 62, then an area of ​​a semiconductor strip 82 that crosses the word line 62 can allow a current to flow from the bit line 64 to the source lines 66 (e.g. in the direction D1).

[0019] The ferroelectric strips 84 are data storage layers that can be polarized in one of two different directions by applying a corresponding voltage difference across the ferroelectric strip 84. Depending on the polarization direction of a specific region of the ferroelectric strip 84, a threshold voltage of a corresponding TFT 68 changes, and a digital value (e.g., 0 or 1) can be stored. For example, if a region of the ferroelectric strip 84 has a first electrical polarization direction, the corresponding TFT 68 can have a relatively low threshold voltage, and if the region of the ferroelectric strip 84 has a second electrical polarization direction, the corresponding TFT 68 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage offset.A larger threshold voltage offset facilitates (e.g., reduces the error rate of) reading the digital value stored in the corresponding memory cell 58. Accordingly, the memory matrix 52 can also be referred to as a FeRAM matrix (FeRAM: ferroelectric direct-access memory).

[0020] To perform a write operation in a specific memory cell 58, a write voltage is applied across a region of the ferroelectric strip 84 corresponding to memory cell 58. The write voltage can be applied, for example, by applying appropriate voltages to the word line 62, the bit line 64, and the source line 66 corresponding to memory cell 58. Applying the write voltage across the region of the ferroelectric strip 84 changes the polarization direction of that region. This allows the corresponding threshold voltage of the TFT 68 to be switched from a low threshold voltage to a high threshold voltage (or vice versa), enabling a digital value to be stored in memory cell 58.Since the word lines 62 and the bit lines 64 intersect in the memory matrix 52, individual memory cells 58 can be selected and written to.

[0021] To perform a read operation in a specific memory cell 58, a read voltage (a voltage between the low and high threshold voltages) is applied to the word line 62 corresponding to memory cell 58. Depending on the polarization direction of the corresponding area of ​​the ferroelectric strip 84, the TFT 68 of memory cell 58 may or may not be switched on. This allows the bit line 64 to be discharged via the source line 66 (e.g., to ground) or not, so that the digital value stored in memory cell 58 can be determined. Since the word lines 62 and the bit lines 64 intersect in the memory matrix 52, individual memory cells 58 can be selected and read.

[0022] The Fig. Figures 3A to 15B are different representations of intermediate stages in the production of a memory matrix 52 according to some embodiments. Only a part of the memory matrix 52 is shown. Some structural elements, such as the stepped word lines (see Fig. 2B), are not shown for the sake of clarity. Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A and Fig. 15A are three-dimensional representations of the memory matrix 52. Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B and Fig. 15B are sectional views taken along a reference cross-section B - B of Fig. 12A are shown.

[0023] In the Fig. 3A and Fig. In step 3B, a substrate 102 is provided. The substrate 102 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 102 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of substrate 102 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof. The substrate 102 may comprise a dielectric material. For example, the substrate 102 may be a dielectric substrate, or it may have a dielectric layer on a semiconductor substrate.Suitable dielectric materials for dielectric substrates are oxides, such as silicon oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; or the like; or combinations thereof, such as silicon oxide nitride, silicon oxide carbide, silicon carbonitride, or the like. In some embodiments, the substrate 102 is made of silicon carbide.

[0024] A multilayer stack 104 is fabricated on top of the substrate 102. The multilayer stack 104 comprises alternating first dielectric layers 104A and second dielectric layers 104B. The first dielectric layers 104A are made of a first dielectric material, and the second dielectric layers 104B are made of a second dielectric material. The dielectric materials can each be selected from those suitable for the substrate 102. In the illustrated embodiment, the multilayer stack 104 comprises five first dielectric layers 104A and four second dielectric layers 104B. However, it should be understood that the multilayer stack 104 can comprise any number of first dielectric layers 104A and second dielectric layers 104B.

[0025] During subsequent processing, the multilayer stack 104 is structured. Therefore, the dielectric materials of the first dielectric layers 104A and the second dielectric layers 104B exhibit high etch selectivity with respect to the substrate 102. The structured first dielectric layers 104A are used to insulate subsequently fabricated TFTs. The structured second dielectric layers 104B are sacrificial (or dummy) layers that are removed during subsequent processing and replaced by word lines for the TFTs. Therefore, the second dielectric material of the second dielectric layers 104B also exhibits high etch selectivity with respect to the first dielectric material of the first dielectric layers 104A.In embodiments where the substrate 102 is made of silicon carbide, the first dielectric layers 104A can be made of an oxide, such as silicon oxide, and the second dielectric layers 104B can be made of a nitride, such as silicon nitride. Other combinations of dielectric materials that have suitable etch selectivity towards each other can also be used.

[0026] Each layer of the multilayer stack 104 can be fabricated using a suitable deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The thickness of each layer can range from approximately 15 nm to approximately 90 nm. In some embodiments, the first dielectric layers 104A are fabricated with a different thickness than the second dielectric layers 104B. For example, the first dielectric layers 104A can be fabricated with a first thickness T1, and the second dielectric layers 104B can be fabricated with a second thickness T2, where the second thickness T2 is approximately 0% to approximately 100% smaller than the first thickness T1. The multilayer stack 104 can have a total height H1 of approximately 1000 nm to approximately 10,000 nm (e.g., approximately 2000 nm).

[0027] As will be explained in more detail later, the Fig. 4A to 11B describe a process in which trenches are structured in the multilayer stack 104 and TFTs are fabricated in the trenches. Specifically, a multi-structuring process is used to fabricate the TFTs. The multi-structuring process can be a double-structuring process, a quadruple-structuring process, or the like. Fig. Figures 4A to 11B show a double structuring process. In a double structuring process, the first trenches are formed (see Figure 106). Fig. 4A and Fig. 4B) in the multilayer stack 104 is structured with a first etching process, and components for a first subset of the TFTs are produced in the first trenches 106. Then second trenches 120 (see Fig. 8A and Fig. 8B) in the multilayer stack 104 is structured using a second etching process, and a second subset of the TFTs is produced in the second trenches 120. By producing the TFTs using a multiple structuring process, each structuring process can be performed with a low feature density, which on the one hand can help to reduce defects while still allowing the memory matrix 52 to have a sufficient memory cell density, and on the other hand can help to prevent an aspect ratio from becoming too high and problems with constructive instability from arising.

[0028] In the embodiment discussed above, it is shown that the memory matrix 52 is fabricated directly on top of the substrate 102 (e.g., a semiconductor substrate) in a FEOL process (FEOL: Front End of Line), but this is for illustrative purposes only and is not intended to limit the embodiments. Rather, the memory matrix 52 can be fabricated either in a FEOL process or in a BEOL process (BEOL: Back End of Line), and it can be fabricated either as an embedded memory matrix or as a separate structure. Any suitable fabrication method for the memory matrix 52 can be used.

[0029] In the Fig. 4A and Fig. In step 4B, first trenches 106 are created in the multilayer stack 104. In the illustrated embodiment, the first trenches 106 extend through the multilayer stack 104 and expose the substrate 102. In another embodiment, the first trenches 106 extend through some, but not all, layers of the multilayer stack 104. The first trenches 106 can be created using suitable photolithographic and etching processes, such as an etching process that is selective for the multilayer stack 104 (e.g., one that etches the dielectric materials of the first dielectric layers 104A and the second dielectric layers 104B faster than the substrate 102 material). The etching can be performed using any suitable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.In some embodiments, where the substrate 102 is made of silicon carbide, the first dielectric layers 104A are made of silicon oxide, and the second dielectric layers 104B are made of silicon nitride, the first trenches 106 can be produced by dry etching using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2) gas.

[0030] A portion of the multilayer stack 104 is located between each pair of the first trenches 106. Each portion of the multilayer stack 104 can have a width W1 of approximately 50 nm to approximately 500 nm (e.g., approximately 240 nm) and a height H1, which is determined with reference to the Fig. 3A and Fig. 3B has been discussed. Furthermore, the individual parts of the multilayer stack 104 are separated from one another by a separation distance S1, which can be approximately 50 nm to approximately 200 nm (e.g., approximately 80 nm). An aspect ratio (AR) of each part of the multilayer stack 104 is a ratio of the height H1 to a width of the narrowest structural element of the part of the multilayer stack 104, which at this processing stage is the width W1. In some embodiments, when producing the first trenches 106, the aspect ratio of each part of the multilayer stack 104 is approximately 5 to approximately 15. If each part of the multilayer stack 104 is produced with an aspect ratio of less than approximately 5, the memory matrix 52 may not have a sufficient memory cell density.However, if each part of the multilayer stack 104 is manufactured with an aspect ratio of more than approximately 15, the multilayer stack 104 may twist or break apart during subsequent processing.

[0031] In the Fig. 5A and Fig. In step 5B, the first trenches 106 are widened to create first sidewall recesses 110. In particular, portions of the sidewalls of the second dielectric layers 104B, exposed by the first trenches 106, are recessed by the first sidewall recesses 110. Although the sidewalls of the second dielectric layers 104B are shown as straight, they can also be concave or convex. The first sidewall recesses 110 can be created using a suitable etching process, such as one that is selective for the material of the second dielectric layers 104B (e.g., one that selectively etches the material of the second dielectric layers 104B faster than the materials of the first dielectric layers 104A and the substrate 102). The etching can be isotropic.In embodiments where the substrate 102 is made of silicon carbide, the first dielectric layers 104A are made of silicon oxide, and the second dielectric layers 104B are made of silicon nitride, the first grooves 106 can be widened by wet etching using phosphoric acid (H3PO4). However, any suitable etching method, such as selective dry etching, can be used.

[0032] After creation, the first sidewall recesses 110 have a depth D3 that extends beyond the sidewalls of the first dielectric layers 104A. To stop the etching of the first sidewall recesses 110 after they have reached a desired depth D3, timed etching processes can be used. For example, if phosphoric acid is used to etch the second dielectric layers 104B, the first sidewall recesses 110 can have a depth D3 of approximately 10 nm to approximately 60 nm (e.g., approximately 40 nm). Creating the first sidewall recesses 110 reduces the width of the second dielectric layers 104B. In the above example, the second dielectric layers 104B can have a width W2 of approximately 50 nm to approximately 450 nm (e.g., approximately 160 nm) after etching.As explained above, the aspect ratio (AR) of each part of the multilayer stack 104 is the ratio of the height H1 to the width of the narrowest structural element of the part of the multilayer stack 104, which at this processing stage is the width W2. By creating the first sidewall recesses 110, the aspect ratio of each part of the multilayer stack 104 is thus increased. In some embodiments, after creating the first sidewall recesses 110, the aspect ratio of each part of the multilayer stack 104 remains within the aforementioned range and is, for example, approximately 5 to approximately 15. Thus, the advantages of such an aspect ratio (discussed above) can still be achieved.

[0033] In the Fig. 6A and Fig. In 6B, first conductive structural elements 112A are produced in the first sidewall recesses 110 to fill and / or overfill the first trenches 106, thereby completing a process for replacing first portions of the second dielectric layers 104B. The first conductive structural elements 112A may each have one or more layers, such as seed layers, adhesive layers, barrier layers, diffusion layers, filler layers, and the like. In some embodiments, the first conductive structural elements 112A each have a seed layer (or adhesive layer) 112A. S and a main layer 112A M on, but in other embodiments the seed layer 112A S be omitted. Each seed layer 112A S extends along three sides (e.g. a top, a side wall and a bottom) of the material of a corresponding main layer 112A M, which is located in the first side wall recesses 110. The seed layers 112A S are manufactured from a first conductive material that can be used to support the growth or adhesion of the subsequently deposited material, such as titanium nitride, tantalum nitride, titanium, tantalum, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides thereof, or the like. The main layers 112A M They can be made from a second conductive material, such as a metal, e.g., tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, or molybdenum nitride, alloys thereof, or the like. The seed layer material is 112A. S is a material with good adhesion to the material of the first dielectric layers 104A, and the material of the main layers 112A M is a material with good adhesion to the material of the seed layer 112A SIn embodiments where the first dielectric layers 104A are made from an oxide, such as silicon oxide, the seed layer 112A S are made of titanium nitride, and the main layers are 112A M can be made from tungsten. The seed layer 112A S and the main layers 112A M can each be produced using a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

[0034] After the first conductive structural elements 112A have been deposited to fill and / or overfill the first trenches 106, they can be planarized to remove excess material outside the trenches 106, so that after planarization, the first conductive structural elements 112A completely span the upper part of the first trenches 106. In one embodiment, the first conductive structural elements 112A can be planarized, for example, using a CMP process (CMP: chemical-mechanical planarization). However, any suitable planarization process, such as a grinding process, can be used.

[0035] In the Fig. 7A and Fig. 7B Second trenches 120 are produced in the multilayer stack 104. In the illustrated embodiment, the second trenches 120 extend through the multilayer stack 104 and expose the substrate 102. In another embodiment, the second trenches 120 extend through some, but not all, layers of the multilayer stack 104. The second trenches 120 can be produced by suitable photolithographic and etching processes, such as an etching process that is selective for the multilayer stack 104 (e.g., one that etches the dielectric materials of the first dielectric layers 104A and the second dielectric layers 104B faster than the substrate 102 material). The etching can be carried out by any suitable etching process and, in some embodiments, may be similar to the etching used to produce the first trenches 106, which is described with reference to the Fig. 4A and Fig. 4B has been discussed.

[0036] A portion of the multilayer stack 104 is located between every second trench 120 and every first trench 106. Each portion of the multilayer stack 104 can have a width W3 of approximately 50 nm to approximately 500 nm and a height H1, which is determined with reference to the Fig. 3A and Fig. as discussed in Section 3B. Furthermore, the individual parts of the multilayer stack 104 are separated from one another by a separation distance S2, which can be approximately 50 nm to approximately 200 nm. The aspect ratio of each part of the multilayer stack 104 is the ratio of the height H1 to the width of the narrowest structural element of the part of the multilayer stack 104, which at this processing stage is the width W3. In some embodiments, when producing the second trenches 120, the aspect ratio of each part of the multilayer stack 104 is approximately 5 to approximately 15. If each part of the multilayer stack 104 is produced with an aspect ratio of less than approximately 5, the storage matrix 52 may not have a sufficient storage cell density. Conversely, if each part of the multilayer stack 104 is produced with an aspect ratio greater than approximately 15, the multilayer stack 104 may twist or break apart during subsequent processing.

[0037] In the Fig. 8A and Fig. In step 8B, the second trenches 120 are widened to create second sidewall recesses 124. In particular, the remaining parts of the second dielectric layers 104B are removed to create the second sidewall recesses 124. The second sidewall recesses 124 thus expose parts of the first conductive structural elements 112A, e.g., the seed layer 112A. S , or in embodiments where the seed layer is 112A S is not present, the main layer 112A MThe second sidewall recesses 124 can be produced by a suitable etching process, such as one that is selective for the material of the second dielectric layers 104B (e.g., one that selectively etches the material of the second dielectric layers 104B faster than the materials of the first dielectric layers 104A and the substrate 102). The etching can be carried out by any suitable etching method, and in some embodiments it can be similar to the etching used to produce the first sidewall recesses 110, as described in the Fig. 5A and Fig. 5B has been discussed. After creation, the second sidewall recesses 124 have a depth D4 that extends beyond the sidewalls of the first dielectric layers 104A. In some embodiments, the depth D4 is similar to the depth D3, which is discussed with reference to the Fig. 5A and Fig. 5B has been discussed. In another embodiment, the depth D4 is different from that discussed with reference to the Fig. 5A and Fig. 5B discussed depth D3 differently (e.g., larger or smaller than this).

[0038] In the Fig. 9A and Fig. 9B Second conductive structural elements 112B are fabricated in the second sidewall recesses 124 to fill and / or overfill the second trenches 120, thereby completing a process for replacing second portions of the second dielectric layers 104B. This results in the burying of inner layers of the first conductive structural elements 112A and the second conductive structural elements 112B (e.g., adhesive layers or seed layers) in the word conductor 112. The second conductive structural elements 112B can be fabricated from materials and processes selected from the same group of eligible materials and processes as for the first conductive structural elements 112A. The first conductive structural elements 112A and the second conductive structural elements 112B can be fabricated from the same material or from different materials.In some embodiments, the second conductive structural elements 112B each have a seed layer 112B. S and a main layer 112B M on, but in other embodiments the seed layer 112B S be omitted. Seed layer 112B S and the main layers 112B M The second conductive structural elements 112B can have similar thicknesses to the seed layer 112A. S or the main layers 112A M the first conductive structural elements 112A have. In some embodiments, the seed layer 112A S and the seed layer 112B S made from similar materials, and in this case the seed layer can be 112A S and the seed layer 112B SThey fuse together during manufacturing so that no discernible interfaces exist between them. In another embodiment (which will be discussed in more detail later), the seed layer 112A S and the seed layer 112B S made from different materials, and in this case the seed layer can be 112A S and the seed layer 112B S They do not fuse during manufacturing, so that recognizable interfaces exist between them.

[0039] After the second conductive structural elements 112B have been deposited to fill and / or overfill the second trenches 120, they can be planarized to remove excess material outside the second trenches 120, so that after planarization, the second conductive structural elements 112B completely span the upper portion of the second trenches 120. In one embodiment, the second conductive structural elements 112B can be planarized, for example, using a CMP process. However, any suitable planarization process, such as a grinding process, can be used.

[0040] The first conductive structural elements 112A and the second conductive structural elements 112B are collectively referred to as word lines 112 of the memory matrix 52. Adjacent pairs of the first conductive structural elements 112A and the second conductive structural elements 112B are in physical contact with each other and are electrically connected. Thus, each pair consisting of a first conductive structural element 112A and a second conductive structural element 112B functions as a single word line 112.

[0041] The Fig. 10A and Fig. Figure 10B shows a back-etching process for removing excess portions of the first conductive structural elements 112A and the second conductive structural elements 112B and for exposing the second dielectric layers 104B. In one embodiment, the back-etching process can be carried out, for example, with an anisotropic etching process. However, any suitable etching method can be used.

[0042] In one embodiment, the etching process is carried out until the materials of the first conductive structural elements 112A and the second conductive structural elements 112B that are not covered by the first dielectric layers 104A have been removed. Therefore, the remaining materials of the first conductive structural elements 112A and the second conductive structural elements 112B have a similar width to the remaining portion of the first dielectric layers 104A (e.g., 80 nm). However, any suitable dimensions can be used.

[0043] As also in Fig. As can be clearly seen in 10B, the first conductive structural element 112A and the second conductive structural element 112B in the word line 112 can have the same widths, which are, for example, each approximately 40 nm. Furthermore, the seed layers (e.g., the seed layers 112A) can S and 112B S) have an H-shape and can also have a thickness T3 along the top and bottom of the first conductive structural elements 112A and the second conductive structural elements 112B, as well as a thickness T4 with which they are buried in the word line 112, with the seed layers 112A S and 112B S They fuse together so that each contributes individually to the thickness. In one embodiment, the thickness T3 can be approximately 0.1 nm (1 Å) to approximately 10 nm (100 Å), while the thickness T4 can be approximately 0.2 nm (2 Å) to approximately 20 nm (200 Å). However, any suitable thickness can be used.

[0044] Fig. Figure 10C shows a further embodiment in which the first conductive structural element 112A in the word line 112 can have a different width than the second conductive structural element 112B in the word line 112. For example, in one embodiment, the second groove 120 can be generated such that it is offset from a midpoint between two of the first grooves 106 (e.g., due to an unintentional misalignment of the masks). Therefore, although the word line 112 can have the same overall width, the second side wall recesses 124 can have a greater width than the first side wall recesses 110, so that the second conductive structural elements 112B in the word line 112 have a greater width than the first conductive structural elements 112A.For example, the first conductive structural elements 112A can have a width W4 of approximately 1 nm (10 Å) to approximately 50 nm (500 Å), while the second conductive structural elements 112B can have a larger width W5 of approximately 1.5 nm (15 Å) to approximately 100 nm (1000 Å). However, any suitable width can be used.

[0045] The Fig. 11A and Fig. Figure 11B shows that TFT layer stacks are fabricated in the first trenches 106 and the second trenches 120. In particular, two ferroelectric strips 114, one semiconductor strip 116, and one dielectric layer 118 are fabricated in each of the first trenches 106 and the second trenches 120. In this embodiment, no further layers are fabricated in the first trenches 106 and the second trenches 120. In another embodiment (which will be discussed in more detail later), further layers are fabricated in the first trenches 106 and the second trenches 120.

[0046] The ferroelectric strips 114 are data storage strips made from a ferroelectric material suitable for storing digital values, such as hafnium zirconium oxide (HfZrO); hafnium aluminum oxide (HfAlO); zirconium oxide (ZrO); hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), or the like; undoped hafnium oxide (HfO); or the like. The material for the ferroelectric strips 114 can be deposited by a suitable deposition process, such as ALD, CVD, physical vapor deposition (PVD), or the like.

[0047] The semiconductor strips 116 are manufactured from a semiconductor material suitable for providing channel regions for TFTs, such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), polysilicon, amorphous silicon, or the like. The material of the semiconductor strips 116 can be deposited using a suitable deposition process, such as ALD, CVD, PVD, or the like.

[0048] The dielectric layers 118 are made from a dielectric material. Suitable dielectric materials are oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; or the like, or combinations thereof, such as silicon oxide nitride, silicon carbonitride, or the like. The material of the dielectric layers 118 can be deposited using a suitable deposition method, such as ALD, CVD, flowable CVD (FCVD), or the like.

[0049] The ferroelectric strips 114, the semiconductor strips 116, and the dielectric layers 118 can be fabricated using a combination of deposition, etching, and planarization. For example, a ferroelectric layer can be conformally deposited on the multilayer stack 104 and in the first trenches 106 (e.g., on sidewalls of the first conductive structural elements 112A and on sidewalls of the first dielectric layers 104A). Then, a semiconductor layer can be conformally deposited onto the ferroelectric layer. The semiconductor layer can then be anisotropically etched to remove horizontal portions of the semiconductor layer, thus exposing the ferroelectric layer. A dielectric layer can then be conformally deposited onto the remaining vertical portions of the semiconductor layer and the exposed portions of the ferroelectric layer.Subsequently, a planarization process is performed on the various layers to remove excess material above the multilayer stack 104. The planarization process can be chemical-mechanical polishing (CMP), a back-etching process, a combination thereof, or the like. The portions of the ferroelectric layer, the semiconductor layer, and the dielectric layer remaining in the initial trenches 106 form the ferroelectric strips 114, the semiconductor strips 116, and the dielectric layers 118, respectively. The planarization process exposes the multilayer stack 104, such that after the planarization process, the top surfaces of the multilayer stack 104, the ferroelectric strips 114, the semiconductor strips 116, and the dielectric layers 118 are coplanar (within process variations).

[0050] In the Fig. 12A and Fig. In the embodiment shown, dielectric pins 132 are formed through the dielectric layers 118 and the semiconductor strips 116. The dielectric pins 132 are insulating columns arranged between adjacent TFTs, physically and electrically isolating them. In the illustrated embodiment, the dielectric pins 132 do not extend through the ferroelectric strips 114. Different regions of the ferroelectric strips 114 can be individually polarized, and thus the ferroelectric strips 114 can function to store values ​​even when adjacent regions are not physically and electrically isolated. In another embodiment, the dielectric pins 132 are also formed through the ferroelectric strips 114. The dielectric pins 132 also extend through the first dielectric layers 104A and the remaining portions of the second dielectric layers 104B.

[0051] As an example of how to fabricate the dielectric pins 132, openings for the dielectric pins 132 can be created through the dielectric layers 118 and the semiconductor strips 116. The openings can be created using suitable photolithographic and etching techniques. Then, one or more dielectric materials are deposited in the openings. Suitable dielectric materials are oxides, such as silicon oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; or the like; or combinations thereof, such as silicon oxide nitride, silicon oxide carbide, silicon carbonitride, or the like. The dielectric materials can be deposited using a suitable deposition technique such as ALD, CVD, or the like. In some embodiments, silicon oxide or silicon nitride is deposited in the openings.A planarization process is then performed on the various layers to remove excess dielectric material above the uppermost first dielectric layer 104A. The planarization process can be a CMP process, a back-etching process, a combination thereof, or the like. The remaining dielectric material forms the dielectric pins 132 in the openings.

[0052] The Fig. 12A and Fig. Figure 12B further shows that bit lines 134 and source lines 136 are fabricated through the dielectric layers 118. The bit lines 134 and the source lines 136 also extend through the first dielectric layers 104A and the remaining portions of the second dielectric layers 104B. The bit lines 134 and the source lines 136 function as the source / drain regions of the TFTs. The bit lines 134 and the source lines 136 are conductive pillars fabricated in pairs, with each semiconductor strip 116 contacting a corresponding bit line 134 and a corresponding source line 136. Each TFT has one bit line 134, one source line 136, one word line 112, and the regions of the semiconductor strip 116 and the ferroelectric strip 114 that intersect the word line 112. The dielectric pins 132 are each arranged between a bit line 134 of one TFT and a source line 136 of another TFT.In other words, a bit line 134 and a source line 136 are arranged on opposite sides of each of the dielectric pins 132. Thus, each dielectric pin 132 physically and electrically isolates adjacent TFTs.

[0053] As an example of how to fabricate the bit lines 134 and the source lines 136, openings for the bit lines 134 and the source lines 136 can be created through the dielectric layers 118. The openings can be created using suitable photolithographic and etching processes. In particular, the openings are created on opposite sides of the dielectric pins 132. Then, one or more conductive materials, e.g., an adhesive layer and a conductive solid, are deposited in the openings. Suitable conductive materials are metals such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, titanium nitride, tantalum nitride, combinations thereof, or the like. The conductive materials can be deposited using a suitable deposition process such as ALD or CVD, a suitable plating process such as electroplating or electroless plating, or the like.In some embodiments, tungsten is deposited in the openings. A planarization process is then performed on the various layers to remove excess conductive material above the uppermost first dielectric layer 104A. The planarization process can be a CMP process, a back-etching process, a combination thereof, or the like. The remaining conductive material forms the bit lines 134 and the source lines 136 in the openings.

[0054] In the Fig. From 13A to 13D, a connecting structure 140 is produced above the intermediate structure, wherein Fig. 13B a ​​sectional view of the structure of Fig. 13A shows, Fig. 13C a top-down view of the structure of Fig. 13A at the level of a first metal conductor 164 shows and Fig. 13D a top-down view of the structure of Fig. Figure 13A shows a metallization structure 142. For the sake of clarity, only some structural elements of the compound structure 140 are shown. Fig. Figure 13A shows the interconnect structure 140, which can, for example, comprise metallization structures 142 in a dielectric material 144. The dielectric material 144 can comprise one or more dielectric layers, such as one or more layers of a dielectric low-k (LK) or extremely low-k (ELK) material. The metallization structures 142 can be metallic interconnects (e.g., metal conductors and vias) fabricated in the one or more dielectric layers. The interconnect structure 140 can be fabricated using a Damascene process, such as a single-Damascene process, a dual-Damascene process, or the like.

[0055] In a particular embodiment described here, the metallization structures 142 of the interconnect structure 140 comprise the following: a first via 162 (e.g., a via 1) that makes contact with the bit lines 134 and the source lines 136; a first metal line 164 (e.g., a first upper metal line); a second via 166 (e.g., a via 1); and a second metal line 168 (e.g., a second upper metal line). These structural elements can each be fabricated as follows: depositing a portion of the dielectric material 144 (for clarity, shown in Fig. 13A not shown separately); generating structures in the portion of the dielectric material 144; filling the structures with one or more conductive materials; and planarizing the conductive materials with the dielectric material 144. However, any suitable number of vias and conductive traces may be used.

[0056] In some embodiments, the metallization structures 142 comprise bit line connections 142B (which are electrically connected to the bit lines 134) and source line connections 142S (which are electrically connected to the source lines 136). Adjacent bit lines 134 are connected to different bit line connections 142B, which helps to prevent a short circuit of the adjacent bit lines 134 when their common word line 112 is activated. Likewise, adjacent source lines 136 are connected to different source line connections 142S, which helps to prevent a short circuit of the adjacent source lines 136 when their common word line 112 is activated.

[0057] As in Fig. As can be seen in Figure 13C, the first vias 162 in the metallization structures 142 of the interconnection structure 140 are electrically connected to the bit lines 134 and the source lines 136. In this embodiment, the bit lines 134 and the source lines 136 are manufactured in a staggered layout, with adjacent bit lines 134 and adjacent source lines 136 along the first direction D1 (see Figure 13C). Fig. 2B) are laterally offset from one another. Thus, each word line 112 is arranged laterally between a dielectric pin 132 and a bit line 134 or a source line 136. The first vias 162 connected to the bit lines 134 and the first vias 162 connected to the source lines 136 each extend along the second direction D2 (see Fig. 2B), e.g., along the columns of the memory matrix 52. The first vias 162, which are connected to the bit lines 134, are connected to alternating bit lines 134 along the columns of the memory matrix 52. The first vias 162, which are connected to the source line connections 142S, are connected to alternating source lines 136 along the columns of the memory matrix 52. By laterally offsetting the bit lines 134 and the source lines 136, the need for cross-connections along the columns of the memory matrix 52 is eliminated, so that the metallization structures 142 located above the bit lines 134 and the source lines 136 can simply be conductive segments. In another embodiment, the bit lines 134 and the source lines 136 are not manufactured in a staggered layout, and instead a cross-connection is implemented in the connection structure 140.

[0058] In particular, it shows Fig. 13D the straight conductive segments in the higher-lying metallization structures 142 (e.g., the second metal conductor 168). As can be seen, since the lower-lying connections have been made in a staggered layout, the bit line connections 142B and the source line connections 142S can be placed in a straight line without the need for cross-connections. Such an alignment significantly increases the conductor density in the metallization layers.

[0059] The Fig. 14A and Fig. Figures 14B show various representations of a memory matrix 52 according to some further embodiments. Only a part of the memory matrix 52 is shown. Some structural elements, such as the stair-like word lines (see Figure 14B), are not shown. Fig. 2B), are not shown for the sake of clarity. Fig. 14A is a three-dimensional representation of the memory matrix 52, and Fig. 14B is a sectional view showing a cross-section similar to the reference cross-section B - B of Fig. 12A is shown.

[0060] In this embodiment, the ferroelectric strips 114 are omitted and replaced by a plurality of dielectric layers 150, which are data storage strips, thus enabling the creation of a NOR flash array. Specifically, first dielectric layers 150A are fabricated on the substrate 102 and in contact with the sidewalls of the word lines 112. Second dielectric layers 150B are fabricated on the first dielectric layers 150A. Third dielectric layers 150C are fabricated on the second dielectric layers 150B. The first dielectric layers 150A, the second dielectric layers 150B, and the third dielectric layers 150C are each fabricated from dielectric materials.Suitable dielectric materials are oxides, such as silicon oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; or the like; or combinations thereof, such as silicon nitride oxide, silicon carbide oxide, silicon carbonitride, or the like. In some embodiments, the first dielectric layers 150A and the third dielectric layers 150C are made from a first dielectric material (e.g., an oxide, such as silicon oxide), and the second dielectric layers 150B are made from another, second dielectric material (e.g., a nitride, such as silicon nitride). The dielectric materials can be deposited by a suitable deposition process such as ALD, CVD, or the like.For example, the first dielectric layers 150A, the second dielectric layers 150B and the third dielectric layers 150C can be produced by a combination of deposition, etching and planarization in a similar manner to that described above for the ferroelectric strips 114.

[0061] The Fig. 15A and Fig. Figure 15B shows various representations of a memory matrix 52 according to some further embodiments. Only a part of the memory matrix 52 is shown. Some structural elements, such as the stair-like word lines (see Figure 15B), are not shown. Fig. 2B), are not shown for the sake of clarity. Fig. 15A is a three-dimensional representation of the memory matrix 52, and Fig. 15B is a sectional view showing a cross-section similar to the reference cross-section B - B of Fig. 12A is shown.

[0062] In this embodiment, conductive strips 160 are produced between the ferroelectric strips 114 and the semiconductor strips 116. The production of the conductive strips 160 helps to prevent or reduce the formation of an interlayer oxide on the ferroelectric strips 114 during the production of the semiconductor strips 116. By preventing or reducing the formation of an interlayer oxide, the lifetime of the memory matrix 52 can be extended.

[0063] The conductive strips 160 can be made of a metal such as ruthenium, tungsten, titanium nitride, tantalum nitride, molybdenum, or the like. The conductive materials of the conductive strips 160 can be deposited using a suitable deposition process such as ALD or CVD, a suitable plating process such as electroplating or electroless plating, or the like. The thickness of the conductive strips 160 can range from approximately 1 nm to approximately 20 nm. The conductive strips 160 can be manufactured in a similar manner to the semiconductor strips 116 and during the manufacturing process of the semiconductor strips 116. The dielectric pins 132 may (or may not) be manufactured by the conductive strips 160.

[0064] The Fig. 16A and Fig. Figure 16B shows various representations of a memory matrix 52 according to some further embodiments. Only a part of the memory matrix 52 is shown. Some structural elements, such as the stair-like word lines (see Figure 16B), are not shown. Fig. 2B), are not shown for the sake of clarity. Fig. 16A is a three-dimensional representation of the memory matrix 52, and Fig. 16B is a sectional view showing a cross-section similar to the reference cross-section B - B of Fig. 12A is shown.

[0065] In this embodiment, the seed layer 112A S and the seed layer 112B S Made from different materials to help reduce the overall specific resistance. For example, the seed layer can be 112A S are produced from a first adhesive material (e.g. titanium nitride), and the seed layer 112B SIt can be made from a second adhesive material (e.g., tantalum nitride) that has a different specific resistance. Therefore, the seed layer 112A S and the seed layer 112B S They do not fuse together during manufacturing, so they remain separate.

[0066] The Fig. 17A and Fig. Figure 17B shows various representations of a memory matrix 52 according to some further embodiments. Only a part of the memory matrix 52 is shown. Some structural elements, such as the stair-like word lines (see Figure 17B), are not shown. Fig. 2B), are not shown for the sake of clarity. Fig. 17A is a three-dimensional representation of the storage matrix 52, and Fig. 17B is a sectional view taken along a reference cross-section B - B of Fig. 17A is shown.

[0067] In this embodiment, the metallization structures 142 of the interconnection structure 140 have only source line connections 142S. A further interconnection structure 170 is fabricated on a side of the substrate 102 opposite the interconnection structure 140. The interconnection structure 170 can be fabricated in a similar manner to the interconnection structure 140. The interconnection structure 170 can, for example, have metallization structures 172 in a dielectric material 174. Conductive vias 180 can be fabricated through the substrate 102 and the ferroelectric strips 114 to electrically connect the metallization structures 172 to the bit lines 134 and / or the source lines 136. The metallization structures 172 include, for example, bit line connections 172B (which are electrically connected to the source lines 136 via the conductive vias 180).

[0068] Furthermore, in this embodiment, the bit lines 134 and the source lines 136 are not constructed in a staggered layout, and thus adjacent bit lines 134 and adjacent source lines 136 are connected along the first direction D1 (see Fig. 2B) are aligned laterally to each other. Thus, each word line 112 is located laterally between a pair of bit lines 134 or a pair of source lines 136. Since the bit lines 134 and the source lines 136 are not constructed in a staggered layout, a cross-connection is established with a subset of the source line connections 142S in the connection structure 140, and a cross-connection is established with a subset of the bit line connections 172B in the connection structure 170. For example, the source line connections 142S are straight conductive segments constructed at an intermediate level of the connection structure 140. At a lower level of the connection structure 140 than that of the source line connections 142S, cross-connections 146 are established between a first subset of the source line connections 142S and the source lines 136.At a lower level of the interconnection structure 140 than that of the source line connections 142S, straight connections 148 are established between a second subset of the source line connections 142S and the source lines 136. Similarly, the bit line connections 172B are straight conductive segments established at an intermediate level of the interconnection structure 170. At a lower level of the interconnection structure 170 than that of the bit line connections 172B, cross connections 176 are established between a first subset of the bit line connections 172B and the bit lines 134. At a lower level of the interconnection structure 140 than that of the bit line connections 172B, straight connections 178 are established between a second subset of the bit line connections 172B and the bit lines 134.

[0069] It should be understood that the layouts of the interconnection structures 140 and 170 can be reversed in other embodiments. For example, the metallization structures 142 of interconnection structure 140 can comprise bit line connections, and the metallization structures 172 of interconnection structure 170 can comprise source line connections.

[0070] The Fig. Figures 18A to 20B are various representations of intermediate stages in the production of a memory matrix 52 according to some further embodiments. Only a part of the memory matrix 52 is shown. Some structural elements, such as the stepped word lines (see Fig. 2B), are not shown for the sake of clarity. Fig. 18A and Fig. Figures 19A are three-dimensional representations of the memory matrix 52. Fig. 18B and Fig. 19B are sectional views taken along the reference cross-section B - B of Fig. 19A are shown. Fig. 20A and Fig. 20B are top-down views of a portion of the memory matrix 52.

[0071] In the Fig. 18A and Fig. 18B will have a structure similar to the structure described with reference to the Fig. 13A and Fig. 13B has been described, but at this stage of processing the ferroelectric strips 114, the semiconductor strips 116 and the dielectric layers 118 are not produced. Instead, the first trenches 106 (see Fig. 4A and Fig. 4B) and the second trenches 120 (see Fig. 8A and Fig. 8B) each filled with a dielectric layer 192. The dielectric layers 192 are made of a dielectric material. Suitable dielectric materials are oxides, such as silicon oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; or the like; or combinations thereof, such as silicon oxide nitride, silicon oxide carbide, silicon carbonitride, or the like. The dielectric materials can be deposited by a suitable deposition method such as ALD, CVD, or the like. In some embodiments, silicon oxide is deposited in the first trench 106 and the second trench 120. Then, a planarization process can be carried out on the various layers to remove excess dielectric material above the uppermost first dielectric layer 104A. The planarization process can be a CMP process, a back-etching process, a combination thereof, or the like.For example, a first planarization process can be carried out after filling the first trenches 106 to produce the dielectric layers 192, and a second planarization process can be carried out after filling the second trenches 120 to produce the dielectric layers 192.

[0072] In the Fig. 19A and Fig. 19B TFT layer stacks are fabricated such that they extend through the dielectric layers 192. The TFT layer stacks each comprise a ferroelectric strip 114, a semiconductor strip 116, and a dielectric layer 118. Then, bit lines 134 and source lines 136 are fabricated at least through the dielectric layers 118.

[0073] The ferroelectric strips 114, the semiconductor strips 116, and the dielectric layers 118 can be fabricated using a combination of deposition, etching, and planarization. For example, openings can be created through the dielectric layers 192. These openings can be produced using suitable photolithographic and etching techniques. A ferroelectric layer can be conformally deposited in the openings through the dielectric layers 192. Then, a semiconductor layer can be conformally deposited onto the ferroelectric layer. Subsequently, the semiconductor layer can be anisotropically etched to remove horizontal portions of the semiconductor layer, thus exposing the ferroelectric layer. A dielectric layer can then be conformally deposited onto the remaining vertical portions of the semiconductor layer and the exposed portions of the ferroelectric layer.A planarization process is then performed on the various layers to remove excess material above the uppermost first dielectric layer 104A. The planarization process can be a CMP process, a back-etching process, a combination thereof, or the like. The portions of the ferroelectric layer, the semiconductor layer, and the dielectric layer that remain in the openings through the dielectric layers 192 form the ferroelectric strips 114, the semiconductor strips 116, and the dielectric layers 118, respectively. The planarization process exposes the uppermost first dielectric layer 104A, so that after the planarization process, the top surfaces of the uppermost first dielectric layer 104A, the ferroelectric strips 114, the semiconductor strips 116, and the dielectric layers 118 are coplanar (within process variations).

[0074] As an example of how to fabricate the bit lines 134 and the source lines 136, openings for the bit lines 134 and the source lines 136 can be created through the dielectric layers 118 and optionally also through the ferroelectric strips 114 and the semiconductor strips 116. The openings can be created using suitable photolithographic and etching processes. In particular, the openings are created such that they are opposite the sides of the remaining portions of the dielectric layers 118. In some embodiments, the openings extend only through the dielectric layers 118, so that the bit lines 134 and the source lines 136 extend only through the dielectric layers 118 (as in Fig.(as shown in Figure 19A). In some embodiments, the openings also extend through the ferroelectric strips 114 and the semiconductor strips 116, so that the bit lines 134 and the source lines 136 also extend through the ferroelectric strips 114 and the semiconductor strips 116. Then, one or more conductive materials are deposited in the openings. Suitable conductive materials are metals such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or the like. The conductive materials can be deposited using a suitable deposition method such as ALD or CVD, a suitable plating method such as electroplating or electroless plating, or the like. In some embodiments, tungsten is deposited in the openings.A planarization process is then performed on the various layers to remove excess conductive material above the uppermost first dielectric layer 104A. The planarization process can be a CMP process, a back-etching process, a combination thereof, or the like. The remaining conductive material forms the bit lines 134 and the source lines 136 in the openings. Connections can then be made over (or under) the bit lines 134 and the source lines 136 using methods similar to those discussed above, so that the bit lines 134 and the source lines 136 can be connected to bit line connections and source line connections, respectively.

[0075] By using the processes described above to manufacture the word lines 112, they can be produced with a reduced risk of wobbling or even breakage. Specifically, by using two separate etching processes and subsequently filling the gaps between them, the widths of the remaining structures at each point in the process remain sufficient to provide adequate structural support to help prevent wobbling and breakage. Furthermore, this risk reduction can be achieved at a low cost and without the need for additional masks.

[0076] The invention is defined by the main claim and the dependent claim. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Method for manufacturing a semiconductor device (50) comprising the following steps: Etching a first trench (106) in a multilayer stack (104), wherein the multilayer stack (104) comprises alternating dielectric layers (104A) and sacrificial layers (104B); Widening the first trench (106) to create the first side wall recesses (110); Deposition of a first conductive material (112A) to fill the first trench (106); after the separation of the first conductive material (112A) etching of a second trench (120) in the multilayer stack (104); Widening the second trench (120) to create second side wall recesses (124); Deposition of a second conductive material (112B) to fill the second trench (120); and Etching of the first conductive material (112A) and the second conductive material (112B). [2] Method according to claim 1, wherein the deposition of the first conductive material (112A) is a deposition of a first seed layer (112A) S ) and a first conductive solid material (112A M ) includes. [3] Method according to claim 2, wherein the deposition of the second conductive material (112B) is a deposition of a second seed layer (112B) S ) in physical contact with the first seed layer (112A S ) includes. [4] Method according to claim 3, wherein after etching the first conductive material (112A) and the second conductive material (112B) the first seed layer (112A S ) and the second seed layer (112B S ) have an H-shape between two of the dielectric layers (104A). [5] Method according to any of the preceding claims, further comprising planarizing the first conductive material (112A) prior to etching the second trench (120), wherein after planarizing the first conductive material (112A) the first conductive material (112A) completely spans an upper part of the first trench (106). [6] Method according to any of the preceding claims, wherein after etching the first conductive material (112A) and the second conductive material (112B) the first conductive material (112A) has a greater width (W4) than the second conductive material (112B). [7] A method according to any of the preceding claims, further comprising: After etching the first conductive material (112A) and the second conductive material (112B), a ferroelectric material (114) is deposited in the first trench (106) and the second trench (120); Separation of canal material (116) in the first trench (106); and Deposition of a dielectric material (118) in the first trench (106) after deposition of the channel material (116). [8] Method for manufacturing a semiconductor device (50) comprising the following steps: Producing an alternating stack (104) of first dielectric materials (104A) and sacrificial materials (104B); Fabricating a first part (112A) of a first word line (112) in the alternating stack (104) from first dielectric materials (104A) and sacrificial materials (104B), wherein the fabrication of the first part (112A) of the first word line (112) comprises the following: Etching a first trench (106) in the alternating stack (104) of first dielectric materials (104A) and sacrificial materials (104B), Creating initial recesses (110) by sparing parts of the sacrificial material (104B) that are exposed in the first trench (106), and Deposition of a first conductive material (112A) in the first recesses (110) to fill the first trench (106); After the first part (112A) of the first word line (112) is produced, a second part (112B) of the first word line (112) is produced in the alternating stack (104) of first dielectric materials (104A) and sacrificial materials (104B), wherein the production of the second part (112B) of the first word line (112) comprises the following: Etching a second trench (120) in the alternating stack (104) of first dielectric materials (104A) and sacrificial materials (104B), Creating second recesses (124) by removing a residue of the sacrificial material (104B), and Deposition of a second conductive material (112B) in the second recesses (124) to fill the second trench (120); and Etching of the first conductive material (112A) and the second conductive material (112B). [9] The method of claim 8, further comprising: Deposition of a ferroelectric material (114) in the first trench (106); and Deposition of a channel material (116) adjacent to the ferroelectric material (114) in the first trench (106). [10] The method of claim 9, further comprising: Etching of the canal material (116); and Deposition of a dielectric material (132) in the first trench (106) to insulate a first part of the channel material (116) and a second part of the channel material. [11] Method according to any one of claims 8 to 10, wherein the deposition of the first conductive material (112A) is a deposition of a first seed layer (112A) S ) includes. [12] Method according to claim 11, wherein the deposition of the second conductive material (112B) is a deposition of a second seed layer (112B) S ) in physical contact with the first seed layer (112A S ) comprising a common thickness (T4) of the first seed layer (112A S ) and the second seed layer (112B S ) greater than a thickness (T3) of the first seed layer (112A S ) adjacent to part of the first dielectric materials (104A). [13] Method according to any one of claims 8 to 12, wherein the first recesses (110) have a smaller width (W4) than the second recesses (124).

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