Transceiver circuit with T-coil, inductive termination and equalization

Abstract

Circuit (100) comprising: a transmitter circuit (102) configured to send an output signal via a first node; a receiver circuit (104) coupled to receive an input signal via the first node; a T-coil circuit (106) coupled between the first node and an input / output node (I / O node), the T-coil circuit (106) including a first inductor coupled between the first node and a second node, and a second inductor coupled between the second node and the I / O node; a termination circuit (108) coupled between the first node and a reference node, the termination circuit (108) including a third inductor; and an equalization circuit (110) configured to equalize a transmitted signal on the second node.

Description

STATE OF TECHNOLOGY IN THE TECHNICAL FIELD

[0001] The present disclosure relates to electronic circuits and more precisely to transceiver circuits. DESCRIPTION OF THE STATE OF THE ART

[0002] In various types of communication systems, both wired and wireless communication channels can be unidirectional or bidirectional. If a communication channel is unidirectional, a transmitter can be connected to one end of the channel, while a receiver is connected to the other. If a communication channel is bidirectional, transceivers can be connected to both ends of the channel. Each transceiver is capable of sending and receiving data, enabling two-way communication over the channel. Depending on the direction of the ongoing communication, one of the transceivers acts as a transmitter, while the other acts as a receiver. To reverse the direction of communication, each transceiver switches its current operating mode to the opposite mode. SUMMARY

[0003] A transceiver circuit comprising a T-coil circuit, an inductive termination, and an equalization circuit is disclosed. In one embodiment, a transceiver includes a transmitter with an output coupled to a first node and a receiver with an input coupled to the first node. A T-coil circuit is coupled between the first node and an input / output (I / O) node. The T-coil circuit includes a first and a second inductor coupled in series between the first node and the I / O node, with the inductors being coupled at a second node. A termination circuit is coupled between the first node and a reference node, with the termination circuit including a third inductor. The transceiver circuit also includes an equalization circuit configured to transmit an equalization signal to the second node.

[0004] In one embodiment, the transceiver includes a control circuit. During operation in a transmit mode (e.g., when the transceiver is sending information), the control circuit activates the equalization circuit while disabling the termination circuit. The equalization circuit is coupled to the second node via a capacitor, which in one embodiment may be a metal-to-metal capacitor. During operation in a receive mode (e.g., when the transceiver is receiving information), the control circuit deactivates the equalization circuit while activating the termination circuit. When activated, the termination circuit provides an on-die termination for the signal path in the transceiver. List of characters

[0005] The following detailed description refers to the accompanying drawings, which will now be briefly described. Fig. Figure 1 is a block diagram of an embodiment of a transceiver circuit. Fig. Figure 2 is a schematic diagram of an embodiment of a transceiver circuit. Fig. Figure 3 is a block diagram of an embodiment of a communication system with transceivers coupled to a communication channel. Fig. Figure 4 is a flowchart illustrating one embodiment of a method for operating a transceiver. Fig. Figure 5 is a block diagram of an embodiment of an exemplary system.

[0006] Although the embodiments disclosed herein are open to numerous modifications and alternative forms, specific embodiments are shown by way of example in the drawings and described in detail herein. It is understood, however, that the drawings and the accompanying detailed description are not intended to limit the scope of protection of the claims to the specific forms disclosed. On the contrary, this application is intended to cover all modifications, equivalents, and alternatives that fall within the nature and scope of protection of the disclosure of the present application, as defined by the accompanying claims.

[0007] This disclosure includes references to “one embodiment,” “a particular embodiment,” “some embodiments,” or “various embodiments.” When the phrases “in one embodiment,” “in a particular embodiment,” “in some embodiments,” or “in various embodiments” appear, they do not necessarily refer to the same embodiment. Particular features, structures, or properties may be combined in any suitable manner consistent with this disclosure.

[0008] Within this disclosure, various entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed to be "configured" to perform one or more tasks or operations. This phrase—[entity] that is configured [to perform one or more tasks]—is used herein to refer to a structure (i.e., something physical, such as an electronic circuit). In particular, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure may be described as "configured to" perform a task even if the structure is not currently operating.A “point distribution circuit configured to distribute points across a multitude of processor cores,” for example, is intended to cover an integrated circuit that has switching logic capable of performing this function during operation, even when the integrated circuit in question is not currently in use (e.g., no power supply is connected to it). Thus, an entity described or specified as “configured to” perform a task refers to something physical, such as a device, a circuit, a memory that stores program instructions executable to implement the task, and so on. This phrase is not used here to refer to something intangible.

[0009] The term "configured to" should not be interpreted as "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a specific function, even though it could be "configurable to" perform that function after appropriate programming.

[0010] The statement in the accompanying claims that a structure is "configured to" perform one or more tasks is expressly not intended to invoke 35 USC § 112(f) for that claim element. Accordingly, none of the claims in this application as filed are to be interpreted as having means-plus-function elements. If the applicant wishes to rely on the application of section 112(f) during the grant proceedings, he shall state claim elements using the construct "means to" [perform a function].

[0011] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is to say, a determination may be based solely on specified factors, or on the specified factors as well as other, unspecified factors. Consider the phrase "determine A based on B." This phrase indicates that B is a factor used to determine A, or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor, such as C. This phrase is also intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least partially on."

[0012] As used herein, the phrase "in response" describes an action to one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is to say, an effect may occur solely in response to these factors, or it may occur in response to the stated factors as well as other, unspecified factors. Consider the phrase "perform A in response to B." This phrase indicates that B is a factor that triggers the performance of A. This phrase does not exclude the possibility that A may also be performed in response to another factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.

[0013] As used herein, the terms "first," "second," etc., are used as labels for suffixed nouns and do not imply any kind of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified. Thus, for example, in a register file with eight registers, the terms "first register" and "second register" may be used to refer to any two of the eight registers, and not, for example, only to the logical registers 0 and 1.

[0014] When used in the claims, the term "or" is used as an inclusive "or" and not as an exclusive "or". For example, the phrase "at least one of x, y or z" means any one of x, y and z as well as any combination thereof.

[0015] The following description presents numerous specific details to provide a comprehensive understanding of the disclosed embodiments. However, the person skilled in the art should recognize that aspects of the disclosed embodiments could be implemented without these specific details. In some cases, generally known circuits, structures, signals, computer program instructions, and techniques have not been described in detail to avoid obscuring the disclosed embodiments. DETAILED DESCRIPTION OF EXECUTION FORMS

[0016] The present disclosure relates to a transceiver circuit that includes one or more equalization circuits, a T-coil circuit, and an inductive termination. In conventional transceiver circuits, the capacitance of an electrostatic discharge (ESD) switching logic can additionally load a capacitor associated with an I / O pad / node. This can be somewhat mitigated by using a T-coil circuit. An equalization switching logic can be provided to improve a transmit span, but it can add an additional capacitive load to an I / O pin, thereby reducing the span for operation in either a transmit or receive mode. To disconnect the additional capacitive load from the output pad, one or more additional switches can be added between the equalization circuit and the output pad.This can also add more to the parasitic capacitive load and contribute to vulnerability to ESD events.

[0017] The transceiver circuit of the present disclosure includes both a T-coil and an equalization circuit. Furthermore, the transceiver circuit also includes an inductive termination circuit. Different embodiments of the disclosure of the transceiver circuit herein can provide tolerance improvements for both voltage and timing control. Furthermore, replacing some active components with passive components can improve DC power consumption. This can also lead to improvements in the power distribution network with respect to switching performance, noise, and signaling / supply reflection. Different embodiments of the transceiver circuit disclosed herein can be suitable for a variety of different packets and transmission channels (including channels of different lengths, from short to long) and are thus flexible for implementation in a number of different types of communication systems and interfaces.

[0018] Fig. Figure 1 is a block diagram of an embodiment of a transceiver circuit. More precisely illustrated... Fig. 1 The basic components of a transceiver circuit according to the present disclosure. In the embodiment shown, the transceiver circuit includes a transmitter circuit. 102 and a receiver circuit 104 One. The transceiver can therefore operate in a transmit mode or a receive mode.

[0019] When operating in transmit mode, data can be transmitted from the transmitter. 102 The signals are sent to an input / output pad / node (I / A pad / node), referred to here as "I / A". The sent signals can be processed via a T-coil circuit. 106 be transmitted. When operating in receive mode, incoming data can be received at the I / O node, which is processed by the T-coil circuit. 106 to an input of the recipient 104 be transmitted. Both the sender 102as well as the recipient 104 They can be coupled with other circuits, such as a processor, a controller, or another type of switching logic. Such switching logic can send data (TxData) to the transmitter. 102 transmit and can receive incoming data (RxData) from the recipient 104 received.

[0020] Besides the transmitter 102 The data to be sent can also be processed by an equalization circuit. 110 be received. The equalization circuit 110 It may include one or more circuits that generate equalization signals which are fed to the T-coil circuit. 106 to be transmitted when it is operating in transmit mode. In one embodiment, the equalization circuit can 110 Perform pre-distortion of digital signals to be transmitted. During operation in receive mode, the equalization circuit can... 110be inactive. Additional equalization (e.g., pre-distortion, multi-tap pre / post-equalization, shunt equalization, etc.) can be implemented using DC-coupled equalization circuits within the transmitter. 102 be performed.

[0021] The final circuit 108 In the illustrated embodiment, an on-die termination (ODT) is provided during operation in receive mode. An example of a possible arrangement of such a termination circuit is discussed in more detail below. The termination circuit 108 It can be switched in such a way that it is activated during operation in receive mode and deactivated during transmission mode. In another embodiment, the termination circuit can 108 also with the transmitter 102 can be used when it is operating in transmit mode. Thus, in such an embodiment, the termination circuit 108remain activated in both transmit and receive modes.

[0022] The control circuit 112 In the embodiment shown, it is used to both the termination circuit 108 as well as the equalization circuit 110 as well as the various equalization modes that are available within the transmitter 102 They can be implemented to control. During operation in transmit mode, the control circuit can 112 the equalization circuit 110 activate / release while completing the final circuit 108 deactivated. During operation in receive mode, the control circuit 112 the equalization circuit 110 deactivate and the final circuit 108 activate. In some embodiments, both the termination circuit and the circuit can be activated. 108 as well as the equalization circuit 110 through the control circuit 112 be deactivated / enabled when the transceiver circuit100 is inactive (e.g., neither sending nor receiving data).

[0023] Fig. Figure 2 is a schematic diagram of an embodiment of a transceiver circuit. 100 In the illustrated embodiment, the transceiver circuit is demonstrated. 100 further details of the various components that are in Fig. Figure 1 shows some additional details not shown therein.

[0024] The broadcaster 102 includes an output that is coupled to a first node P1, which is also connected to an input of the receiver. 104 It is coupled. The signal path for both sending and receiving data runs through the T-coil. 106 to the I / O pad. Similarly, the receiver closes 104 It also has an input that is coupled to P1. So, if the transceiver 100 When operating in transmit mode, data is transmitted from the transmitter's output. 102 via the T-coil 106Sent to the I / O pad on P1. If the transceiver 100 When operating in receive mode, data is received from the I / O pad via the T-coil. 106 to node P1 to the receiver input 104 transmitted.

[0025] The T-coil circuit 106 In the illustrated embodiment, the inductors L1 and L2 are connected at a second node P2. The T-coil 106 This also includes capacitor C1, which is coupled between P1 and the I / O pad. ESD diodes DP and DN are also coupled to P2 via their anodes and cathodes, respectively. The anode of DN is coupled to the reference node Vss, while the cathode of DP is coupled to the supply voltage node Vdd. Diodes DP and DN can also provide noise isolation, as noise seen on P2 is effectively isolated from any switching logic outside the T-coil. 106, including at the supply voltage node Vdd and the reference node Vss, is isolated.

[0026] In the illustrated embodiment, capacitor C1 is a feedforward capacitor. Specifically, high-frequency signals (or high-frequency components of data) can pass through C1 between P1 and the I / O node. More generally, C1 provides a low-impedance path at high frequencies. The value of capacitor C1 can therefore be selected based on the desired frequency in the feedforward path.

[0027] The inductors L1 and L2 can have a coupling factor selected for the specific application. The two coils, which can be interlaced in an IC implementation, have a coupling factor K. Current flowing into one of the inductors L1 and L2 can be electromagnetically coupled to the other inductor L1 and L2.

[0028] The equalization circuit 110 In this particular embodiment, a pre-drive circuit is included. 210 , a pull-up transistor M1 and a pull-down transistor M2. The driver 210 includes a first input that is coupled to receive data to be sent (TxData, also by the sender) 102 received) and an activation signal En, which is received by the control circuit 112 is received, to be received. Depending on the received data, the driver circuit can 210 Activate one of the transistors M1 or M2 to generate an equalization signal. This signal is transmitted via capacitor C3, which in one embodiment is a metal-to-metal capacitor providing AC coupling to the equalization circuit. 110at P2. The use of a metal-to-metal capacitor can be advantageous insofar as it may lack physical parasitic properties (e.g., no parasitic diodes, a lower temperature coefficient, and better ESD robustness). One terminal of capacitor C3 is coupled to the junction of M1 and M2, while the other terminal is coupled to P2. It is noteworthy that, unlike previous embodiments, the equalization circuit 110 not through a switch with node P2 of the T-coil 106 is coupled. Capacitor C3 provides both ESD protection and isolation between the equalization circuit. 110 and node P2 is ready when the former is not active or transmitting equalization signals. The absence of a switch in the illustrated embodiment can also minimize switching noise generated by the transceiver. 100is generated. When the equalization circuit 110 If M1 is not active (e.g., when both M1 and M2 are switched off), it can transition into a high-impedance state, thus reducing the capacitive load.

[0029] It is noted that the timing of the generation and transmission of equalization signals to node P2 can be time-controlled to compensate for inherent delays in the signal path through the T-coil. 106 This must be taken into account. Depending on the specific implementation, the equalization signal timing control can be punctual (arriving simultaneously with the signal from the transmitter), early, or delayed. Furthermore, the equalization circuit can... 110 Several sub-circuits may be included, each capable of adjusting to a different level of equalization. Some embodiments may also include a calibration circuit to adjust the strength of the equalization circuit(s).110 to calibrate the provided signal(s). Furthermore, in embodiments with multiple sub-circuits, the arrival times at P2 may be staggered in some cases. The settings can be determined for each individual bit within a byte / channel.

[0030] The final circuit 108 In the illustrated embodiment, a third inductor L3, a switch S1, and a resistor R1 are included. The inductor L3 is coupled between the reference node Vss and the switch S1. The other terminal of the switch S1 is coupled to node P3, which in turn is coupled to one terminal of R1. The other terminal of R1 is coupled to node P1. The termination circuit 108 can be controlled by a corresponding control signal from the control circuit 112 It can be activated during operation in receive mode. Activation of the termination circuit 108This can be done by closing switch S1. The input capacitor C2 represents an unintended load capacitance (instead of an intentionally implemented capacitor) connected in parallel to the termination circuit. 108 is, and can be charged when switch S1 is closed to complete the termination circuit 108 to activate before the on-die termination (ODT) is fully formed. The inductance L3 can be activated when the termination circuit is complete. 108 When activated, the circuit briefly forms an open circuit, allowing C2 to charge before the ODT is complete. In one embodiment, the ODT can have a higher impedance value (e.g., 60 ohms compared to previous embodiments where the ODT has an impedance of, for example, 34 / 48 ohms). This can provide significant power savings during receive-mode operation.

[0031] The transceiver 100This also includes an additional resistor R2 and switch S2, which are coupled between P1 and the supply voltage node Vdd. Switch S2 can be closed during operation in receive mode. These components can be used when a specific type of signaling requires a termination at Vdd, while R1 and S1 are used when the type of signaling requires a termination at Vdd / 2.

[0032] The transceiver circuit 100 In the embodiment shown, an ESD circuit is also included. 205 and a decoupling capacitor C3. The ESD circuit 205 is coupled to resistor RVdd (whose other terminal is coupled to the supply voltage node Vdd) and resistor RVss (whose other terminal is coupled to the reference node Vss). In the event of an ESD event near the transceiver 100 can the ESD circuit 205Provide a safe discharge path to prevent damage to other nearby circuits. In the illustrated embodiment, RVdd and RVss can be minimized because a smaller resistance can be more effective for ESD protection. This can allow the ESD circuit to 205 is more effective in handling ESD events.

[0033] The control circuit 112 In the illustrated embodiment, it is coupled to receive one or more mode signals indicating whether the transceiver 100 The control circuit can be configured to operate in transmit mode, receive mode, or otherwise be inactive, depending on the operating mode. 112 the activation of the final circuit 108 (in receive mode) or the activation of the equalization circuit 110 (in transmit mode). In transmit mode, the control circuit can 112 cause the final circuit 108It is deactivated by opening switch S1. In receive mode, the control circuit 112 a deactivation of the equalization circuit 110 by deactivating the activation signal En.

[0034] Fig. Figure 3 is a block diagram of an embodiment of a communication system (or part thereof) with transceivers coupled to a communication channel. In the embodiment shown, the system is 300 a communication system with at least one bidirectional communication channel 305 The transceivers 100 They can be coupled to either end of the communication channel. During operation, and depending on the direction of data flow, one of the transceivers can be used. 100 One transceiver operates in transmit mode, while the other operates in receive mode. A change in the data flow direction can be achieved by changing the operating mode of both transceivers. 100can be achieved within the system.

[0035] The communication system 300 It can be one of a number of different types of systems in which data is exchanged between transceivers. For example, the communication channel 305 a line of a data bus in a storage subsystem, wherein a transceiver 100 One transceiver is implemented in, for example, a memory controller, while the other transceiver is implemented in the memory itself. Other possible examples of a communication system 300 , which fall within the scope of protection of this disclosure, include other types of wired communication systems (e.g. network interfaces) as well as wireless communication systems (e.g. WiFi or other systems).

[0036] It should be noted that the communication system shown here 300This is a simplified diagram provided for illustrative purposes and is not intended to be restrictive. Other components (e.g., antennas, amplifiers, etc.) may be included in various embodiments while still falling within the general scope of protection of what is illustrated herein.

[0037] Fig. Figure 4 is a flowchart illustrating one embodiment of a method for operating a transceiver. The method 400 can be achieved by using various embodiments of one of the above with reference to Fig. 1 to Fig. The transceiver circuit described in section 3 is carried out. Embodiments of a transceiver capable of performing the procedure are described. 400 Items that are not explicitly discussed herein but can also fall within the scope of protection of this disclosure.

[0038] The procedure 400begins by operating a transceiver circuit in a receive mode, working in receive mode (block 405 Operating the transceiver in receive mode involves receiving an input signal at a receiver circuit input coupled to a first node, wherein receiving the input signal includes transmitting the input signal from an input / output node (I / O node) through a first and a second inductor of a T-coil circuit to the receiver input and activating a termination circuit with a third inductor. The method 400 furthermore includes operating the transceiver circuit in a transmit mode (block 410). Operation in transmit mode involves a transmitter sending an output signal to the first node, passing the output signal from the first node through the T-coil circuit to the I / O node, and providing an equalization signal to a second node using an equalization circuit, with the second node coupling the first and second inductors together.

[0039] In various embodiments, the method can include activating the termination circuit during operation in receive mode using a control circuit and deactivating the termination circuit during operation in transmit mode using the control circuit. The method can further include activating the equalization circuit during operation in transmit mode using the control circuit and deactivating the equalization circuit during operation in receive mode using the control circuit.

[0040] Activating the termination circuit involves closing a switch coupled between the third inductor and a termination resistor, wherein the termination resistor is further coupled to the first node, and wherein the third inductor is coupled between the switch and a reference node.

[0041] The equalization circuit generates the equalization signal and, in various embodiments, transmits it to the second node via a metal-to-metal capacitor. When operating in transmit mode, the method further includes providing data values ​​to both the transmitter and the equalization circuit, sending the data values ​​from the transmitter circuit to the first node, and simultaneously sending the equalization signal based on the data values ​​from the transmitter circuit.

[0042] Next, referring to Fig. 5 is a block diagram of an embodiment of a system 150 shown. In the illustrated embodiment, the system closes 150 at least one instance of an integrated circuit 10 one that comes with external storage 158 is coupled. The integrated circuit 10 may include a memory controller that interacts with the external memory 158 is coupled. The integrated circuit 10 is connected to one or more peripheral devices 154 and the external storage 158 coupled. A power supply is also required. 156 provided, which the integrated circuit 10 the supply voltages and the storage 158 and / or the peripheral devices 154 supplies one or more supply voltages. In some embodiments, more than one instance of the integrated circuit can be used. 10be included (and it can also be more than one external storage device). 158 (be included).

[0043] The peripheral devices 154 can include any desired switching logic, depending on the type of system 150 For example, in one embodiment the system 150 a mobile device (e.g. a personal digital assistant (PDA), a smartphone, etc.), and the peripheral devices 154 These can include devices for various types of wireless communication, such as WiFi, Bluetooth, cellular networks, global positioning systems, etc. The peripheral devices 154 They can also include additional storage, including RAM, semiconductor memory, or disk storage. The peripherals 154User interface devices may include a display screen, including touchscreens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc. In other embodiments, the system may 150 any type of computing system (e.g. desktop personal computer, laptop, workstation, tablet, etc.).

[0044] The external storage 158 It can include any type of storage. For example, external storage can be... 158 This could be SRAM, dynamic RAM (DRAM), such as synchronous DRAM (SDRAM), SDRAM with double data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, DDR1-5, LPDDR1-5, etc.), RAMBUS DRAM, etc. The external memory 158 may include one or more memory modules to which the memory devices are attached, such as single-row memory modules (SIMM), dual-row memory modules (DIMM), etc.

[0045] In various embodiments, one or more instances of a transceiver circuit discussed above can be integrated into the system. 150 be implemented.

[0046] For example, a memory controller (e.g., implemented in the integrated circuit) can be used. 10 ) and a storage device 158 Each includes a number of transceivers as described above, which implement a memory interface. Other implementations of such transceivers can also be found, for example, in peripheral devices. 154 or otherwise in the system 150 It should be included.

[0047] Numerous variations and modifications become apparent to the person skilled in the art once the foregoing disclosure is fully understood. It is intended that the following claims be interpreted to include all such variations and modifications.

Claims

[1] Circuit, comprising: a transmitter circuit configured to send an output signal via a first node; a receiver circuit that is coupled to receive an input signal via the first node; a T-coil circuit coupled between the first node and an input / output node (I / O node), wherein the T-coil circuit includes a first inductance coupled between the first node and a second node, and a second inductance coupled between the second node and the I / O node; a termination circuit coupled between the first node and a reference node, wherein the termination circuit includes a third inductor; and an equalization circuit configured to equalize a transmitted signal at the second node. [2] Circuit according to claim 1, wherein the T-coil circuit includes a capacitor coupled between the I / O node and the first node. [3] Circuit according to claim 1, wherein the termination circuit includes: a terminating resistor with a first terminal that is coupled to the first node; a switch coupled to a second terminal of the terminating resistor; and an inductor coupled between the switch and the reference node. [4] Circuit according to claim 1, wherein the equalization circuit includes a driver circuit coupled to receive data which is also transmitted to the transmitter, a pull-up transistor coupled between an output of the equalization circuit and a power supply node, a pull-down transistor coupled between the output of the equalization circuit and the reference node, and a metal-to-metal capacitor coupled between the output of the equalization circuit and the second node. [5] Circuit according to claim 1, further comprising an input capacitor coupled between the first node and the reference node. [6] Circuit according to claim 1, further comprising a control circuit configured to activate the termination circuit and deactivate the equalization circuit during a receive mode, and further configured to deactivate the termination circuit and activate the equalization circuit during a transmit mode. [7] Procedures, comprehensive: Operating a transceiver circuit in a receive mode, including operation in receive mode: Receiving an input signal at a receiver circuit input coupled to a first node, wherein receiving the input signal includes transmitting the input signal from an input / output node (I / O node) through a first and a second inductor of a T-coil circuit to the receiver input; and Activating a termination circuit with a third inductor; Operating the transceiver circuit in a transmit mode, including operation in transmit mode: a transmitter that sends an output signal to the first node; Transmitting the output signal from the first node through the T-coil circuit to the I / O node and Providing an equalization signal to a second node using an equalization circuit, with the second node coupling the first and second inductors together. [8] Method according to claim 7, further comprising: Activate, using a control circuit, the termination circuit during operation in receive mode; Deactivate, using the control circuit, the termination circuit during operation in transmit mode; Activate, using the control circuit, the equalization circuit during operation in transmit mode and Deactivate, using the control circuit, the equalization circuit during operation in receive mode. [9] Method according to claim 7, wherein activating the termination circuit includes closing a switch coupled between the third inductor and a termination resistor, wherein the termination resistor is further coupled to the first node and wherein the third inductor is coupled between the switch and a reference node. [10] Method according to claim 7, wherein providing the equalization signal comprises: Generating the equalization signal through the equalization circuit and Transmitting the equalization signal to the second node via a metal-to-metal capacitor. [11] Method according to claim 7, wherein operating in transmit mode further comprises: Providing data values ​​to both the transmitter and the equalization circuit; Sending the data values ​​from the sender to the first node; Sending the equalization signal, based on the data values, simultaneously with sending the data values ​​from the transmitter. [12] System, encompassing: a bidirectional communication channel and a transceiver circuit configured to send signals into the communication channel and to receive signals from the communication channel, wherein the transceiver circuit comprises: a transmitter circuit configured to send an output signal via a first node; a receiver circuit that is coupled to receive an input signal via the first node; a T-coil circuit coupled between the first node and an input / output node (I / O node) of the communication channel, wherein the T-coil circuit has a first inductance coupled between the first node and a second node, and a second inductor coupled between the second node and the I / O node; a termination circuit coupled between the first node and a reference node, wherein the termination circuit includes a third inductor; and an equalization circuit configured to equalize a transmitted signal at the second node. [13] System according to claim 12, wherein the transceiver is coupled to a first end of the communication channel and wherein the system further includes a second transceiver coupled to a second end of the communication channel. [14] System according to claim 12, further comprising a control circuit configured to activate the termination circuit and deactivate the equalization circuit during a receive mode, and further configured to deactivate the termination circuit and activate the equalization circuit during a transmit mode. [15] System according to claim 12, wherein the equalization circuit includes a driver circuit coupled to receive data which is also transmitted to the transmitter, a pull-up transistor coupled between an output of the equalization circuit and a power supply node, and a pull-down transistor coupled between the output of the equalization circuit and the reference node, and wherein the transceiver further includes a metal-to-metal capacitor coupled between the output of the equalization circuit and the second node.

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