Semiconductor test equipment, test procedures for semiconductor devices and procedures for manufacturing semiconductor devices

Abstract

Semiconductor test equipment, comprising: a power supply (1); a high-voltage wire (11) connecting high-voltage terminals (7a) of a plurality of semiconductor devices (7), which are objects to be tested, to a high-voltage side of the power supply (1); a low-voltage wire (12) connecting low-voltage terminals (7c) of the semiconductor devices (7) to a low-voltage side of the power supply (1); first switches (13) each connected in series with the semiconductor devices (7), each of the first switches (13) having one end connected to the low-voltage side of the power supply (1) via the low-voltage wire (12) and another end connected to the low-voltage terminal (7c); second switches (14) each connected to the semiconductor devices (7), each of the second switches (14) having one end connected to the high-voltage terminal (7a) and another end connected to the low-voltage terminal (7c); and a control circuit (5a) that controls the first switches (13) and the second switches (14).

Description

Background of the invention: Area

[0001] The present invention relates to a semiconductor test device that tests a semiconductor device, a test method for semiconductor devices that uses the semiconductor test device, and a method for manufacturing semiconductor devices. background

[0002] In the manufacturing process for a semiconductor device, for example, elements containing a large number of crystal defects and having a relatively short lifetime are rejected as defective products by performing a burn-in test to subject them to high loads such as temperature and voltage. This ensures the reliability of the semiconductor device. In particular, compared to a semiconductor device made primarily of silicon (Si), a semiconductor device made primarily of silicon carbide (SiC) exhibits more crystal defects. Therefore, rejection via the burn-in test is crucial.

[0003] One problem with such a burn-in test is that the test time is long. The related technique discloses a semiconductor test device that can perform the burn-in test by simultaneously applying a voltage to a plurality of semiconductor devices formed on a semiconductor wafer (see, for example, JP 2019-046907A).

[0004] DE 10 2014 115 204 A1 describes a method for testing devices, wherein each device comprises a plurality of cells. Each cell includes a field-effect transistor and a switch configured to selectively connect a second contact of the corresponding field-effect transistor to a common test lead of the device. A control unit of the device is configured to control the switch so that it is in a closed position. At least one terminal is provided configured to apply a load voltage to a common mains line, wherein the common mains line is connected to a first contact of the field-effect transistor and the common test lead. Summary

[0005] In conventional semiconductor test equipment, however, if a defect such as a leakage current equal to or greater than a reference value occurs in some of the many semiconductor devices to which voltage is simultaneously applied, a test circuit is short-circuited by the semiconductor device if the voltage application is subsequently continued. This presents a problem, as the test cannot be continued for the other semiconductor devices with good device characteristics.

[0006] The present invention was made to solve the problems described above, and one object of the present invention is to obtain a semiconductor test device that can test a plurality of semiconductor devices simultaneously and, even if a defect occurs in some of the semiconductor devices, can continue to test the other semiconductor devices with good device characteristics.

[0007] The problem underlying the invention is solved according to the invention in a semiconductor test device by the features of claim 1, in a test method for semiconductor devices according to the invention by the features of claim 11, and in a method for manufacturing semiconductor devices according to the invention by the features of claim 12. Advantageous embodiments are the subject of the respective dependent claims.

[0008] A semiconductor test apparatus according to the present invention comprises: a power supply; a high-voltage wire connecting high-voltage terminals of a plurality of semiconductor devices, which are objects to be tested, to a high-voltage side of the power supply; a low-voltage wire connecting low-voltage terminals of the semiconductor devices to a low-voltage side of the power supply; first switches, each connected in series with the semiconductor devices, each of the first switches having one end connected via the low-voltage wire to the low-voltage side of the power supply and another end connected to the low-voltage terminal; second switches, each connected with the semiconductor devices, each of the second switches having one end connected to the high-voltage terminal and one end connected to the low-voltage terminal;and a control circuit that controls the first switches and the second switches;

[0009] A test method for semiconductor devices according to the present invention comprises: electrically connecting high-voltage terminals of a plurality of semiconductor devices to a high-voltage side of a power supply; electrically connecting low-voltage terminals of the semiconductor devices to a low-voltage side of the power supply; initiating a simultaneous application of a voltage to the plurality of semiconductor devices to detect leakage currents; and identifying the semiconductor device in which the leakage current, equal to or greater than a reference value, is detected as a defective semiconductor device, disconnecting the defective semiconductor device from the low-voltage side of the power supply, and subsequently raising a potential of the low-voltage terminal of the defective semiconductor device to a potential of the high-voltage terminal.

[0010] A method for fabricating semiconductor devices according to the present invention comprises: forming a drift layer on a front surface of a substrate; selectively forming a well region on the drift layer; selectively forming a source region on a surface layer portion of the well region; forming a gate insulating film on the front surface of the drift layer, the well region, and the source region; forming a gate electrode on the gate insulating film; forming a source electrode on the source region; and forming a drain electrode on a rear surface of the substrate.a semiconductor wafer, on which a plurality of semiconductor devices are formed by the above steps, placed on a wafer table such that one side of a lower surface of the semiconductor wafer comes into contact with the wafer table, and an electrical connection of the drain electrode to a high-voltage side of a power supply; a contacting of a probe with one side of an upper surface of the semiconductor wafer and an electrical connection of the source electrode to a low-voltage side of the power supply; a commencement of a simultaneous application of a voltage to the plurality of semiconductor devices in order to detect leakage currents;Identifying the semiconductor device in which leakage current equal to or greater than a reference value is detected as a defective semiconductor device; disconnecting the defective semiconductor device from the low-voltage side of the power supply; raising the potential of the source electrode of the defective semiconductor device to the potential of the drain electrode; marking the semiconductor device identified as a defective product; singulating the semiconductor devices formed on the semiconductor wafer; and sorting the singulated semiconductor devices into non-defective and defective products.

[0011] In the semiconductor test apparatus according to the present invention, first switches are each connected in series with a plurality of semiconductor devices, which are the objects to be tested. Each of the first switches has one end connected to a low-voltage side of a power supply and another end connected to a low-voltage terminal of the semiconductor device. Second switches are each connected to the semiconductor devices, and each of the second switches has one end connected to the high-voltage terminal of the semiconductor device and another end connected to the low-voltage terminal. Therefore, even if some semiconductor devices are defective, it is possible to continue the test without affecting the other semiconductor devices when the plurality of semiconductor devices are tested together.

[0012] Other and further tasks, features and advantages of the present invention will become more fully apparent from the following description. Brief description of the drawings Fig. Figure 1 is a schematic diagram illustrating a semiconductor test setup according to a first embodiment. Fig. Figure 2 is a circuit diagram illustrating a test circuit of the semiconductor test device according to a first embodiment. Fig. Figure 3 is a flowchart to illustrate a test procedure using the semiconductor test equipment according to a first embodiment. Fig. Figure 4 is a circuit diagram illustrating the test circuit at the time of the start of a test of the semiconductor test equipment according to a first embodiment. Fig. Figure 5 is a circuit diagram illustrating an example of the test circuit after the start of testing of the semiconductor test equipment according to a first embodiment. Fig. Figure 6 is a circuit diagram illustrating a test circuit of a modification of the semiconductor test device according to the first embodiment. Fig. Figure 7 is a circuit diagram illustrating a test circuit of a semiconductor test device according to a second embodiment. Fig. Figure 8 is a circuit diagram illustrating the test circuit at the time of the start of testing of the semiconductor test equipment according to the second embodiment. Fig. Figure 9 is a circuit diagram illustrating an example of the test circuit after the start of testing of the semiconductor test equipment according to the second embodiment. Fig. Figure 10 is a circuit diagram illustrating a test circuit of a modification of the semiconductor test device according to the second embodiment. Fig. Figure 11 is a circuit diagram illustrating a test circuit of a semiconductor test device according to a third embodiment. Fig. Figure 12 is a circuit diagram illustrating a test circuit of an application example of the semiconductor test device according to the third embodiment. Fig. Figure 13 is a flowchart to explain the process for manufacturing semiconductor devices according to a fourth embodiment. Description of embodiments

[0013] With reference to the drawings, embodiments are explained below. In the drawings referenced below, identical or equivalent sub-areas are designated with the same reference numerals and symbols, and a further explanation of the sub-areas is not repeated. First embodiment

[0014] A semiconductor test apparatus according to a first embodiment is described with reference to Fig. 1 to 5 explained. Fig. Figure 1 is a schematic diagram illustrating a semiconductor test apparatus 100 according to this embodiment. Fig. Figure 2 is a circuit diagram illustrating a test circuit 110 of the semiconductor test facility 100. Fig. Figure 3 is a flowchart to explain a test procedure using the semiconductor test equipment 100. Fig. Figure 4 is a circuit diagram illustrating the test circuit 110 at the time of the start of a test. Fig. Figure 5 is a circuit diagram illustrating an example of test circuit 100 after the start of the test.

[0015] First, with reference to Fig. 1. The configuration of the semiconductor test facility 100 is explained.

[0016] The semiconductor test setup 100 includes a power supply 1, a wafer table 2 connected to a high-voltage side of the power supply 1, a plurality of probes 3 that are electrically independent of one another, a probe card 4 that holds the probes 3 and is connected to a low-voltage side of the power supply 1, and a control unit 5 which contains internally a switch and a control circuit 5a. The probes 3 are also electrically connected to the high-voltage side of the power supply 1 via the control unit 5. A semiconductor wafer 6 and semiconductor devices 7 formed on the semiconductor wafer 6 are objects to be tested and are not included in the configuration of the semiconductor test setup 100. Some of the components are in Fig. 1 omitted. However, the semiconductor test facility 100 is configured to perform the in Fig. 2 illustrated test circuits 110 are included. Fig. 2 is explained below.

[0017] As an example, the following explanation uses a vertical SiC MOSFET (metal-oxide-semiconductor field-effect transistor) as a test target for the semiconductor test facility 100. The example is explained in detail below.

[0018] The semiconductor device 7, which is the object to be tested, is a vertical SiC MOSFET comprising a drain electrode 7a (a high-voltage terminal), a gate electrode 7b, and a source electrode 7c (a low-voltage terminal), as shown in a dashed-line frame in Fig. 2 is illustrated. Fig. In Figure 1, the drain electrode 7a, the gate electrode 7b, and the source electrode 7c are not illustrated. However, a plurality of drain electrodes 7a of a plurality of semiconductor devices 7 are formed within the plurality of semiconductor devices 7 on the back surface of the semiconductor wafer 6, that is, on the wafer table side. A plurality of gate electrodes 7b and a plurality of source electrodes 7c of the semiconductor devices 7 are each formed independently within the plurality of semiconductor devices 7 on the front surface of the semiconductor wafer 6, that is, on the probe side.

[0019] The wafer table 2 is a conductive table for placing the semiconductor wafer 6. The wafer table 2 is electrically connected to the high-voltage side of the power supply 1 via the control unit 5 using a high-voltage wire 11. In other words, the semiconductor wafer 6 is placed on the wafer table 2 such that the drain electrodes 7a formed on the side of the lower surface of the semiconductor wafer 6 come into contact with the wafer table 2. Consequently, the wafer table 2 electrically connects the drain electrodes 7a of the semiconductor devices 7 and the high-voltage side of the power supply 1. Since the drain electrodes 7a are each formed on the side of the back surface of the semiconductor wafer 6, the drain electrodes 7a of the plurality of semiconductor devices 7 are electrically connected to the high-voltage side of the power supply 1 via the wafer table 2.

[0020] The probes 3 are a plurality of terminals held by the probe card 4 and are independent of each other. The probes 3 are independently connected to the source electrodes 7c, which are formed on the upper surface side of the semiconductor wafer 6. The probes 3 are electrically connected to the low-voltage side of the power supply 1 via the probe card 4 and the control unit 5 using a low-voltage wire 12. In other words, the probes 3 are brought into contact with the source electrodes 7c of the semiconductor devices 7 to electrically connect the source electrodes 7c of the semiconductor devices 7 and the low-voltage side of the power supply 1. The source electrodes 7c are each formed independently of each other in the plurality of semiconductor devices 7. The respective source electrodes 7c are electrically connected to the low-voltage side of the power supply 1 via the plurality of probes 3. Fig. In simplified terms, the low-voltage wire 12, which is connected from the probes 3 to the control unit 5 via the probe card 4, is shown. However, the low-voltage wire 12 can actually be a multiple of wires, each independently connected to a multiple terminal. The probes 3 are also electrically connected to the high-voltage side of the power supply 1 via the control unit 5.

[0021] In this way, the drain electrodes 7a formed on the lower surface of the semiconductor wafer 6 and the source electrodes 7c formed on the upper surface of the semiconductor wafer 6 are electrically connected to the power supply 1 using the wafer table 2 and the probes 3, respectively. Consequently, the semiconductor test device 100 can simultaneously apply a voltage between the drains and sources of the plurality of semiconductor devices 7 and perform the burn-in test.

[0022] As explained above, probe card 4 holds the probes 3. Probe card 4 is configured to be removable from the semiconductor test setup 100 along with the probes 3. Because probe card 4 is removable, it can be replaced with different probe cards depending on the test objectives and purposes. Probe card 4 can also contain internal circuit components such as a power supply and a switch, as required.

[0023] To control the test circuit of the semiconductor test device 100, the control unit 5 is configured to be connected to the high-voltage wire 11, which is connected to the high-voltage side of the power supply 1, and to the low-voltage wire 12, which is connected to the low-voltage side of the power supply 1. The control unit 5 includes as its internal components the control circuit 5a and a plurality of interrupt switches 13 (first switches) which are located in the test circuit 110. Fig. Figure 2 illustrates a variety of drain-source switches 14 (secondary switches). Details of the interrupter switches 13 and the drain-source switches 14 are explained below in an explanation of the test circuit 110. The control unit 5 may further include a (not illustrated) voltage detection circuit that measures a voltage between shunt resistors.

[0024] The semiconductor test device 100 also includes a (not illustrated) leakage current detection circuit to measure a leakage current during the application of a voltage in order to detect a defect and deterioration of the semiconductor device 7.

[0025] The test circuit 110 of the semiconductor test device 100 is described with reference to Fig. 2 explained.

[0026] The test circuit 110 contains the high-voltage wire 11 connected to the high-voltage side of the power supply 1, the low-voltage wire 12 connected to the low-voltage side of the power supply 1, the interrupt switches 13 (the first switches) connected to the source electrode side 7c of the semiconductor devices 7, which are the objects to be tested, and the drain-source switches 14 (the second switches) connected between the drains and sources of the semiconductor devices 7. All those shown in the frame with the dashed line in Fig. Figure 2 illustrates the semiconductor devices 7, which are the objects to be tested. The semiconductor devices 7 are not included in the configuration of the semiconductor test equipment 100.

[0027] As in Fig. As illustrated in Figure 2, the multiple semiconductor devices 7 are connected in parallel in the test circuit 110 of the semiconductor test device 100. Consequently, it is possible to apply a voltage between the drains and the sources of the respective semiconductor devices 7 simultaneously and to test the multiple semiconductor devices 7 at the same time.

[0028] The high-voltage wire 11 electrically connects the high-voltage side of the power supply 1 and the drain electrodes 7a (the high-voltage terminals) of the semiconductor devices 7. The low-voltage wire 12 electrically connects the low-voltage side of the power supply 1 and the source electrodes 7c (the low-voltage terminals) of the semiconductor devices 7. Since the semiconductor test device 100 is connected to the semiconductor devices 7 in this way, a voltage can be applied between the drain electrodes 7a and the source electrodes 7c of the semiconductor devices 7.

[0029] The interrupt switches 13 (the first switches) are a plurality of switches connected to the respective semiconductor devices 7 between the source electrodes 7c and the low-voltage side of the power supply 1. By switching off the interrupt switches 13, the semiconductor devices 7 connected to the switched-off interrupt switches 13 are disconnected from the test circuits. As components of the semiconductor test device 100, the interrupt switches 13 are in the Fig. 1 illustrated control unit 5 included.

[0030] The drain-source switches 14 (the second switches) are switches whose one end is connected to the drain electrodes 7a of the respective semiconductor devices 7 and whose other end is connected to the source electrodes 7c of the respective semiconductor devices 7. By switching on the drain-source switches 14, the potential of the source electrodes 7c on the low-voltage side is raised to the potential of the drain electrodes 7a on the high-voltage side. As components of the semiconductor test device 100, the drain-source switches 14 are located in the Fig. 1 illustrated control unit 5 included.

[0031] During the burn-in test, when a voltage is applied between the drain electrodes 7a and the source electrodes 7c of the semiconductor devices 7, the circuit breaker switches 13 are opened and the drain-source switches 14 are opened in all semiconductor devices 7 that are measurement targets. If a semiconductor device is already known to have a defect at this time, the circuit breaker switch 13 can be opened and the drain-source switch 14 can be opened at the beginning of the voltage application.

[0032] Once the switches are controlled in this manner to initiate the voltage application, if a leakage current equal to or greater than a predetermined reference value is detected in any portion of the plurality of semiconductor devices 7, which are the objects under test, the control circuit 5a designates that semiconductor device as defective. The control circuit 5a controls only the interrupt switch 13 and the drain-source switch 14 connected to the defective semiconductor device. First, the control circuit 5a switches the interrupt switch 13 off and then switches the drain-source switch 14 on. The defective semiconductor device can be disconnected from the test circuit by switching off the interrupt switch 13. The potential of the source electrode 7c is raised to the potential of the drain electrode 7a by subsequently switching on the drain-source switch 14.Therefore, the application of voltage to the defective semiconductor device, for which the test is to be suspended, can be reliably prevented. Consequently, it is possible to continue the test without affecting the other semiconductor devices.

[0033] A test procedure for testing semiconductor devices using the semiconductor test equipment 100 is described with reference to Fig. 3 explained.

[0034] First, the semiconductor wafer 6 is placed on the wafer table 2 such that the side of the lower surface of the semiconductor wafer 6 comes into contact with the wafer table 2 (step S101). The position of the semiconductor wafer 6 is adjusted as needed to bring the drain electrodes 7a formed on the side of the lower surface of the semiconductor wafer 6 into contact with the wafer table 2. Consequently, the high-voltage side of the power supply 1 and the drain electrodes 7a (the high-voltage terminals) of the semiconductor devices 7 are electrically connected.

[0035] The probes 3 are then brought into contact with the plurality of source electrodes 7c formed on the upper surface side of the semiconductor wafer 6 (step S102). This electrically connects the low-voltage side of the power supply 1 and the source electrodes 7c (the low-voltage terminals) of the semiconductor devices 7. The probes 3 can be connected to the source electrode 7c of some of the plurality of semiconductor devices 7 formed on the semiconductor wafer 6, or they can be connected to the source electrodes 7c of all semiconductor devices 7.

[0036] After the drain electrodes 7a and the source electrodes 7c are each connected to the power supply 1 in this manner, a voltage test is initiated (step S103). At this time, a voltage is applied between the drain electrodes 7a and the source electrodes 7c of the plurality of semiconductor devices 7 from the power supply 1 via the wafer table 2 connected to the high-voltage wire 11 and the probes 3 connected to the low-voltage wire 12. When the voltage is applied, as described in Fig. As illustrated in Figure 4, the interrupt switches 13 (the first switches) are controlled to the ON position, and the drain-source switches 14 (the second switches) are controlled to the OFF position. The voltage-activated test can be performed at room temperature or at high temperature within the range permitted by the semiconductor test rig 100.

[0037] When the test has been started with voltage applied, the leakage current detection circuit determines whether a leakage current equal to or greater than the previously specified reference value is detected in any of the multitude of test target semiconductor devices 7 (step S104).

[0038] If a leakage current equal to or greater than the reference value is detected in any of the semiconductor devices 7 (Yes in step S104), the control circuit 5a determines that the semiconductor device is a defective semiconductor device. First, the control circuit 5a switches the interrupt switch 13 connected to the defective semiconductor device off, and then switches the drain-source switch 14 connected to the defective semiconductor device on (step S105). For example, if a leakage current equal to or greater than the reference value is detected in the semiconductor device 7 at the right end of the test circuit 110 at the time of the step S104, the control circuit 5a determines that the semiconductor device is defective. Fig. The detection of the test start, as illustrated in section 4, determines how in Fig. As illustrated in Figure 5, the control circuit 5a represents a semiconductor device 71 as a defective semiconductor device 71. The control circuit 5a controls the drain-source switch 14 and the interrupt switch 13, which are connected to the defective semiconductor device 71. First, the control circuit 5a switches the interrupt switch 13 off and then switches the drain-source switch 14 on. When the interrupt switch 13 is switched off first, the defective semiconductor device 71 is disconnected from the test circuit. When the drain-source switch 14 is then switched on, the potential of the source electrode 7c is raised to the potential of the drain electrode 7a. Consequently, the potential of the defective semiconductor device 71 can be stabilized. At this time, the voltage application to the other semiconductor devices 7 continues.

[0039] If a leakage current equal to or greater than the reference value is not detected in all the semiconductor devices 7 (No in step S104) or after the switching control as above in step S105 has been performed, the control circuit 5a then determines whether all the test target semiconductor devices 7 are determined to be defective semiconductor devices, that is, the switching control in step S105 is performed on all the test target semiconductor devices 7 (step S106).

[0040] When the switching control in step S105 is performed on all the semiconductor devices 7, that is, when the interrupt switches 13 are switched off or the drain-source switches 14 are switched on (YES in step S106), all the semiconductor devices 7 are disconnected from the test circuit. No voltage is applied to any of the semiconductor devices 7. Therefore, the control circuit 5a proceeds to step S108, suspends the voltage application, and ends the test.

[0041] If, on the other hand, the switching control in step S105 is not performed on all the semiconductor devices 7, that is, if the semiconductor device 7 to which a voltage is currently applied is present (No in step S106), the semiconductor test device 100 determines whether a specified test time has elapsed (step S107). The test time is predetermined.

[0042] If it is determined that the test time has not elapsed (No in step S107), the control circuit 5a returns to step S104 and continues the detection using the leakage current detection circuit.

[0043] If, on the other hand, it is determined that the specified test time has elapsed (Yes in step S106), the control circuit 5a ends the test by applying voltage (step S108).

[0044] After the test with voltage applied ends, the control circuit 5a releases the contact of the probes 3 that were brought into contact with the source electrode 7c (step S109).

[0045] Finally, the semiconductor wafer 6 placed on wafer table 2 is removed from the setup as the measurement target, and the test ends (step S110).

[0046] By performing the burn-in test using the semiconductor test device 100 as described above, it is possible to apply a positive voltage between the drains and sources of the multitude of semiconductor devices 7 and to reject any semiconductor device containing a large number of crystal defects and exhibiting a relatively short device lifetime as a defective product. This makes it possible to ensure the reliability of the semiconductor devices.

[0047] A check of the characteristics of the semiconductor devices can be performed between steps S102 and S103, i.e., before the start of the voltage test, and between steps S107 and S108, i.e., after the end of the voltage test. By performing the check of the characteristics before the start of the voltage test, it is possible, particularly in semiconductor device 7 where a defect is found, to first switch off the interrupt switch 13 and switch on the drain-source switch 14, and to disconnect the semiconductor device from the test circuit, thus preventing a voltage from being applied to the semiconductor device.

[0048] The effects of the semiconductor test facility 100 configured in this way are explained.

[0049] In conventional semiconductor test equipment, when a voltage is applied simultaneously to a large number of semiconductor devices to perform a burn-in test, the test duration can sometimes be long. Therefore, if a defect occurs and leakage current develops in some of the semiconductor devices, the test circuit is short-circuited and the power supply is switched off when the voltage is subsequently applied. This creates the problem that the test cannot be continued for the other semiconductor devices with good device characteristics.On the other hand, in this embodiment of the semiconductor test device, there is an effect that, when a test is performed on a large number of semiconductor devices, the test can be performed on a large number of semiconductor devices simultaneously and can be continued until the very end, even if a defect occurs in one part of the semiconductor device.

[0050] This means that in the configuration of the semiconductor test device 100 in this embodiment, the interrupt switches 13 and the drain-source switches 14 are provided in the test circuit 110. Therefore, if a leakage current equal to or greater than the reference value is detected in a portion of the semiconductor devices, that semiconductor device can be identified as defective and disconnected from the test circuit. The potential of the semiconductor device can then be stabilized, and the test can be continued without affecting the remaining semiconductor devices with good device characteristics.

[0051] A modification of the semiconductor test device in the first embodiment is described with reference to Fig. 6 explained. Fig. Figure 6 is a circuit diagram illustrating a test circuit 120 obtained by modifying the test circuit 110 of the semiconductor test device 100 in this embodiment.

[0052] First, with reference to Fig. 6 explains the test circuit 120.

[0053] The test circuit 120 differs from the test circuit 110 in the first embodiment in that the test circuit 120 additionally includes a plurality of power supplies 10 between drains and sources for applying a voltage between gates and sources, and furthermore includes gate-source switches 15 (fourth switches) connected in parallel with the power supplies 10 and gate-source disconnect switches 19 (fifth switches) connected in series with the power supplies 10 between the gate electrodes 7b and the source electrodes 7c.

[0054] If a voltage is also applied between the gates and the sources of the semiconductor devices 7, the following are considered with reference to Fig. 1. The probes 3, as explained in Figure 1, were each independently brought into contact with the gate electrodes 7b of the semiconductor device 7. The power supplies 10 are each connected between the gate electrodes 7b and the source electrodes 7c. The test circuit 120 was configured as shown in Figure 1. Fig. As illustrated in Figure 6, it is desirable to connect the high-voltage side of the power supplies 10 to the side of the source electrodes 7c and to connect the low-voltage side of the power supplies 10 to the side of the gate electrodes 7b.

[0055] The gate-source switches 15 (the fourth switches) are connected in parallel to the power supplies 10 to the gate electrodes 7b and the source electrodes 7c of the respective semiconductor devices 7. During the burn-in test, when a voltage is applied between the gate electrodes 7b and the source electrodes 7c, the gate-source switches 15 are off at the start of the voltage application. After the test has started, if a leakage current equal to or greater than the reference value is detected in any of the multiple target semiconductor devices 7, the control circuit 5a simultaneously opens the drain-source switches 14 and the gate-source switches 15. Consequently, it is possible to raise the potential of the source electrodes 7c to the potential of the gate electrodes 7b.

[0056] The gate-source disconnect switches 19 (the fifth switches) are connected in series with the power supplies 10 to the gate electrodes 7b and the source electrodes 7c of the respective semiconductor devices 7. During the burn-in test, when a voltage is applied between the gate electrodes 7b and the source electrodes 7c, the gate-source disconnect switches 19 are turned on at the start of the voltage application. After the test has started, if a leakage current equal to or greater than the reference value is detected in any of the multiple target semiconductor devices 7, the control circuit 5a opens the interrupt switch 13 and simultaneously opens the gate-source disconnect switch 19. Consequently, it is possible to disconnect the voltage between the gate and the source and isolate the semiconductor device 7 from the test circuit.

[0057] By applying a positive voltage between the drains and sources of the semiconductor devices 7 and a negative voltage between the gates and sources in this way, it is possible to perform the test on a MOSFET with a low threshold voltage.

[0058] A test procedure for testing semiconductor devices using a semiconductor test setup containing test circuit 120 is explained with a focus on differences compared to the semiconductor test setup 100 containing test circuit 110.

[0059] In the test procedure for testing semiconductor devices using the semiconductor test equipment containing the test circuit 120, steps S103 and S105 are distinct from the steps in the test procedure of the semiconductor test equipment 100, which refers to Fig. The steps explained in section 3 differ slightly. The remaining steps are the same.

[0060] In step S103, at the time voltage is applied, the interrupt switches 13 are switched on and the drain-source switches 14 are switched off. Additionally, the gate-source disconnect switches 19 are switched on and the gate-source switches 15 are switched off.

[0061] In step S105, control circuit 5a first switches the interrupt switches 13 to off. At the same time, control circuit 5a also switches the gate-source disconnect switches 19 to off. Then, control circuit 5a switches the drain-source switches 14 to on. Simultaneously, control circuit 5a also switches the gate-source switches 15 to on. Consequently, after a defective semiconductor device is disconnected from the test circuit, the potential between the drain and the source and between the gate and the source can be adjusted to the same potential. Therefore, the potential of the defective semiconductor device disconnected from the test circuit stabilizes. It is possible to continue the test without affecting the other semiconductor devices.

[0062] When performing a burn-in test on a SiC MOSFET, applying a positive voltage between the drain and source and simultaneously a negative voltage between the gate and source is particularly effective. In such a case, the following benefits arise: by providing the interrupt switch 13, the drain-source switch 14, and the gate-source switch 15, a defective semiconductor device in which a leakage current equal to or greater than the reference value is detected can be stably disconnected from the test circuit, allowing testing of the remaining semiconductor devices with good device characteristics to continue.

[0063] In this embodiment, the semiconductor device 7, which is the object to be tested, is described as an example of the SiC MOSFET, which includes terminals for the drain electrode 7a, the gate electrode 7b, and the source electrode 7c. However, the semiconductor device 7 is not limited to this. When a Si MOSFET, an IGBT (insulated-gate bipolar transistor), or the like is tested, the same effect is obtained by providing switches in their test circuit that are equivalent to the breaker switch 13 (the first switch), the drain-source switch 14 (the second switch), and the gate-source switch 15 (the fourth switch).

[0064] In this embodiment, the semiconductor wafer 6 is the test target of the semiconductor test device 100. However, not only this, but, for example, an alligator wire can be used as the wafer table 2 or the probes 3, if the semiconductor test device 100 is a semiconductor test device that includes the following: Fig. 2 illustrated test circuit 110 or the one in Fig. Figure 6 illustrates the test circuit 120. In this case, the test target is not limited to the semiconductor wafer. A plurality of independent semiconductor devices, a plurality of semiconductor modules, or the like can be the test target. The same applies to the other embodiments. Second embodiment

[0065] A semiconductor test device in a second embodiment is described with reference to Fig. Explained in sections 7 to 9. Fig. Figure 7 is a circuit diagram illustrating a test circuit 210 of the semiconductor test device in this embodiment. Fig. Figure 8 is a circuit diagram illustrating the test circuit 210 at the time of the start of a test. Fig. Figure 9 is a circuit diagram illustrating an example of test circuit 210 after the start of testing.

[0066] First, with reference to Fig. 7 explains the test circuit 210.

[0067] The test circuit 210 of the semiconductor test device in this embodiment differs from the test circuit 110 of the semiconductor test device 100 in the first embodiment insofar as, as in Fig. Figure 7 illustrates that the test circuit 210 includes connecting switches 16 between sources (third switches) for electrically switching on or off between the source electrodes 7c (the low-voltage terminals) of the plurality of semiconductor devices 7. The other components of the semiconductor test setup in this embodiment are the same as the components of the semiconductor test setup 100 in the first embodiment. Therefore, a schematic diagram and an explanation of the semiconductor test setup are omitted.

[0068] As in Fig. As illustrated in Figure 7, the connecting switches 16 between sources (the third switches) are provided such that the source electrode 7c of each of the semiconductor devices 7 can be switched on or off independently of the source electrodes 7c of all the other semiconductor devices.

[0069] In Fig. In the case of 7, four semiconductor devices 7 are connected in parallel and are being tested. Six interconnect switches 16 are used between the sources and six wires for this purpose. Consequently, each of the semiconductor devices 7 is connected to the other semiconductor devices 7 via the interconnect switches 16 between the sources. If N semiconductor devices 7 are connected in parallel, (1+2+ ... +(N-1)) interconnect switches 16 are provided between the sources and (1+2+ ... +(N-1)) wires accordingly. Consequently, each of the N semiconductor devices 7 can be independently connected to all the other semiconductor devices 7 via the interconnect switches 16 between the sources.By providing the multitude of connecting switches 16 between sources that are to be connected under the respective semiconductor devices 7, it is possible, even if a defect occurs in any semiconductor device 7, to disconnect only one defective semiconductor device while keeping the source electrodes 7c connected in the other semiconductor devices 7.

[0070] In the test using test circuit 210, the test is performed as in the first embodiment by applying a voltage between the drains and sources of the plurality of semiconductor devices 7 via the high-voltage wire 11 and the low-voltage wire 12 from the power supply 1. In this case, by switching on all the connecting switches 16 between the sources, a source potential of the test targets can be set simultaneously during the test. Consequently, it is possible to stabilize any noise that occurs during the test. The control circuit 5a contained in the control unit 5 can control the connecting switches 16 between the sources. A separate IC (not illustrated) can be used for this control.

[0071] A test procedure for testing semiconductor devices using the semiconductor test equipment in this embodiment is described with reference to Fig. 8 and Fig. 9 explained.

[0072] In the test procedure for testing the semiconductor devices using the semiconductor test equipment in this embodiment, steps S103 and S105 are distinct from the steps of the test procedure of the semiconductor test equipment 100, which refers to Fig. The steps of the test procedure for testing the semiconductor devices using the semiconductor test equipment in this embodiment are partially different from those in the first embodiment. Therefore, a detailed explanation of these steps is omitted.

[0073] Step S103 is a step in which a voltage is applied between the drains and sources of the semiconductor devices 7. At the time of the voltage application in the test, in which the semiconductor test setup is used in this embodiment, as described in Fig. As illustrated in Figure 8, when the drain-source switches 14 are switched off, the interrupt switches 13 are switched on, and the connecting switches 16 between sources are switched on. By switching on the connecting switches 16 between sources in this way, the potential on the source electrode side 7c of the respective semiconductor devices 7 can be set together. Therefore, the influence of a weak leakage current and noise can be suppressed. The control circuit 5a then proceeds to step S104 and detects a leakage current as in the first embodiment.

[0074] Step S105 is a step in which the switches of the semiconductor test setup are controlled when a leakage current equal to or greater than the reference value is detected in step S104. Control circuit 5a switches all the connecting switches 16 between sources linking a defective semiconductor device, in which the leakage current equal to or greater than the reference current is detected, and the other semiconductor devices to OFF. Then, control circuit 5a switches the interrupter switch 13 connected to the defective semiconductor device to OFF and subsequently switches the drain-source switch 14 to ON.

[0075] For example, if a leakage current equal to or greater than the reference value occurs in the semiconductor device 7 at the right end in the Fig. The test circuit illustrated in section 8 is detected, as determined by how in Fig. As illustrated in Figure 9, the control circuit 5a first identifies the semiconductor device 71, in which the leakage current equal to or greater than the reference value is detected, as a defective semiconductor device 71. The control circuit 5a then switches all the interconnecting switches 16 between sources connected to the defective semiconductor device 71 to off, subsequently switches the interrupter switch 13 to off, and then switches the drain-source switch 14 to on. Consequently, after the source electrode 7c of the defective semiconductor device 71, in which the leakage current is detected, and the source electrodes 7c of the other semiconductor devices 7 are electrically disconnected, it is possible to disconnect the defective semiconductor device 71 from the test circuit and raise the potential of the source electrode 7c to the potential of the drain electrode 7a.In this way, the defective semiconductor device 71, in which the leakage current is detected, can be disconnected from the test circuit after the connection on the source electrode 7c side is broken. Therefore, it is possible to prevent noise from switching the switches from affecting the other semiconductor devices 7 with good device characteristics. At this time, the voltage is applied to the other semiconductor devices 7.

[0076] As a common element for the explanation in the present invention, the test circuit is schematically illustrated in the drawings. Accordingly, for example, in Fig. 9 The source electrode 7c of the semiconductor device 71, in which a leakage current equal to or greater than the reference value is detected, and the source electrodes 7c of the other semiconductor devices are kept connected by the low-voltage wire 12, even when the connecting switches 16 between sources are switched off. In fact, compared to the connecting switches 16 between sources, the low-voltage wire 12 connected to the power supply 1 is positioned far away and is long. Therefore, even when the source electrodes 7c are connected by the low-voltage wire 12, there is virtually no influence of noise between the semiconductor device 71 and the other semiconductor devices 7.In other words, since the connecting switches 16 between sources are provided near the source electrodes 7c of the semiconductor devices 7, it is possible in the semiconductor test device in this embodiment to stabilize a fluctuation in the potential due to the influence of noise or the like between the semiconductor device 71 and the other semiconductor devices 7.

[0077] The effects of the semiconductor test setup in this embodiment, configured as described above, are explained.

[0078] During a burn-in test, a high voltage is applied, or the test is performed at a high temperature. Even if the target semiconductor device is not detected as defective, leakage current or noise is likely present. This is especially true when the test is performed on a semiconductor wafer with numerous semiconductor devices, as these devices are easily affected by noise or similar interference from other semiconductor devices located nearby.

[0079] If a leakage current equal to or greater than the reference value occurs in some of the semiconductor devices during voltage application in the burn-in test, the defective semiconductor device 71 can be disconnected from the test circuit by controlling the interrupt switch 13. However, noise occurs, for example, during the switching of the switch. If the noise is transmitted to the other semiconductor devices, a linked breakage or a defect is likely to occur in the semiconductor devices with good device characteristics.

[0080] Therefore, in this embodiment of the semiconductor test setup, a common potential for the semiconductor devices 7 can be set by switching on the connecting switches 16 between sources and connecting the source electrodes 7c of the respective semiconductor devices 7 during the test. This results in the particular effect of reducing the influence of noise during the test.

[0081] When a leakage current equal to or greater than the reference value is detected in a portion of the semiconductor devices, all the interconnect switches 16 between sources connected to the defective semiconductor device are first switched off, and then the interrupt switch 13 and the drain-source switch 14 are activated. Consequently, there is a special effect that noise caused by switching devices such as the interrupt switch 13 or the drain-source switch 14 can be switched off, and even if some of the noise is propagated, it is stabilized by its connection to the other semiconductor devices, thus suppressing damage to semiconductor devices with good device characteristics.

[0082] A modification of the semiconductor test device in the second embodiment is described with reference to Fig. 10 explained. Fig. Figure 10 is a circuit diagram illustrating a test circuit 220 obtained by modifying the test circuit 210 of the semiconductor test device in this embodiment.

[0083] The test circuit 220 differs from the test circuit 210 in the second embodiment in that the test circuit 220 includes a switch connection wire 17 (a third switch connection wire) that is connected to the low-voltage side of the power supply 1, and the connecting switches 16 between sources, which are connected to the side of the source electrodes 7c of the respective semiconductor devices 7, are connected together with the switch connection wire 17.

[0084] To electrically switch the respective source electrodes 7c of the plurality of semiconductor devices 7 on or off via the connecting switches 16 between sources, as explained above, if the number of semiconductor devices 7 is N, (1+2+ ... +(N+1)) connecting switches 16 between sources are usually necessary. By providing the switch connecting wire 17, the connecting switches 16 between sources, which are independently connected to the source electrodes 7c of the respective semiconductor devices 7, are therefore connected together by the switch connecting wire 17. Consequently, it is possible to electrically switch the respective source electrodes 7c on or off independently. Therefore, there is a special effect that the number of connecting switches 16 between sources and the number of wires can be reduced to N. Third embodiment

[0085] A semiconductor test device in a third embodiment is described with reference to Fig. 11 explained. Fig. Figure 11 is a circuit diagram illustrating a test circuit 310 of the semiconductor test device in this embodiment.

[0086] First, with reference to Fig. 11 explains the test circuit 310.

[0087] The test circuit 310 of the semiconductor test device in this embodiment differs from the test circuit 110 of the semiconductor test device 100 in the first embodiment insofar as, as in Fig. As illustrated in Figure 11, the test circuit 310 contains bidirectional diodes 18 that electrically switch the source electrodes 7c of the plurality of semiconductor devices 7 on or off. The remaining components of the semiconductor test device in this embodiment are the same as the components of the semiconductor test device 100 in the first embodiment. Therefore, a schematic diagram and an explanation of the semiconductor test device are omitted.

[0088] The bidirectional diodes 18 are provided in the same number and at the same positions as the connecting switches 16 between sources of the test circuit 210 in the second embodiment described. In each of the bidirectional diodes 18, two diodes are connected in parallel such that they are oriented in opposite directions, so that if a potential difference equal to or greater than a fixed threshold occurs between the two ends of the bidirectional diode 18, an electric current flows only in the direction of one of the ends. Since the source electrode side 7c of the respective semiconductor devices 7 is connected via the bidirectional diodes 18, accordingly, if noise occurs on the source electrode side 7c of any of the semiconductor devices 7, an electric current flows in one direction to cancel out the influence of the noise.When no noise and no potential difference are present, the bidirectional diodes 18 are in an off state. Therefore, no electric current flows between the source electrodes 7c.

[0089] A test procedure for testing semiconductor devices using the semiconductor test equipment in this embodiment is not related to the control of the bidirectional diodes 18. The test procedure is the same as the test procedure described with reference to Fig. 3 was explained in the first embodiment. Therefore, an explanation of the test procedure is omitted.

[0090] The effects of the semiconductor test setup in this embodiment, configured as described above, are explained.

[0091] In the semiconductor test setup of this embodiment, the bidirectional diodes 18 connected between the source electrodes 7c of the plurality of semiconductor devices 7 provide an effect that the potential between the source electrodes 7c of the respective semiconductor devices 7 can be kept common, thus reducing the influence of noise during the test. In particular, when the connecting switches 16 between sources described in the second embodiment are used, these switches must be controlled. However, when the bidirectional diodes 18 are used, there is a special effect that on / off control of the switches is not necessary.

[0092] As in the second embodiment of the test circuit 220, which is described in Fig. As illustrated in Figure 10, the switch connection wire 17 (a connection wire for bidirectional diodes) can be used for the test circuit 310 of the semiconductor test device in this embodiment. In this case, as in the second embodiment, it is possible to reduce the number of bidirectional diodes 18 and the wires.

[0093] An application example of the semiconductor test device in the third embodiment is given with reference to Fig. 12 explained. Fig. Figure 12 is a circuit diagram illustrating a test circuit 320 for which the test circuit 310 of the semiconductor test device is used in this embodiment.

[0094] The test circuit 320 is as described in Fig. Figure 12 illustrates an application example for applying the semiconductor test device in this embodiment to semiconductor devices 8, which are current-sensing MOSFETs containing a plurality of source electrodes in a semiconductor device. The semiconductor devices 8 are in Fig. Figure 12 is illustrated in the frame with dashed lines. Since the semiconductor devices are objects to be tested, they are not included in the semiconductor test setup configuration.

[0095] Each of the semiconductor devices 8 contains, in addition to a drain electrode 8a and a gate electrode 8b, two types of source electrodes, namely a main source electrode 8c and a measuring source electrode 8d. The main source electrodes 8c and the measuring source electrodes 8d are formed in the respective semiconductor devices 8.

[0096] In such semiconductor devices 8, when a large number of semiconductor devices 8 are tested simultaneously and a defect such as a leakage current occurs, the potential of the respective source electrodes is affected by noise. Usually, the capacitance of the measuring source electrodes 8d is relatively smaller than the capacitance of the main source electrodes 8c, and the capacitance of the measuring source electrodes 8d is slightly affected by noise. This is a break or interruption due to noise.

[0097] As in Fig. As illustrated in Figure 12, the bidirectional diodes 18 are therefore connected between the main source electrodes 8c and the measuring source electrodes 8d. Consequently, as explained in the test circuit 310, there is a special effect that the influence of noise can be suppressed.

[0098] In the above explanation, the bidirectional diode 18 is connected between the main source electrode 8c and the measuring source electrode 8d of the same semiconductor device 8 in the test circuit 320. Furthermore, the connecting switch 16 can be provided between sources, or the bidirectional diode 18 can be provided between source electrodes of different semiconductor devices 8. Fourth embodiment

[0099] A fourth embodiment relates to a method for manufacturing a semiconductor device using the semiconductor test equipment according to one of the first to third embodiments. Fig. Figure 13 is a flowchart to explain the process for manufacturing semiconductor devices in this embodiment.

[0100] First, the method for manufacturing semiconductor devices in this embodiment is described with reference to Fig. 13 explained.

[0101] First, an n-type SiC substrate is prepared (step S201).

[0102] Subsequently, an n-type SiC drift layer is formed on the front surface of the SiC substrate by epitaxial growth (step S202).

[0103] A p-type trough region containing aluminium (Al), which is a first defect, as a p-type defect is selectively formed on the formed SiC drift layer by means of ion injection (step S203).

[0104] An n-type source region containing nitrogen (N), which is a second defect, as an n-type defect is selectively formed by ion injection on a surface layer section of the formed trough region (step S204).

[0105] A heat treatment is then carried out to activate the defects (step S205).

[0106] After heat treatment, a gate insulating film consisting of silicon dioxide (SiO2) is formed on the side of the front surface of the SiC drift layer containing the trough area and the source area, except for a part on the side of the front surface of the source area (step S206).

[0107] Furthermore, a polysilicon film with electrical conductivity is formed on the gate insulating film, and a gate electrode is formed by structuring the polysilicon film (step S207).

[0108] Subsequently, an intermediate insulating layer is formed on the gate electrode (step S208).

[0109] Then, a source electrode electrically connected to the source area is formed on the source area (step S209).

[0110] A drain electrode is then formed on the back surface of the SiC substrate (step S210).

[0111] In this way, a semiconductor wafer is completed on which a large number of semiconductor devices are formed (step S211).

[0112] The semiconductor wafer is then placed in the semiconductor test setup in any of the first to third embodiments, and the burn-in test is performed (step S212). This test step is the same as described in reference to Fig. The test procedures described in the first to third embodiments are explained below. A detailed explanation of the test step is omitted.

[0113] After the test ends, a semiconductor device identified as defective is marked (step S213).

[0114] Subsequently, an ineffective area in the outer periphery of the wafer is cut off and a chip is singulated (step S214).

[0115] After the semiconductor wafer has been cut and the individual semiconductor devices have been completed, the semiconductor devices identified as defective products are excluded and the semiconductor devices are sorted into non-defective products and defective products (step S215).

[0116] In this way, non-defective semiconductor devices are completed (step S216).

[0117] As explained above, in this embodiment of the semiconductor device manufacturing process, to produce non-defective semiconductor devices, it is possible to connect the rear surface of the semiconductor wafer 6 to the high-voltage side of the power supply 1 and the front surface of the semiconductor wafer 6 to the low-voltage side of the power supply 1 to perform the test. Therefore, a large number of vertical MOSFETs can be measured simultaneously at the time the semiconductor wafer 6 is completed.

[0118] In this embodiment of the semiconductor device testing procedure, semiconductor devices are manufactured using the semiconductor test equipment described in the first to third embodiments. Therefore, a large number of semiconductor devices can be tested simultaneously. Furthermore, test interruptions due to a defect in some of the semiconductor devices can be avoided. Since this reduces the testing time, the overall manufacturing time for semiconductor devices can be reduced.

[0119] An application example of the method for manufacturing semiconductor devices in the fourth embodiment is explained.

[0120] In the fourth embodiment of the semiconductor device manufacturing process, the vertical SiC MOSFET is fabricated, such as a planar or trench type. However, the fourth embodiment of the semiconductor device manufacturing process can also be applied to a manufacturing process for the current-sensing MOSFET described in the application example of the third embodiment.

[0121] When the MOSFET incorporating current sensing is manufactured, among the [missing information] are [missing information]. Fig. Of the 13 illustrated manufacturing steps, steps S210 and S213 are the main differences. An explanation of the other manufacturing steps is omitted.

[0122] Step S210 is a step for forming a source electrode. In the case of a current-sensing MOSFET, a semiconductor device contains two electrodes: a main source electrode and a measuring source electrode. Therefore, in the source electrode formation step, the main source electrode is provided in a large portion of a source region, and the measuring source electrode is provided in a portion of a region where the main source electrode is not present. At this stage, the main source electrode and the measuring source electrode are provided independently.

[0123] Step S213 is a step of the burn-in test. As explained in the application example of the third embodiment, the burn-in test is performed by connecting a bidirectional diode between the main source electrode and the measuring source electrode. Consequently, it is possible to prevent a situation in which the measuring source electrode is influenced by the main source electrode and a defect occurs in the measuring source electrode, or the measuring source electrode is interrupted or destroyed.

Claims

[1] Semiconductor test equipment comprising: a power supply (1); a high-voltage wire (11) connecting high-voltage terminals (7a) of a plurality of semiconductor devices (7), which are objects to be tested, to a high-voltage side of the power supply (1); a low-voltage wire (12) connecting low-voltage terminals (7c) of the semiconductor devices (7) to a low-voltage side of the power supply (1); first switches (13) each connected in series with the semiconductor devices (7), each of the first switches (13) having one end connected to the low-voltage side of the power supply (1) via the low-voltage wire (12) and another end connected to the low-voltage terminal (7c); second switches (14) each connected to the semiconductor devices (7), each of the second switches (14) having one end connected to the high-voltage terminal (7a) and another end connected to the low-voltage terminal (7c); and a control circuit (5a) that controls the first switches (13) and the second switches (14). [2] Semiconductor test device according to claim 1, wherein the control circuit (5a) at the start of a test controls the first switches (13) to ON and the second switches (14) to OFF, and after the start of the test the control circuit (5a) determines the semiconductor device (7) in which a leakage current equal to or greater than a reference value is detected as a defective semiconductor device (7), controls the first switch (13) connected to the defective semiconductor device (7) to OFF, and then controls the second switch (14) connected to the defective semiconductor device (7) to ON. [3] Semiconductor test apparatus according to claim 2, further comprising a plurality of third switches (16) which are connected to the low voltage terminals (7c) of the semiconductor devices (7) and which electrically switch on or off between the low voltage terminals (7c). [4] Semiconductor test device according to claim 3, wherein the control circuit (5a) controls the third switches (16) to On at the time of the start of the test and after the start of the test the control circuit (5a) controls the third switch (16) connected to the low voltage terminal (7c) of the defective semiconductor device (7) to Off and then controls the first switch (13) connected to the defective semiconductor device (7) to Off. [5] Semiconductor test apparatus according to claim 3 or 4, further comprising a connecting wire (17) for third switches, which connects the plurality of third switches (16) to the low-voltage side of the power supply (1), wherein one ends of the third switches (16) are independently connected to the low-voltage terminals (7c) of the semiconductor devices (7) and the other ends of the third switches (16) are jointly connected to the connecting wire (17) for third switches. [6] Semiconductor test device according to claim 2, further comprising a plurality of bidirectional diodes (18) which are connected to the low voltage terminals (7c) of the semiconductor devices (7) and which electrically switch on or off between the low voltage terminals (7c). [7] Semiconductor test apparatus according to claim 6, further comprising a connecting wire (17) for bidirectional diodes, which connects the plurality of bidirectional diodes (18) to the low-voltage side of the power supply (1), wherein one end of the bidirectional diodes (18) is independently connected to the low-voltage terminals (7c) of the semiconductor devices (7) and the other end of the bidirectional diodes (18) is jointly connected to the connecting wire (17) for bidirectional diodes. [8] Semiconductor test device according to any one of claims 2 to 7, further comprising a fourth switch (15), wherein the semiconductor devices (7) are MOSFETs with a gate electrode (7b), a drain electrode (7a) which is the high voltage terminal (7a), and a source electrode (7c) which is the low voltage terminal (7c), one end of the fourth switch (15) being connected to the gate electrodes (7b) of the semiconductor devices (7) and the other ends of the fourth switch (15) being connected to the source electrodes (7c) of the semiconductor devices (7). [9] Semiconductor test device according to claim 8, wherein the control circuit (5a) controls the fourth switches (15) to Off at the time of the start of the test and after the start of the test the control circuit (5a) simultaneously controls the second switch (14) connected to the defective semiconductor device (7) and the fourth switch (15) connected to the defective semiconductor device (7) to On. [10] Semiconductor test device according to any one of claims 1 to 9, wherein the object to be tested is a semiconductor wafer (6) containing a plurality of MOSFETs, Each of the MOSFETs has a gate electrode (7b), a drain electrode (7a), which is the high-voltage terminal (7a), and a source electrode (7c), which is the low-voltage terminal (7c). the drain electrodes (7a) are formed on one side of a rear surface of the semiconductor wafer (6), the source electrodes (7c) and the gate electrodes (7b) are formed on one side of a front surface of the semiconductor wafer (6), the semiconductor test facility comprises a wafer table (2), probes (3), a probe card (4) and a control unit (5), the wafer table (2) is connected to the high-voltage wire (11), when the semiconductor wafer (6) is placed on the wafer table (2) such that one side of a lower surface of the semiconductor wafer (6) comes into contact with the wafer table (2), the wafer table (2) is electrically connected to the drain electrodes (7a) of the plurality of MOSFETs, the probes (3) are positioned opposite the wafer table (2), are brought into contact with one side of an upper surface of the semiconductor wafer (6) and are independently connected to the source electrodes (7c) of the plurality of MOSFETs, the probe card (4) is connected to the low-voltage wire (12) and holds the probes (3) and the control unit (5) is connected to the high voltage wire (11) and the low voltage wire (12) and contains inside the first switches (13), the second switches (14) and the control circuit (5a). [11] Test method for semiconductor devices comprising: an electrical connection of high-voltage terminals (7a) of a plurality of semiconductor devices (7) to a high-voltage side of a power supply (1); an electrical connection of low-voltage terminals (7c) of the semiconductor devices (7) to a low-voltage side of the power supply (1); a commencement of a simultaneous application of a voltage to the plurality of semiconductor devices (7) in order to detect leakage currents; and a determination of the semiconductor device (7) in which the leakage current, which is equal to or greater than a reference value, is detected as a defective semiconductor device (7), a disconnection of the defective semiconductor device (7) from the low-voltage side of the power supply (1) and then a raising of a potential of the low-voltage terminal (7c) of the defective semiconductor device (7) to a potential of the high-voltage terminal (7a). [12] Method for manufacturing semiconductor devices comprising: the formation of a drift layer on a front surface of a substrate; a selective formation of a trough area on the drift layer; a selective formation of a source area on a surface layer section of the trough area; a formation of a gate insulating film on the front surfaces of the drift layer, the trough area and the source area; a formation of a gate electrode (7b) on the gate insulating film; forming a source electrode (7c) on the source area; a formation of a drain electrode (7a) on a rear surface of the substrate; placing a semiconductor wafer (6) on which a plurality of semiconductor devices (7) are formed by the above steps on a wafer table (2) such that one side of a lower surface of the semiconductor wafer (6) comes into contact with the wafer table (2), and electrically connecting the drain electrode (7a) to a high-voltage side of a power supply (1); bringing a probe (3) into contact with one side of an upper surface of the semiconductor wafer (6) and electrically connecting the source electrode (7c) to a low-voltage side of the power supply (1); a commencement of a simultaneous application of a voltage to the plurality of semiconductor devices (7) in order to detect leakage currents; a determination of the semiconductor device (7) in which the leakage current, which is equal to or greater than a reference value, is detected as a defective semiconductor device (7), a disconnection of the defective semiconductor device (7) from the low-voltage side of the power supply (1) and then a raising of a potential of the source electrode (7c) of the defective semiconductor device (7) to a potential of the drain electrode (7a); a marking of the semiconductor device identified as defective (7); a singulation of the semiconductor devices (7) formed on the semiconductor wafer (6); and a sorting of the individual semiconductor devices (7) into non-defective products and defective products. [13] Method for manufacturing semiconductor devices according to claim 12, wherein the semiconductor device (7) is a current sensing semiconductor device comprising a main source electrode and a measuring source electrode as the source electrode (7c); the measuring source electrode has a smaller capacitance than that of the main source electrode, when the source electrode (7c) is formed, the main source electrode and the measuring source electrode are formed and, When the voltage is applied, a bidirectional diode (18) is connected between the main source electrode and the measuring source electrode.

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