CAPACITY REDUCTION FOR A DEVICE WITH A REAR POWER SUPPLY RAIL

Abstract

Semiconductor transistor device comprising: a channel structure (102), a gate structure (104) enclosing the channel structure (102), a first epitaxial source / drain structure (106) and a second epitaxial source / drain structure (108) arranged at opposite ends of the channel structure (102), a gate contact (110) arranged on the gate structure (104), and a rear source / drain contact (120) arranged beneath the first epitaxial source / drain structure (106), wherein the first epitaxial source / drain structure (106) has a concave lower surface contacting the rear source / drain contact (120), and a rear dielectric cover (126) arranged beneath and in contact with the second epitaxial source / drain structure (108), wherein the second epitaxial source / drain structure (108) has a concave lower surface that contacts the rear dielectric cover (126).

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US application serial no. 63 / 022,666, which was filed on May 11, 2020 and is incorporated herein in its entirety by cross-reference. STATE OF THE ART

[0002] The integrated semiconductor (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Function density (i.e., the number of interconnected components per unit area of ​​the chip) has generally increased throughout IC development, while geometric size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) has decreased. This miniaturization process (scaling) offers fundamental advantages by increasing production efficiency and reducing associated costs. However, such miniaturization has also increased the complexity of processing and manufacturing ICs. List of characters

[0003] Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a cross-sectional view of some embodiments of a semiconductor transistor device having a rear-side power supply rail. Fig. Figure 2 shows a cross-sectional view of some additional embodiments of a semiconductor transistor device having a rear-side power supply rail. Fig. Figure 3 shows a cross-sectional view of some additional embodiments of a semiconductor transistor device having a rear-side power supply rail. Fig. Figure 4 shows a cross-sectional view of some additional embodiments of a semiconductor transistor device having a rear-side power supply rail. Fig. Figure 5 shows a perspective view of some embodiments of a semiconductor transistor device having a rear-side power supply rail. Fig. 6A is a cross-sectional view of some embodiments of a semiconductor transistor device, extending along line AA' of Fig. 5 is drawn. Fig. 6B is a cross-sectional view of some embodiments of a semiconductor transistor device, extending along line BB' of Fig. 5 is drawn. Fig. 6C shows a cross-sectional view of some embodiments of a semiconductor transistor device extending along line CC' of Fig. 5 is drawn. Fig. 7 to Fig. Figure 27B shows various views of some embodiments of a method for forming a semiconductor transistor device having a rear-side power supply rail at various stages. Fig. 28 shows a flowchart of some embodiments of the method, which Fig. 7 to Fig. 27B corresponds. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.

[0006] As used here, "about," "approximately," "about," or "essentially" generally means within 20 percent, or within 10 percent, or within 5 percent of a given value or range. The numerical values ​​given here are approximate, which means that the use of the term "about," "approximately," "about," or "essentially" can be assumed unless explicitly stated.

[0007] Gate-all-around transistor (GAA) structures can be structured using any suitable method. For example, the structures can be structured using one or more photolithographic processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, smaller pitches than would otherwise be achievable using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithographic process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can be used to structure the GAA transistor structures. After forming the GAA transistor structures, an interconnect structure can be built over them, featuring power supply rails and signal lines located within in-line dielectric (ILD) layers.

[0008] As the semiconductor process shrinks further, for example beyond 3 nm, current power supply rail designs will feature complex metal-layer routing in the back-end-of-line (BEOL). This complex routing necessitates more masks and increases voltage drop (also known as IR drop) as metal wires become thinner.

[0009] In light of the foregoing, the present disclosure relates to a semiconductor transistor device having a rear-facing power supply rail and to a manufacturing process for it. By relocating the power supply rail from the front to the rear of the semiconductor transistor device, the metal layer routing in the BEOL is simplified. Therefore, fewer masks are required, the IR dropout is improved, and both the power supply rail area and the active region can be increased.

[0010] In particular, some embodiments of the present disclosure relate to a GAA device. The GAA device comprises: a channel structure, a gate structure enclosing the channel structure, a first epitaxial source / drain structure and a second epitaxial source / drain structure arranged at opposite ends of the channel structure, and a gate contact arranged on the gate structure. The GAA device further comprises: a rear source / drain contact landing on a recessed lower surface of the first epitaxial source / drain structure, and a rear power supply rail arranged beneath and contacting the rear source / drain contact. The rear source / drain contact and the rear power supply rail may, for example, be made of metallic materials.In some embodiments, a lower surface of the first epitaxial source / drain structure can be recessed to a position deeper than a lower surface of the gate or channel structure. Therefore, the cell capacity can be reduced.

[0011] In some embodiments, the rear source / drain contact is self-adjusting, formed by creating a rear sacrificial contact prior to the formation of the first epitaxial source / drain structure. The rear dummy contact is subsequently selectively removed and replaced by the rear source / drain contact, thus eliminating any overlay displacement of the contact landing.

[0012] In some additional embodiments, the GAA device further features a backside dielectric cover located beneath the gate structure and the second epitaxial source / drain structure. The backside dielectric cover can comprise an oxide, nitride, carbon nitride, or low-k dielectric material. The backside dielectric cover replaces an original semiconductor body material, thereby reducing cell capacitance and eliminating current leakage problems, such as leakage current between the gate structure and the backside source / drain contact.

[0013] Furthermore, the second epitaxial source / drain structure can have a recessed lower surface. The recessed lower surface of the second epitaxial source / drain structure can extend to a position that is vertically aligned with, or even deeper than, a lower surface of the gate structure. Therefore, the cell capacity can be further reduced.

[0014] The GAA devices presented here feature a p-GAA or an n-GAA configuration. Furthermore, the GAA devices may include one or more channel regions (e.g., semiconductor nanowires, nanodots, etc.) associated with a single, contiguous gate structure or multiple gate structures. An average person skilled in the art may recognize other examples of semiconductor transistor devices that could benefit from aspects of this disclosure. The GAA devices may be a section of an integrated circuit (IC) that includes static random-access memory (SRAM), logic circuits, passive components such as resistors, capacitors, and inductors, and / or active components such as...p-type field-effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), biopolar transistors, high-voltage transistors, high-frequency transistors, other memory cells and combinations thereof.

[0015] Fig. Figure 1 shows a cross-sectional view of a semiconductor transistor device 100 according to some embodiments. The semiconductor transistor device 100 exhibits a channel structure 102 and a gate structure 104 , which the canal structure 102 surrounds, on. The canal structure 102 can have a stack of semiconductor layers separated by a stack of metal components of the gate structure 104 are separated and surrounded by it. A first epitaxial source / drain structure. 10and a second epitaxial source / drain structure are located at opposite ends of the channel structure. 102 arranged. Inner spacers 128 are located on opposite ends of the metal components of the gate structure 104 arranged to form the gate structure 104 of the first and second epitaxial source / drain structure 106 , 108 to isolate. In some embodiments, gate spacers are used. 134 along opposite side walls of an upper section of the gate structure 104 arranged. The outer surfaces of the inner spacers 128 can be essentially coplanar with the outer surfaces of the channel structure 102 and / or the gatespacer 134 In some embodiments, an upper insulation structure is used. 220 in trenches between the gatespacers 134 arranged. The upper insulation structure 220 provides electrical isolation between the gate structures 104ready. The channel structure can serve as an example. 102 They should be pure silicon layers, not doped with p- and n-type impurities. The thickness of the channel structure 102 The size can lie in a range between approximately 3 nm and approximately 15 nm. The gate structure can serve as an example. 104 A gate dielectric material, such as high-K materials (where K is greater than 7), an exit work metal material, and a filler metal material, such as tungsten or aluminum. The gate structure thickness 104 The diameter can lie in a range between approximately 2 nm and approximately 10 nm. In some embodiments, the first and second epitaxial source / drain structures exhibit a specific structure. 106 , 108 a semiconductor material, such as silicon, germanium, or silicon-germanium. The first and second epitaxial source / drain structures. 106 , 108They can have hexagonal or diamond-like shapes. In some embodiments, the first and second epitaxial source / drain structures exhibit a specific structure. 106 , 108 Different conductivity types are observed. For example, the first epitaxial source / drain structure can be 106 one epitaxial N-structure, and the second epitaxial source / drain structure 108 It can be an epitaxial P-structure, or vice versa. The first and second epitaxial source / drain structures 106 , 108 Each can be a source or a drain of the semiconductor transistor device 100 be.

[0016] On one front side of the semiconductor transistor device 100 can a front-end interconnect structure 114 above the gate structure 104 and the first and second epitaxial source / drain structures 106,108. The front-side interconnect structure 114can have multiple front metal layers 116 exhibiting a front-side dielectric intermediate layer 112 are arranged and surrounded by them. The front metal layers 116 They feature vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal traces. The front-side interconnect structure 114 Electrically connects different features or structures of the semiconductor transistor device. For example, a gate contact can 110 on the gate structure 104 arranged and connected to external circuits through the front metal layers 116 be connected.

[0017] On one rear side of the semiconductor transistor device 100 In some embodiments, a rear source / drain contact is used. 120 arranged in such a way that it lies beneath the first epitaxial source / drain structure 106lies and the first epitaxial source / drain structure 106 with a rear power supply rail 122 connects, which are located under the rear source / drain contact 120 lies. In some embodiments, a dielectric sidewall spacer is used. 118 along a side wall of the rear source / drain contact 120 arranged and separates the rear source / drain contact 120 from the rear dielectric cover 126 The rear source / drain contact 120 and the rear power supply rail 122 They may, for example, contain metal materials. For example, the rear source / drain contact may... 120 a metal, such as tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), or other suitable materials. Therefore, the first epitaxial source / drain structure can 106with external circuits from the back of the semiconductor transistor device 100 via the rear source / drain contact 120 They can be connected. This provides greater flexibility in the routing of the metal conductors and allows the cell capacity to be reduced.

[0018] Furthermore, the rear source / drain contact 120 on a recessed lower surface 106b the first epitaxial source / drain structure 106 can be placed. In some embodiments, the lower surface can be 106b the first epitaxial source / drain structure 106 as a convex shape that extends to a position vertically lower than a lower surface 104b the gate structure 104 .

[0019] Furthermore, in some embodiments, the rear of the semiconductor transistor device 100 a rear-side dielectric cover126 under the gate structure 104 arranged. The rear dielectric cover 126 It can also be located below the second epitaxial source / drain structure 108 extend. The rear dielectric cover 126 replaces an original semiconductor body material, helps to improve the gate structure 105 and the rear source / drain contact 120 to separate and isolate, thus reducing cell capacity and eliminating current leakage problems, such as leakage current between the gate structure 104 and the rear source / drain contact 120 The rear dielectric cover 126 may contain an oxide, a nitride, a carbon nitride, or low-k dielectric materials.

[0020] Fig. Figure 2 shows a cross-sectional view of a semiconductor transistor device 200, which has a rear-mounted power supply rail, according to some embodiments. In addition to features described with reference to Fig. 1 are disclosed, in some further embodiments the lower surface 106b the first epitaxial source / drain structure 106 even deeper recesses can be cut out to a position that is vertically beyond a lower surface 102b the canal structure 102 The cell capacity is compared to the semiconductor transistor device. 100 from Fig. 1 further reduced, whereby the lower surface 106b the first epitaxial source / drain structure 106 under the lowest part of the canal structure 102 is located.

[0021] Fig. Figure 3 shows a cross-sectional view of a semiconductor transistor device 300, which has a rear-mounted power supply rail, according to some embodiments. In addition to features described with reference to Fig. 1 and Fig. 2 disclosed, in some further embodiments a lower surface 108b the second epitaxial source / drain structure 108 up to a position that is at the same level as a lower surface 104b the gate structure 104 lies, be recessed and have a concave shape, as in Fig. 1 and Fig. 2 shown. The cell capacity can be compared with semiconductor transistor devices. 100 , 200 from Fig. 1, Fig. 2 will be further reduced.

[0022] Fig. Figure 4 shows a cross-sectional view of a semiconductor transistor device 400, which has a rear-mounted power supply rail, according to some embodiments. In addition to features disclosed above, in some further embodiments the lower surface can 108b the second epitaxial source / drain structure 108 to be recessed into a position that is vertically lower than the lower surface 104b the gate structure 104 , and the cell capacity can be compared with semiconductor transistor devices 100 , 200 , 300 from Fig. 1, Fig. 2, Fig. 3 more will be reduced.

[0023] Fig. Figure 5 shows a perspective view of the semiconductor transistor device 400 from Fig. 4 according to some embodiments. Fig. Figure 4 can be considered the cross-sectional view along the x-direction of Fig. 5 is drawn. Fig. 6A to Fig. 6C can be considered as the cross-sectional views that each extend along the y-direction into a gate region, a first source / drain region, and a second source / drain region of Fig. 5 are drawn. Alternatively, Fig. 4 to Fig. Figure 6C and the following figures may also be independent to show different embodiments, and features discussed that are associated with one figure may, if applicable, be included in another.

[0024] As in Fig. 5 to Fig. As shown in 6C, in some embodiments a lower insulation structure may be incorporated. 160 , a medium insulation structure 132 and a hard mask 136 together they act as an isolation structure, separating two semiconductor transistor devices 400a , 400b along the y-direction. As in Fig. As shown in 6A, in some embodiments it has a gate structure 104a gate dielectric layer 232 and a gate electrode 230 on. The gate electrode 230 It has one or more exit metal layers and a filler metal. The gate dielectric layer 232 can be designed in such a conformal manner that it forms the outer surfaces of the gate electrode 230 lines the gate dielectric layer. 232 can be used with the lower insulation structure 160 and a canal structure 102 are in contact. In some embodiments, the gate dielectric layer has 232 a high-x material (where κ is greater than 7), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), hafnium aluminum oxide (HfAlO2), hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3) or other suitable materials.

[0025] As in Fig. 5 and Fig. As shown in 6C, a first epitaxial source / drain structure can be seen. 106a lower surface that is recessed (e.g. convex), and a rear source / drain contact. 120 , which is electrically coupled to the recessed lower surface. As in Fig. 5, Fig. 6A and Fig. As shown in Figure 6B, a second epitaxial source / drain structure can be observed. 108 a lower surface that is recessed (e.g. convex), and a rear dielectric cover 126 , which are located directly below the second epitaxial source / drain structure 108 and the gate structure 104 is arranged, exhibit. The rear dielectric cover 126 can be done through the lower insulation structure 160 be surrounded. In some embodiments, air gaps may be present. 192 are formed in such a way that they form lower sections of the first epitaxial source / drain structure 106 and the second epitaxial source / drain structure 10 surrounded.

[0026] Fig. 7 to Fig. Figure 27B shows a method for fabricating a semiconductor transistor device at various stages according to some embodiments of the present disclosure. In some embodiments, the Fig. 7 to Fig. 27B, the semiconductor transistor device shown, may be an intermediate device or a section thereof manufactured during the processing of an integrated circuit (IC), which may include static random access memory (SRAM), logic circuits, passive components such as resistors, capacitors and inductors, and / or active components such as p-type field-effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), biopolar transistors, high-voltage transistors, high-frequency transistors, other memory cells and combinations thereof.

[0027] As in a perspective view of Fig. Figure 7 shows a stacked structure in some embodiments. 150 on a substrate 140 formed. In some embodiments, the substrate can 140 a part of a wafer and can comprise silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or other suitable semiconductor materials. In some embodiments, the substrate is 140 a SOI structure (semiconductor on an insulator) that forms a bulk substrate 142 , an insulating substrate layer 144 on the bulk substrate 142 and a semiconductor substrate layer 146 on the insulator substrate layer 144 exhibits. In various embodiments, the substrate can 140 exhibiting any number of different substrate structures and materials.

[0028] The stacked structure 150 exhibits first semiconductor layers152 and second semiconductor layers 154 on, which are stacked alternately. The first semiconductor layers 152 will serve as channel regions of the semiconductor transistor device, and the second semiconductor layers 154 These are sacrificial layers that are subsequently removed and replaced by a gate material. The first semiconductor layers 152 and the second semiconductor layers 154 are manufactured as materials exhibiting different lattice constants and can comprise one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the first semiconductor layers 152 and the second semiconductor layers 154 Made from Si, a Si composition, SiGe, Ge, or a Ge composition. The stacked structure 150 can be applied to the substrate 140They are formed using epitaxy, so that the stacked structure 150 forms crystal layers. Although Fig. 7 four layers of the first semiconductor layer 152 and three layers of the second semiconductor layer 154 As shown, the number of layers is not limited in this way and can be as small as 1 for each layer. In some embodiments, 2 to 10 layers of each of the first and second semiconductor layers are formed. By adjusting the number of stacked layers, the drive current of the semiconductor transistor device can be set.

[0029] In some embodiments, the first semiconductor layers can 152 They should be pure silicon layers, free of germanium. The first semiconductor layers 152They can also be essentially pure silicon layers, for example with a germanium atom percentage of less than approximately 1 percent. Furthermore, the first semiconductor layers can 152 They must be intrinsic, meaning they are not doped with p- and n-type impurities. In some embodiments, the thickness of the first semiconductor layers is [missing information]. 152 in a range between approximately 3 nm and approximately 15 nm.

[0030] In some embodiments, the second semiconductor layers can 154 These are SiGe layers that have a germanium atom percentage greater than zero. In some embodiments, the germanium percentage of the second semiconductor layers is... 154 in a range between approximately 10 percent and approximately 50 percent. In some embodiments, the thickness of the second semiconductor layers is 154 in a range between approximately 2 nm and approximately 10 nm.

[0031] As in a perspective view of Fig. As shown in Figure 8, in some embodiments the stacked structure 150 (see Fig. 7) structured to create fin structures 156 and ditches 158 to form structures that extend in the X direction. In some embodiments, the stacked structure 150 through an etching process that creates a structured mask layer 157 used as an etching mask, structured so that sections of the stacked structure 150 , which do not match the mask layer 157 are covered, and must be removed. The semiconductor substrate layer 146 The mask layer can also be partially or completely removed during this process. 17The system can have a first mask layer and a second mask layer. The first mask layer can be a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The second mask layer can be made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low-pressure kinetic plasma-assisted vapor deposition (LPCVD) and plasma-enhanced kinetic plasma-assisted vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable process. 157 can be structured using a variety of different structuring techniques. Fig. Figure 8 shows two fin structures 156The fin structures are arranged in the Y-direction and parallel to each other, but the number of fin structures is not limited and can be as small as one, three, or more. In some embodiments, one or more dummy fin structures are placed on both sides of the main fin structures. 156 trained to improve structural accuracy in structuring processes.

[0032] As in a perspective view of Fig. As shown in Figure 9, in some embodiments a lower insulation structure is used. 160 above the insulator substrate layer 144 in the lower sections of the trenches 158 formed, which is also referred to as an STI structure (shallow trench isolation). Upper sections of the fin structures 156 are from the lower insulation structure 160 exposed. The lower insulation structure 160can be formed by placing an insulating material over the insulator substrate layer 144 The insulation material is then removed to form the lower insulation layer. 160 to develop, so that the upper sections of the fin structures 156 The insulating material can be a dielectric material, such as a nitride (e.g., silicon nitride, silicon oxynitride, silicon oxygen-carbon nitride), a carbide (e.g., silicon carbide, silicon oxygen carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), a low-κ dielectric material with a dielectric constant of less than 7 (e.g., a carbon-doped oxide, SiCOH), or the like. In some embodiments, the lower insulating structures are 160formed by means of various steps that include a thermal oxidation or deposition process (e.g. physical vapor deposition (PVD), chemical vapor deposition (CVD), PECVD, atomic layer deposition (ALD), sputtering, etc.) and removal processes (e.g. wet etching, dry etching, chemical-mechanical planarization (CMP), etc.).

[0033] As in a perspective view of Fig. As shown in 10, a semiconductor cladding layer is used. 161 about the outer surfaces of the fin structures 156 formed. In some embodiments, the semiconductor cladding layer has 161 a semiconductor material, such as germanium, silicon germanium, or the like. In some embodiments, the semiconductor cladding layer has 161 the same material as the second semiconductor layers 154 Furthermore, in some embodiments, the semiconductor cladding layer can161 formed using an epitaxial growth process or a deposition process (e.g. PVD, CVD, PE-CVD, ALD, sputtering, etc.).

[0034] As in a perspective view of Fig. As shown in 11, in some embodiments a middle insulation structure is used. 132 above the lower insulation structure 160 between the fin structures 156 trained. A dielectric liner 130 can be used to distinguish between the middle insulation structure 132 and the lower insulation structure 10 along the sidewalls of the semiconductor cladding layer 161 and the lower insulation structure 160 be trained. A hard mask 136 can then be placed on the upper side of the middle insulation structure 132 and the dielectric liner 130 be formed. The medium insulation structure 132 and the dielectric liner 130They provide electrical insulation between the fin structures. 156 ready, and the hard mask 136 prevents a loss of the middle insulation structure 132 during future structuring steps.

[0035] In some embodiments, the dielectric liner 130 , the middle insulation structure 132 and the hard mask 136 Formed by deposition (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.) and removal processes (e.g., etching, chemical-mechanical planarization (CMP), etc.). The middle insulation structure 132 can an upper surface be found beneath that of the fin structures? 156 exhibit. In some, not in Fig. In the embodiments shown in 11, the planarization process of the hard mask can be described. 126 including the semiconductor cladding layer 161 from above the fin structures 156 remove the hard mask 136may have an upper surface that is similar to that of the fin structures 156 It is coplanar. In some embodiments, the dielectric liner can 130 and the middle insulation structure 132 and the lower insulation structures 160 Each component comprises a low-κ dielectric material with a dielectric constant of less than 7, such as silicon oxynitride, silicon carbon nitride, silicon oxygen carbide, silicon oxygen-carbon nitride, silicon nitride, or another suitable low-κ dielectric material. The dielectric liner 130 For selective removal processes, it may have a different material than the average insulation structure. 132 The hard mask 136may have a high-κ dielectric material with a dielectric constant greater than 7, such as hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide or another suitable high-κ dielectric material.

[0036] As in the perspective view of Fig. As shown in 12, the hard mask 136 in some embodiments from the top of the fin structures 156 selectively removed. Upper surfaces of the first semiconductor layer 152 and the semiconductor cladding layer 161 can be exposed during the removal process. In some embodiments, the hard mask 136 for example, selectively etched by a dry etching process and / or a wet etching process.

[0037] As in the perspective view of Fig. Figure 13 shows that dummy gate structures are used in some embodiments. 170 above the fin structures156 along the γ-direction such that they are spaced apart from each other in the x-direction. In some embodiments, the dummy gate structures can 170 a sacrificial gated dielectric layer 162 , a sacrificial gate electrode layer 164 , a pad layer 166 and a layer of masks 168 exhibiting, one of which is stacked on top of the other in the aforementioned order. Although two dummy gate structures 170 in Fig. The number of dummy gate structures shown is 13. 170 not limited to this and can be more or less than two. In some embodiments, the sacrificial gated dielectric layer can 162 For example, they may contain a dielectric material, such as a nitride (silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), or another suitable material. The sacrificial gate electrode layer 164It may, for example, contain polysilicon. The pad layer 166 and the mask layer 168 They may contain thermal oxide, nitride and / or other hard mask materials and are formed using photolithographic processes.

[0038] Gatespacers are then used. 134 along opposite side walls of the dummy gate structures 170 Formed. For example, a full-surface layer of insulating material for sidewall spacers is formed using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), subatmospheric chemical vapor deposition (SACVD), or the like, in such a way that it conforms to the dummy gate structures. 170The covering layer is deposited in a conformal manner, so that it is formed in such a way that it has essentially the same thickness on vertical surfaces, such as the side walls, horizontal surfaces and the top of the dummy gate structures. 170 In some embodiments, the insulating material of the area layer can be a silicon nitride-based material. The area layer is then etched using an anisotropic process to create the gate spacers. 134 on opposite side walls of the dummy gate structures 170 to train.

[0039] As in the perspective view of Fig. 14A, the cross-sectional view in the x-direction of Fig. 14B, the cross-sectional view in the y-direction of Fig. 14C in a gate area and the cross-sectional view in the y-direction of Fig. In 14D representations in a source region or a drain region, a removal process is carried out in some embodiments to remove fin structures. 156 from a first source / drainage area 176 and a second source / drainage area 178 according to the dummy gate structures 170 to remove. Consequently, the first semiconductor layers are removed. 152 and the second semiconductor layers 154 shortened along the x-direction and can be vertically attached to the gate spacers 145 to be aligned. As an example, the exposed sections of the fin structures will be shown. 156removed using an SSD (strained source / drain) etching process. The SSD etching process can be carried out in various ways. In some embodiments, the SSD etching process can be carried out by chemical dry etching with a plasma source and a reaction gas. The plasma source can be inductively coupled plasma (ICR) etching, transformer-coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion (RIE) etching, or the like, and the reaction gas can be a fluorine-based gas, chloride (Cl2), hydrogen bromide (HBr), oxygen ( O2), the like, or combinations thereof. In some other embodiments, the SSD etching process can be carried out by a chemical wet etching, such as with ammonium peroxide mixture (APM), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), combinations thereof, or the like. In still other embodiments, the SSD etching step can be carried out by a combination of chemical dry etching and chemical wet etching. Furthermore, in some embodiments, the removal process can also involve the removal of an upper portion of the semiconductor substrate layer. 146 between the dummy gate structures 170 after removing the lowest first semiconductor layer 152 remove. The semiconductor substrate layer 146 or the lowest first semiconductor layer 152 A concave upper surface can occur along the x-direction in the first source / drain region. 176 and the second source / drainage area 178exhibit. The upper surface can be located between the lower insulation structure. 160 be omitted.

[0040] Furthermore, the removal process can also include an isotropic etchant to remove end sections of the second semiconductor layers. 154 among the gatespacers 134 and / or the dummy gate structures 170 to remove further. Therefore, after the removal process, the first semiconductor layers are 152 wider in the x-direction than the second semiconductor layers 154 The first semiconductor layers 152 can be formed as the channel structure of the transistor device after the removal process. It is understood that the channel structure can have stacked rectangular shapes, as shown in the cross-sectional view of Fig. 14B and other figures, while in other embodiments the channel structure may have other shapes, such as circles, octagons, ovals, diamonds or the like.

[0041] As in the perspective view of Fig. 15A and the cross-sectional view in the x-direction of Fig. As shown in 15B, in some embodiments inner spacers are used. 128 at the ends, in the x-direction, of the second semiconductor layers 154 , which have outer walls. The outermost side walls of the inner spacers. 128 can be essentially coplanar with the outer surfaces of the first semiconductor layers 152 and / or the gatespacer 134 be. In some embodiments, the inner spacers 128The layer is formed by a deposition process (e.g., CVD, PCV, PE-CVD, ALD, sputtering, etc.), which may be followed by a selective removal process (e.g., etching). For example, in some embodiments, a continuous layer can first be deposited along sidewalls and over the dummy gate structures. 170 They are formed. Then a vertical etching process can be carried out to remove sections of the continuous layer that are not vertically aligned with the gate spacers. 134 are covered, to remove in order to access the inner spacers 128 to form. Furthermore, in some embodiments, the inner spacers 128 a low-κ dielectric material (e.g., the dielectric constant is less than 7), such as silicon oxynitride, silicon carbon nitride, silicon oxygen carbide, silicon oxygen-carbon nitride, silicon nitride, or another suitable material.

[0042] As in the perspective view of Fig. 16A, the cross-sectional view in the x-direction of Fig. 16B and the cross-sectional view in the y-direction of Fig. 16C is shown in the first source / drain region; in some embodiments, a first sacrificial source / drain contact is shown. 180 below the first source / drain area 176 formed, with a hard mask layer 182 the second source / drainage area 178 covers. In some embodiments, a trench is formed by first covering a section of the first semiconductor layer. 152 and / or the semiconductor substrate layer 146 directly below the first source / drain area 176 It is etched. Then sacrificial material is poured into the trench to establish the initial sacrificial source / drain contact. 180 to form. In some embodiments, the first sacrificial source / drain contact can 180a SiGe material containing a germanium atom percentage greater than zero. In some embodiments, the germanium percentage of the first sacrificial source / drain contact is 180 in a range between approximately 10 percent and approximately 50 percent. In some embodiments, the first sacrificial source / drain contact exhibits 180 the same material as the second semiconductor layers 154 Furthermore, in some embodiments, the first sacrificial source / drain contact can be 180 They are formed using an epitaxial growth process or a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). This is achieved by forming the trench and the initial victim-source / drain contact. 180 In this way, a source / drain contact can later be self-adjusting, by the first victim source / drain contact 180 is replaced, thus eliminating any overlay shifting of a contact landing.

[0043] As in the perspective view of Fig. 17A, the cross-sectional view in the x-direction of Fig. 17B, ​​the cross-sectional view in the y-direction of Fig. 17C in the first source / drain area and the cross-sectional view in the y-direction of Fig. In 17D, the second source / drain region is shown; in some embodiments, a first epitaxial source / drain structure is shown. 106 and a second epitaxial source / drain structure 108 on opposite sides of the dummy gate structure 180 trained (see Fig. 17B). In some embodiments, the first and second epitaxial source / drain structures can be 106 , 108 ends of the first semiconductor layer 152 Contact us directly. The first epitaxial source / drain structure 106 can occur on the first victim source / drain contact 180 be trained (see Fig. 17C). The second epitaxial source / drain structure 108 can be located on the lowest first semiconductor layer 152 or the semiconductor substrate layer 146 be trained (see Fig. 17D). The first and second epitaxial source / drain structures 106, 108 can each be a source and a drain, respectively, of the semiconductor transistor device. In some embodiments, the first and second epitaxial source / drain structures have 106 , 108 a semiconductor material. For example, the first and second epitaxial source / drain structures can comprise silicon, germanium, or silicon-germanium. In some embodiments, the first and second epitaxial source / drain structures are 106 , 108 formed by means of an epitaxial growth process. The first and second epitaxial source / drain structures 106,108 can have hexagonal or diamond-like shapes. Air gaps192 can be formed in such a way that they form lower sections of the first epitaxial source / drain structure 106 and the second epitaxial source / drain structure 10 surrounded.

[0044] As in the perspective view of Fig. 18A, the cross-sectional view in the x-direction of Fig. 18B, the cross-sectional view in the y-direction of Fig. 18C in the first source / drain area and the cross-sectional view in the y-direction of Fig. In 18D, shown in the second source / drain region, an upper insulation structure is used in some embodiments. 220 formed above the previously formed structure, which constitutes the first and second epitaxial source / drain structure 106 , 108 covers. A planarization process is then carried out to cover the gatespacers. 134 to lower, and the sacrificial gated dielectric layer 162 and the sacrificial gate electrode layer 164to expose on the same horizontal plane. Although not shown in the figure, an etch stop liner lining the previously formed structure can be applied before the upper isolation structure is formed. 220 conformal. The etch-stop liner can be subjected to tensile stress and can be formed from Si3N4. In some other embodiments, the etch-stop liner comprises materials such as oxynitrides. In still other embodiments, the etch-stop liner can have a composite structure comprising several layers, such as a silicon nitride layer over a silicon oxide layer. The etch-stop liner can be formed using plasma-enhanced electrochemical vapor deposition (PECVD), but other suitable methods, such as low-pressure electrochemical vapor deposition (LPCVD), atomic layer deposition (ALD), and the like, can also be used. The upper insulation structure 220It can be formed using chemical vapor deposition (CVD), high-density plasma CVD, spin-on deposition, sputtering, or other suitable methods. In some embodiments, the upper insulation structure has 220 Silicon oxide. In some other embodiments, the upper insulating structure 220 Silicon oxynitride, silicon nitride, compositions containing Si, O, C and / or H (e.g., silicon dioxide, SiCOH and SiOC), low-κ materials, or organic materials (e.g., polymers). The planarization process may involve a chemical-mechanical process (CMP).

[0045] As in the perspective view of Fig. 19A, the cross-sectional view in the x-direction of Fig. 19B, the cross-sectional view in the y-direction of Fig. In some embodiments, a gate exchange process is carried out to create a gate structure, as shown in 19C in the gate area. 104to train. The sacrificial gated dielectric layer 162 and the sacrificial gate electrode layer 164 are removed, thereby removing the first and second semiconductor layers 152 , 154 be exposed. The upper insulation structure 220 protects the first and second epitaxial source / drain structure 106 , 108 during the removal of the sacrificial gated dielectric layer 162 and the sacrificial gate electrode layer 164 The sacrificial gate electrode layer 164 can be removed using plasma dry etching and / or wet etching. If the sacrificial gate electrode layer 164 Polysilicon is and the upper insulation structure 220 If silicon oxide is present, a wet etchant, such as a TMAH solution, can be used to remove the sacrificial gate electrode layer. 164 to selectively remove the sacrificial gate electrode layer. 164It can be removed using plasma dry etching and / or wet etching. The sacrificial gated dielectric layer is then removed. 162 also removed. Therefore, the first and second semiconductor layers are removed. 152 , 154 exposed.

[0046] The second semiconductor layers 154 and the semiconductor cladding layer 161 (see Fig. 14C) are then removed or etched using an etchant that removes the second semiconductor layers 154 and the semiconductor cladding layer 161 with a faster etching rate than the etching of the first semiconductor layers 152 It can selectively etch. The inner spacers 128 They protect the first and second epitaxial source / drain structures 106 , 108 before the etching agent used in the etching of the second semiconductor layers 154 and the semiconductor cladding layer 161is used because the inner spacers 128 are formed from a material that exhibits an etch selectivity compared to that of the second semiconductor layers 154 and the semiconductor cladding layer 161 exhibits.

[0047] A gate structure 104 then between the gate spacers 134 and the inner spacers 128 trained and / or filled. That is, the gate structure 104 orbits (or surrounds or encloses) the first semiconductor layers 152 , in which the first semiconductor layers 152 These are referred to as channels of the semiconductor transistor device. The gate spacers 134 are located on opposite sides of the gate structure 104 arranged. The gate structure 104 has a gate dielectric layer 232 and a gate electrode 230 on. The gate electrode 230It has one or more exit metal layers and a filler metal. The gate dielectric layer 232 can be formed conformally. That is, the gate dielectric layer 232 stands with the lower insulation structure 160 and the first semiconductor layers 152 in contact. In some embodiments, the gate dielectric layer has 232 a high-κ material (where κ is greater than 7), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), hafnium aluminum oxide (HfAlO2), hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), or other suitable materials. In some embodiments, the gate dielectric layer may be 232 be trained by performing an ALD process or another suitable process.

[0048] The exit metal layer of the gate electrode 230 is applied to the gate dielectric layer 232formed, and in some embodiments the exit metal layer surrounds the first semiconductor layers 152 The exit work metal layer can comprise materials such as titanium nitride (TiN), tantalum nitride (TaN), titanium-aluminum-silicon (TiAlSi), titanium-silicon nitride (TiSiN), titanium-aluminum (TiAl), tantalum-aluminum (TaAl), or other suitable materials. In some embodiments, the exit work metal layer can be formed by performing an ALD process or another suitable process. The gate electrode filler metal 230 fills the remaining space between the gatespacers 134 and between the inner spacers 128 This means that the exit work metal layer(s) is / are in contact with the gate dielectric layer. 232and the filler metal and is located in between. The filler metal can be a material such as tungsten or aluminum. After the deposition of the gate dielectric layer 232 and the gate electrode 230 A planarization process, such as a CMP process, can then be performed to remove excess sections of the gate dielectric layer. 232 and to remove the gate electrode to modify the gate structure 104 to train.

[0049] In some embodiments, an interface layer (not shown) is optionally formed before the gate structure is created. 104 designed in such a way that they expose areas of the first semiconductor layers 152 and exposed areas of the semiconductor substrate layer 146surrounds. In various embodiments, the interface layer can comprise a dielectric material, such as silicon oxide (SiO2) or silicon oxynitride (SiON), and can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD) and / or other suitable processes.

[0050] As in the perspective view of Fig. Figure 20 shows that in some embodiments a front-side interconnect structure is used. 114 above the gate structure 104 and the first and second epitaxial source / drain structure 106 , 108 trained. The front-side interconnect structure 114 can have multiple front metal layers 116 exhibiting a front-side dielectric intermediate layer 112 are arranged and surrounded by them. The front-side interconnect structure 114electrically connects different features or structures (e.g., a gate contact). 110 and / or other contacts) of the semiconductor transistor device. The front-side metal layers 116 They feature vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal conductors. The various interconnect features can implement different conductive materials, including copper, tungsten, and silicide. In one example, a Damascene process is used to form a copper multilayer interconnect structure. Subsequently, a support substrate is applied. 240 above the front-side interconnect structure 114 trained. For example, the carrier substrate is 240 to the front-side interconnect structure 114 bonded. In some embodiments, the carrier substrate is 240 Sapphire. In some other embodiments, the support substrate is 240Silicon, a thermoplastic polymer, an oxide, a carbide or another suitable material.

[0051] As in the perspective view of Fig. As shown in Figure 21, in some embodiments the workpiece is “turned around” and thinned to create the first sacrificial source / drain contact. 180 and the semiconductor substrate layer 146 from one side to thin. The bulk substrate 142 , the insulator substrate layer 144 and at least one upper section of the lower insulation structure 160 are removed. The bulk substrate 142 and the lower insulation structure 160 can be removed in several process steps, for example by first removing the bulk substrate 142 is removed, whereupon the lower insulation structure is removed. 160 This follows. In some embodiments, the removal processes include the removal of the bulk substrate. 142 and the lower insulation structure150 for example using a CMP, an HNA and / or a TMAH etching process.

[0052] As in the perspective view of Fig. 22A, the cross-sectional view in the x-direction of Fig. 22B and the cross-sectional view in the y-direction of Fig. 22C is shown in the first source / drain region; in some embodiments, the first sacrificial source / drain contact is shown. 180 removed, and the underlying first epitaxial source / drain structure 106 The rear side is left out to create a rear source / drain contact trench. 234 to form, which is located in an upper section of the first epitaxial source / drain structure 106 is omitted. The first epitaxial source / drain structure 106 can be masked or etched using an etching agent that reveals the first epitaxial source / drain structure 106selectively etching with a faster etch rate than etching surrounding dielectric materials.

[0053] As in the perspective view of Fig. 23A, the cross-sectional view in the x-direction of Fig. 23B and the cross-sectional view in the y-direction of Fig. 23C is shown in the first source / drain region; in some embodiments, a second sacrificial source / drain contact is shown. 236 into the rear source / drain contact trench 234 filled. In some embodiments, the second sacrificial source / drain contact is 236 formed by placing a dielectric material, such as silicon nitride, in the rear source / drain contact groove 234 is separated, followed by a planarization process to remove excess sections, so that the second victim source / drain contact 236 coplanar with the lower insulation structure 160 and the semiconductor substrate layer 146may be.

[0054] As in the perspective view of Fig. 24A, the cross-sectional view in the x-direction of Fig. 24B and the cross-sectional view in the y-direction of Fig. 24C is shown in the second source / drain region; in some embodiments, the semiconductor substrate layer 146 removed to cover the back 238 above the second epitaxial source / drain structure 108 and the gate structure 104 to form. The underlying second epitaxial source / drain structure 108 and the gate structure 104 can be exposed. In some embodiments, the second epitaxial source / drain structure is 108 from the back side, which is located in an upper section of the second epitaxial source / drain structure 108 is omitted.

[0055] As in the perspective view of Fig. 25A, the cross-sectional view in the x-direction of Fig. 25B, the cross-sectional view in the y-direction of Fig. 25C in the gate area and the cross-sectional view in the y-direction of Fig. 25D shown in the second source / drain region, in some embodiments a rear dielectric cover is used. 126 in the rear cover trenches 238 trained (see Fig. 24A). The rear dielectric cover 126 can be placed directly above the second epitaxial source / drain structure 108 and the gate structure 104 be trained. The rear dielectric cover 126 can be formed, for example, using a deposition process to create a dielectric material in the rear cover trenches. 226 to separate, followed by a CMP process to remove excess dielectric material outside the rear cover trenches. 238to remove. In some embodiments, the rear dielectric cover has 126 a dielectric material that is connected to the second sacrificial source / drain contact 236 The material used varies, for example, silicon dioxide. Other suitable materials may include SiO2, SiN, SiCN, SiOCN, Al2O3, AION, ZrO2, HfO2, combinations thereof, or the like. In some embodiments, the rear dielectric cover has... 126 a convex upper surface 126s at an interface between the rear dielectric cover 126 and the second epitaxial source / drain structure 108 on.

[0056] As in the perspective view of Fig. 26A, the cross-sectional view in the x-direction of Fig. 26B and the cross-sectional view in the y-direction of Fig. 26C is shown in the first source / drain region; in some embodiments, a rear source / drain contact is provided. 120in at least one section of the rear source / drain contact trench 234 trained to make the second victim-source / drain contact 236 replaced (see Fig. 23A). In some embodiments, an outer section of the second sacrificial source / drain contact is 236 in the rear source / drain contact trench 234 as a dielectric sidewall spacer 118 leave the rear source / drain contact 120 from the rear dielectric cover 126 separates. The rear source / drain contact 120 extends to a recessed lower surface 106b the first epitaxial source / drain structure 106 The lower surface 106b can be omitted during previous steps, for example by Fig. 22A to Fig. 22C shown. In some embodiments, before the rear source / drain contact is formed, 120a back-side metal alloy layer on the first epitaxial source / drain structure 106 The backside metal alloy layer can be a silicide layer formed by means of a self-adjusting silicide process. The backside metal alloy layer can comprise a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel-platinum silicide, erbium silicide, palladium silicide, cobalt, or other suitable materials. In some embodiments, the backside metal alloy layer can include germanium. In some embodiments, the backside source / drain contact can be 120 They can be made from metals such as tungsten, cobalt, rubric, aluminum, copper, or other suitable materials. After deposition of the back-side source / drain contact. 120A planarization process, such as a chemical-mechanical planarization process (CMP process), can then be carried out. In some embodiments, a barrier layer can be placed in the backside source / drain contact trench. 234 before forming the rear source / drain contact 120 The barrier layer can be made from TiN, TaN, or combinations thereof.

[0057] As in the perspective view of Fig. 27A and the cross-sectional view in the x-direction of Fig. As shown in 27B, in some embodiments a rear power supply rail is used. 122 and a rear-side interconnect structure 124 designed in such a way that they are connected to the rear source / drain contact 120 are electrically coupled.

[0058] Fig. 28 shows a flowchart of some embodiments of a process 2800to form an integrated chip that has multiple transistor devices with a high device density due to air spacer structures and high-κ dielectric spacer structures.

[0059] Although the procedure 2800 Where the following is illustrated and described as a series of processes or events, it is understood that the presented sequence of such processes or events should not be interpreted as restrictive. In addition to those illustrated and / or described here, some processes may, for example, occur in other sequences and / or simultaneously with other processes or events. Furthermore, processes not illustrated may be necessary to implement one or more aspects or embodiments of this description. Finally, one or more of the processes described here may be carried out in one or more separate processes and / or phases.

[0060] During the process 2802 Several fin structures are formed from stacked first and second semiconductor layers on a substrate. An insulating structure is formed between the fin structures (see e.g. Fig. 7 to Fig. 12). Fig. 7 to Fig. Figure 12 shows the perspective views of some embodiments that illustrate the process 2802 are equivalent to.

[0061] During the process 2804 Several dummy gate structures are formed, which lie above the fin structures. Fig. Figure 13 shows the perspective view of some embodiments that illustrate the process 2804 are equivalent to.

[0062] During the process 2806Sections of the fin structures not covered by the dummy gate structures are etched and removed from opposite sides of the dummy gate structure. The second semiconductor layers are horizontally recessed from the first semiconductor layers. Fig. 14A to Fig. Figure 14C shows the different views of some embodiments that describe the process 2806 are equivalent to.

[0063] During the process 2808 Inner spacers are formed at opposite ends of the second semiconductor layers. Fig. Figures 15A-15B show different views of some embodiments that describe the process 2808 are equivalent to.

[0064] During the process 2810 A first dummy back contact is formed in the substrate. Fig. 16A to Fig. Figure 16C shows the different views of some embodiments that describe the process 2810 are equivalent to.

[0065] During the process 2812A first and a second epitaxial source / drain structure are formed on opposite sides of the recessed fin structure. Fig. Figures 17A to 170 show the different views of some embodiments that describe the process. 2812 are equivalent to.

[0066] During the process 2814 The second semiconductor layers are replaced by a metal gate structure. Fig. 18A to Fig. Figure 19C shows the different views of some embodiments of the process 2814 are equivalent to.

[0067] During the process 2816 A gate contact and a front-side interconnect structure are formed. Fig. Figure 20 shows the perspective view of some embodiments that illustrate the process 2816 are equivalent to.

[0068] During the process 2818 A lower surface of the first epitaxial source / drain structure is left out. Fig. 21 to Fig. 22C show the different views of some embodiments that describe the process 2818 are equivalent to.

[0069] During the process 2820 A second dummy rear contact is formed, extending onto the recessed lower surface of the first epitaxial source / drain structure. Fig. 23A to Fig. 23C show the different views of some embodiments that describe the process 2820 are equivalent to.

[0070] During the process 2822 A lower surface of the second epitaxial source / drain structure is left out. Fig. 24A to Fig. 24D shows the different views of some embodiments that describe the process. 2822 are equivalent to.

[0071] During the process 2824 A rearward dielectric cover is formed on the lower surface of the second epitaxial source / drain structure. Fig. 25A to Fig. 25D show the different views of some embodiments that describe the process 2824 are equivalent to.

[0072] During the process 2826 A rear source / drain contact is formed, extending to a lower surface of the first epitaxial source / drain structure. Fig. 26A to Fig. 26C show the different views of some embodiments that describe the process 2826 are equivalent to.

[0073] During the process 2828 A rear power supply rail and a rear interconnect structure are formed. Fig. Figures 27A-27B show the different views of some embodiments that describe the process 2828 are equivalent to.

[0074] Accordingly, in some embodiments, the present disclosure relates to a semiconductor transistor device. The semiconductor transistor device comprises a channel structure and a gate structure enclosing the channel structure. The semiconductor transistor device further comprises a first epitaxial source / drain structure and a second epitaxial source / drain structure arranged at opposite ends of the channel structure, and a rear-side source / drain contact located beneath the first epitaxial source / drain structure. The first epitaxial source / drain structure has a concave lower surface that contacts the rear-side source / drain contact. The semiconductor transistor device further comprises a gate contact located on the gate structure.

[0075] In other embodiments, the present disclosure relates to a semiconductor transistor device. The semiconductor transistor device comprises a channel structure and a gate structure enclosing the channel structure. The semiconductor transistor device further comprises a first epitaxial source / drain structure and a second epitaxial source / drain structure arranged at opposite ends of the channel structure, and a rear-side source / drain contact located beneath and contacting the first epitaxial source / drain structure. The semiconductor transistor device further comprises a gate contact located on the gate structure and a rear-side dielectric cover located beneath and contacting the second epitaxial source / drain structure and the gate structure.

[0076] In some other embodiments, the present disclosure relates to a method for fabricating a semiconductor transistor device. The method comprises: forming a fin structure over a substrate by alternately stacking first and second semiconductor layers, and forming a dummy gate structure over the fin structure. The method further comprises: removing a portion of the fin structure exposed by the dummy gate structure, and forming inner spacers on opposite sides of the remaining portions of the first semiconductor layers. The method further comprises forming a first epitaxial source / drain structure and a second epitaxial source / drain structure at opposite ends of the fin structure. The method further comprises replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.The process further comprises removing the substrate and forming a backside cover trench to expose a lower surface of the metal gate structure and a lower surface of the second epitaxial source / drain structure. The lower surface of the second epitaxial source / drain structure is recessed. The process further comprises forming a backside dielectric cover in the backside cover trench and forming a backside source / drain contact beneath and contacting the first epitaxial source / drain structure.

[0077] The foregoing outlines features of several embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure.

Claims

[1] Semiconductor transistor device comprising: a canal structure, a gate structure that encloses the channel structure, a first epitaxial source / drain structure and a second epitaxial source / drain structure located at opposite ends of the channel structure, a gate contact that is arranged on the gate structure, and a rearward source / drain contact located beneath the first epitaxial source / drain structure, wherein the first epitaxial source / drain structure has a concave lower surface that contacts the rear source / drain contact. [2] Semiconductor transistor device according to claim 1, further comprising a rear dielectric cover arranged under the second epitaxial source / drain structure and in direct contact with it. [3] Semiconductor transistor device according to claim 2, wherein the second epitaxial source / drain structure has a concave lower surface that contacts the rear dielectric cover. [4] Semiconductor transistor device according to claim 2 or 3, wherein the rear dielectric cover extends below the gate structure. [5] Semiconductor transistor device according to one of claims 2 to 4, wherein the rear dielectric cover directly contacts the gate structure. [6] Semiconductor transistor device according to one of claims 2 to 5, further comprising a middle insulation structure surrounding the gate structure, the first epitaxial source / drain structure and the second epitaxial source / drain structure. [7] Semiconductor transistor device according to claim 6, further comprising a lower insulation structure arranged below the middle insulation structure and surrounding the rear dielectric cover. [8] Semiconductor transistor device according to one of the preceding claims, further comprising a dielectric sidewall spacer arranged along a sidewall of the rear source / drain contact. [9] Semiconductor transistor device according to one of the preceding claims, further comprising an inner spacer separating the gate structure from the first epitaxial source / drain structure and the second epitaxial source / drain structure. [10] Semiconductor transistor device according to one of the preceding claims, wherein the channel structure comprises a stack of semiconductor nanowires. [11] Semiconductor transistor device comprising: a canal structure, a gate structure that encloses the channel structure, a first epitaxial source / drain structure and a second epitaxial source / drain structure located at opposite ends of the channel structure, a gate contact that is arranged on the gate structure, and a rearward source / drain contact that is located below and contacts the first epitaxial source / drain structure, and a rear-side dielectric cover that is positioned beneath and contacts the second epitaxial source / drain structure and the gate structure. [12] Semiconductor transistor device according to claim 11, wherein the second epitaxial source / drain structure has a lower surface that is positioned higher than a lower surface of the gate structure. [13] Semiconductor transistor device according to claim 11 or 12, wherein the rear source / drain contact has an upper surface which is arranged higher than a lower surface of the gate structure. [14] Semiconductor transistor device according to one of claims 11 to 13, further comprising a dielectric side wall spacer arranged between the rear source / drain contact and the rear dielectric cover. [15] Semiconductor transistor device according to one of claims 11 to 14, wherein the gate structure comprises: a gate electrode, and a gate dielectric between the gate electrode and the channel structure. [16] Semiconductor transistor device according to one of claims 11 to 15, wherein the channel structure comprises a stack of semiconductor nanowires. [17] Semiconductor transistor device according to one of claims 11 to 16, further comprising an inner spacer separating the gate structure from the first epitaxial source / drain structure and the second epitaxial source / drain structure. [18] Semiconductor transistor device according to any one of claims 11 to 17, wherein the rear dielectric cover comprises SiO2, SiN, SiCN, SiOCN, Al2O3, AlON, ZrO2, HfO2 or combinations thereof. [19] Method for forming a semiconductor transistor device, the method comprising: Forming a fin structure over a substrate by alternately stacking first semiconductor layers and second semiconductor layers, Forming a dummy gate structure over the fin structure, Removing a section of the fin structure that is not covered by the dummy gate structure, Formation of inner spacers on opposite sides of remaining sections of the first semiconductor layers, Formation of a first epitaxial source / drain structure and a second epitaxial source / drain structure at opposite ends of the fin structure, Replacing the dummy gate structure and the first semiconductor layers with a metal gate structure, Removing the substrate and forming a backside cover trench to expose a lower surface of the metal gate structure and a lower surface of the second epitaxial source / drain structure, leaving the lower surface of the second epitaxial source / drain structure untouched. Forming a rear dielectric cover in the rear cover trench, and Forming a back-side source / drain contact beneath and contacting the first epitaxial source / drain structure. [20] Method according to claim 19, wherein forming the rear source / drain contact comprises: Forming a rear contact trench after forming the inner spacers, Filling the rear contact trench with a sacrificial semiconductor material, Removal of the sacrificial semiconductor material and replacement with a sidewall spacer dielectric material prior to forming the rear cover trench, Removal of at least one section of the sidewall spacer dielectric material, and Replace by the rear source / drain contact after forming the rear dielectric cover.