Carrier spacers and method for manufacturing a semiconductor device
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2020-10-29
- Publication Date
- 2026-07-23
AI Technical Summary
Existing semiconductor wafer transfer methods using dedicated housings and carrier spacers risk scratching or damaging the wafers due to direct contact and adhesion of foreign matter during vertical stacking and handling.
A carrier spacer with an annular main body, tapered portions, flat surfaces, peripheral edge, alignment projections, and handles is used to support semiconductor wafers, allowing for non-contact handling and reducing contact areas to prevent scratches and foreign matter adhesion.
The carrier spacer enables efficient, scratch-free transfer and handling of semiconductor wafers, improving yield and reducing foreign material adhesion, while allowing for precise stacking and handling of thin wafers without direct contact.
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Abstract
Description
Background of the invention; Field of the invention
[0001] The present invention relates to a carrier spacer and a method for manufacturing a semiconductor device using the carrier spacer. Description of the state of the art
[0002] When a semiconductor wafer is transferred in a manufacturing step of a semiconductor device, a dedicated wafer transfer housing is used. This housing allows multiple semiconductor wafers to be vertically stacked and transferred. However, when multiple wafers are vertically stacked, vertically adjacent wafers can come into contact and be damaged. Therefore, a carrier spacer is used between vertically adjacent wafers (see, for example, Japanese Patent Application Disclosure No. 2009-40431).
[0003] However, in a technique disclosed in Japanese Patent Application No. 2009-40431, it is assumed that the semiconductor wafers are transferred individually while mounted on the support spacers. If each semiconductor wafer is transferred individually, it is therefore necessary to grasp an outer peripheral portion of the semiconductor wafer with tweezers and to suction a central portion of the semiconductor wafer with vacuum tweezers or the like for transport. Consequently, there was a risk of scratching the semiconductor wafer or of foreign material adhering to it, depending on the frequency of contact with a front surface of the semiconductor wafer. Summary
[0004] It is an object of the present invention to provide a technique that is able to reduce contact with a front surface of a semiconductor wafer and to suppress damage to the semiconductor wafer and adhesion of foreign material when the semiconductor wafer is transferred individually.
[0005] The support spacer according to the present invention is a support spacer that is inserted between vertically adjacent semiconductor wafers when a plurality of semiconductor wafers are vertically stacked. The support spacer comprises an annular main body, a first tapered portion, a second tapered portion, a flat surface, a peripheral edge portion, an arcuate cutout portion, and a pair of handles. The first tapered portion is formed on an inner peripheral portion of the front surface of the main body and is inclined such that an inner peripheral side is located below an outer peripheral side. The second tapered portion is formed on the inner peripheral portion of the rear surface of the main body and is inclined such that the inner peripheral side is located above the outer peripheral side.The flat surface is formed on the outer peripheral side of the first tapered section on the front surface of the main body and supports the rear surface of the outer peripheral part of the semiconductor wafer. The peripheral edge section is formed on the outer peripheral side of the flat surface of the main body and has a step whose height is higher than that of the flat surface. The cutout section extends from the peripheral edge section of the main body towards the flat surface. The pair of handles projects from the peripheral edge section towards the outer peripheral side.
[0006] An operator can transfer the semiconductor wafer using the handle pair along with the carrier spacer when transferring the semiconductor wafer individually. This can reduce contact with the front surface of the semiconductor wafer and thus prevent scratches on the semiconductor wafer or the adhesion of foreign material to the semiconductor wafer.
[0007] These and other tasks, features, aspects and advantages of the present invention will become clearer with reference to the following detailed description of the present invention in conjunction with the accompanying figures. List of characters Fig. Figure 1 is a perspective view of a support spacer according to a preferred embodiment; Fig. 2 is a sectional view, which runs along line AA in Fig. 1 is taken from; Fig. 3 is a sectional view, which runs along line BB in Fig. 1 is taken from; Fig. 4 is a section view, which runs along line CC in Fig. 1 is taken from; Fig. 5 is a view which is equipped with Fig. 4 corresponds to a modified example of the preferred embodiment; Fig. Figure 6 is a perspective view of the support spacer and an enlarged perspective view of an overhang contained in the support spacer; Fig. Figure 7 is a diagram illustrating a step for storing the semiconductor wafer on one side of the front face of the support spacer; Fig. Figure 8 is a diagram illustrating a step for removing the semiconductor wafer, which is mounted on the support spacer; Fig. Figure 9 is a perspective view showing a state in which the carrier spacers, which hold the semiconductor wafers, are stacked and stored in a transfer housing; and Fig. 10 A diagram illustrating a step for removing the semiconductor wafer from the transfer package in a related technique. Description of the preferred embodiment<Bevorzugte Ausführungsform>
[0008] A preferred embodiment of the present invention is described below with reference to the figures. Fig. Figure 1 is a perspective view of a support spacer. 1 according to the preferred embodiment. Fig. 2 is a sectional view, which runs along line AA in Fig. 1 is taken from. Fig. 3 is a sectional view, which runs along line BB in Fig. 1 is taken from. Fig. 4 is a section view, which runs along line CC in Fig. 1 is taken from. Fig. 5 is a view which is equipped with Fig. 4 corresponds to a modified example of the preferred embodiment. Fig. Figure 6 is a perspective view of the support spacer. 1 and an enlarged perspective view of an overhang 8 , which is in the support spacer 1 is included.
[0009] The support spacer 1 is an element that is located between vertically adjacent semiconductor wafers 100 inserted when a plurality of semiconductor wafers 100 (see Fig. 9) is stacked vertically, and each of the semiconductor wafers 100 is on the support spacer 1 stored. Here, it is referred to as the one on the support spacer. 1 Semiconductor wafers to be stored 100 a semiconductor wafer used for power devices.
[0010] As in Fig. As shown in 1, the support spacer includes 1 a ring-shaped main body 2 and a pair of handles 11 . Parts of the support spacer 1 , which of the main body 2 and the pair of handles 11 are, for example, made of a resin material which has a conductivity to prevent damage to the semiconductor wafer. 100 to prevent static electricity.
[0011] As in the Fig. 1 and Fig. As shown in section 2, the main body comprises 2 rejuvenated parts 3 , 4 , flat surfaces 5 , 6 , a peripheral marginal part 7 , a plurality of (for example, three) protrusions 8 , a plurality of (for example, two) alignment overhangs 9 , and a section 10 .
[0012] The rejuvenated part 3is located on an inner peripheral part of an anterior surface of the main body 2 It is formed and is an inclined surface whose inner peripheral side lies below an outer peripheral side. The tapered part 4 is located on the inner peripheral part of a rear surface of the main body 2 It is formed and is an inclined surface whose inner peripheral side lies above the outer peripheral side. The tapered part corresponds to this. 3 with a first tapered part, and the tapered part 4 corresponds to a second, rejuvenated part.
[0013] The flat surface 5 is on the outer peripheral side of the tapered part 3 on the front surface of the main body 2 formed, and holds the rear surface of the outer peripheral part of the semiconductor wafer 100 Furthermore, the flat surface 6on the outer peripheral side of the tapered part 4 on the rear surface of the main body 2 formed. A width D of the flat surfaces 5 , 6 This corresponds to less than or equal to 5 mm. A lower limit of the width D corresponds to a diameter of the semiconductor wafer. 100 determined.
[0014] The semiconductor wafer 100 contacts the rejuvenated part 3 on the front surface of the main body 2 no, and consequently a contact area between the support spacer is not possible. 1 and the semiconductor wafer 100 be reduced. In a state where a majority of the support spacers 1 Once stacked, the semiconductor wafers next to each other come into view. 100 Furthermore, it does not come into contact with the rejuvenated part. 4 on the rear surface of the main body 2This can be caused by scratches or similar defects on the front surface of the semiconductor wafer. 100 impede.
[0015] The peripheral marginal part 7 is on the outer peripheral side of the flat surfaces 5 , 6 of the main body 2 formed. On the front surface of the peripheral edge part. 7 is a level 7a formed, which has a height position higher than that of the flat surface 5 is. The level 7a It is positioned higher than the front surface of the semiconductor wafer. 100 and covers the outer peripheral side of the semiconductor wafer 100 , and consequently, the semiconductor wafer may protrude 100 to be prevented towards the outer peripheral side.
[0016] On the rear surface of the peripheral edge part 7 is also a groove 7btrained, into which a level 7a of the peripheral marginal part 7 of the downwardly adjacent support spacer 1 can be fitted in a state in which the majority of support spacers 1 is stacked. As a result, the vertically adjacent support spacers can 1 They can be stacked with small gaps, and consequently a large number of semiconductor wafers can be stacked. 100 be transferred to a smaller area.
[0017] As in Fig. As shown in section 4, the two alignment projections are 9 on a front surface of the peripheral marginal part 7 formed, specifically at a position of the peripheral marginal part 7 , at which the overhangs 8 are not trained, in positions where the alignment overhangs 9 with respect to a center point of the main body 2are facing each other. Visual observation of the two alignment protrusions. 9 An operator can avoid errors regarding vertical and horizontal directions if the support spacers are used. 1 They can be stacked vertically. It should be noted that on the rear surface of the peripheral edge section... 7 two depressions 9a are formed into which the two alignment projections 9 the downwardly adjacent support spacers 1 are fitted in a state in which the majority of support spacers 1 is stacked.
[0018] As in Fig. As shown in section 5, the two alignment overhangs can be used instead. 9 two alignment depressions 19 be trained. In this case, there are two overhangs. 19a , which are located in the two alignment depressions 19can be fitted onto the rear surface of the peripheral edge part 7 trained.
[0019] As in Fig. As shown in 6, the three protrusions are 8 , which protrude towards the inner peripheral side, on a surface of an inner side of the step 7a formed at predefined intervals. The three protrusions 8 In a top view, they have a triangular shape with the inner peripheral side of the main body 2 as a tip, and hold the semiconductor wafer 100 by line contacting with three predefined positions at the outer peripheral end of the semiconductor wafer 100 .
[0020] In the semiconductor wafer 100 For power devices, a metal electrode of approximately a few µm is required on the semiconductor wafer. 100are formed. During the transfer of the transfer housing, in which the majority of carrier spacers are stacked and stored, in some cases a layer is formed which is located on the outer peripheral end of the semiconductor wafer. 100 is applied, comes into contact with the carrier spacers or the transfer housing, and the layer is detached, generating dust and reducing the yield of the semiconductor wafer. 100 This is reduced. To prevent such a case, contact with the outer peripheral end of the semiconductor wafer is avoided. 100 fixed on a line contact.
[0021] As in the Fig. 1, Fig. 3 and Fig. Shown in section 6 is the section below. 10 in an arc shape on the outer peripheral part of the main body 2 trained. Specifically, the excerpt is 10 from a part of the peripheral border 7 of the main body 2to part of the flat surfaces 5 , 6 trained in this. Wafer tweezers. 20 can be viewed from the side of the cutout section 10 be introduced to the semiconductor wafer 100 to remove or store, since an arc length of the cutout part 10 is longer than the arc length at one end of the wafer forceps 20 Furthermore, it is possible to place a buffer between the wafer tweezers. 20 and the support spacer 1 to suppress, since the cutout part 10 has the same arc shape as the end of the wafer tweezers 20 .
[0022] Next, the pair of handles will be 11 described. As in the Fig. 1 and Fig. As shown in figure 6, the pair of handles protrudes. 11 from an outer surface of the peripheral border part 7 of the main body 2 protrudes towards the outer peripheral side. The pair of handles11 is about the alignment overhangs 9 provided around, that is, at positions which are relative to the center of the main body 2 are facing each other. The operator can adjust the carrier spacer. 1 by grasping the pair of handles 11 transfer, and the semiconductor wafer 100 thus together with the support spacer 1 transfer without the semiconductor wafer 100 to touch directly.
[0023] Next, a method for manufacturing a semiconductor device using the carrier spacer will be described. 1 described. Fig. Figure 7 is a diagram illustrating one step in storing the semiconductor wafer. 100 on the side of the front surface of the support spacer 1 . Fig. Figure 8 is a diagram illustrating one step in removing the material from the support spacer. 1stored semiconductor wafers 100 . Fig. Figure 9 is a perspective view showing a state in which the support spacers 1 , which are the semiconductor wafers 100 are stored, stacked and stored in the transfer case.
[0024] As in Fig. As shown in Figure 7, the operator first grasps the outer peripheral part of the semiconductor wafer. 100 using wafer tweezers 20 and stores the semiconductor wafer 100 on the side of the front surface of the support spacer 1 from the side of the cutout section 10 .
[0025] As in Fig. As shown in section 8, the operator next grasps the pair of handles. 11 , takes the support spacer 1 out, stores the support spacer 1 in the transfer housing 21 during the semiconductor wafer 100is mounted on the support spacer, and stacks the majority of support spacers. 1 as in Fig. 9 shown.
[0026] After the transfer case 21 Once the wafer has been transferred to a peripheral of a wafer processing device (not shown), the operator grasps the pair of handles. 11 and takes a support spacer 1 one after the other from the transfer case 21 out. Next, the operator uses the wafer tweezers. 20 , to the outer peripheral part of the semiconductor wafer 100 from the side of the cutout section 10 to grasp, takes each semiconductor wafer 100 from the side of the cutout section 10 out, and sets each semiconductor wafer 100 into the wafer processing device.
[0027] In the wafer processing device, the front face of each semiconductor wafer is 100coated or provided with an electrode. Alternatively, instead of these steps, the front surface of each semiconductor wafer is coated. 100 irradiated with an electron beam or a particle beam.
[0028] As described above, the support spacer includes 1 according to the preferred embodiment, a ring-shaped main body 2 , a rejuvenated part 3 , which is located on an inner peripheral part of an anterior surface of the main body 2 is formed and inclined in such a way that an inner peripheral side lies lower than an outer peripheral side, a tapered part 4 , which is located on the inner peripheral part of a rear surface of the main body 2 is formed and inclined in such a way that the inner peripheral side lies above the outer peripheral side, forming a flat surface 5 , which are located on the outer peripheral side of the tapered part 3on the front surface of the main body 2 is formed and the rear surface of the outer peripheral part of the semiconductor wafer 100 holds a peripheral marginal part 7 , which is located on the outer peripheral side of the flat surface 5 of the main body 2 is trained and with a level 7a is provided which has a height position that is higher than a height position of the flat surface 5 is an arc-shaped cutout section 10 , which is from the peripheral marginal part 7 to the flat surface 5 of the main body 2 is trained in this way, and a pair of handles 11 , which is from the peripheral marginal part 7 protrudes towards the outer peripheral side.
[0029] The operator can move the semiconductor wafer 100 therefore using the pair of handles 11 individually together with the support spacers 1transfer. This can transfer contact with the front face of the semiconductor wafer. 100 reduce scratches on the semiconductor wafer 100 or the adhesion of foreign material to the semiconductor wafer 100 impede.
[0030] As described above, the operator can adjust the carrier spacer. 1 by grasping the pair of handles 11 transfer, and the semiconductor wafer 1 This allows for simpler transfer methods. This can improve the efficiency of a transfer process. Furthermore, scratches on or adhesion of foreign material to the semiconductor wafer can be prevented. 100 This can be prevented, and consequently the yield of the semiconductor wafer can be increased. 100 can be improved. Furthermore, the support spacer can be improved. 1 even after the semiconductor wafer has been removed 100 can be reused.
[0031] Furthermore, the support spacer includes 1additionally the majority of overhangs 8 , which from the peripheral marginal part 7 protrudes towards the inner peripheral side and the outer peripheral end of the semiconductor wafer 100 holds. The majority of overhangs 8 holds the outer peripheral end of the semiconductor wafer 100 in a line contact, and consequently the contact area can be connected to the outer peripheral end of the semiconductor wafer. 100 This can be reduced. This can avoid a case in which the particles on the outer peripheral end of the semiconductor wafer 100 applied layer during the transfer of the transfer housing 21 in contact with the support spacer 1 or the transfer housing 21 comes, and the layer moves from the semiconductor wafer 100 detaches, creating dust.
[0032] The support spacer 1 It also has a groove 7bon which is located on the rear surface of the peripheral edge part 7 is trained so that the level 7a of the peripheral marginal part 7 of the downwardly adjacent support spacer 1 into the groove 7b can be fitted. Consequently, the vertically adjacent support spacers can be 1 They can be stacked with small gaps, and consequently a large number of semiconductor wafers can be stacked. 100 be transferred to a smaller area.
[0033] Furthermore, the support spacer 1 furthermore the alignment overhangs 9 or the alignment depressions 19 on which is located on the front surface of the peripheral edge part 7 are formed. Optical observation of the two alignment protrusions. 9 or the alignment depressions 19The operator can therefore prevent errors regarding vertical and horizontal directions if the support spacers are used. 1 They can be stacked vertically, and this allows the support spacers to be used. 1 stacked in the correct direction.
[0034] Furthermore, damage to the semiconductor wafer can 100 due to the support spacer 1 The generated static electricity is suppressed because parts of the support spacer 1 contain a conductive material.
[0035] Furthermore, the method for manufacturing a semiconductor device according to the preferred embodiment comprises a step (a) for storing the semiconductor wafer. 100 on the side of the front surface of the support spacer 1 , a step (b) to store the support spacer 1 in the transfer housing 21 using the pair of handles 11, and a step (c) to remove the support spacer 1 from the transfer housing 21 using the pair of handles 11 , and subsequent removal of the semiconductor wafer 100 from the side of the cutout section 10 of the support spacer 1 using wafer tweezers 20 , and the insertion of the semiconductor wafer 100 into the wafer processing device.
[0036] Therefore, it is possible to use the thin semiconductor wafer 100 for power modules, which is difficult to handle without difficulty. This can cause scratches on the semiconductor wafer. 100 or the adhesion of foreign material to the semiconductor wafer 100 impede.
[0037] The wafer processing device is a device that applies a coating or an electrode to the semiconductor wafer. 100 trains. In the same way as in Fig. In the related technique shown in Figure 10, it was necessary in the wafer processing device to create a thin region at the center of the semiconductor wafer. 100 physically with a vacuum tweezers 22 or to suck in the front side to grip the semiconductor wafer 100 to handle. There was a quality problem, such as a scratch or a wafer break on the semiconductor wafer. 100 . Fig. Figure 10 is a diagram illustrating one step in removing the semiconductor wafer. 100 from the transfer housing 21 in the related technology. The two-dot dashed line shows a state in which the semiconductor wafer 100 suctioned up and removed using vacuum tweezers 22 is handled.
[0038] In contrast, in the method for manufacturing the semiconductor device according to the preferred embodiment, it is possible to use the semiconductor wafer 100to handle by holding only the outer peripheral part, which determines the quality of the semiconductor wafer 100 This does not affect the process. This suppresses the occurrence of scratches or wafer fractures.
[0039] The wafer processing device is a device that processes the semiconductor wafer. 100 irradiated with an electron beam or a particle beam. The carrier spacer 1 It can therefore be handled in one step for irradiation with an electron beam or a particle beam and inserted into the wafer processing device, and the irradiation can be carried out without direct contact with the semiconductor wafer. 100 be carried out.
[0040] It should be noted that the preferred embodiment may be suitably modified or omitted within the scope of the present invention.
[0041] While the invention has been shown and described in detail, the foregoing description is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be conceived without departing from the scope of the invention.
Claims
[1] A carrier spacer (1) which is inserted between semiconductor wafers (100) which are vertically adjacent when a plurality of the semiconductor wafers (100) are vertically stacked, the carrier spacer comprising: • a main body (2) having a ring shape; • a first tapered part (3) formed on an inner peripheral part of a front surface of the main body (2) and inclined such that an inner peripheral side is below an outer peripheral side; • a second tapered part (4) formed on the inner peripheral part of a rear surface of the main body (2) and inclined such that the inner peripheral side is above the outer peripheral side; • a flat surface (5) formed on the outer peripheral side of the first tapered part (3) on the front surface of the main body (2) and holding the rear surface of the outer peripheral part of the respective semiconductor wafers (100); • a peripheral edge part (7) formed on the outer peripheral side of the flat surface (5) of the main body (2) and provided with a step (7a) having a height position higher than a height position of the flat surface (5); • a cutout part (10) having an arc shape formed from the peripheral edge part (7) of the main body (2) to the flat surface (5); and • a pair of handles (11) projecting from the peripheral edge portion (7) toward the outer peripheral side. [2] The carrier spacer (1) according to claim 1, further comprising a plurality of projections (8) projecting from the peripheral edge portion (7) toward the inner peripheral side and holding an outer peripheral end of the semiconductor wafer (100). [3] The support spacer (1) according to claim 1 or 2, further comprising a groove (7b) formed on the rear surface of the peripheral edge portion (7) so that the step (7a) of the peripheral edge portion (7) of the downwardly adjacent support spacer (1) can be fitted into the groove (7b). [4] The carrier spacer (1) according to any one of claims 1 to 3, further comprising an alignment projection (9) or an alignment recess (19) formed on a front surface of the peripheral edge portion (7). [5] Carrier spacer (1) according to one of claims 1 to 4, wherein parts of the carrier spacer (1) contain a conductive material. [6] A method of manufacturing a semiconductor device using the carrier spacer (1) according to any one of claims 1 to 5, the method comprising: (a) storing the semiconductor wafers (100) on the front surface side of the carrier spacer (1); (b) storing the carrier spacer (1) in a transfer housing (21) using the pair of handles (11); and (c) removing the carrier spacer (1) from the transfer housing (21) using the pair of handles (11), and then removing the semiconductor wafers (100) from the cutout part (10) of the carrier spacer (1) using wafer tweezers (20), and inserting the semiconductor wafer (100) into a wafer processing device. [7] A method of manufacturing the semiconductor device according to claim 6, wherein the wafer processing apparatus is an apparatus which forms a coating or an electrode on the semiconductor wafers (100). [8] A method for manufacturing a semiconductor device according to claim 6, wherein the wafer processing apparatus is an apparatus which irradiates the semiconductor wafers (100) with an electron beam or a particle beam.