Method for manufacturing a semiconductor body and semiconductor arrangement

Abstract

A method for producing a semiconductor body, in particular an optoelectronic device, comprising: - providing an auxiliary carrier (1); - depositing a sequence of layers on the auxiliary carrier (1) comprising a first layer (2) with a doped semiconductor material, in particular a III-V semiconductor material, and a second layer (3) with an undoped semiconductor material on the first layer (2); - electrochemically porosifying the first layer (2), wherein a porosity degree is at least 20 volume %; - forming a functional semiconductor body (6), in particular an active semiconductor body suitable for light emission, on the second layer (3); - removing the semiconductor body (6) from the auxiliary carrier (1); wherein the deposition of the sequence of layers comprises: - applying a structured mask (8) to the second layer (3) for the selective porosification of the first layer (2);- Removal of the structured mask (8) after the electrochemical porosification step.;

Description

[0001] The present invention relates to a method for manufacturing a semiconductor body, in particular an optoelectronic component. The invention also relates to a semiconductor body, in particular an optoelectronic component.

[0002] In the production of semiconductor devices, it is often necessary to rebond the partially completed semiconductor layer stack, i.e., to transfer it from a first substrate to a second substrate. This can be particularly challenging with thin-film or thin-layer devices due to their fragility and requires increased effort.

[0003] For example, in thin-film devices based on GaN, the GaN epitaxial layer must be separated from the semiconductor substrate that forms the device. One method that can be used for this is laser lift-off (LLO). In this process, the epitaxially grown GaN interface with the (sapphire) substrate is decomposed by laser irradiation of a suitable wavelength. Several problems can arise during this process. Firstly, laser lift-off requires a high power density to vaporize the epitaxial GaN interface. This can damage the subsequent epitaxial layers and thus at least affect the electronic structure of the active region. To prevent this, the buffer layers are made correspondingly thicker.

[0004] Furthermore, the optically limited focusing of the laser beam through the sapphire substrate can make it difficult, depending on the application, to selectively detach very small, individual pre-structured chips with the laser without also affecting, damaging, or accidentally detaching the neighboring chip. This problem applies particularly to optoelectronic components with small dimensions of a few micrometers to a few tens of micrometers, so-called p-LEDs (< 20 µm or < 10 µm or < 5 µm edge length), when these are transferred directly onto a receiver substrate (backplane) via LLO.

[0005] On the other hand, in special products with very large chips (4-10 mm edge length), the substrate, for example, the sapphire substrate in single LLO, is only removed after the chips have been mounted in the component. Since a high power density must be applied across the entire chip, there is an increased risk of chip breakage. If the optical material contrast or the thermal contrast between the substrate and the epitaxial layer is insufficient (as, for example, in the case of homoepitaxy of InGaN on GaN wafers), the LLO process is not a practical solution.

[0006] There is therefore a need to provide a method for manufacturing a semiconductor device that can reduce the problems mentioned above. SUMMARY OF THE INVENTION

[0007] The following describes a method in which the holding force between the sapphire substrate and the layers that form part of the component is reduced. This results in easier removal, for example with a laser lift-off, but also with mechanical methods such as stamping processes or similar.

[0008] The inventors propose a method for processing a semiconductor body, which in a first step involves providing an auxiliary substrate. Subsequently, a layer sequence is deposited on the substrate, including a first layer of a doped semiconductor material, in particular a III-V semiconductor material, and a second layer of an undoped semiconductor material on the first layer. In a subsequent step, the first layer is electrochemically porous, with a porosity of at least 20 volume%. A porosity between 50 volume% and 90 volume% is also acceptable. A semiconductor device, and in particular an active semiconductor suitable for light emission, is formed on the second layer. Finally, the semiconductor body is removed from the auxiliary substrate.

[0009] In this context, a lattice constant is understood to be the length of a unit cell in a defined material system. This material system is uniform and contains no defects or lattice flaws; it is therefore unstressed. The lattice constant is a characteristic value for each material system and, with respect to the unstressed material system, is also referred to as the specific lattice constant. Different material systems can thus have different specific lattice constants, as illustrated in the link above. Therefore, when material systems with different lattice constants are combined, a strain occurs in a boundary region between these systems, meaning the lattice constants change. This change decreases with increasing distance from the boundary region. Furthermore, excessively large differences in the lattice constants can lead to defects or flaws.This effect can be specifically exploited through the proposed method and also the embodiments according to the invention.

[0010] In the following, a functional semiconductor layer sequence or functional semiconductor body refers to a sequence of layers structured in such a way that it can perform an electrical function as a finished component. A functional semiconductor layer sequence can be divided into individual elements, with each individual element then exhibiting the desired functionality. An example of a functional semiconductor layer sequence would be a sequence of layers that includes, for instance, a region suitable for light emission. Another example would be an npn junction, which possesses transistor functionality. The layer sequence can also combine several functions.

[0011] An auxiliary substrate is a support made of an inert material that serves as a base for subsequent processes, particularly the epitaxial deposition of semiconductor materials. Examples of auxiliary substrate materials include sapphire (Al₂O₃), silicon nitride, and others. It can be advantageous for the material to be inert to the various etching processes used in the fabrication of semiconductor devices. In some cases, the auxiliary substrate remains attached to the device and becomes part of it. In this case, the auxiliary substrate is also referred to simply as the substrate. In other cases, a device fabricated on the auxiliary substrate is detached (as described below).

[0012] A semiconductor material is generally understood to be an undoped compound semiconductor material, unless explicitly stated otherwise. In this context, "undoped" means that no dedicated, deliberate, and intentional doping with another element or material is carried out. Defects or impurities, which are always present in practice, do not constitute doping within the meaning of this application. A compound semiconductor material is a combination of two, three, or more elements produced in a crystal structure such that an electronic band structure is formed, and the resulting element exhibits electrical semiconductor properties. A typical compound semiconductor is a so-called III-V compound semiconductor, consisting of one or more elements from group 5 and one or more elements from group 3.Examples of compound semiconductor materials are GaAs, AlGaAs, GaN, AlGaN, InGaP, InGaN, GaP, AlGaP, AlInGaN, and others mentioned here.

[0013] A doped semiconductor is a semiconductor material into which a dopant has been introduced. Depending on the desired doping, the dopant can be Si, Te, Se, or Ge for n-type doping in a III-V compound semiconductor, and, for example, Mg for p-type doping. Further dopants are listed in this application. The dopant is introduced during epitaxial deposition of the III-V compound semiconductor material, but doping can also be carried out subsequently using various methods. The dopant concentration is several orders of magnitude lower than the concentration of atoms in the starting or base material. For example, the concentration is in the range of 1 × 10⁻⁶. 17 dopants / cm³ 3 up to 1*10 21 dopants / cm³ 3 .

[0014] Electrochemical decomposition, or electrochemical etching, is a process in which a semiconductor material is dissolved using an electrical voltage and current. This allows a layer of the semiconductor material to be dissolved or etched. However, this process is not uniform but rather uneven, for example, due to dislocations or material defects. This can be exploited by selecting appropriate parameters, such as the applied voltage and the concentration of a dopant and the semiconductor material being etched. For example, different rates and porosities of the material being etched can be achieved. The term electrochemical porosification thus refers to an electrochemical process that selectively dissolves material from a body, leaving behind a porous or sponge-like structure.A porous semiconductor body or layer thus creates a network structure similar to a Schwann or a bone, which has sufficient mechanical stability while having low mass or material volume.

[0015] A layer can be subjected to a selective porosification process in which a structured mask is applied prior to the process. This mask reduces or prevents current flow in certain areas of the layer due to a phenomenon known as shading, resulting in no or very low porosity in the areas covered by the mask. Accordingly, a non-porosified semiconductor body does not exhibit a network-like or sponge-like structure, although it may still contain various defects or lattice flaws. Furthermore, in some applications, effects can occur at the interface where a section of an otherwise non-porosified area exhibits low porosity, particularly at the edges of such an area, with the so-called porosity level (see below) decreasing with increasing distance from the edges.

[0016] In non-porous areas, the penetration of electrolyte beneath the shaded areas during the electrochemical etching process is hindered or even prevented, thus preventing the formation of further etch channels or the expansion of existing channels by the electrolyte. As a result, the material removal rate is significantly lower beneath the shaded areas, leading to considerably less or even no porosity of the material there.

[0017] The term porosity describes the ratio of material volume to the total volume of the layer. A porosity of around 20% means that 20% of the original material has been removed. At a porosity of 90%, 90% of the material has been removed by the electrochemical deposition process, leaving only 10%.

[0018] The inventors recognized that the electrochemical process and the removal of the material significantly reduce the adhesive force of the first layer's material to the support substrate or the second layer, thus requiring considerably less force or energy to break the bond. This can, for example, simplify a laser lift-off process because a lower laser intensity is needed. Furthermore, it was discovered that despite the porosity, the absorption of the laser light remains largely unchanged, so that energy deposition continues to occur primarily at the interface where the fracture is intended to occur.

[0019] Overall, this makes the various removal methods simpler, reducing the risk of breakage or damage to the component(s).

[0020] Furthermore, it was found that the second undoped layer is not removed, or is removed to a significantly lesser extent, by the electrochemical etching process than the doped first layer. Suitable dopants include silicon, with the etching or removal rate depending on the concentration of the dopant and the applied electrical voltage.

[0021] In one aspect, the first layer comprises a doped semiconductor material. At least one of the following semiconductor materials, among others, can serve as the base or substrate: GaN, GaP, GaAs, AlGaN, InGaN, AlInGaN, AlInGaP, GaAs, AlGaAs, and AlGaP. In some aspects, the doped and undoped semiconductor materials can share the same base semiconductor material. During the epitaxial deposition of the first layer, it can be doped. The dopant can be Si, C, Se, Te, Sn, Ge, or Mg at a concentration in the range of 1 × 10⁻⁶. 17 atoms / cm² 3up to 1*10 21 atoms / cm² 3 The process involves doping the first layer to accelerate the electrochemical etching process. More generally, the method involves selecting materials for the first and second layers such that electrochemical porosification occurs more rapidly in the first layer than in the second.

[0022] In addition, it is possible to include one or more buffer layers between the support substrate and the first layer, for example, for planarization or to compensate for lattice mismatch. These can be removed during the electrochemical etching process or left on the support substrate. In some examples, the thickness of the first layer can range from 100 nm to 4000 nm, particularly from 100 nm to 1000 nm. The thickness of the second layer, in some designs, ranges from 10 nm to 300 nm, particularly from 50 nm to 200 nm.

[0023] Another aspect concerns the formation of an active semiconductor body suitable for light emission. A third semiconductor layer can then be deposited on the second layer, in which at least one active layer configured for light emission is formed. Contact areas are then formed on the third semiconductor layer to contact the active layer configured for light emission. This step is optional and can be omitted or adapted to the design. For example, only one contact area can be formed.

[0024] In some aspects, it is envisaged that after the semiconductor body is detached from the support substrate, the porous first layer remains on the functional semiconductor body and is optionally designed as an output coupling structure for electromagnetic radiation. This allows the porous layer to be used functionally for further purposes.

[0025] Another step involves a process in which additional supports, pedestals, or other retaining structures remain even after porosification. In one example, the deposition of an initial layer sequence includes applying a structured dielectric mask to the second layer for the selective porosification of the first layer. The structured mask is then removed after the electrochemical porosification step. By structuring the second layer with a non-conductive mask, areas in the first layer are shaded by the mask. This prevents current from flowing through the shaded areas during the electrochemical etching process, or changes the resistance in these areas. Similarly, the penetration of an electrolyte under the shaded areas during the electrochemical etching process is hindered or even prevented, thus preventing the formation of further etch channels.Existing channels are not enlarged by the electrolyte. As a result, the erosion rate is significantly lower in the shaded areas, so that the material becomes significantly less porous, or not porous at all, in these areas.

[0026] In one aspect, the plan is to choose a structural dimension of the mask that is at least as large as the desired structure formed in the first layer after electrochemical porosification. In other words, the mask should be dimensioned slightly larger than the desired structure in some respects to compensate for the undercut caused by the process. For nitrides, the undercut can range from 200 nm to approximately 800 nm, while for GaAs or GaP-based materials, it can exceed 1000 nm. The dimensions and lateral extent must be chosen accordingly.

[0027] In some aspects, after selective porosification, the mask is removed and a third semiconductor layer is deposited on top of the second layer, in which at least one active layer configured for light emission is formed. Optionally, one or more contact areas can be formed on the third semiconductor layer, which contact the active layer configured for light emission.

[0028] Depending on the design, areas between non-porous structures in the first layer can be removed before or after the above step, especially by structured etching, so that a semiconductor body suitable for light emission is created over a non-porous structure.

[0029] In this way, semiconductor structures can be isolated on a support structure formed by the non-porous areas. The porous areas of the first layer can be removed by selective etching. Due to their small surface area, the remaining non-porous areas exhibit lower holding force and thus, in some designs, form a pedestal-shaped support structure. This support structure has a smaller surface area than the area occupied by the semiconductor structure (in top view). In some configurations, the support structure can form a truncated cone or a trapezoid, with the smaller base of this shape connected to the device.

[0030] In some examples, the removal, especially by structured etching of areas between non-porous structures, can be carried out in such a way that material is removed down to the substrate.

[0031] Finally, the detachment of the semiconductor body from the support can include the detachment of the light-emitting semiconductor body from the non-porous structure of the first layer.

[0032] Another aspect concerns a semiconductor arrangement comprising a support substrate and a first layer arranged on the support substrate, the first layer having at least one first region and at least one second region. A second layer is arranged on the first layer, and a functional semiconductor layer sequence is arranged on the second layer. According to the proposed principle, the at least one first region of the first layer comprises a porous semiconductor material with a porosity of at least 20 volume%, and the at least one second region of the first layer essentially has a porosity of less than 10 volume%, in particular less than 5 volume%, and is a doped semiconductor material.

[0033] Alternatively, a semiconductor arrangement can be provided comprising a support substrate and a first layer arranged on the support substrate. A second layer is arranged on the first layer, and a sequence of functional semiconductor layers is arranged on the second layer. According to the proposed principle, the first layer is provided to be planarly, with a porosity level of at least 20 volume%.

[0034] To ensure porosity, the second layer is formed with a doping concentration that differs from that of at least one other region of the first layer. In particular, the second layer can be undoped, i.e., it can be undoped.

[0035] The functional semiconductor layer sequence can in some aspects comprise an active semiconductor layer sequence suitable for light emission, wherein at least one contact area is provided for contacting on the side of the layer sequence facing away from the second and first layers.

[0036] In one embodiment, the functional semiconductor layer sequence is configured with at least one trench that separates regions of the functional semiconductor layer sequence from one another. Each section thus separated forms a functional semiconductor body and is arranged above a second region of the first layer. List of characters

[0037] Further aspects and embodiments of the proposed principle will become apparent with regard to the various embodiments and examples described in detail in conjunction with the accompanying drawings. These show: Fig. 1 several steps of a process for manufacturing a functional semiconductor body, which implement some aspects of the proposed principle; Fig. 2A and Fig. 2B another embodiment with several process steps for the production of a functional semiconductor body, which realizes some aspects of the proposed principle; Fig. 3. A design of a layer sequence with an additional separating layer according to some aspects of the proposed principle; Fig. 4A to Fig. 4C Aspects of a manufacturing process for a semiconductor body with some aspects of the proposed principle. DETAILED DESCRIPTION

[0038] The following embodiments and examples illustrate various aspects and their combinations according to the proposed principle. The embodiments and examples are not always to scale. Likewise, various elements may be enlarged or reduced to highlight specific aspects. It is understood that the individual aspects and features of the embodiments and examples shown in the figures can readily be combined without affecting the principle of the invention. Some aspects exhibit a regular structure or shape. It should be noted that minor deviations from the ideal shape may occur in practice without contradicting the inventive concept.

[0039] Furthermore, the individual figures, features, and aspects are not necessarily depicted at the correct size, and the proportions between the individual elements may not be entirely accurate. Some aspects and features are emphasized by being shown enlarged. However, terms such as "above," "above," "below," "below," "larger," "smaller," and the like are correctly represented in relation to the elements within the figures. Thus, it is possible to deduce such relationships between the elements from the illustrations.

[0040] The inventors discovered that the partial electrochemical decomposition (referred to here as porosification) of a defined GaN-containing layer significantly reduces the holding force between a GaN epitaxy stack and the epitaxy substrate (sapphire or Si, GaN). This process etchs very uniform pores (in the range of 20 nm to 100 nm) – homogeneously distributed – into the specific GaN layer. The selectivity of the porosification can be achieved by a high n-doping concentration, for example with Si, of the GaN layer. This means that only sufficiently doped layers become porous.

[0041] Since chemical etching occurs via vertical dislocation of the material within the GaN epitaxy stack across the entire surface, "porosity" can occur across the entire wafer. The layer to be porous may be buried beneath other GaN layers.

[0042] Alternatively, a laterally selective etching attack can be achieved through partial passivation of the surface during porosification. An applied mask prevents the buried areas in the first layer to be porosified from being laterally porosified or only minimally etched beneath the masked surface areas, resulting in different chemical and mechanical properties in subsequent process steps. Optionally, one or more additional second layers can be inserted between the first layer to be porosified and the subsequent layers forming the semiconductor device. These additional second layers can then serve as mechanical fracture surfaces in a further process step.

[0043] The inventors recognized that the ratio of porous to non-porous area is crucial for the damage-free removal of the component from the substrate. At the same time, they realized that even with greater porosity, mechanical stability is largely maintained, allowing this ratio to be greater than 2 and even greater than 5.

[0044] Fig. Figure 1 shows an exemplary first embodiment of a method according to the proposed principle for the production of a semiconductor body which can be removed from a substrate particularly easily by means of a porous separating layer.

[0045] In a first step, a support substrate 1 is provided as an auxiliary support. In the present embodiments, this is a sapphire support substrate; however, a support substrate with a different material system can also be used. Suitable examples include silicon-based, silicon nitride-based, or, as shown, sapphire-based support substrates. The auxiliary support is selected, among other things, according to the material system used later.

[0046] In a next step S2, a first layer 2 of the layer sequence 4 is deposited on the support 1. This first layer 2 is also doped with a dopant during epitaxial growth on the substrate of the support 1. In the present embodiment, GaN is used as the material for the first layer, which is epitaxially grown on the support 1 with silicon (Si) as the dopant. The dopant concentration of silicon atoms is in the range of 10 × 10 18 atoms / cm² 3Additionally, one or more buffer layers can be applied to the material of the support 1 before the epitaxial growth of the GaN layer 2. These are not shown separately in step S2, but can be used for further planarization of the support 1 or for subsequent current expansion for the electrochemical process. Furthermore, depending on the material system used, the additional buffer layers also serve as etch stop or lattice-fitting structures.

[0047] In a subsequent step S3, an undoped GaN layer 3 is deposited onto the doped, epitaxially grown GaN layer 2. This undoped GaN layer 3 is significantly thinner than the doped GaN layer 2 and also exhibits different mechanical, chemical, and electrical properties. The undoped GaN layer 3 and the doped GaN layer 2 together form layer sequence 4.

[0048] In step S4, the wafer produced in this way is subjected to an electrochemical dissolution process. This is also known as the porosification process. A voltage is applied to the formed wafer structure and the layer sequence 4, causing a current to flow through the undoped GaN layer 3 and the doped GaN layer 2. This current flow causes partial chemical decomposition or dissolution of the doped GaN layer. This process is called porosification. During this process, the electrochemical process etches uniform pores with a size ranging from a few tens of nm to 100 nm into the doped GaN layer 2. The distribution of the pores was found to be essentially homogeneous.The etch rate, pore size, and associated material removal depend on the applied voltage, the current flow during the electrochemical process, and the concentration of dopants in GaN layer 2. It should be noted that the undoped GaN layer 3 is also affected by the electrochemical process. Material removal occurs in both layers because they are not electrically insulating. However, the conductivity of the undoped GaN layer is significantly lower, so the silicon doping in layer 2 ensures selectivity during the porosification process.

[0049] In other words, the doped GaN layer 2 is attacked and etched much more intensely during the electrochemical process, resulting in material being removed, than the undoped GaN layer 3. Since the current in this example is applied across the entire surface of the wafer during porosification, the electrochemical process in layer stack 4 proceeds across the entire surface. The porosified layer 2a in step S4 is thus buried beneath the undoped GaN layer 3.

[0050] The amount of material removed during porosification is adjustable by the duration and the parameters described above. To ensure successful subsequent removal by laser lift-off or other mechanical methods, the inventors propose a porosity level of at least 20 volume%. It was found that up to a porosity level of approximately 90 to 95 volume%, the mechanical stability of the remaining material is still sufficient to enable the subsequent manufacturing steps. However, the high material removal significantly reduces the adhesive force between the substrate 1 and the porous GaN layer 2a, and between this layer and the undoped GaN layer 3. Therefore, a porosity level between 40 and 90 volume% is considered advantageous.

[0051] After porosity of the first layer 2 of the layer sequence 4, the wafer produced in this way can be further processed and a functional semiconductor body can be formed on it. Various manufacturing processes and designs for the respective semiconductor bodies are conceivable and some are known to those skilled in the art.

[0052] Steps S5 and S5' illustrate two different examples where a functional semiconductor body is configured as a functional layer sequence 6. This sequence includes a multiple quantum well 11, configured to emit light of a specific wavelength. Two contact areas, 7 and 7a, are provided within the functional layer sequence 6 to connect this multiple quantum well 11. Contact area 7a extends through the multiple quantum well 11 and contacts the buried doped layer between the porous layer 2a and the multiple quantum well 11. The other contact area 7 contacts the layer of the functional layer sequence 6 opposite the multiple quantum well 11.

[0053] A similar embodiment is shown in step S5', where the respective contact areas 7 are simply recessed into the layer. In addition to the four contact areas shown, other elements can also be used.

[0054] During this manufacturing process, a so-called "rebonding" or "transfer" onto a support 5 is performed. For this purpose, after the fabrication of the layer sequence 6 and, if applicable, the contact areas 7 and 7a, an additional support 5 is provided, which is bonded to the contact areas 7 and 7a and / or the layer sequence 6 (as shown in step S5'). The auxiliary support 1 can then be removed using a laser lift-off process. For this purpose, laser light is shone through the auxiliary support 1, which is absorbed in the porous doped GaN layer 2a and heats it intensely. The resulting energy input detaches the support 1 from the porous layer 2a, allowing it to be removed.

[0055] Modifying the interface towards the support carrier 1 enables a laser lift-off process with a comparatively low laser power. This also reduces damage to the support carrier, potentially allowing it to be reused. Reusing the support carrier further reduces the manufacturing costs of such semiconductor devices. Furthermore, the reduced adhesive force makes laser lift-off possible and advantageous even for large chips, as a stress-reduced lift-off process should be achievable for these semiconductor devices as well. The porosity significantly facilitates the removal of the entire support carrier using a laser lift-off, or even a mechanical or chemical process, and allows for highly selective removal with less energy input, even with a small vertical material contrast.

[0056] Fig. 2A and Fig. Figure 2B shows various steps of a further development of the proposed principle, in which additional measures and a structuring of the layer sequence 4 are implemented. This allows for further applications.

[0057] In step S1 of this embodiment, after providing an auxiliary support 1, a doped GaN layer 2 is epitaxially grown on the support 1. A thin sintering or separation layer 3a is then additionally deposited on the doped GaN layer 2. This layer can be formed, for example, from AlGaInN or from intrinsic silicon nitride, SiN (approximately a monolayer), and in this embodiment also extends over the entire wafer. The undoped GaN layer 3 is then deposited over the thin sintering layer 3a. The resulting layer sequence 4 on the support substrate 1 is shown in step S2.

[0058] In step S3, a structured mask 8 is applied to two locations on the undoped GaN layer 3. The mask 8 is chemically inert to the subsequent electrochemical porosification step and is, for example, a hard mask. As shown in step S4, the electrochemical porosification is carried out after the application of the structured mask 8. The structure of the mask 8 acts as a shading layer, so that areas below the mask 8 in the first layer 2a are not porous or etched, but remain as non-porous areas 2b. In the example of steps S3 and S4, these are two areas that are a few µm wide and essentially form squares in plan view. However, other dimensions and / or a different number of such areas can also be provided. Likewise, the shape can be different, for example as polygons, circles, or rectangles.

[0059] The reason for this selective porosification is that the insulating properties of mask 8 largely prevent current flow through layer 3, layer 3a, and the first layer 2. In other words, the current always takes the path of least resistance and would therefore not flow below the areas covered or shaded by mask 8 during the electrochemical process. As a result, porosification due to current flow occurs primarily in the unshaded areas of the first layer, leading to the formation of porous regions 2c there.

[0060] The dimensions of mask 8 are adapted to the dimensions of the subsequent non-porosified areas 2b. Although the surface resistance beneath the mask is higher and the current flow there significantly lower, slight under-etching still occurs to a limited extent in the edge region. Due to this under-etching during electrochemical porosification, it is advantageous to make the lacquer mask 8 slightly larger than the intended dimensions of the subsequent non-porosified area. This compensates for the slight under-etching beneath the mask and thus into the shaded area.

[0061] Step S5 illustrates the result of such a selective porosification process. The structured lacquer mask created several non-porosified areas 2b in the first layer 2, each surrounded by porosified areas 2c. In plan view (not shown here), the non-porosified areas 2b are essentially square and completely enclosed by the porosified areas 2c. After removing the lacquer mask 8, the first n-doped layer 10 of the functional layer sequence 6 is applied to the undoped GaN layer 3. This layer can consist of GaN or another material system, e.g., InGaN. In this embodiment, layer 10 is n-doped. However, this is not necessary; other doping or no doping at all can also be used.

[0062] During step S6, further epitaxial deposition processes are carried out to form a multiple quantum well 11 and a p-doped layer 12. This creates an optically active semiconductor body suitable for light emission on the layer sequence 4. After the formation of the functional layer sequence 6 and thus the functional semiconductor body, a structured mask with several structural elements 8a is again applied to the surface of the p-doped layer 12. As shown in the figure of step S6, the mask material is deposited over the non-porous regions 2b of the second layer 2.

[0063] Subsequently, in step S7, the structure thus formed is subjected to a selective etching process, so that the uncovered areas of the functional layer sequence and the porous uncovered areas of the first layer 2 are selectively etched. Selective etching of layer sequence 6 and layer 2 can be carried out using wet chemical methods or gaseous etching. Dry etching methods are also suitable for smaller etching operations.

[0064] The etching process creates grooves that extend from the surface of layer 12 down to the substrate of the support 1. The result of such a selective etching process is shown in step S7. After removing the mask structure 8a, contact areas 7 and 7a can also be applied to the surface of the p-doped layer 12. The contact areas 7a are electrically isolated from the p-doped layer 12 and extend through the p-doped layer 12, the multiple quantum well 11, and into the n-doped layer 10. The contact areas 7 make direct contact with the p-doped layer 12.

[0065] By selectively etching and forming the mesa structure and the trenches 20 in the preceding steps, the buried porous regions 2c in layer 2 can now be easily accessed. These are selectively removed in a subsequent wet-chemical step, for example, by a lateral etching attack. After removal by an etching process, the non-porous regions remain as column or pedestal structures. They thus form support structures 20b on which the separated semiconductor bodies 60 are arranged. The support structures 20b with the semiconductor bodies 60 are shown in the result in step S8. Their surface facing the layer sequence 6 is smaller than the side facing the support, so that the pedestal structures form not only a column-like shape but also a truncated cone, a truncated pyramid, or a trapezoid.The smaller contact area compared to the area facing the substrate further reduces the holding force. This decrease in diameter, or more generally, a change in diameter, is achieved through varying doping levels during the epitaxial deposition of the first layer. The doping also controls the rate of porosification, thus influencing the etching beneath the shaded areas.

[0066] In step S9, these semiconductor bodies can now be selectively detected using a punch 30 and separated from the holding structures 20b by a laser lift-off or a mechanical process (e.g., using a punch). The intended separation layer 3a may be damaged in the process, but without impairing the functionality of the components. Depending on the design, the intended separation layer 3a is structured as a sacrificial layer. Alternatively, layer 3a can also be chemically roughened (if this has not already been done by the preceding etching step to remove areas 2c), so that during operation, light can be coupled out particularly well through this surface.

[0067] Depending on the application, various variations of the proposed principle, i.e., the porosification of a first layer of a layer sequence, are now possible.

[0068] Fig. Figure 3 shows such an example, in which differently doped areas are proposed to generate different degrees of porosity. Fig. Figure 3 shows the result of the first steps in the fabrication process of a semiconductor device. A first layer 2 was epitaxially deposited on a support carrier 1. This layer comprises a region 2' adjacent to the support carrier 1 and a region 2''. Regions 2' and 2'' are separated by a thin separating layer 3b. Separating layer 3b serves as a predetermined breaking point and comprises AlGaInN or silicon nitride, SiN. Furthermore, layer 3b separates different doping concentrations. Thus, the doping levels of regions 2' and 2'' differ, resulting in different porosity levels during a subsequent electrochemical process. In the present embodiment, the doping concentration in region 2' is significantly higher than in region 2''.As a result, significantly more material is removed and decomposed during the electrochemical process in region 2' than in region 2'', which is closer to the undoped GaN layer 3.

[0069] The structure produced in this way is particularly suitable, for example, as an output coupling structure. After forming a functional semiconductor body configured for light emission, the support is separated from the material 2' and the separating layer 3b. In a further step, the predetermined breaking point 3b can also be removed, so that only the porous region 2'' of the first layer remains on the device. The porosity of this porous layer is chosen such that layer 2'' serves as the output coupling structure, since its pore structure forms a suitable refractive index step. Subsequent roughening with KOH or other measures is therefore unnecessary. Such a doping profile, or more generally, a doping profile that changes across the layer, allows for further variation during the delamination process.For example, it is possible to choose the doping profile so that it increases towards layer sequence 6. If selective porosity is then carried out, as in the example of... Fig. 2. If the process is carried out, the undercutting can cause the areas in the Fig. The structures shown in the two diagrams are created, in which the cross-section changes and, for example, becomes smaller towards layer sequence 6. Fig. 4A to Fig. Figure 4C shows further embodiments of processing and manufacturing a semiconductor body according to the proposed principle. Fig. In 4A, for example, after porosification of the first layer 2, a mesa structure was introduced into the layer sequence 4, which has a multitude of periodically arranged trenches 20. Subsequently, the layer sequence 4 is covered with a planarization layer 10 made of InGaN. Here, the thickness of the trenches 20 is chosen such that the InGaN layer is not filled into the trenches, but forms bridges, so that the trenches essentially remain as cavities in the structure thus formed. This further reduces the bond strength between the substrate of the support 1 and the porous areas 2c of the first layer 2.

[0070] After forming a functional semiconductor body and a layer sequence of 6 in Fig.As shown in 4C, the resulting component is transferred and separated from the support substrate 1. The functional layer sequence 6, with its p-doped layer 12, is now connected to a metallic p-contact 70 and arranged on a support 100. Further metallic contacts 7 can be applied to the porous areas 2c of the layer sequence 4. This allows, for example, individual areas of the functional layer 6 to be selectively controlled, thus enabling adjustment of the intensity of a light emission. The porous areas 2C can also serve as an output coupling structure.

[0071] In the illustrated embodiments, the thickness of the first layer is in the range of 100 nm to 2000 nm. Preferably, it is in the range of 500 nm to 1000 nm. The top layer 10 of the functional layer sequence can be in the range of 50 nm to 200 nm before further growth.

Claims

[1] Method for producing a semiconductor body, in particular an optoelectronic component, comprising: - Providing an auxiliary carrier; - depositing a layer sequence on the auxiliary carrier comprising a first layer with a doped semiconductor material, in particular a III-V semiconductor material, and a second layer with an undoped semiconductor material on the first layer; - electrochemically porosifying the first layer, wherein a degree of porosity is at least 20% by volume; - forming a functional semiconductor body, in particular an active semiconductor body suitable for light emission, on the second layer; - Detaching the semiconductor body from the auxiliary carrier. [2] The method of claim 1, wherein the first layer comprises at least one of the following semiconductor materials: - GaN; - GaP - AlGaN; - InGaN - AlInGaN; - AlInGaP; and - AlGaAs; and the first layer is doped with a dopant during epitaxial deposition. [3] Method according to claim 2, wherein the dopant comprises at least one of Si, Ge, Te, Se or Mg, Zn, C, Be with a concentration in the range of 1*10 17 1 / cm 3 up to 1*10 21 1 / cm 3 includes. [4] Method according to one of the preceding claims, in which the doped and the undoped semiconductor material comprise the same base semiconductor material. [5] Method according to one of the preceding claims, wherein a material of the first and second layer is selected such that electrochemical porosification occurs faster in the first layer than in the second layer. [6] Method according to one of the preceding claims, wherein a thickness of the first layer is in the range from 100 nm to 4000 nm, in particular in the range from 100 nm to 1000 nm and / or a thickness of the second layer is in the range from 10 nm to 300 nm, in particular in the range from 50 nm to 200 nm. [7] A method according to any one of the preceding claims, wherein forming a functional semiconductor body comprises: - applying a third semiconductor layer on the second layer, in which at least one active layer designed for light emission is formed; - Forming contact areas on the third semiconductor layer, which contacts the active layer formed for light emission. [8] Method according to one of the preceding claims, in which, after the detachment of the semiconductor body from the auxiliary carrier, the porous first layer remains on the functional semiconductor body and is optionally designed as a coupling-out structure for electromagnetic radiation. [9] Method according to one of the preceding claims, in which the deposition of a first layer sequence comprises: - Applying a structured mask on the second layer for selective porosification of the first layer; - Removing the structured mask after the electrochemical porosification step. [10] The method of claim 9, wherein the structured mask has structural dimensions that are at least equal to the dimensions of a non-porosified structure formed in the first layer after electrochemical porosification. [11] The method of claim 9, wherein forming a functional semiconductor body comprises: - applying a third semiconductor layer on the second layer, in which at least one active layer designed for light emission is formed; - forming contact regions on the third semiconductor layer, which contacts the active layer designed for light emission; and - forming depressions or trenches, in particular by structured etching of regions between non-porous structures in the first layer, so that a semiconductor body suitable for light emission is formed over a non-porous structure; - Removal, in particular by etching of the porous first layer. [12] Method according to claim 11, wherein the shaping is carried out, in particular by structured etching of regions between non-porous structures, in such a way that material is removed down to the carrier. [13] Method according to one of claims 9 to 12, wherein the detachment of the semiconductor body from the auxiliary carrier comprises detaching the semiconductor body suitable for light emission from non-porous structures of the first layer, wherein detachment is carried out in particular by a laser lift-off or a mechanical method such as a stamping method. [14] Semiconductor device, comprising: - a carrier substrate; - a first doped layer arranged on the carrier substrate, which has at least one first region; - a second layer arranged on the first doped layer; - a functional semiconductor layer sequence arranged on the second layer; wherein the at least one first region of the first doped layer comprises a porous semiconductor material with a degree of porosity of at least 20% by volume. [15] Semiconductor device according to claim 14, wherein the first doped layer comprises at least one second region, and the at least one second region of the first layer substantially has a porosity level of less than 10% by volume, in particular less than 5% by volume, and a doped semiconductor material. [16] Semiconductor arrangement according to claim 14 or 15, wherein the functional semiconductor layer sequence comprises an active semiconductor layer sequence suitable for light emission, wherein the functional semiconductor layer sequence has at least one contact region for contacting on the side of the layer sequence facing away from the second and first layer. [17] Semiconductor arrangement according to one of claims 14 to 16, wherein the second layer has a lower doping than the at least one second region of the first layer, in particular no doping. [18] Semiconductor arrangement according to one of claims 14 to 17, wherein the functional semiconductor layer sequence has at least one trench which separates regions of the functional semiconductor layer sequence from one another and each of these regions is arranged above a second region of the first layer. [19] Semiconductor arrangement according to one of claims 14 to 18, wherein the porous first layer remains on the functional semiconductor body and is optionally designed as a coupling-out structure for electromagnetic radiation. [20] Semiconductor device according to claims 14 to 19, wherein a concentration of the dopant within the first layer increases from the carrier substrate to the second layer. [21] Semiconductor arrangement according to claim 15, wherein the at least one second region, after removal of the porous regions, has a diameter which decreases in the direction of the functional semiconductor layer sequence.

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