STORAGE DEVICE AND METHOD FOR FORMING THE SAME

Abstract

Storage device (500, 600, 700), comprising: a first layer arranged on a substrate (101), the first layer comprising: a first layer stack (110); a first gate electrode (124) penetrating the first layer stack (110); a first channel layer (120) arranged between the first layer stack (110) and the first gate electrode (124); and a first ferroelectric layer (122) arranged between the first channel layer (120) and the first gate electrode (124); and a second layer arranged on top of the first layer, the second layer comprising: a second layer stack (210, 210'); a second gate electrode (224) penetrating the second layer stack (210); a second channel layer (220) arranged between the second layer stack (210) and the second gate electrode (224);and a second ferroelectric layer (222) arranged between the second channel layer (220) and the second gate electrode (224).

Description

BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced exponential growth. The technological progress in IC materials and design has resulted in generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry size (i.e., the smallest component (or line) that can be generated using a fabrication process) has decreased. This downsizing process generally offers advantages in increasing production efficiency and lowering the costs associated therewith.Such downsizing has also increased the complexity of processing and manufacturing ICs, and in order for these advances to be realized, has required similar developments in processing and manufacturing ICs. For example, a three-dimensional (3D) memory device, such as a 3D NOR memory, has been introduced to replace a planar memory device. 3D memory devices are not fully satisfactory in every respect, however, because additional problems which should be solved arise.US 2018 / 0 366 489 A1 discloses a method dealing with low cost, low resistance metal compounds and mechanical stability in a high aspect ratio structure. US 2007 / 0 057 309 A1 discloses a nonvolatile semiconductor memory device comprising a plurality of pillars projecting upwardly from a semiconductor substrate and having respective top surfaces and opposing sidewalls.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various elements are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various elements may be arbitrarily increased or decreased. FIGS. 1 to 6A are cross-sectional views of a method of forming a three-dimensional memory device (3D memory device) according to a first embodiment. FIG. 6B is a plan view taken along a cross section I-I' of FIG. 6A. FIG. 7A is a cross-sectional view of a 3D memory device according to a second embodiment. FIG. 7B is a plan view taken along a cross section II-II' of FIG. 7A. FIG. 8 is a cross-sectional view of a 3D memory device according to a third embodiment. FIG. 9 is a cross-sectional view of a 3D memory device according to a fourth embodiment. FIGS. 10 to 16 are cross-sectional views of a method of forming a 3D memory device according to a fifth embodiment. FIG. 17 is a cross-sectional view of a 3D memory device according to a sixth embodiment. FIG. 18 is a cross-sectional view of a 3D memory device according to a seventh embodiment. FIG. 19 shows a flow diagram of a method of forming a 3D memory device, in accordance with some embodiments.DETAILED DESCRIPTIONThe invention is defined by the independent claims. Embodiments of the invention are provided in the dependent claims, the description and the figures. The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "below," "above," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature or to other elements or features as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may also be interpreted accordingly.According to some embodiments, a three-dimensional (3D) memory device includes a first layer having a plurality of first memory cells and a second layer having a plurality of second memory cells stacked over the first layer. The second memory cells are stacked on the first memory cells to allow a simple modification to increase the number of memory cells in the memory device, thereby improving the memory cell density. In addition, a dielectric material (e.g., an isolation structure) is disposed between the first and second memory cells to reduce or eliminate leakage current between two vertically adjacent memory cells, thereby improving device performance.FIGS. 1 to 6A are cross-sectional views of a method of forming a 3D memory device 100 according to a first embodiment. FIG. 6B is a plan view taken along a cross section I-I' of FIG. 6A. The 3D memory device 100 is a 3D memory device including a ferroelectric material and may be, but is not limited to, a 3D NOR memory device.Referring to FIG. 1, a plurality of electrical components 104 such as transistors, resistors, capacitors, inductors, diodes, or the like are formed in a device region of a semiconductor substrate 102 in front-end-of-line (FEOL) processing of semiconductor manufacturing. The semiconductor substrate 102 may be a bulk substrate, such as a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may include other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The electrical components 104 may be formed in / on the semiconductor substrate 102 using any suitable formation method known or used in semiconductor fabrication.After the electrical components 104 are formed, an interconnect structure is formed over the semiconductor substrate 102 to connect the electrical components 104 to form functional circuits. The interconnect structure may include a plurality of dielectric layers (e.g., 106, 108) and electrically conductive features 105 (e.g., vias, metal lines) formed in the dielectric layers. In some embodiments, the interconnect structure is formed in back-end-of-line (BEOL) processing of semiconductor fabrication. The formation of the interconnect structure is known in the art, therefore details are not repeated here. To avoid disordering and facilitate discussion, the semiconductor substrate 102, the electrical components 104, and the interconnect structure over the semiconductor substrate 102 are collectively referred to as substrate 101 in the following discussion, and the details of the substrate 101 illustrated in FIG. 1 may be omitted in the following figures.FIGS. 2 to 6A illustrate additional processing steps in the BEOL processing to form the 3D storage device 100 according to the first embodiment. Referring to FIG. 2, a layer stack 110 may be formed on the substrate 101. In detail, the layer stack 110 may include a dielectric layer 112, a conductive layer 114, a dielectric layer 116, and a conductive layer 118 sequentially formed on the substrate 101.In some embodiments, the dielectric layers 112 and 116 may include a dielectric material such as an organic dielectric material or an inorganic dielectric material. The organic dielectric material may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. The inorganic dielectric material may be: a nitride such as silicon nitride or the like; an oxide such as silicon oxide; an oxynitride such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or a combination thereof. The dielectric layer 112 may be formed by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, dielectric layers 112 and 116 comprise the same dielectric material, such as silicon oxide. However, embodiments of the present disclosure are not limited thereto, in other embodiments, the dielectric layers 112 and 116 include different dielectric materials.In some embodiments, the conductive layers 114 and 118 may include a conductive material such as metal. For example, the conductive layers 114 and 118 may be formed of the same source / drain (S / D) material as W, Ru, or the like. In this case, the conductive layers 114 and 118 may also be referred to as a first source / drain metal layer 114 and a second source / drain metal layer 118, respectively.Depending on the type (e.g., n-type or p-type) of device formed, the first source / drain metal layer 114 and the second source / drain metal layer 118 may be formed of a metal of an n-metal or a p-metal. In some embodiments, Sc, Ti, Cr, Ni, Al, or the like is used as an n-type metal for forming the first source / drain metal layer 114 and the second source / drain metal layer 118. In some embodiments, Nb, Pd, Pt, Au, or the like is used as a p-type metal for forming the first source / drain metal layer 114 and the second source / drain metal layer 118. The n-type or p-type metal layer may be formed by a suitable formation method such as CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. In some alternative embodiments, the source / drain metal layers 114 and 118 comprise different metal materials.Next, referring to FIG. 3, a plurality of openings 10 are formed in the layer stack 110 to expose the substrate 101. That is, the openings 10 penetrate the layer stack 110 and the substrate 101 is exposed at the bottoms of the openings 10. Additionally, the openings 10 expose sidewalls of the dielectric layers 112, 116 and sidewalls of the conductive layers 114, 118. It should be noted that in the present discussion, a sidewall of the layer stack 110 includes the corresponding sidewalls of all constituent layers (e.g., 112, 114, 116, and 118) of that layer stack. For example, a sidewall of the layer stack 110 exposed by the opening 10 includes the sidewalls of the dielectric layers 112, 116 and the sidewalls of the conductive layers 114, 118 exposed by the opening 10.In some embodiments, the openings 10 are formed by an anisotropic etching process, such as a plasma etching process. A mask pattern, such as a patterned resist, may be formed on the layer stack 110. The anisotropic etching process may then be performed using the mask pattern as an etch mask to form the openings 10. After the anisotropic etching process is completed, the mask pattern (e.g., patterned photoresist) may be removed by a suitable removal process such as ashing or stripping.Referring to FIG. 4, a channel layer 120 is first formed to cover the sidewalls of the openings 10. In some embodiments, the channel layer 120 is formed by depositing a channel material conformally covering the bottoms and sidewalls of the openings 10 and further covering the top surface of the conductive layer 118; and then performing an anisotropic etching process to remove the channel material at the bottoms of the openings 10 and at the top surface of the conductive layer 118. In this case, the channel layer 120 may have a rounded or curved top surface adjacent to the conductive layer 118. In some embodiments, the channel layer 120 may have a flat top surface, as shown in FIG. 4.In some embodiments, the channel layer 120 may include a metal oxide such as indium gallium zinc oxide (IGZO) formed by a suitable formation method such as PVD, CVD, ALD, or the like. Other suitable materials for the channel layer 120 include zinc oxide (ZnO), indium tungsten oxide (IWO), tungsten oxide (WO), tantalum oxide (TaO), and molybdenum oxide (MoO). In an exemplary embodiment, dielectric layers 112 and 116 are formed of SiO 2 conductive layers 114 and 118 are formed of tungsten (W), and channel layer 120 is formed of IGZO.Next, as shown in FIG. 4, a ferroelectric layer 122 is formed in the openings 10 to cover the channel layer 120. The ferroelectric layer 122 may include a ferroelectric material such as HZO, HSO, HfSiO, HfLaO, HfO 2, HfZrO 2, ZrO 2 or HfO 2, which are doped with La, Y, Si or Ge, and may be formed by PVD, CVD, ALD or the like. In some embodiments, the ferroelectric layer 122 is formed by depositing a ferroelectric material conformally covering the channel layer 120, the bottom of the openings 10, and further covering the top surface of the conductive layer 118; and then performing an anisotropic etching process to remove the ferroelectric material at the bottoms of the openings 10 and at the top surface of the conductive layer 118. In this case, the ferroelectric layer 122 may have a rounded or curved top surface.Thereafter, as shown in FIG. 4, a conductive material is formed to fill the openings 10. The conductive material may include copper, tungsten, cobalt, aluminum, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cadmium, zinc, alloys thereof, combinations thereof, and the like, and may be formed by a suitable deposition method such as CVD, PVD, ALD, plating, or the like. After the conductive material is formed, a planarization process, such as a chemical mechanical planarization (CMP) process, may be performed to remove excess portions of the conductive material from the top surface of the conductive layer 118. In this case, the remaining portions of the conductive material in the openings 10 form conductive pillars 124 (also referred to as gate electrodes 124).After forming the conductive pillars 124, as shown in FIG. 4, a plurality of gate structures 125 formed in the openings 10 are achieved. In detail, each gate structure 125 may include the channel layer 120, the ferroelectric layer 122, and the conductive pillar 124. The ferroelectric layer 122 surrounds the conductive column 124. The ferroelectric layer 122 is sandwiched between and in physical contact with the channel layer 120 and the conductive pillar 124. The channel layer 120 is arranged between the layer stack 110 and the ferroelectric layer 122. That is, the channel layer 120 (or gate structures 125) is(are) surrounded by the dielectric layers 112, 116 and the conductive layers 114, 118.Referring to FIG. 5, a portion of the conductive layer 118 and a portion of the dielectric layer 116 are removed by one or more etch processes (e.g., anisotropic etch processes) using an etch mask to form a staircase region 150. The etch time for each of the etch processes may be adjusted to achieve a different amount (e.g., depth) of the etch.As shown in FIG. 5, after the staircase-shaped region 150 is formed, a portion of the upper surface of the conductive layer 114 is exposed. In the example of FIG. 5, the dielectric layer 112 and the conductive layer 114 have the same width W 1. The dielectric layer 116 and the conductive layer 118 have a same width W2that is less than the width W1. That is, the conductive layer 118 in the staircase region 150 has a sidewall aligned along the same line with a respective sidewall of the dielectric layer 116. In addition, the respective widths of the conductive layers 114 and 118 increase in a direction toward the substrate 101 so that the upper conductive layer 118 has a width smaller than a width of the lower conductive layer 114. The staircase portion 150 facilitates access to the conductive layer 114 for the subsequently formed contacts 128 (see FIG. 6A).Referring to FIG. 6A, a dielectric material 126 is formed over the structure of FIG. 5. A plurality of contacts 128 (also referred to as contact plugs) are formed in the dielectric material 126 and electrically coupled to the conductive pillars 124 or the conductive layers 114 and 118. In some embodiments, contacts 128 electrically coupled to conductive pillars 124 are also referred to as gate contacts 128G, and contacts 128 electrically coupled to conductive layers 114 and 118 are also referred to as source / drain contacts 128SD. In some embodiments, a length of the source / drain contact 128SD contacting the conductive layer 114 is greater than a length of the source / drain contact 128SD contacting the conductive layer 118.The dielectric material 126 may include an organic dielectric material or an inorganic dielectric material. The organic dielectric material may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. The inorganic dielectric material may be: a nitride such as silicon nitride or the like; an oxide such as silicon oxide; an oxynitride such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or a combination thereof. The dielectric material 126 may be formed by spin coating, lamination, CVD, or the like. Additionally, the contacts 128 may be formed by forming openings in the dielectric material 126 to expose an underlying conductive feature (e.g., 124, 114, or 118), and filling the opening with a conductive material such as copper, tungsten, cobalt, gold, silver, alloys thereof, combinations thereof, or the like.Next, a plurality of connectors 130 (also referred to as conductive connectors or conductive bumps) are formed over and electrically coupled to the contacts 128. The connectors 130 may be solder balls, metal pillars, chip-connection-with-controlled-collapse (C4 bumps), micro bumps, electroless nickel-electroless palladium-immersion-gold (ENEPIG) technique bumps, a combination thereof (e.g., a metal pillar with a solder ball attached thereto), or the like. The connectors 130 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the connectors 130 include a eutectic material and may include, for example, a solder ball or a solder ball. The solder material may be, for example, lead-based and lead-free solders such as Pb-Sn compositions for lead-based solder; lead-free solders including InSn; tin, silver, and copper (SAC) compositions; and other eutectic materials that have a common melting point and form conductive solder joints in electrical applications. The connectors 130 may form a grid, such as a ball grid array (BGA). In some embodiments, a reflow process may be performed that gives the connectors 130 the shape of a partially-shaped sphere in some embodiments. Alternatively, the connectors 130 may have other shapes. The connectors 130 may also include non-spherical conductive connectors.In some embodiments, the connectors 130 include metallic elements (such as copper pillars or copper lines) formed thereon by sputtering, printing, electroplating, electroless plating, CVD, or the like, with or without solder material. The metal pillars may be solder free and have substantially vertical sidewalls or tapered sidewalls.Figure 6B shows the 3D memory device of Figure 6A but taken along the cross-section I-I' in Figure 6A. In the cross-sectional view of FIG. 6B, the ferroelectric layer 122 surrounds (e.g., surrounds) the conductive pillar 124, and the channel layer 120 surrounds the ferroelectric layer 122. The area to the right of the dashed line 160 corresponds to the staircase shaped area 150 of the 3D memory device 100.As shown in FIG. 6A, the dashed box in FIG. 6A shows a memory cell 140 of the 3D memory device 100. The 3D memory device 100 includes a plurality of such memory cells. The memory cell 140 includes the gate structure 125 penetrating the layer stack 110 and the conductive layers 114 and 118 (hereinafter referred to as S / D layers 124). The gate structure 125 may include the conductive pillar 124 (hereinafter referred to as gate electrode 124), the ferroelectric layer 122 enclosing the gate electrode 124, the channel layer 120, and the channel layer 120 between the layer stack 110 and the ferroelectric layer 122. The channel layer 120 is arranged between the S / D layers 114 and 118 of the layer stack 110, wherein each of the memory cells 140 of the 3D memory device 100 is a transistor with the ferroelectric layer 122 in the embodiment shown. The dashed arrows 145 in FIG. 6A show possible current flow directions in the channel layer 120 when the transistor of the memory cell is turned on.In the example of FIG. 6A, two memory cells are depicted side by side. To avoid disorder, in addition to the memory cell 140, the other memory cells are not identified by dashed boxes. The memory cell 140 may be programmed (e.g., written to and / or read from) via connectors 130 electrically connected to the gate and S / D terminals of the transistor of the memory cell, e.g., connectors 130 labeled Vg1, Vs1, and Vd1. Similarly, connectors 130 labeled Vg2, Vs1, Vd1may be used to program another memory cell that is located adjacent to memory cell 140.To perform a write operation on a particular memory cell, e.g., memory cell 140, a write voltage is applied across a portion of the ferroelectric layer 122 corresponding to the memory cell 140. The write voltage may be applied, for example, by applying a first voltage to the gate electrode 124 of the memory cell 140 (via connector 130 labeled Vg1and applying a second voltage to the S / D layers 114 and 118 (via connectors 130 labeled Vs1or Vd1. The voltage difference between the first voltage and the second voltage determines the polarization direction of the ferroelectric layer 122. Depending on the polarization direction of the ferroelectric layer 122, the threshold voltage V T of the corresponding transistor of the memory cell 140 may be switched from a low threshold voltage V L to a high threshold voltage V H or vice versa. The threshold voltage value (V L or V H) of the transistor may be used to indicate a bit of "0" or "1" stored in the memory cell.To perform a read operation on the memory cell 140, a read voltage that is a voltage between the low threshold voltage V L and the high threshold voltage V H is applied to the transistor, e.g., between the gate electrode 124 and the second S / D layer 118. Depending on the polarization direction of the ferroelectric layer 122 (or the threshold voltage of the transistor), the transistor of the memory cells 140 may or may not be turned on. As a result, when a voltage is applied, e.g., to the first S / D layer 114, an electric current may or may not flow between the first S / D layer 114 and the second S / D layer 118 through the channel layer 120. The electrical current can thus be detected in order to determine the digital bit stored in the memory cell.Note that in the present embodiment, the gate structure 125 is vertically disposed on the substrate 101 and penetrates the layer stack 110 such that the S / D layers 114 and 118 wrap or surround the gate structure 125, thereby forming a similar gate all-round memory device (GAA). In this case, the memory cells are surrounded by the S / D layers 114 and 118 disposed on the same plane, so that the memory cells share the same S / D voltage (Vs1 or Vd1), thereby simplifying the routing layout of the S / D layers. Further, the memory device of the present embodiment can effectively use the area of the chip in the horizontal direction and increase the integration density of the memory device, as compared with the planar memory device, thereby facilitating miniaturization of the chip.While the disclosed embodiments illustrate the process of forming the S / D layers 114 and 118, these embodiments are illustrative and not limiting as another example. In alternative embodiments, the S / D layers 114 and 118 may be formed by a replacement process. Specifically, the layer stack including a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer stacked in this order is formed on the substrate 101. The openings 10 are formed in the layer stack to expose the substrate 101. The gate structures 125 are formed in the openings 10, respectively. One or more slits are formed adjacent the openings 10 and penetrate through the stack of layers. The first and second nitride layers are then replaced with the source / drain (S / D) material such as W, Ru, or the like. In some embodiments, the replacement process includes the steps of: removing the first and second nitride layers by an etching process, such as a wet etching process, to form multiple gaps between the first and second oxide layers; and filling the S / D material into the gaps between the first and second oxide layers to form the S / D layers 114 and 118. Prior to the replacement process, the portions of the S / D layers 114 and 118 are removed to form the staircase region 150.FIG. 7A is a cross-sectional view of a 3D memory device 300 according to a second embodiment. FIG. 7B is a plan view taken along a cross section II-II' of FIG. 7A. The 3D memory device 200 is similar to the 3D memory device 100 of FIG. 6A, but with additional processing to increase (e.g., double) the memory cell density.In some embodiments, to form the 3D memory device 200, the processing steps in FIGS. 1 to 5 are performed for the 3D memory device 100. Next, a slit-shaped opening is formed in each of the conductive pillars 124. The slit-shaped opening vertically extends from an upper surface of the conductive column 124 distal from the substrate 101 to a lower surface of the conductive column 124 directly facing the substrate 101. In a plan view, the slot-shaped opening extends along a diameter of the conductive pillar 124, for example, and separates the conductive pillar 124 into two separate gate pillars 124A and 124B (hereinafter referred to as gate electrodes). The slit-shaped opening also extends into the ferroelectric layer 122 and the channel layer 120 and intersects the ferroelectric layer 122 into two separate segments 122A and 122B, and further intersects the channel layer 120 further into two separate segments 120A and 120B in the illustrated example of FIG. 7B. That is, the slit-shaped opening intersects the gate structure 125 into two separate segments 125A and 125B.In addition, as shown in FIG. 7A, each of the gate electrodes 124A and 124B has an upper portion extending along an upper surface of the ferroelectric layer 122, and therefore the conductive pillar 124A (or 124B) has an L-shaped cross section. The upper portion of the gate electrodes 124A and 124B allows more flexibility in selecting the positions of the connectors 130 coupled to the gate electrodes In some alternative embodiments, the upper portions of the gate electrodes 124A and 124B may be omitted if the width of the gate electrodes 124A and 124B embedded in the stack layer 110 is large enough to be coupled to the connectors 130.Next, as shown in FIG. 7A, a dielectric material 127 such as silicon oxide, silicon nitride, or the like is formed to fill the slit-shaped openings. The dielectric material 127 may be referred to as an isolation structure to electrically isolate the gate electrodes 124A and 124B. Thereafter, the dielectric material 126 is formed over the conductive layer 118 and the contacts 128 are formed in the dielectric material 126 to electrically couple with the respective underlying conductive features (e.g., the gate electrodes 124A / 124B or the S / D layers 114 / 118). Next, the connectors 130 are formed over and electrically coupled to the respective contacts 128. FIG. 7B shows the cross-sectional view of the 3D storage device 200 of FIG. 7A, but along the cross-section II-II" in FIG. 7A. In some embodiments, the filling of the slit-shaped openings and the formation of the dielectric material 126 are performed together in the same deposition process, and therefore the dielectric material 127 filling the slit-shaped openings is the same as the dielectric material 126 over the conductive layer 118. However, embodiments of the present disclosure are not limited thereto, in other embodiments, the dielectric material 127 and the dielectric material 126 may be formed in different deposition processes and include different dielectric materials.Due to the dielectric material 127 separating the conductive pillar 124 into two separate, independently controlled (e.g., with different gate voltages) gate electrodes 124A and 124B, the number of memory cells in the 3D memory device 200 is twice as large as that of the 3D memory device 100. The dashed boxes 140A and 140B in FIG. 7A show two memory cells formed in a region corresponding to the memory cell 140 in FIG. 6A. As shown in FIG. 7A, each of the memory cells 140A / 140B is half as large as the memory cell 140 in FIG. 6A. In the example of FIG. 7A, there are four connectors 130 (labeled Vg1, Vg2, Vg3, and Vg4), each of which is electrically coupled to a gate of a transistor of a memory cell. In addition, there are two connectors 130 labeled Vs1and Vd1, the two connectors 130 being coupled to the S / D layers 114 and 118 of a transistor of a memory cell. Thus, the example of FIG. 7A shows four memory cells, wherein each of the memory cells may be programmed by applying appropriate voltages to the gate and S / D terminals of the transistor of each memory cell.FIG. 8 is a cross-sectional view of a 3D memory device 300 according to a third embodiment.The 3D memory device 300 is similar to the 3D memory device 100 of FIG. 6A, but the connectors 130 labeled Vg1and Vg2in FIG. 6A are replaced with electrically conductive features 136 in the substrate 101. The electrically conductive features 136 may be formed as a portion of the interconnect structures of the substrate 101. Additionally, electrically conductive regions 132 are formed in the substrate 101 under (e.g., directly below and with physical contacts) and electrically coupled to the gate electrodes 124. In some embodiments, the electrically conductive regions 132 are epitaxial regions comprising epitaxially grown semiconductor material. In some embodiments, the electrically conductive regions 132 are doped regions, e.g., semiconductor regions doped with an n-type or p-type dopant. FIG. 8 also shows an electrical path 134, such as a conductive line in the substrate 101, connecting the electrically conductive features 136 to the respective electrically conductive regions 132. The electrical path 134 may be conductive lines in the interconnect structures of the substrate 101. The gate voltages of the 3D memory device 300 are applied to the gate electrodes 124 via the electrically conductive feature 136.FIG. 9 is a cross-sectional view of a 3D memory device 400 according to a fourth embodiment.The 3D storage device 400 is similar to the 3D storage device 300 of FIG. 8. However, the electrically conductive regions 132 are electrically connected to the connectors 138 at the bottom surface of the substrate 101 by another electrical path 135, such as through substrate vias (TSVs). Therefore, the gate voltages of the 3D memory device 400 are applied to the connectors 138.It should be noted that, in some embodiments, the gate voltages of the 3D memory device 300 or 400 may be applied from the interconnect structures of the substrate 101, thereby simplifying the routing layout of the gate electrode. In addition, the disclosed embodiments enable simple modification to increase the number of memory cells in the memory device, thereby improving the memory cell density. The disclosed formation methods for the 3D memory devices can be easily integrated into an existing BEOL process, thereby enabling integration of memory devices into various semiconductor devices at low production costs.FIGS. 10 to 16 are cross-sectional views of a method of forming a 3D memory device 500 according to a fifth embodiment. The 3D memory device 500 is similar to the 3D memory device 100 of FIG. 6A, but with additional processing to increase (e.g., double) the memory cell density.In some embodiments, to form the 3D storage device 500, the processing steps in FIGS. 1 to 6A are performed for the 3D storage device 100. Next, referring to FIG. 10, a dielectric material 226 ais formed over the structure of FIG. 6A. In some embodiments, the dielectric material 226 amay include an organic dielectric material or an inorganic dielectric material. The organic dielectric material may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. The inorganic dielectric material may be: a nitride such as silicon nitride or the like; an oxide such as silicon oxide; an oxynitride such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or a combination thereof. The dielectric material 226 amay be formed by spin coating, lamination, CVD, or the like.Referring to FIG. 11, a plurality of contacts 228 a(also referred to as contact plugs) are formed in the dielectric material 226 aand electrically coupled to the connectors 130 denoted Vs 1 and Vd 1. In some embodiments, contacts 228 amay be formed by forming openings in dielectric material 226 ato expose underlying connectors 130 labeled Vs 1 and Vd 1, and filling the openings with a conductive material such as copper, tungsten, cobalt, gold, silver, alloys thereof, combinations thereof, or the like. After the conductive material is formed, a planarization process such as a CMP process may be performed to remove excess portions of the conductive material from the top surface of the dielectric material 226 a.Referring to FIG. 12, a conductive layer 214 and a dielectric layer 212 are sequentially formed on the dielectric material 226 a. The conductive layer 214 and the dielectric layer 212 are then patterned to expose the top surface of the contact 228a, denoted Vd1, in the staircase region 150, while the contact 228a, denoted Vs1, is covered by the conductive layer 214 and the dielectric layer 212. The structure, material, and function of the conductive layer 214 and / or the dielectric layer 212 are similar to those of the conductive layer 114 and / or the dielectric layer 112 and have been described in the above embodiment, therefore the details are omitted here.Referring to FIG. 13, a dielectric material 226 bis formed adjacent to the conductive layer 214 and the dielectric layer 212 and covers the dielectric material 226 a. On the contact 228a, a contact 228b is formed which is connected to the connector 130 denoted by Vd1. That is, the contact 228a is extended to reach the height of the upper surface of the dielectric layer 212. The dielectric material 226 band the dielectric material 226 amay include the same dielectric material, such as SiO 2. In other words, the dielectric materials 226 aand 226 bmay be referred to as the same dielectric layer or film 226. In addition, the contacts 228 aand 228 bmay include the same metal material as Cu. In other words, contacts 228 aand 228 bmay be referred to as the same contact plug or conductive via 228. In some embodiments, a length of the contact 228 contacting the connector 130 labeled Vd 1 is greater than a length of the contact 228 athat contacts the connector 130 labeled Vs 1.Referring to FIG. 14, a conductive layer 218 and a dielectric layer 216 are sequentially formed on the dielectric material 226 band the conductive layer 214, thereby forming a layer stack 210. In particular, the conductive layer 218 is in physical contact with the contact plug 228 coupled to the connector 130 labeled Vd 1. On the other hand, conductive layer 214 is in physical contact with contacts 228 connected to connector 130, labeled Vs1. In the example of FIG. 14, the dielectric layer 212 and the conductive layer 214 have the same width W 3. The dielectric layer 216 and the conductive layer 218 have an equal width W 4 that is greater than the width W 3. That is, the conductive layer 214 in the staircase region 150 has a sidewall aligned along the same line with a respective sidewall of the dielectric layer 212.The structure, material, and function of the conductive layer 218 and / or the dielectric layer 216 are similar to those of the conductive layer 118 and / or the dielectric layer 116 and have been described in the above embodiment, thus the details are omitted here.Referring to FIG. 15, a plurality of gate structures 225 are formed in a plurality of openings 20 penetrating through the layer stack 210, respectively. In detail, each gate structure 225 may include a channel layer 220, a ferroelectric layer 222, and a conductive pillar 224. The ferroelectric layer 222 surrounds the conductive column 224. The ferroelectric layer 222 is disposed between and in physical contact with the channel layer 220 and the conductive pillar 224. The channel layer 220 is arranged between the layer stack 210 and the ferroelectric layer 222. The channel layer 220 (or gate structures 225) is surrounded by the dielectric layers 212, 216 and the conductive layers 214, 218. The structures, materials, and functions of the channel layer 220, the ferroelectric layer 222, and the conductive pillar 224 are similar to those of the channel layer 120, the ferroelectric layer 122, and the conductive pillar 124, and have been described in the above embodiment, so the details are omitted herein.Referring to FIG. 16, a dielectric material 227 is formed over the structure of FIG. 15. A plurality of contacts 229 (also referred to as contact plugs) are then formed in the dielectric material 227 and electrically coupled to the conductive pillars 224. In some embodiments, contacts 229 electrically coupled to conductive pillars 224 are also referred to as gate contacts 229G. Next, a plurality of connectors 230 (also referred to as conductive connectors or conductive bumps) are formed over and electrically coupled to the contacts 229. The structures, materials, and functions of the dielectric material 227, the contacts 229, and the connectors 230 are similar to those of the dielectric material 126, the contacts 128, and the connectors 130 and have been described in the above embodiment, and therefore the details are omitted here.As shown in FIG. 16, after the connectors 230 are formed, the memory device 500 is completed. In detail, the storage device 500 may include a first layer T 1 on the substrate 101 and a second layer T 2 stacked over the first layer T 1. The first layer T 1 may include the first layer stack 110 and the first gate structures 125 penetrating the first layer stack 110. The second layer T 2 may include the second layer stack 210 and the second gate structures 225 penetrating the second layer stack 210. The memory device 500 further includes a first electrical path P 1 and a second electrical path P 2 in the staircase region 150 between the first layer T 1 and the second layer T 2. The first electrical path P 1 is electrically connected to the conductive layers 114 and 218 and receives a first S / D voltage from the connector 130 labeled Vd 1. The second electrical path P2 is electrically connected to the conductive layers 118 and 214 and receives a second S / D voltage from the connector 130, labeled Vs1. That is, the conductive layers 114 and 218 share the first S / D voltage, while the conductive layers 118 and 214 share the second S / D voltage that is different than the first S / D voltage.In addition, the dashed box in FIG. 16 also shows a memory cell 240 of the 3D memory device 500. The 3D memory device 500 includes a plurality of such memory cells. The memory cell 240 includes the second gate structure 225 penetrating the second layer stack 210 and the conductive layers 214 and 218 (hereinafter referred to as S / D layers 224). The second gate structure 225 may include the conductive pillar 224 (hereinafter referred to as gate electrode 224), the ferroelectric layer 222 enclosing the gate electrode 224, the channel layer 220, and the channel layer 220 between the second layer stack 210 and the ferroelectric layer 222. Since the channel layer 220 is arranged between the S / D layers 214 and 218 of the second layer stack 210, each of the memory cells 240 of the 3D memory device 500 is a transistor with the ferroelectric layer 222 in the embodiment shown. The dashed arrows 245 in FIG. 16 illustrate possible current flow directions in the channel layer 220 when the transistor of the memory cell is turned on.Due to the second layer T 2 including the memory cells 240 stacked over the first layer T 1 including the memory cells 140, the number of the memory cells in the 3D memory device 500 is twice as large as that of the 3D memory device 100. In the example of FIG. 16, four memory cells are illustrated. To avoid disorder, in addition to the memory cells 140 and 240, the other memory cells are not indicated by dashed boxes. The memory cell 140 may be programmed (e.g., written to and / or read from) via connectors 130 electrically coupled to the gate and S / D terminals of the transistor of the memory cell, e.g., connectors 130 labeled Vg1, Vs1, and Vd1. Similarly, connectors 130 labeled Vg2, Vs1, Vd1may be used to program another memory cell that is located adjacent to memory cell 140. The memory cell 240 may be programmed via connectors 230 and 130, where connector 230 is electrically coupled to the gate terminal of the transistor of the memory cell, e.g., connector 230 labeled Vg3, and connectors 130 are electrically coupled to the S / D terminals of the transistor of the memory cell, e.g., connectors 130 labeled Vs1 and Vd1. Similarly, connectors 230 labeled Vg2and connectors 130 labeled Vs1, Vd1may be used to program another memory cell that is located adjacent memory cell 240. In some embodiments, the gate structures 125 and 225 are electrically independent of each other, so that the routing layout and operation are more flexible.It should be noted that, in the present embodiment, the memory cells 240 are stacked on the memory cells 140 to allow simple modification to increase the number of memory cells in the memory device, thereby improving the memory cell density. In addition, the dielectric material 226 ais disposed between the memory cells 140 and 240 to reduce or eliminate the leakage current between two vertically adjacent memory cells 140 and 240, thereby improving the device performance. While the disclosed embodiments illustrate two layers T 1 and T 2 over the substrate 101, these embodiments are illustrated as another example. If more than two layers are formed over the substrate 101, it would be possible to form more memory cells in the 3D memory device.FIG. 17 is a cross-sectional view of a 3D storage device 600 according to a sixth embodiment.The 3D storage device 600 is similar to the 3D storage device 500 of FIG. 16, that is, the structures, materials, and functions of the 3D storage device 600 are similar to those of the 3D storage device 500 and have been described in the above embodiment, so the details are omitted here. The main difference between the 3D memory devices 500 and 600 is that the gate structures 225 and 125 share the same gate voltage (Vg 1 or Vg 2) across a third electrical path P 3 between the memory cells 140 and 240, thereby simplifying circuit complexity.FIG. 18 is a cross-sectional view of a 3D memory device 700 according to a seventh embodiment.The 3D storage device 700 is similar to the 3D storage device 500 of FIG. 16, that is, the structures, materials, and functions of the 3D storage device 700 are similar to those of the 3D storage device 500, and have been described in the above embodiment, so the details are omitted here. The main difference between the 3D memory devices 500 and 700 is that the conductive layers 114, 118, 214, and 218 of the memory device 700 are electrically independent of each other.Specifically, the memory device 700 includes a second layer T2' stacked over the first layer T1. The second layer T2' may include a second layer stack 210' including the dielectric layer 212, the conductive layer 214, the dielectric layer 216, and the conductive layer 218 sequentially formed on the dielectric material 226a. In the example of FIG. 18, the dielectric layer 212 and the conductive layer 214 have the same width W 5. The dielectric layer 216 and the conductive layer 218 have an equal width W 6 that is less than the width W 5. That is, the conductive layer 218 in the staircase region 150 has a sidewall aligned along the same line with a respective sidewall of the dielectric layer 216. The second gate structures 225 penetrate the second layer stack 210'. The dielectric material 227 is formed over the second layer stack 210' and the second gate structures 225. The contacts 229 are formed in the dielectric material 227 and electrically coupled to the conductive pillars 224 or the conductive layers 214 and 218. In some embodiments, contacts 229 electrically coupled to conductive pillars 224 are also referred to as gate contacts 229G, and contacts 229 electrically coupled to conductive layers 214 and 218 (hereinafter, S / D layers) are also referred to as source / drain contacts 229SD. The connectors 230 are formed over and electrically coupled to the contacts 229.In the example of FIG. 18, there are four connectors 130 and 230 (denoted by Vg 1, Vg 2, Vg 3, and Vg 4), each of which is electrically coupled to a gate of a transistor of a memory cell. In addition, there are two connectors 130 labeled Vs1and Vd1, the two connectors 130 being coupled to the S / D layers 114 and 118 of a transistor of a memory cell. Further, there are two connectors 230 denoted Vs2 and Vd2, the two connectors 230 being connected to the S / D layers 214 and 218 of a transistor of a memory cell. Thus, the example of FIG. 18 shows four memory cells, wherein each of the memory cells may be programmed by applying appropriate voltages to the gate and S / D terminals of the transistor of each memory cell.It is noted that although only two planes T1 and T2' are illustrated in FIG. 18, the embodiments of the present disclosure are not limited thereto. In other embodiments, more than two levels may be formed over the substrate 101. This would allow more memory cells to be formed in the 3D memory device. The disclosed formation methods for the 3D memory devices can be easily integrated into an existing BEOL process, thereby enabling integration of memory devices into various semiconductor devices at low production costs.Moreover, the first layer T 1 of the 3D memory devices 500, 600, and 700 may be replaced with the structure 400 illustrated in FIG. 9. In this case, another layer stack may be stacked under the bottom surface of the substrate 101, thereby increasing the memory cell density.FIG. 19 shows a flow diagram 1000 of a method for forming a memory device, in accordance with some embodiments. It is understood that the execution method shown in FIG. 19 is only one example of many possible execution methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as shown in FIG. 19 may be added, removed, replaced, rearranged, or repeated.Referring to FIG. 19, in block 1010, a stack of the first layer is formed over a substrate, the stack of the first layer including a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer stacked in sequence. At block 1020, a first opening is formed in the stack of the first layer to penetrate through the stack of the first layer. At block 1030, a first gate structure is formed in the first opening. At block 1040, a portion of the second conductive layer and a portion of the second dielectric layer are removed to expose a portion of the first conductive layer, thereby forming a staircase region. At block 1050, a stack of the second layer is formed on the stack of the first layer, the stack of the second layer including a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer stacked in sequence. At block 1060, a first electrical path and a second electrical path are formed in the staircase region between the stacks of the first and second layers, respectively, the first electrical path being electrically connected to the first and fourth conductive layers and the second electrical path being electrically connected to the second and third conductive layers. At block 1070, a second opening is formed in the stack of the second layer to penetrate the stack of the second layer. At block 1080, a second gate structure is formed in the stack of the second layer, wherein the second gate structure and the first gate structure are electrically independent of each other.According to an embodiment, the memory device comprises a first layer on a substrate and a second layer on the first layer. The first layer includes a first layer stack; a first gate electrode penetrating the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second layer includes a second layer stack; a second gate electrode penetrating the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.According to an embodiment, a method of forming a memory device comprises: forming a first layer stack on a substrate, the first layer stack including a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer stacked in sequence; forming a first opening in the stack of the first layer to penetrate the stack of the first layer; forming a first gate structure in the first opening; removing a portion of the second conductive layer and a portion of the second dielectric layer to expose a portion of the first conductive layer, thereby forming a staircase region; forming a second layer stack on the first layer stack, the second layer stack including a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer stacked in sequence; forming a first electrical path and a second electrical path in the staircase region between the stacks of the first and second layers, respectively, wherein the first electrical path is electrically connected to the first and fourth conductive layers and the second electrical path is electrically connected to the second and third conductive layers; forming a second opening in the second layer stack to penetrate the stack of the second layer; and forming a second gate structure in the stack of the second layer, wherein the second gate structure and the first gate structure are electrically independent of each other.According to an embodiment, a memory device comprises: a layer stack disposed on a substrate, the layer stack comprising a first dielectric layer, a first source / drain (S / D) layer, a second dielectric layer and a second S / D layer stacked in sequence; a first conductive pillar penetrating the layer stack; a first ferroelectric layer enclosing the first conductive pillar; and a first channel layer disposed between the layer stack and the first ferroelectric layer, the first ferroelectric layer being in contact with the first channel layer and the first conductive pillar.

Claims

A memory device (500, 600, 700) comprising: a first layer arranged on a substrate (101), the first layer comprising: a first layer stack (110); a first gate electrode (124) penetrating the first layer stack (110); a first channel layer (120) arranged between the first layer stack (110) and the first gate electrode (124); and a first ferroelectric layer (122) arranged between the first channel layer (120) and the first gate electrode (124); and a second layer arranged on the first layer, the second layer comprising: a second layer stack (210, 210'); a second gate electrode (224) penetrating the second layer stack (210); a second channel layer (220) disposed between the second layer stack (210) and the second gate electrode (224); and a second ferroelectric layer (222) disposed between the second channel layer (220) and the second gate electrode (224).The memory device (500, 600, 700) of claim 1, wherein the first layer stack (110) comprises: a first dielectric layer (112); a first conductive layer (114) disposed on the first dielectric layer (112); a second dielectric layer (116) disposed on the first conductive layer (114); and a second conductive layer (118) disposed on the second dielectric layer (116), wherein the first channel layer (120) is in contact with the first dielectric layer (112), the first conductive layer (114), the second dielectric layer (116), and the second conductive layer (118).The memory device (500, 600, 700) of claim 2, wherein the first dielectric layer (112) and the first conductive layer (114) have a first width, the second dielectric layer (116) and the second conductive layer (118) have a second width, and the second width is less than the first width.The memory device (500, 600, 700) of claim 2 or 3, wherein the second layer stack (210) comprises: a third conductive layer (214) disposed over the second conductive layer (118); a third dielectric layer (212) disposed on the third conductive layer (214); a fourth conductive layer (218) disposed on the third dielectric layer (212); and a fourth dielectric layer (216) disposed on the fourth conductive layer, wherein the second channel layer (222) is in contact with the third conductive layer (214), the third dielectric layer (212), the fourth conductive layer (218), and the fourth dielectric layer (216).The memory device (500, 600, 700) of claim 4, wherein the third conductive layer (214) and the third dielectric layer (212) have a third width, the fourth conductive layer (218) and the fourth dielectric layer (216) have a fourth width, and the fourth width is greater than the third width.The memory device (500, 600, 700) of claim 4 or 5, wherein the first and fourth conductive layers (114, 218) are connected to a first connector (130) and the second and third conductive layers (118, 214) are connected to a second connector (120) different from the first connector (130).The memory device (600) of claim 4, wherein the first gate electrode (124) and the second gate electrode (224) are connected to a third connector (130).The memory device (700) of claim 2, wherein the second layer stack (210) comprises: a third dielectric layer (212) disposed over the second conductive layer (118); a third conductive layer (214) disposed on the third dielectric layer (212); a fourth dielectric layer (216) disposed on the third conductive layer (214); and a fourth conductive layer (218) disposed on the fourth dielectric layer (216), wherein the second channel layer (222) is in contact with the third dielectric layer (212), the third conductive layer (214), the fourth dielectric layer (216), and the fourth conductive layer (218).The memory device (700) of claim 8, wherein the third conductive layer (214) and the third dielectric layer (212) have a third width, the fourth conductive layer (218) and the fourth dielectric layer (216) have a fourth width, and the fourth width is less than the third width.The memory device of claim 7, wherein the first, second, third and fourth conductive layers (114, 118, 214, 218) are electrically independent of one another.A method of forming a memory device (500, 700), comprising: forming a first layer stack (110) on a substrate (101), the first layer stack (110) having a first dielectric layer (112), a first conductive layer (114), a second dielectric layer (116) and a second conductive layer (118) stacked in sequence; forming a first opening (10) in the first layer stack (110) to penetrate the first layer stack (110); forming a first gate structure (125) in the first opening (10); removing a portion of the second conductive layer (118) and a portion of the second dielectric layer (116) to expose a portion of the first conductive layer (114), thereby forming a staircase region (150); forming a second layer stack (210) on the first layer stack (110), the second layer stack (210) comprising a third conductive layer (214), a third dielectric layer (212), a fourth conductive layer (218) and a fourth dielectric layer (216) stacked in sequence; forming a first electrical path (P1) and a second electrical path (P2) in the staircase region (150) between the first and second layer stacks (210), respectively, wherein the first electrical path (P1) is electrically connected to the first and fourth conductive layers (114, 218) and the second electrical path (P2) is electrically connected to the second and third conductive layers (118, 214); forming a second opening (20) in the second layer stack (210) to penetrate the second layer stack (210); and forming a second gate structure (225) in the second layer stack (210), wherein the second gate structure (225) and the first gate structure (125) are electrically independent of each other.The method of claim 11, wherein forming the first gate structure (125) comprises: forming a first channel layer (120) on a sidewall of the first opening (10), the first and second conductive layers (114, 118) surrounding and in physical contact with the first channel layer (120); forming a first ferroelectric layer (122) on the first channel; and filling the first opening (10) with a conductive material to form a first gate electrode (124).The method of claim 11 or 12, wherein forming the second gate structure (225) comprises: forming a second channel layer (220) on a sidewall of the second opening (20), the third and fourth conductive layers (214, 218) surrounding and in physical contact with the second channel layer (220); forming a second ferroelectric layer (222) on the second channel; and filling the second opening (20) with a conductive material to form a second gate electrode (224).The method of any of claims 11 to 13, wherein the first electrical path (P1) comprises a first contact plug (128) in physical contact with the first conductive layer (114), wherein the second electrical path (P2) comprises a second contact plug (128) in physical contact with the second conductive layer (118), and wherein the first contact plug (128) has a length greater than a length of the second contact plug (128).The method of any of claims 11 to 14, wherein the second electrical path (P2) comprises a third contact plug (228) in physical contact with the third conductive layer (214), wherein the first electrical path (P1) comprises a fourth contact plug (128) in physical contact with the fourth conductive layer (218), and wherein the fourth contact plug (128) has a length greater than a length of the third contact plug (128).A memory device (100, 200, 300, 400, 500, 600, 700) comprising: a layer stack (110) disposed on a substrate (101), the layer stack (110) comprising a first dielectric layer (112), a first source / drain layer, S / D layer (114), a second dielectric layer (116), and a second S / D layer (118) stacked in sequence; a first conductive pillar (124) penetrating the layer stack (110); a first ferroelectric layer (122) enveloping the first conductive pillar (124); and a first channel layer (120) disposed between the layer stack (110) and the first ferroelectric layer (122), the first ferroelectric layer (122) being in contact with the first channel layer (120) and the first conductive pillar (124).The memory device (100, 200, 300, 400, 500, 600, 700) of claim 16, wherein a portion of the first S / D layer (114) is exposed by the second dielectric layer (116) and the second S / D layer (118) to form a staircase region (150).The memory device (100, 200, 300, 400, 500, 600, 700) of claim 17, further comprising: a first contact plug (128) disposed on the first S / D layer (114) in the staircase region (150); a second contact plug (128) disposed on the second S / D layer (118) in the staircase region (150), the first contact plug (128) having a length greater than a length of the second contact plug (128); a second conductive pillar (124B) disposed adjacent to the first conductive pillar (124A) and penetrating the layer stack (110); a second ferroelectric layer (122B) enclosing the second conductive pillar (124B); and a second channel layer (120B) disposed between the layer stack (110) and the second ferroelectric layer (122B), wherein the second ferroelectric layer (122B) is in contact with the second channel layer (120B) and the second conductive pillar (124B), and the first and second conductive pillars (124A, B) are electrically independent of each other.The memory device (200) of any of claims 16 to 18, further comprising: an isolation structure (127) embedded in the first conductive pillar (124) to divide the first conductive pillar (124) into two gate pillars (124A,B).The storage device (300, 400) of any one of claims 16 to 19, further comprising: a conductive region (132) disposed in the substrate (101) below the first conductive pillar (124), the conductive region (132) being in contact with a bottom surface of the first conductive pillar; a connector core (136, 138) disposed in the substrate (101) or on a bottom surface of the substrate (101); and an electrical path (134) electrically connected to the conductive region (132) and the connector (136, 138).

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