Controlled ferroelectric storage cells for storage cell arrays and their manufacturing process

Abstract

Semiconductor device (300) comprising: at least one controlled ferroelectric memory cell (200, 201) comprising: - a dielectric material layer (120) arranged over a substrate (110); - a metallic lower electrode (122); and a ferroelectric dielectric layer (130) that contacts a top surface of the metallic lower electrode (122); a pillar semiconductor channel (140) that lies above the ferroelectric dielectric layer (130) and is capacitively coupled to the metallic lower electrode (122) through the ferroelectric dielectric layer (130); a gate dielectric layer (150) that has a horizontal gate dielectric section (150H) that lies above the ferroelectric dielectric layer (130) and a tubular gate dielectric section (150T) that laterally surrounds the pillar semiconductor channel (140);a gate electrode strip (160) comprising a horizontal gate electrode section (160H) located above the horizontal gate dielectric section (150H), and a tubular gate electrode section (160T) laterally surrounding the tubular gate dielectric section (150T); and a metallic top electrode (182) contacting a top surface of the pillar semiconductor channel (140).

Description

BACKGROUND A ferroelectric material is one that can maintain an electrical polarization in the absence of an external electric field. The electrical polarization in a ferroelectric material exhibits a hysteresis effect, which allows a data bit to be encoded as a polarization direction within the material. In a ferroelectric tunnel junction device, a change in the polarization direction causes a change in the tunnel resistance, which can be used to measure the direction of the electrical polarization and extract the value of the data bit stored in the ferroelectric tunnel junction. The state of the art includes US 2019 / 0198525A1 and CN106158877A. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A is a vertical cross-sectional view of an exemplary structure following the formation of CMOS transistors (complementary metal-oxide-semiconductor transistors), metallic interconnect structures embedded in dielectric material layers, and a dielectric material layer at the interconnect via level according to an embodiment of this disclosure.Figure 1B is a vertical cross-sectional view of the first exemplary structure during the formation of the array of fin-back-gate field-effect transistors according to an embodiment of the present disclosure. Figure 1C is a vertical cross-sectional view of the first exemplary structure after the formation of upper-level metal interconnect structures according to an embodiment of the present disclosure. Figure 2A is a horizontal cross-sectional view of the exemplary structure after etching and structuring the first metal conduction trenches in the first dielectric material layer according to an embodiment of the present disclosure. Figure 2B is a vertical cross-sectional view of the exemplary structure along plane B-B' of Figure 2A. Figure 2C is a vertical cross-sectional view of the exemplary structure along plane A-A' of Figure 2A.Figure 3A is a horizontal cross-sectional view of the exemplary structure after the deposition and planarization of a conductive metal material in the first metal conduit trench to form first metal conduits according to an embodiment of the present disclosure. Figure 3B is a vertical cross-sectional view of the exemplary structure along the plane B-B' of Figure 3A. Figure 3C is a vertical cross-sectional view of the exemplary structure along the plane A-A' of Figure 3A. Figure 4A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (that is, the plane B-B') after the deposition of a number of layers, including a ferroelectric dielectric layer and a semiconductor channel material layer, over the first metal conduits and the substrate according to an embodiment of the present disclosure.Figure 4B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after the deposition of a number of layers, including a ferroelectric dielectric layer and a semiconductor channel material layer, over the first metal conductors and the substrate according to an embodiment of the present disclosure. Figure 5A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after the etching and structuring of pillar semiconductor channels of a driven ferroelectric memory cell according to an embodiment of the present disclosure.Fig. 5B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after etching and structuring pillar semiconductor channels of a driven ferroelectric memory cell according to an embodiment of the present disclosure. Fig. 6A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after depositing a gate dielectric layer over the formed pillar semiconductor channels of the driven ferroelectric memory cell according to an embodiment of the present disclosure.Figure 6B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after the deposition of a gate dielectric layer over the formed pillar semiconductor channels of the controlled ferroelectric memory cell according to an embodiment of the present disclosure. Figure 7A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a conductive metal material layer over the formed pillar semiconductor channels and the gate dielectric layer of the controlled ferroelectric memory cell according to an embodiment of the present disclosure.Figure 7B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after the deposition of a conductive metal material layer over the formed pillar semiconductor channels and the gate dielectric layer of the driven ferroelectric memory cell according to an embodiment of the present disclosure. Figure 8A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after structuring the conductive metal material layer to form word lines and gate electrodes of the driven ferroelectric memory cell according to an embodiment of the present disclosure.Figure 8B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after structuring the conductive metal material layer to form word lines and gate electrodes of the controlled ferroelectric memory cell according to an embodiment of the present disclosure. Figure 9A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after depositing a first dielectric material layer over the field-controlled vertical current switch according to an embodiment of the present disclosure.Figure 9B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after the deposition of a first dielectric material layer over the field-controlled vertical current switch according to an embodiment of the present disclosure. Figure 10A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after planarizing the conductive metal material layer, the gate dielectric layer, and the pillar semiconductor channels of the controlled ferroelectric memory cell according to an embodiment of the present disclosure.Figure 10B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after planarizing the conductive metal material layer, the gate dielectric layer, and the pillar semiconductor channels of the driven ferroelectric memory cell according to an embodiment of the present disclosure. Figure 11A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after a selective etching process for vertically removing an upper annular section of the gate electrode strip of the field-controlled vertical current switch according to an embodiment of the present disclosure.Figure 11B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd1 (i.e., the plane A-A') after a selective etching process for vertically removing an upper annular section of the gate electrode strip of the field-controlled vertical current switch according to an embodiment of the present disclosure. Figure 12A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after depositing a conductive metal material to form a bit line of the field-controlled vertical current switch according to an embodiment of the present disclosure.Figure 12B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd1 (i.e., the plane A-A') after the deposition of a conductive metal material to form a bit line of the field-controlled vertical current switch according to one embodiment of the present disclosure. Figure 13A is a vertical cross-sectional view of a second alternative embodiment structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a number of layers, including a ferroelectric dielectric layer, an upper metal electrode layer, and a semiconductor channel material layer, over the first metal conductors and the substrate according to one embodiment of the present disclosure.Figure 13B is a vertical cross-sectional view of the second alternative embodiment structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a number of layers, including a ferroelectric dielectric layer, an upper metal electrode layer, and a semiconductor channel material layer, over the first metal conductors and the substrate according to an embodiment of the present disclosure. Figure 14A is a vertical cross-sectional view of the second alternative embodiment structure along a first horizontal direction hd1 (i.e., the plane B-B') after etching and structuring pillar semiconductor channels of a driven ferroelectric memory cell according to an embodiment of the present disclosure.Figure 14B is a vertical cross-sectional view of the second alternative embodiment structure along a second horizontal direction hd2 (i.e., the plane A-A') after etching and structuring pillar semiconductor channels of a driven ferroelectric memory cell according to an embodiment of the present disclosure. Figure 15A is a vertical cross-sectional view of the structure of the second alternative embodiment along a first horizontal direction hd1 (i.e., the plane B-B') after depositing a conductive metal material to form a bit line of the field-controlled vertical current switch according to an embodiment of the present disclosure.Figure 15B is a vertical cross-sectional view of the second alternative embodiment structure along a second horizontal direction hd1 (that is, the plane A-A') after the deposition of a conductive metal material to form a bit line of the field-controlled vertical current switch according to one embodiment of the present disclosure. Figure 16A is a partial perspective view of the exemplary semiconductor memory device according to various embodiments of the present disclosure. Figure 16B is a schematic top view of the exemplary semiconductor memory device of Figure 16A. Figure 16C is a partial perspective cross-sectional view of the exemplary semiconductor memory device of Figure 16A along the memory structures of the semiconductor memory device. Figure 16D is an enlarged cross-sectional view of a section P of Figure 16C.Figure 17A is a vertical perspective partial cross-sectional view of a semiconductor memory device according to a second embodiment of the present disclosure. Figure 17B is an enlarged cross-sectional view of section P of Figure 17A. Figure 18 is a perspective partial cross-sectional view of a semiconductor memory device according to another embodiment of the present disclosure. Figure 19 is a flowchart showing the steps for forming a semiconductor memory device according to different embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed. Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify descriptions and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly. Unless explicitly stated otherwise, it is assumed that each element with the same reference number has the same material composition and a thickness within the same thickness range. The present disclosure relates to semiconductor devices, and in particular to a vertical field-controlled current selector switch that can operate as a memory cell selector in conjunction with a memory cell device. Various embodiments of the present disclosure may relate to a controlled ferroelectric memory device and methods for its manufacture. Storage devices consist of a grid of independently functioning memory cells formed on a substrate. Storage devices can include volatile or non-volatile (NV) memory cells. Emerging storage technologies aim to store more data at a lower cost than the expensive silicon chips used in mainstream consumer electronics. Such emerging storage devices could be used to replace current storage technologies, such as flash memory, in the near future. While today's resistive random-access memory is generally adequate for its purpose, it is no longer satisfactory in every respect, given the ongoing miniaturization of devices.Emerging non-volatile memory technologies include, for example, resistive random access memory (RRAM or ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) and phase change memory (PCM). RRAM is a type of NV-RAM that operates by changing the resistance of a dielectric solid-state material, often called a memristor. MRAM is a type of NV-RAM that stores data in magnetic domains. Unlike conventional RAM chip technologies, data in MRAM is not stored as electrical charge or current flows, but rather by magnetic storage elements. These elements are formed from two ferromagnetic plates, each capable of accepting a magnetization, separated by a thin insulating layer. One of the plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match that of an external field to store the memory. If the insulating layer is thin enough (typically a few nanometers), electrons can tunnel from one ferromagnet to the other.This configuration is called a magnetic tunnel junction (MTJ) and is the simplest structure for an MRAM bit. Ferroelectric RAM (FeRAM, F-RAM, or FRAM) is a random-access memory similar in structure to dynamic RAM (DRAM), but it uses a ferroelectric dielectric layer instead of a layer of dielectric material to achieve non-volatility. Phase-change memory (also known as PCM, PCME, PRAM, PCRAM, OUM (Ovonic Unified Memory), and C-RAM or CRAM (Chalcogenide RAM)) is a type of non-volatile RAM. PRAMs take advantage of the unique behavior of chalcogenide glass. In older generations of PCM, the heat generated by passing an electric current through a heating element, typically made of titanium nitride (TiN), was used to either rapidly heat and quench the glass, rendering it amorphous, or to hold it within its crystallization temperature range for a period of time, causing it to transition into a crystalline state.PCM also has the ability to achieve a series of independent intermediate states, giving it the capacity to store multiple bits in a single cell. In each of these memory technologies, a selection transistor may be required to energize and select a specific memory cell for a read or write operation. In some memory devices, CMOS transistors can be used as the selection transistor. However, the size limitations of CMOS transistor technology can be the limiting factor in improving the size and memory cell density of memory devices. The various embodiments described here improve the size and memory cell density by forming driven ferroelectric memory devices in BEOL. Fig. 1A is a vertical cross-sectional view of an exemplary structure after the formation of complementary metal-oxide-semiconductor transistors (CMOS transistors), metal interconnect structures embedded in dielectric material layers, and a dielectric material layer at the interconnection via layer prior to the formation of an array of memory structures according to various embodiments of the present disclosure. Fig. 1 illustrates an exemplary structure according to one embodiment of the present disclosure. The exemplary structure comprises complementary metal-oxide-semiconductor transistors (CMOS transistors) and metal interconnect structures formed in dielectric material layers. More precisely, the first exemplary structure comprises a substrate 8 containing a semiconductor material layer 10.The substrate 8 can comprise a bulk semiconductor substrate, such as a silicon substrate, in which the semiconductor material layer extends continuously from a top surface to a bottom surface of the substrate 8, or a semiconductor-on-insulator layer comprising the semiconductor material layer 10 as a top semiconductor layer located above a buried insulator layer (such as a silicon oxide layer). Flat-trench insulation structures 12 containing a dielectric material such as silicon oxide can be formed in a top section of the substrate 8. Suitable doped semiconductor wells, such as p-wells and n-wells, can be formed within any region that may be laterally enclosed by a section of the flat-trench insulation structures 12. Field-effect transistors can be formed on top of the substrate 8.For example, each field-effect transistor can have active source / drain regions 14, a semiconductor channel 15 having a surface section of the substrate 8 extending between the active source / drain regions 14, and a gate structure 20. Each gate structure 20 can include a gate dielectric 22, a gate electrode strip 24, a gate cap dielectric 28, and a dielectric gate spacer 26. An active source / drain region 18 made of a metal-semiconductor alloy can be formed on each active source / drain region 14. Although planar field-effect transistors are illustrated in the drawings, embodiments are expressly considered here in which the field-effect transistors may additionally or alternatively include fin field-effect transistors (FinFET transistors), gate-all-around field-effect transistors (GAA-FET transistors) or any other type of field-effect transistor (FET). The exemplary structure can include a memory array region 50, in which an array of memory elements can subsequently be formed, and a peripheral region 52, in which logic devices supporting the operation of the array of memory elements can be formed. In one embodiment, devices (such as field-effect transistors) in the memory array region 50 can include lower electrode access transistors that provide access to the lower electrodes of the memory cells to be formed subsequently. Upper electrode access transistors that provide access to the upper electrodes of the memory cells to be formed subsequently can be formed in this processing step in the peripheral region 52.Devices (such as field-effect transistors) in the peripheral region 52 can provide functions that may be required for the operation of the array of memory cells to be subsequently formed. More specifically, devices in the peripheral region can be configured to control the programming, erasing, and sensing (reading) operations of the array of memory cells. For example, the devices in the peripheral region can include a sensing circuit and / or an upper electrode bias circuit. The devices formed on the top side of the substrate 8 can include complementary metal-oxide-semiconductor transistors (CMOS transistors) and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.) and are collectively referred to as the CMOS circuit 75. Subsequently, various interconnect-level structures can be formed prior to the formation of an array of fin-back-gate field-effect transistors. These structures are referred to here as lower interconnect-level structures (L0, L1, L2). If a two-dimensional array of TFTs is subsequently formed across two layers of metal conductors at the interconnect level, the lower interconnect-level structures (L0, L1, L2) can comprise an interconnect-level structure L0, a first interconnect-level structure L1, and a second interconnect-level structure L2. The dielectric material layers can, for example, include a dielectric material layer 31A at the contact level, a first dielectric material layer 31B at the metal conductor level, and a second dielectric material layer 32 at the conductor and via level.Various metallic interconnect structures embedded in dielectric material layers can then be formed over the substrate 8 and the devices (such as field-effect transistors).The metallic interconnect structures can include: device contact via structures 41V formed in the dielectric material layer 31A at the contact level (structure L0 at the interconnect level) and contacting a respective component of the CMOS circuit 75; first metal conductor structures 41L formed in the first dielectric material layer 31B at the metal conductor level (structure L1 at the interconnect level); first metal via structures 42V formed in a lower section of the second dielectric material layer 32 at the conductor and via level; second metal conductor structures 42L formed in an upper section of the second dielectric material layer 32 at the conductor and via level (structure L2 at the interconnect level). Each of the dielectric material layers (31A, 31B, and 32) can contain a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metallic interconnect structures (41V, 41L, 42V, and 42L) can contain at least one conductive material, which may be a combination of a metallic lining layer (such as a metallic nitride or a metallic carbide) and a metallic filler material. Each metallic lining layer can contain TiN, TaN, WN, TiC, TaC, and WC, and each metallic filler material component can contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the considered scope of the disclosure may also be used.In one embodiment, the first metal via structures 42V and the second metal conductor structures 42L can be formed as integrated conductor and via structures by a dual damascening process, and the second metal via structures 43V and the third metal conductor structures 43L can be formed as integrated conductor and via structures. The dielectric material layers (31A, 31B, and 32) can be located at a lower level relative to a memory cell array to be subsequently formed. Therefore, the dielectric material layers (31A, 31B, and 32) are referred to here as lower-level dielectric material layers, meaning dielectric material layers located at a lower level with respect to the memory cell array to be subsequently formed. The metal interconnect structures (41V, 41L, 42V, and 42L) are referred to here as lower-level metal interconnect structures.A subset of the metal interconnect structures (41V, 41L, 42V, and 42L) comprises lower-level metal conductors (such as the third metal conductor structure 42L) embedded within the dielectric material layers of a lower level, with top surfaces within a horizontal plane that includes the uppermost surface of the dielectric material layers of a lower level. In general, the total number of metal conductor levels within the dielectric material layers (31A, 31B, and 32) of a lower level can range from 1 to 3. The exemplary structure can comprise various device regions, which may include a memory array region 50 in which at least one array of non-volatile memory cells can subsequently be formed. For example, the at least one array of non-volatile memory cells can comprise resistive random-access memory (RRAM or ReRAM), magnetic / magnetoresistive random-access memory (MRAM), ferroelectric random-access memory (FeRAM), and phase-change memory (PCM). The exemplary structure can also include a peripheral logic region 52 in which electrical connections can subsequently be formed between each array of non-volatile memory cells and a peripheral circuit comprising field-effect transistors. Regions of the memory array region 50 and the logic region 52 can be used to form various elements of the peripheral circuit. Referring to Fig. 1B, an array 95 of non-volatile memory cells and TFT selection devices can be formed in the memory array region 50 above the second structure L2 at the interconnect level. The details of the structure and the processing steps for the array 95 of driven non-volatile ferroelectric memory cells are subsequently described in detail. A third dielectric material layer 33 at the interconnect level can be formed during the formation of the array 95 of driven non-volatile ferroelectric memory cells. The set of all structures formed at the level of the array 95 of non-volatile memory cells and driven ferroelectric memory cell devices is referred to here as a third structure L3 at the interconnect level. Referring to Fig. 1C, third metallic interconnect structures (43V, 43L) can be formed at the interconnect level in the third dielectric material layer 33. These third metallic interconnect structures (43V, 43L) can include second metallic via structures 43V and third metallic conductors 43L. Subsequently, further interconnect-level structures can be formed, referred to here as structures (L4, L5, L6, L7) at an upper interconnect level. For example, the structures (L4, L5, L6, L7) at an upper interconnect level can include a fourth interconnect-level structure L4, a fifth interconnect-level structure L5, a sixth interconnect-level structure L6, and a seventh interconnect-level structure L7.The fourth structure L4 at the interconnect level can have a fourth dielectric material layer 34 at the interconnect level, in which fourth metal interconnect structures (44V, 44L) are formed at the interconnect level, which can include third metal via structures 44V and fourth metal conductors 44L. The fifth structure L5 at the interconnect level can have a fifth dielectric material layer 35 at the interconnect level, in which fifth metal interconnect structures (45V, 45L) are formed at the interconnect level, which can include fourth metal via structures 45V and fifth metal conductors 45L. The sixth structure L6 at the interconnect level can have a sixth dielectric material layer 36 at the interconnect level, in which sixth metal interconnect structures (46V, 46L) are formed at the interconnect level, which can include fifth metal via structures 46V and sixth metal conductors 46L.The seventh interconnect-level structure L7 can include a seventh dielectric material layer 37, in which sixth metal via structures 47V (which are the seventh metal interconnect structures at the interconnect level) and metal bonding pads 47B are formed. The metal bonding pads 47B can be configured for solder bonding (for which C4 bead bonding or wire bonding can be used) or can be configured for metal-to-metal bonding (such as copper-to-copper bonding). Each dielectric material layer at the interconnect level can be designated as an interconnect level dielectric (ILD) 30 (i.e., 31A, 31B, 32, 33, 34, 35, 36, and 37). Each metal interconnect structure at the interconnect level can be designated as a metal interconnect structure 40. Each adjacent combination of a metal via structure and an overlying metal conductor located within the same interconnect level structure (L2–L7) can be formed sequentially as two independent structures using two single-damascene processes, or it can be formed simultaneously as a unitary structure using a dual-damascene process.Each of the metal interconnect structures 40 (i.e., 41V, 41L, 42V, 42L, 43V, 43L, 44V, 44L, 45V, 45L, 46V, 46L, 47V, 47B) can have a respective metallic lining (such as a layer of TiN, TaN, or WN with a thickness in the range of 2 nm to 20 nm) and a respective metallic filler material (such as W, Cu, Co, Mo, Ru, other elemental metals, or an alloy or a combination thereof). Other suitable materials for use as a metallic lining material and metallic filler material are also considered. Various etch stop layers of dielectric material and dielectric capping layers can be inserted between vertically adjacent pairs of ILD layers 30 or can be integrated into one or more of the ILD layers 30. Although the present disclosure is described using an embodiment in which the array 95 of non-volatile memory cells and TFT selectors can be formed as a component of a third structure L3 at the interconnect level, embodiments in which the array 95 of non-volatile memory cells and TFT selectors can be formed as components of any other structure (for example, L1-L7) at the interconnect level are also expressly considered here. Furthermore, although the present disclosure is described using an embodiment in which a set of eight structures is formed at the interconnect level, embodiments in which a different number of structures are used at the interconnect level are also expressly considered here.Furthermore, embodiments in which two or more arrays 95 of non-volatile memory cells and TFT selectors can be arranged within multiple interconnect-level structures in the memory array region 50 are expressly considered here. Although the present disclosure describes an embodiment in which an array 95 of non-volatile memory cells and TFT selectors can be formed in a single interconnect-level structure, embodiments in which an array 95 of non-volatile memory cells and TFT selectors can be formed across two vertically adjacent interconnect-level structures are also expressly considered here. Fig. 2A is a horizontal cross-sectional view of the exemplary structure after etching and structuring first metal conduit trenches in the first dielectric material layer according to one embodiment of the present disclosure. Fig. 2B is a vertical cross-sectional view of the exemplary structure along plane B-B' of Fig. 2A. Fig. 2C is a vertical cross-sectional view of the exemplary structure along plane A-A' of Fig. 2A. With reference to Figs. 2A-2C, a first dielectric material layer 120 can be deposited on a substrate 110. The substrate 110 can be any suitable substrate, such as a semiconductor device substrate. In other embodiments, the substrate 110 can be the third dielectric material layer 33 at the interconnect level, as shown in Fig. 1C.The first dielectric material layer 120 can comprise a dielectric material such as silicon dioxide (SiO2), undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. The first dielectric material layer 120 can be deposited by any one of a range of suitable deposition processes or grown over the ILD layer 30. A photoresist layer (not shown) can be applied over the first dielectric material layer 120 and can be structured to form trenches 121 within regions of the first dielectric material layer 120 in which initial metal conductors can subsequently be formed. For example, the photoresist structure can be formed by depositing a photoresist material and subsequently structuring the deposited photoresist material by phototolithography.The structured photoresist can mask sections of the first dielectric material layer 120 to protect these sections in a subsequent etching process. An etching process can be performed to form first metal conduit trenches 121 in the first dielectric material layer 120. For example, the first dielectric material layer 120 can be etched using any suitable etching process, such as a wet or dry etching process. In one embodiment, each first metal conduit trench 121 can be arranged within an upper section of the first dielectric material layer 120. The first metal conduit trenches 121 can extend laterally along a first horizontal direction hd1 and can be spaced apart from each other laterally along a second horizontal direction hd2, which is perpendicular to the first horizontal direction hd1.The photoresist can then be removed, for example, by ashyming or a chemical process. Fig. 3A is a horizontal cross-sectional view of the exemplary structure after the deposition and planarization of a conductive metal material in the first metal conduit trench to form first metal conduits according to an embodiment of the present disclosure. Fig. 3B is a vertical cross-sectional view of the exemplary structure along plane B-B' of Fig. 3A. Fig. 3C is a vertical cross-sectional view of the exemplary structure along plane A-A' of Fig. 3A. With reference to Figs. 3A-3C, first metal conduits 122 can be formed in the first metal conduit trenches 121. An electrically conductive material can be deposited over the first dielectric material layer 120 to fill the first metal conduit trenches 121.The first metal conductors 122 can be formed from an electrically conductive metal material such as copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, or the like. Other suitable electrically conductive materials are also considered for the first metal conductors 122. The first metal conductors 122 (also referred to as plate conductors or source conductors 122) can be formed by depositing a layer of conductive material using any suitable deposition process.For the purposes of this text, “suitable deposition processes” may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, or similar processes. A planarization process, such as a chemical-mechanical polishing (CMP) process or the like, can then be performed to remove excess electrically conductive metal material from the surface of the first dielectric material layer 120 and to make the top surface of the first metal conductors 122 coplanar with the top surface of the first dielectric material layer 120. In one embodiment, each first metal conductor 122 can be arranged within an upper section of the first dielectric material layer 120. The first metal conductors 122 can extend laterally along a first horizontal direction hd1 and can be spaced apart from each other laterally along a second horizontal direction hd2, which is perpendicular to the first horizontal direction hd1. Fig. 4A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a number of layers, including a ferroelectric dielectric layer 130 and a semiconductor channel material layer 140L, over the first metal conductors 122 and the substrate 110 according to an embodiment of the present disclosure. Fig. 4B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after the deposition of a number of layers, including a ferroelectric dielectric layer 130 and a semiconductor channel material layer 140L, over the first metal conductors 122 and the substrate 110 according to an embodiment of the present disclosure. With reference to Fig. 4A and Fig.4B a layer of ferroelectric (FE) material 130 covering the entire surface can be deposited over the first dielectric material layer 120 and the first metal conductors 122. The ferroelectric dielectric layer (FE) 130 can be formed from any suitable ferroelectric material, for example HfO2, ZrO2, HfZrO2, AlScN, PbZrO3, Pb[ZrxTi1-x]O3, (0 ≤ x ≤) (PZT), Ba-TiO3, PbTiO3, PbNb2O6, LiNbO3, LiTaO3, polyvinylidene fluoride (PVDF), potassium dihydrogen phosphate (KDP), PbMg1 / 3Nb2 / 3O3(PMN), PbSc1 / 2Ta1 / 2O3PbSc1 / 2Ta1 / 2O3(PST), SrBi2Ta2O9(SBT), Bi1 / 2Na1 / 2TiO3Bi1 / 2Na1 / 2TiO3, combinations thereof, or the like. In particular, the ferroelectric dielectric layer 130 can be deposited on the first dielectric material layer 120 in such a way that it covers the first metal conductors 122. A semiconductor material layer 140L can be deposited onto the ferroelectric dielectric layer 130. The semiconductor material layer 140L can contain polysilicon, amorphous silicon, or a semiconducting oxide, such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaOx, InOx, or the like, or other suitable semiconductor materials. In some embodiments, the pillar semiconductor channels 140 can preferably be formed from IGZO. The IGZO can be intrinsic or can contain dopants if necessary. The conductivity range of the semiconductor material layer 140L can be at least from 1 x 10⁻⁵ S / m to 1 S / m and can range from 1 x 10⁻¹⁰ S / m to 1 x 120 S / m, although higher or lower conductivities can also be considered.The semiconductor material layer 140L enables the subsequent formation of a ferroelectrically controlled memory cell to control and select a memory cell formed from the underlying ferroelectric dielectric layer 130. The semiconductor material layer 140L can be deposited using any suitable deposition process. For the purposes of this text, "suitable deposition processes" may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, or the like. Fig. 5A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after etching and structuring pillar semiconductor channels of a driven ferroelectric memory cell according to an embodiment of the present disclosure. Fig. 5B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after etching and structuring pillar semiconductor channels of a driven ferroelectric memory cell according to an embodiment of the present disclosure. With reference to Fig. 5A and Fig. 5B, the semiconductor material layer 140L can be structured to form pillar semiconductor channels 140. For example, a two-dimensional array of etch mask material, such as a photoresist material (not shown), can be deposited over the semiconductor material layer 140L.A photolithography process can transfer a structure onto the photoresist material. By anisotropic etching of unmasked sections of the semiconductor channel material layer 140 selectively to the ferroelectric dielectric layer 130, using the two-dimensional array of etch mask material sections as an etch mask, the remaining sections of the semiconductor channel material layer 140 can be structured to comprise the two-dimensional array of pillar semiconductor channels. In general, a two-dimensional array of pillar semiconductor channels 140 can be formed over the ferroelectric dielectric layer 130. Each row of pillar semiconductor channels 140 is formed over one of the first metal conductors 122 and is capacitively coupled to it. The resulting pillar semiconductor channel 140 can have the form of a column, a pillar, or a nanowire. However, the pillar semiconductor channels 140 are not limited to a specific shape. The pillar semiconductor channel 140 can be oriented vertically with respect to the first dielectric material layer 120. In other words, a longitudinal axis of each pillar semiconductor channel 140 can extend perpendicular to a plane of the first dielectric material layer 120 and / or an underlying semiconductor substrate. After the pillar semiconductor channel 140 has been formed, the photoresist material (not shown) can be removed, for example, by ashyming or a chemical process. After the pillar-semiconductor channel structures 140 have been formed, a two-dimensional array of memory cells 100 can be provided. Each memory cell 100 can have a lower section of a pillar-semiconductor channel 140, a section of the ferroelectric dielectric layer 130 with an area overlap with the pillar-semiconductor channel 140, and a section of a first metal conductor 122 with an area overlap with the pillar-semiconductor channel 140. Thus, the memory cell 100 can be a metal-ferroelectric-semiconductor (MFS) capacitor. As discussed below, the memory cell 100 can also be a metal-ferroelectric-metal capacitor. Furthermore, other memory cell structures 100 can also be considered. For example, memory cell 100 can be formed as a PCM, ReRAM, MRAM or another suitable memory cell structure. Fig. 6A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a gate dielectric layer over the formed pillar semiconductor channels of the driven ferroelectric memory cell according to an embodiment of the present disclosure. Fig. 6B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after the deposition of a gate dielectric layer over the formed pillar semiconductor channels of the driven ferroelectric memory cell according to an embodiment of the present disclosure. With reference to Fig. 6A and Fig. 6B, a gate dielectric layer can be conformally deposited over the ferroelectric dielectric layer 130 and the two-dimensional array of pillar semiconductor channels 140.The gate dielectric layer 150 can be deposited on the ferroelectric dielectric layer 130 such that it covers the pillar semiconductor channels 140. The gate dielectric layer 150 can be formed from any suitable dielectric material, such as silicon oxide or a dielectric material with a high k-value. In this text, “dielectric materials with a high k-value” have a dielectric constant of more than 3.9. Examples of suitable dielectric materials include silicon nitride, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (Hf0.5Zr0.5O2) (HZO)), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium dioxide-aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2) or other suitable dielectric materials. The gate dielectric layer 150 can be formed by any suitable deposition process. For the purposes of this text, "suitable deposition processes" may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, or the like. In various embodiments, the gate dielectric layer 150 can have a thickness thkim in the range of 0.5–5.0 nm, for example 1–4 nm, although greater or lesser thicknesses can also be used. In various embodiments, the pillar semiconductor channel 140 can have a thickness tcim in the range of 1–20 nm, for example 3–15 nm, although greater or lesser thicknesses can also be used. Sections of the gate dielectric layer 150 can extend vertically (for example, perpendicular to a plane of the first dielectric material layer 120) from the first dielectric material layer 120 and form surrounding gate insulators (SGIs) 150A (see Fig. 16D and Fig. 17B), each surrounding the pillar semiconductor channel 140. Fig. 7A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a conductive metal material layer as a gate electrode and word lead over the formed pillar semiconductor channels and the gate dielectric layer of the controlled ferroelectric memory cell according to an embodiment of the present disclosure. Fig. 7B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after the deposition of a conductive metal material layer as a gate electrode and word lead over the formed pillar semiconductor channels and the gate dielectric layer of the controlled ferroelectric memory cell according to an embodiment of the present disclosure. With reference to Fig. 7A and Fig.7B A gate electrode material layer 160L can be deposited on the gate dielectric layer 150 by a conformal or non-conformal deposition process. The gate electrode material layer 160L can be formed from an electrically conductive metal material such as copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, or the like, or other suitable electrically conductive materials. The gate electrode material 160L can be deposited using any suitable electrically conductive material, such as a gate metal, and any suitable deposition process. For the purposes of this text, "suitable deposition processes" may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, or similar processes. Fig. 8A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after structuring the conductive metal material layer to form word lines and gate electrodes of the controlled ferroelectric memory cell according to an embodiment of the present disclosure. Fig. 8B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after structuring the conductive metal material layer to form word lines and gate electrodes of the controlled ferroelectric memory cell according to an embodiment of the present disclosure. Referring to Figures 8A and 8B, the gate electrode material layer 160L can be structured to form gate electrodes 160 and a gate electrode strip. For example, a two-dimensional array of etch mask material, such as a photoresist material 177, can be deposited onto the semiconductor material layer 160L, which lies above the respective gap of pillar semiconductor channels 140. A photolithography process can transfer a structure over the photoresist material 177.By anisotropic etching of unmasked sections of the gate electrode material layer 160 using the two-dimensional array of photoresist material 177 as an etch mask, the remaining sections of the gate electrode material layer 140 can be structured to include the gate electrode 160, which can surround the respective pillar semiconductor channels 140 and the gate dielectric layer 150, as well as gate electrode strips 160 that can function as word lines. The gate electrode strip 160 can be formed as a gate all-around gate (GAA gate) to laterally surround the pillar semiconductor channel 140, thereby enabling improved gate control. The photoresist layer material 177 can then be removed, for example, by ashes. Fig. 9A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a first dielectric material layer over the field-controlled vertical current switch according to an embodiment of the present disclosure. Fig. 9B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after the deposition of a first dielectric material layer over the field-controlled vertical current switch according to an embodiment of the present disclosure. With reference to Fig. 9A and Fig. 9B, a dielectric matrix layer 170 can be deposited to embed the pillar semiconductor channel 140, the gate dielectric layers 150, and the gate electrode strips 160. The dielectric matrix layer 170 can be formed from silicon oxide or another suitable dielectric material with a high k-value. The dielectric matrix layer 170 can be formed from the same material as the first dielectric material layer 120 or from a different material. The dielectric matrix layer 170 can be formed by any suitable deposition process. Fig. 10A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after planarizing the conductive metal material layer, the gate dielectric layer, and the pillar semiconductor channels of the driven ferroelectric memory cell according to an embodiment of the present disclosure. Fig. 10B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd2 (i.e., the plane A-A') after planarizing the conductive metal material layer, the gate dielectric layer, and the pillar semiconductor channels of the driven ferroelectric memory cell according to an embodiment of the present disclosure. With reference to Fig. 10A and Fig.10B A planarization process, such as CMP, can be performed to planarize the top surfaces of the pillar semiconductor channel 140, the gate dielectric layer 150, and the gate electrode strip 160 such that the top surfaces of the pillar semiconductor channel 140, the gate dielectric layer 150, and the gate electrode strip 160 are coplanar. In particular, sections of the dielectric matrix layer 170, the gate electrode strip 160, and the gate dielectric layer 150 above the horizontal plane, including the top surfaces of the pillar semiconductor channels 140, can be removed. After the planarization process, each pillar semiconductor channel 140 within the two-dimensional array of pillar semiconductor channels 140 can have a respective top surface that lies within a horizontal plane comprising a planarized top surface of the dielectric matrix layer 170.Furthermore, each gate electrode strip 160 can have an annular top surface 161 located within the horizontal plane that comprises the planarized top surface of the dielectric matrix layer 170. Fig. 11A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after a selective etching process for vertically removing an upper annular section of the gate electrode strip of the field-controlled vertical current switch according to an embodiment of the present disclosure. Fig. 11B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd1 (i.e., the plane A-A') after a selective etching process for vertically removing an upper annular section of the gate electrode strip of the field-controlled vertical current switch according to an embodiment of the present disclosure. With reference to Fig. 11A and Fig.11B A selective etching process can be performed to vertically recess each annular top surface of the gate electrode strips 160 relative to the planarized top surface of the dielectric matrix layer 170 and the top surfaces of the two-dimensional array of pillar semiconductor channels 140. The etching process selectively etches the gate electrode material to both the gate electrode strip material 160 and the dielectric matrix layer 170. The etching process can be an isotropic etching process, such as a wet etching process, or an anisotropic etching process, such as a reactive ion etching process. The recess depth of the gate electrode strips 160 can result in a gate electrode 160 that surrounds the pillar semiconductor channel 140 to a height of 60%–90% of the height of each pillar semiconductor channel 140.In other words, the recess depth of the etching process can range from 10% to 40% of the height of each pillar semiconductor channel 140. As a result of the etching process, which vertically recesses the gate electrode 160, annular cavities 171 can be formed. Fig. 12A is a vertical cross-sectional view of the exemplary structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a conductive metal material to form a bit line of the field-controlled vertical current switch according to an embodiment of the present disclosure. Fig. 12B is a vertical cross-sectional view of the exemplary structure along a second horizontal direction hd1 (i.e., the plane A-A') after the deposition of a conductive metal material to form a bit line of the field-controlled vertical current switch according to an embodiment of the present disclosure. With reference to Fig. 12 and Fig. 12B, annular cavities 171 can be filled with the dielectric material of a second dielectric material layer 180 after the deposition of the second dielectric material layer 180.For example, a conformal deposition process (such as a chemical vapor deposition process) can be used to deposit the second dielectric material layer 180. In such an embodiment, the second dielectric material layer 180 can comprise a two-dimensional array of tubular sections 172 of dielectric material that fill the cylindrical cavities 171 and contact an annular top surface of a respective tubular section of the gate electrode strips 160T. A photoresist material (not shown) can be deposited onto the second dielectric material layer 180. The photoresist material can be structured by photolithographic techniques to mask the second dielectric material layer 180, forming conduction trenches (not shown) that extend laterally along the first horizontal direction hd1 in the second dielectric material layer 180 after an etching process. The conduction trenches can be filled with at least one metallic filler material. Each metallic filler material section can be any suitable electrically conductive electrode material, such as copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, or the like. Other suitable materials for the second metallic conduction can also be used.The second metal conductors 182 can be formed by depositing a layer of conductive material using any suitable deposition process. For the purposes of this text, “suitable deposition processes” may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, or the like. In some embodiments, an optional metallic lining material may be deposited prior to the metallic filling section. Each metallic lining layer may contain TiN, TaN, WN, TiC, TaC, and WC.Other suitable materials may also be used within the considered scope of the disclosure. Excess sections of the at least one metallic material can be removed from above the horizontal plane, including the top surface of the second dielectric material layer 180, by a planarization process, such as a chemical-mechanical polishing process. Each remaining section of the at least one metallic material filling a respective conductor trench in the second dielectric material layer 180 comprises a second metallic conductor 182, which can function as an effective bit conductor. Each of the second metallic conductors 182 can be formed directly on a respective set of top surfaces of the pillar semiconductor channels 140.Thus, the second metal conductors 182 can be formed above the two-dimensional array of pillar semiconductor channels 140, with each of the second metal conductors 182 being formed directly on the top surfaces of a respective row of pillar semiconductor channels 140. As mentioned above, in other embodiments a metallic lining (not shown) can be used to improve the electrical coupling between the second metal conductors 182 and the pillar semiconductor channels 140. In this way, a controlled ferroelectric memory cell 200 can be arranged above each memory cell 100. The controlled ferroelectric memory cell 200 can have a pillar semiconductor channel 140 and a section of a gate electrode strip 160 that laterally surrounds the pillar semiconductor channel 140. A two-dimensional array of controlled ferroelectric memory cells 200 is provided. Each controlled ferroelectric memory cell 200 has a series connection of a memory element 100, a field-controlled vertical current switch 600, and a metallic top electrode, which is a section of a second metal conductor 182.Thus, each controlled ferroelectric memory cell 200 comprises a metallic lower electrode, which may be a section of a first metal conductor 122, a section of a ferroelectric dielectric layer 130, a pillar semiconductor channel 140, a section of a gate dielectric layer 150, a section of a gate electrode strip 160, and a metallic upper electrode, which is a section of a second metal conductor 182. Fig. 13A is a vertical cross-sectional view of a second alternative embodiment structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a number of layers, including a ferroelectric dielectric layer, an upper metal electrode layer, and a semiconductor channel material layer, over the first metal conductors and the substrate according to one embodiment of the present disclosure. Fig. 13B is a vertical cross-sectional view of the second alternative embodiment structure along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a number of layers, including a ferroelectric dielectric layer, an upper metal electrode layer, and a semiconductor channel material layer, over the first metal conductors and the substrate according to one embodiment of the present disclosure. With reference to Fig. 13A and Fig.13B An intermediate structure, as shown in Figs. 3A-3C, can be provided. As described above, a full-surface layer of ferroelectric (FE) material 130 can be deposited over the first dielectric material layer 120 and the first metal conductors 122. The ferroelectric dielectric layer (FE) 130 can be formed from any suitable ferroelectric material, for example HfO2, ZrO2, HfZrO2, AlScN, PbZrO3, Pb[ZrxTi1-x]O3, (0 ≤ x ≤) (PZT), BaTiO3, PbTiO3, PbNb2O6, LiNbO3, LiTaO3, polyvinylidene fluoride (PVDF), potassium dihydrogen phosphate (KDP), PbMg1 / 3Nb2 / 3O3(PMN), PbSc1 / 2Ta1 / 2O3PbSc1 / 2Ta1 / 2O3(PST), SrBi2Ta2O9(SBT), Bi1 / 2Na1 / 2TiO3Bi1 / 2Na1 / 2TiO3, combinations thereof, or the like. In particular, the ferroelectric dielectric layer 130 can be deposited on the first dielectric material layer 120 in such a way that it covers the first metal conductors 122. A semiconductor material layer 140L can be deposited onto the ferroelectric dielectric layer 130. The semiconductor material layer 140L can contain polysilicon, amorphous silicon, or a semiconducting oxide, such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaOx, InOx, or the like, or other suitable semiconductor materials. In some embodiments, the pillar semiconductor channels 140 can preferably be formed from IGZO. The IGZO can be intrinsic or can contain dopants if necessary. The conductivity range of the semiconductor material layer 140L can be at least from 1 x 10⁻⁵ S / m to 1 S / m and can range from 1 x 10⁻¹⁰ S / m to 1 x 120 S / m, although higher or lower conductivities can also be considered.The semiconductor material layer 140L enables the subsequent formation of a ferroelectrically controlled memory cell to control and select a memory cell formed from the underlying ferroelectric dielectric layer 130. The semiconductor material layer 140L can be deposited using any suitable deposition process. Furthermore, an intermediate metal electrode 142L can be deposited between the semiconductor material layer 140L and the ferroelectric dielectric layer 130. The intermediate metal electrode 142L can be made of materials such as copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, their alloys, or the like. Other suitable electrically conductive materials for the intermediate metal electrode 142L are also being considered.In such alternative embodiments, the intermediate metal electrode 142L can subsequently be structured into a two-dimensional array of intermediate metal electrodes, the two-dimensional array of etch mask material sections being used as an etch mask. The intermediate metal electrode 142L can be structured to form an upper metal plate 142 over the ferroelectric dielectric layer 130 in a metal-ferroelectric-metal capacitor storage cell. Fig. 14A is a vertical cross-sectional view of the second alternative embodiment structure along a first horizontal direction hd1 (i.e., the plane B-B') after etching and structuring pillar semiconductor channels of a driven ferroelectric memory cell according to an embodiment of the present disclosure. Fig. 14B is a vertical cross-sectional view of the second alternative embodiment structure along a second horizontal direction hd2 (i.e., the plane A-A') after etching and structuring pillar semiconductor channels of a driven ferroelectric memory cell according to an embodiment of the present disclosure. Referring to Fig. 14A and Fig. 14B, and similarly to the steps described above with reference to Fig. 5A and Fig. 5B, the semiconductor material layer 140L can be structured to form pillar semiconductor channels 140.By anisotropic etching of unmasked sections of the semiconductor channel material layer 140 selectively to the ferroelectric dielectric layer 130, using the two-dimensional array of etch mask material sections as an etch mask, the remaining sections of the semiconductor channel material layer 140 can be structured to comprise the two-dimensional array of pillar semiconductor channels. In general, a two-dimensional array of pillar semiconductor channels 140 can be formed over the ferroelectric dielectric layer 130. Each row of pillar semiconductor channels 140 is formed over one of the first metal conductors 122 and is capacitively coupled to it. Additionally, as shown in Fig. 14A and Fig.As shown in Fig. 14B, the etching process that structures the pillar semiconductor channel 140 can also etch and structure the intermediate metal electrode 142L to form the upper metal plate 142 between the pillar semiconductor channel 140 and the ferroelectric dielectric layer 130, as shown in Fig. 4B. In this respect, the upper metal plate 142, the ferroelectric dielectric layer 130, and the first metal conductor 122 can be used to form a metal-ferro-metal junction memory cell device. Such memory cell devices can exhibit improved memory lifetime and data retention. After the pillar semiconductor channel 140 has been formed, the photoresist material (not shown) can be removed, for example, by ashing or a chemical process. Fig. 15A is a vertical cross-sectional view of the structure of the second alternative embodiment along a first horizontal direction hd1 (i.e., the plane B-B') after the deposition of a conductive metal material to form a bit line of the field-controlled vertical current switch according to an embodiment of the present disclosure. Fig. 15B is a vertical cross-sectional view of the structure of the second alternative embodiment along a second horizontal direction hd1 (i.e., the plane A-A') after the deposition of a conductive metal material to form a bit line of the field-controlled vertical current switch according to an embodiment of the present disclosure. With reference to Fig. 15A and Fig. 15B, the process steps can be carried out as described above with reference to Figs. 6A-12B. In this way, an alternative controlled ferroelectric memory cell 601 can be arranged above each memory cell 101.A two-dimensional array of memory cells 101 can be provided. Each memory cell 101 can have a lower section of a pillar semiconductor channel 140, a section of the ferroelectric dielectric layer 130 having a planar overlap with the pillar semiconductor channel 140, and an intermediate metal layer forming an upper electrode 142. The driven ferroelectric memory cell 601 can have a pillar semiconductor channel 140 and a section of a gate electrode strip 160 that laterally surrounds the pillar semiconductor channel 140. A two-dimensional array of driven ferroelectric memory cells 201 is provided. Each driven ferroelectric memory cell 201 contains a series connection of a memory element 101, a driven ferroelectric memory cell 601, and a metallic upper electrode, which is a section of a second metal conductor 182.Thus, each controlled ferroelectric memory cell 201 comprises a metallic lower electrode, which may be a section of a first metal conductor 122, a section of a ferroelectric dielectric layer 130, an upper electrode 142, a pillar semiconductor channel 140, a section of a gate dielectric layer 150, a section of a gate electrode strip 160, and a metallic upper electrode, which is a section of a second metal conductor 182. Fig. 16A is a perspective partial view of a semiconductor memory device according to various embodiments of the present disclosure. Fig. 16B is a schematic top view of the semiconductor memory device of Fig. 16A. Fig. 16C is a perspective partial cross-sectional view of the semiconductor memory device of Fig. 16A along the memory structures of the semiconductor memory device. Fig. 16D is an enlarged cross-sectional view of a section P of Fig. 16C. Fig. 17A is a vertical perspective partial cross-sectional view of a semiconductor memory device according to another embodiment of the present disclosure. Fig. 17B is an enlarged cross-sectional view of a section P of Fig. 17A. For example, Fig. 16A can illustrate a perspective view of a completed two-dimensional array 300 of controlled ferroelectric memory cells 200, as shown in Figs. 12A and 12B. The two-dimensional array 300 of controlled ferroelectric memory cells 200 comprises a two-dimensional array of field-controlled vertical current switches 600. Each controlled ferroelectric memory cell 200 can have a field-controlled vertical current switch 600 formed across, and coupled to, a memory element (100, 101) (see Figs. 12A, 12B, 15A, 15B, 16D, and 17B). The field-controlled vertical current switch 600 comprises a gate electrode strip 160 and a gate dielectric layer 150 surrounding a pillar semiconductor channel 140. A distal end 140S of the pillar semiconductor channel 140 can be electrically coupled to a second metal conductor 182.A proximal end 140D of the pillar semiconductor channel 140 can be electrically connected in series with a storage element 100, 101. The storage element 100, 101 can comprise a metal-ferroelectric-metal capacitor storage element (MFM capacitor storage element) 100 or a metal-ferroelectric-semiconductor capacitor storage element (MFS capacitor storage element) 100. For example, with reference to Fig. 12A, Fig. 12B and Fig. 16D, in one embodiment the storage element 100 can have a ferroelectric tunnel junction of a metal-ferroelectric-semiconductor capacitor (MFS capacitor) that operates as a capacitor or ferroelectric tunnel junction storage cell. As shown in Figures 12A, 12B and 16D, a ferroelectric dielectric layer 130 can be arranged between a first metal conductor 122 made of electrically conductive metal and a pillar semiconductor channel 140. In such an embodiment, a lower section of the pillar semiconductor channel 140 can function as an upper electrode of the capacitor or FTJ storage device.An upper section of the first metal conductor 122 can function as a lower electrode of the capacitor or FTJ storage device. The first metal conductor 122 can be coupled to a first metal conductor via 128, which can extend vertically through the dielectric interconnect layers. In another embodiment, as illustrated in Figs. 15A, 15B, 17A, and 17B, a completed two-dimensional array 301 of controlled ferroelectric memory cells 201 can be provided. The two-dimensional array 301 of controlled ferroelectric memory cells 201 is similar to the two-dimensional array 300 of controlled ferroelectric memory cells 200 shown in Fig. 16A. However, in the two-dimensional array 301 of controlled ferroelectric memory cells 201, an intermediate metal electrode 142 can be formed between the ferroelectric dielectric layer 130 and the pillar semiconductor channel 140.In such an embodiment, a metal-ferroelectric-metal capacitor (MFM capacitor) can be formed using an upper section of the first metal conductor 122 as a lower metal plate, the ferroelectric dielectric layer 130 as an inter-node dielectric, and the intermediate metal electrode 142 as an upper metal plate. The intermediate metal electrode 142 can be electrically connected in series with the pillar semiconductor channel 140. With reference to Figures 1A-12B and 16A-16D, together and according to various embodiments of the present disclosure, a semiconductor device 300 can be provided, comprising at least one controlled ferroelectric memory cell 200, 201, each of the controlled ferroelectric memory cells 200, 201 having a dielectric material layer 120 arranged over a substrate 110. The memory cell 200, 201 further comprises a metallic lower electrode 122 and a ferroelectric dielectric layer 130, which contacts a top surface of the metallic lower electrode 122. The controlled ferroelectric storage cell 200, 201 further comprises a pillar semiconductor channel 140, which lies above the ferroelectric dielectric layer 130 and is capacitively coupled to the metallic lower electrode 122 through the ferroelectric dielectric layer 130. As shown in Figs. 12A, 12B, 15A and 16B.As shown in Fig. 15B, the ferroelectric memory cell 200, 201 further comprises a gate dielectric layer 150, which includes a horizontal gate dielectric section 150H, located above the ferroelectric dielectric layer 130, and a tubular gate dielectric section 150T, which laterally surrounds the pillar semiconductor channel 140. The driven ferroelectric memory cell 200 also has a gate electrode strip 160, which lies above the horizontal gate dielectric 150H and laterally surrounds the tubular gate dielectric 150T. As shown in Fig. 12A, Fig. 12B, Fig. 15A and Fig.As shown in Figure 15B, the ferroelectric memory cell 200, 201 further comprises a gate electrode strip 160, which includes a horizontal gate electrode strip section 160H located above the horizontal gate dielectric section 150H, and a tubular gate electrode strip section 160T that laterally surrounds the tubular gate dielectric section 150T. The horizontal section of the gate electrode strip 160H can be coupled to a gate electrode via 168, which can extend vertically through the dielectric interconnect layers. The driven ferroelectric memory cell 200, 201 further comprises a metallic top electrode 182 that contacts a top surface of the pillar semiconductor channel 140. The metallic upper electrode 182 can be coupled to a metallic upper electrode via 188 which can extend vertically through the dielectric interconnect layers. In various embodiments, the pillar semiconductor channel 140 of the memory cell 200 can have a bottom surface that is in contact with a top surface of the ferroelectric dielectric layer 130; and the driven ferroelectric memory cell 200 comprises a metal-ferroelectric-semiconductor capacitor (MFS capacitor) 100. In one embodiment of the semiconductor device 301, an intermediate metal electrode 142 contacts a bottom surface of the pillar semiconductor channel 140 and a top surface of the ferroelectric dielectric layer 130; and the driven ferroelectric storage cell 201 comprises a metal-ferroelectric-metal capacitor (MFM capacitor) 101. In one embodiment of the semiconductor device 301, a circumferential edge of a top surface of the intermediate metal electrode 142 coincides with a circumferential edge of the bottom surface of the pillar semiconductor channel 140. In one embodiment of the semiconductor device 300, the horizontal gate dielectric section 150H and the tubular gate dielectric section 150T can be connected sections of a continuously extending dielectric material layer 150 and have the same thickness and material composition. In one embodiment of the semiconductor device 300, the gate electrode strip 160 comprises a horizontal gate electrode strip section 160H and a tubular gate electrode strip section 160T, which can be interconnected sections of a continuously extending gate electrode strip material and of the same material composition. In one embodiment of the semiconductor device 300, an annular top surface of the tubular gate dielectric section 150T is located in the same horizontal plane as the top surface of the pillar semiconductor channel 140. In one embodiment of the semiconductor device 300, the tubular gate electrode strip section 160T comprises an annular top surface 161, which is vertically spaced from the upper electrode 182 by a uniform vertical distance. In one embodiment of the semiconductor device 300, the semiconductor device 300 can comprise at least one array of driven ferroelectric memory cells 200, wherein each of the driven ferroelectric memory cells 200 can be arranged within each array of driven ferroelectric memory cells along a first horizontal direction. Furthermore, metallic lower electrodes 122 of each array of driven ferroelectric memory cells 200 comprise sections of a respective first metal conductor 122 extending laterally along the first horizontal direction; and metallic upper electrodes of each array of driven ferroelectric memory cells comprise sections of a respective second metal conductor 182 extending laterally along the second horizontal direction. In one embodiment, the semiconductor device 300 can have a two-dimensional array of controlled ferroelectric memory cells, wherein the two-dimensional array of controlled ferroelectric memory cells comprises multiple columns of controlled ferroelectric memory cells 200 and multiple rows of controlled ferroelectric memory cells 200. Each row of controlled ferroelectric memory cells 200 can comprise a respective set of controlled ferroelectric memory cells arranged along the first horizontal direction with a first periodicity. Each column of controlled ferroelectric memory cells 200 can comprise a respective set of controlled ferroelectric memory cells arranged along the second horizontal direction with a second periodicity.Furthermore, each column of addressed ferroelectric memory cells 200 can include a gate electrode strip 160, wherein the gate electrode strip 160 can comprise a respective section of a continuously extending strip of gate electrode material 160 that laterally surrounds each pillar semiconductor channel 140 within the column of addressed ferroelectric memory cells 200. In this way, the various embodiments can provide a FeRAM device (200, 300) that can be manufactured in the BEOL with a field-controlled vertical current switch 600 capable of selecting a storage element 100. The storage element 100 can include an MFM or an MFS capacitor. By forming both the storage element 100 and the field-controlled vertical current switch 600 capable of selecting a storage element 100 in the BEOL, the storage density can be increased by synergistically utilizing the smaller area required to form the field-controlled vertical current switch 600 capable of selecting a storage element 100. Furthermore, the field-controlled vertical current switch 600 can be directly coupled to the storage element 100.Therefore, the controlled ferroelectric memory cell 200, which has the field-controlled vertical current switch 600 in direct contact with a memory element 100, has a more compact configuration than other configurations. Other configurations may, for example, have transistors arranged below word lines or laterally to the side of memory cells. Therefore, the controlled ferroelectric memory cell 200 can enable a higher memory cell density than conventional memory structures. Furthermore, the GAA gate electrode strip 160, which laterally surrounds the pillar semiconductor channel 140, allows for improved gate control. Applying a voltage to the GAA gate electrode strip 160 can selectively control the current flow to the storage element 100. The gate electrode strips 160 can provide a gate voltage for the field-controlled vertical current switch 600 to control the current flow through the pillar semiconductor channel 140 and to the storage element 100. Each storage element 100 can have a ferroelectric dielectric layer 130 that forms a tunnel barrier. Accordingly, the storage elements 100 can be referred to as FE storage cells. In various embodiments, a section of the pillar semiconductor channel 140 (for example, the drain side of the channel) directly contacts the ferroelectric dielectric layer 130 and can act as an upper electrode, a section of the first metal conductor 122 can act as the lower electrode, and a section of the ferroelectric dielectric layer 130 can act as the FE tunnel barrier. In various embodiments, the storage element 100 can function as a ferroelectric tunneling junction (FTJ). More precisely, the FE tunneling junction can be a ferroelectric film thin enough to allow electrons to tunnel through it. For example, the FE tunneling junction 130 can be approximately 1 nanometer (nm) to approximately 50 nm thick, such as approximately 5 nm to approximately 25 nm or approximately 10 nm thick. According to another embodiment of the present disclosure, a semiconductor device 300 is provided comprising: at least one two-dimensional array of controlled ferroelectric memory cells 200, each of the at least one two-dimensional array of controlled ferroelectric memory cells 200 comprising: first metal conductors 122 embedded in a first dielectric material layer 120 and extending laterally along a first horizontal direction; a ferroelectric dielectric layer 130 extending continuously over the first metal conductors 122; a two-dimensional array of pillar semiconductor channels 140 lying over the ferroelectric dielectric layer 130, each row of pillar semiconductor channels 140 being arranged along the first horizontal direction and capacitively coupled to one of the respective first metal conductors 122;a gate dielectric layer 150 comprising a horizontal gate dielectric section lying above the ferroelectric dielectric layer 130 and a tubular gate dielectric section laterally surrounding the pillar semiconductor channels 140; gate electrode strips 160 laterally surrounding a respective column of pillar semiconductor channels 140 arranged along the second horizontal direction and laterally spaced from one another along the first horizontal direction; and second metal conductors 182 embedded in a second dielectric material layer 180, extending laterally along the first horizontal direction and contacting the top surfaces of a respective row of pillar semiconductor channels 140. In one embodiment, the pillar semiconductor channel 140 of the semiconductor device 300 contacts a top surface of the ferroelectric dielectric layer 130. In another embodiment, each of the at least one two-dimensional array of addressed ferroelectric memory cells 201 comprises a two-dimensional array of intermetal electrodes 142 in contact with the ferroelectric dielectric layer 130 and with a respective pillar semiconductor channel 140 within the two-dimensional array of pillar semiconductor channels 140. Fig. 18 is a perspective partial cross-sectional view of a semiconductor memory device 400 according to various embodiments of the present disclosure. With reference to Fig. 18, the memory device 400 comprises a first two-dimensional array 300A of controlled ferroelectric memory cells and a second two-dimensional array 300B of controlled ferroelectric memory cells, vertically stacked. Each of the first and second two-dimensional arrays (300A, 300B) of controlled ferroelectric memory cells can be the same as each of the two-dimensional array 300 of controlled ferroelectric memory cells described above.Thus, in one embodiment of the semiconductor device 300, at least one two-dimensional array of controlled ferroelectric memory cells comprises several two-dimensional arrays of controlled ferroelectric memory cells 300A, 300B, arranged over a common substrate and stacked vertically along a vertical direction perpendicular to a top surface of the common substrate 110. The semiconductor memory device 400 can have multiple two-dimensional arrays of addressed ferroelectric memory cells, such as those shown in Figures 1A-17B. In this respect, the semiconductor memory device 400 can offer a higher storage density than a memory device with only a single memory layer. Although Figure 18 shows two two-dimensional arrays 300 of addressed ferroelectric memory cells (200 or 201), the memory device 400 can have additional two-dimensional arrays 300 of addressed ferroelectric memory cells (200 or 201), such as 3 to 20 interconnect memory layers. The compact configuration of each individual memory layer allows for a further increase in storage density. Fig. 19 is a flowchart showing the steps for forming a semiconductor storage device 300, 301, 400 according to various embodiments of the present disclosure. With reference to Figs. 2A-2C and 19, in operation 501, first metal conductors 122 extending along a first horizontal direction can be formed within an upper section of a dielectric material layer 120. With reference to Figs. 3A-3C and 19, in operation 502, a ferroelectric dielectric layer 130 can be deposited over the tops of the first metal conductors 122. With reference to Figures 4A-5B and 19, in Operation 503 a two-dimensional array of pillar semiconductor channels 140 can be formed over the ferroelectric dielectric layer 130, wherein each row of pillar semiconductor channels 140 is formed over one of the first metal conductors 122 and capacitively coupled to it. With reference to Figures 6A, 6B and 19In operation 504, a gate dielectric layer 150 can be deposited over the two-dimensional array of pillar semiconductor channels 140. Referring to Figures 7A-11A and 19, in operation 505, gate electrode strips 160 can be formed over the gate dielectric layer 150, each of the gate electrode strips 160 laterally surrounding a corresponding column of pillar semiconductor channels 140. Referring to Figures 12A, 12B, and 19, in operation 506, second metal conductors 182 can be formed over the two-dimensional array of pillar semiconductor channels 140, each of the second metal conductors 182 being formed directly on the top surfaces of a respective row of pillar semiconductor channels 140. According to various embodiments, storage structures and devices are provided that offer a higher storage cell density than previous storage configurations. The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text.

Claims

Semiconductor device (300) comprising: at least one controlled ferroelectric memory cell (200, 201) comprising: - a dielectric material layer (120) arranged over a substrate (110); - a metallic lower electrode (122); and a ferroelectric dielectric layer (130) that contacts a top surface of the metallic lower electrode (122); a pillar semiconductor channel (140) that lies above the ferroelectric dielectric layer (130) and is capacitively coupled to the metallic lower electrode (122) through the ferroelectric dielectric layer (130); a gate dielectric layer (150) that has a horizontal gate dielectric section (150H) that lies above the ferroelectric dielectric layer (130) and a tubular gate dielectric section (150T) that laterally surrounds the pillar semiconductor channel (140);a gate electrode strip (160) comprising a horizontal gate electrode section (160H) located above the horizontal gate dielectric section (150H), and a tubular gate electrode section (160T) laterally surrounding the tubular gate dielectric section (150T); and a metallic top electrode (182) contacting a top surface of the pillar semiconductor channel (140). Semiconductor device (300) according to claim 1, wherein the pillar semiconductor channel (140) has a bottom surface in contact with a top surface of the ferroelectric dielectric layer (130); and wherein the driven ferroelectric storage cell (200, 201) has a metal-ferroelectric semiconductor capacitor, MFS capacitor. Semiconductor device (300) according to claim 1 or 2, wherein an intermediate metal electrode (142) contacts a bottom surface of the pillar semiconductor channel (140) and a top surface of the ferroelectric dielectric layer (130); and wherein the driven ferroelectric storage cell (200, 201) comprises a metal-ferroelectric-metal capacitor, MFM capacitor. Semiconductor device (300) according to claim 3, wherein a circumferential edge of a top surface of the intermediate metal electrode (142) is connected to a circumferential edge of the bottom surface of the pillar- Semiconductor device (300) according to one of the preceding claims, wherein the horizontal gate dielectric section (150H) and the tubular gate dielectric section (150T) are connected sections of a dielectric material layer (150) that extends continuously and has the same thickness and material composition. Semiconductor device (300) according to one of the preceding claims, wherein the horizontal gate electrode strip section (160H) and the tubular gate electrode strip section (160T) are connected sections of a gate electrode strip material that extends continuously and have the same material composition. Semiconductor device (300) according to claim 6, wherein the tubular gate electrode strip section (160T) has an annular top surface (161) which is spaced vertically from the upper electrode (182) by a uniform vertical distance. Semiconductor device (300) according to claim 1, wherein an annular top surface of the tubular gate dielectric section (150T) lies within the same horizontal plane as the top surface of the pillar semiconductor channel (140). Semiconductor device (300) according to one of the preceding claims, further comprising: at least one series of controlled ferroelectric memory cells (200), the at least one controlled ferroelectric memory cell (200), wherein controlled ferroelectric memory cells (200) are arranged within each series of controlled ferroelectric memory cells along a first horizontal direction, wherein metallic lower electrodes (122) of each series of controlled ferroelectric memory cells (200) comprise sections of a respective first metal conductor (122) extending laterally along the first horizontal direction, wherein metallic upper electrodes (182) of each series of controlled ferroelectric memory cells (200) comprise sections of a respective second metal conductor (182) extending laterally along the second horizontal direction. Semiconductor device (300) according to claim 9, further comprising: a two-dimensional array of controlled ferroelectric memory cells, comprising: - the at least one series of controlled ferroelectric memory cells (200) arranged with a first periodicity along a first horizontal direction;and- at least one column of driven ferroelectric memory cells (200) arranged with a second periodicity along a second horizontal direction, wherein the at least one column of driven ferroelectric memory cells (200) comprises a respective set of driven ferroelectric memory cells, wherein the at least one column of driven ferroelectric memory cells (200) has a gate electrode strip (160), wherein the gate strip electrode (160) comprises a respective section of a continuously extending gate electrode strip material strip that laterally surrounds each pillar semiconductor channel (140) within the at least one column of driven ferroelectric memory cells (200). Semiconductor device (300) comprising: at least one two-dimensional array of driven ferroelectric memory cells (200), each of the at least one two-dimensional array of driven ferroelectric memory cells (200) comprising: - first metal conductors (122) embedded in a first dielectric material layer (120) and extending laterally along a first horizontal direction; and - a ferroelectric dielectric layer (130) extending continuously over the first metal conductors (122); a two-dimensional array of pillar semiconductor channels (140) lying over the ferroelectric dielectric layer (130), each row of pillar semiconductor channels (140) being arranged along the first horizontal direction and capacitively coupled to a respective first metal conductor (122);a gate dielectric layer (150) comprising a horizontal gate dielectric section (150H) lying above the ferroelectric dielectric layer (130) and a tubular gate dielectric section (150T) laterally surrounding the pillar semiconductor channels (140); gate electrode strips (160) laterally surrounding a respective column of pillar semiconductor channels (140) arranged along the second horizontal direction and laterally spaced apart along the first horizontal direction; and second metal conductors (182) embedded in a second dielectric material layer (180), extending laterally along the first horizontal direction and contacting the top surfaces of a respective row of pillar semiconductor channels (140). Semiconductor device (300) according to claim 11, wherein each pillar semiconductor channel (140) in the two-dimensional array of pillar semiconductor channels (140) contacts a top surface of the ferroelectric dielectric layer (130). Semiconductor device (300) according to claim 12, wherein each of the at least one two-dimensional array of ferroelectric memory cells (201) controlled has a two-dimensional array of intermetal electrodes (142) that is in contact with the ferroelectric dielectric layer (130) and with a respective pillar semiconductor channel (140) within the two-dimensional array of pillar semiconductor channels (140). Semiconductor device (300) according to one of claims 11 to 13, wherein the at least one two-dimensional array of controlled ferroelectric memory cells (300A, 300B) comprises several two-dimensional arrays of controlled ferroelectric memory cells (300A, 300B) arranged over a common substrate (110) and stacked vertically along a vertical direction perpendicular to a top surface of the common substrate (110). A method for fabricating a semiconductor device (300, 301, 400), comprising: forming first metal conductors (122) extending along a first horizontal direction within an upper section of a dielectric material layer (120); depositing a ferroelectric dielectric layer (130) over the tops of the first metal conductors (122); forming a two-dimensional array of pillar semiconductor channels (140) over the ferroelectric dielectric layer (130), wherein each row of pillar semiconductor channels (140) is formed over and capacitively coupled to a respective first metal conductor (122); depositing a gate dielectric layer (150) over the two-dimensional array of pillar semiconductor channels (140); forming gate electrode strips (160) over the gate dielectric layer (150), wherein each of the gate electrode strips (160) forms a respective column of pillar semiconductor channels (140) laterally surrounds;and forming second metal conductors (182) over the two-dimensional array of pillar semiconductor channels (140), each of the second metal conductors (182) being formed directly on top surfaces of a respective row of pillar semiconductor channels (140). The method of claim 15, further comprising: depositing a dielectric matrix layer (170) over the gate electrode strip (160); and planarizing the dielectric matrix layer (170), the gate electrode strip (160) and the gate dielectric layer (150), wherein each pillar semiconductor channel (140) within the two-dimensional array of pillar semiconductor channels (140) has a respective top surface which lies within a horizontal plane which contains a planarized top surface of the dielectric matrix layer (170), wherein each gate electrode strip (160) has a column of annular top surfaces (161) which lie within the horizontal plane which contains the planarized top surface of the dielectric matrix layer (170). The method of claim 16, further comprising: vertically recessing each annular top surface (161) of the gate electrode strips (160) relative to the planarized top surface of the dielectric matrix layer (170) and the top surfaces of the two-dimensional array of pillar semiconductor channels (140); and depositing a dielectric filler ring within each cavity formed by vertically recessing the annular top surfaces (161) of the gate electrode strips (160). A method according to any one of claims 15 to 17, wherein forming the two-dimensional array of pillar semiconductor channels (140) comprises: depositing a semiconductor channel material layer (140) over the ferroelectric dielectric layer (130); forming a two-dimensional array of etch mask material sections over the semiconductor channel material layer (140); and anisotropic etching of unmasked sections of the semiconductor channel material layer (140) selectively relative to the ferroelectric dielectric layer (130) using the two-dimensional array of etch mask material sections as an etch mask, wherein remaining sections of the semiconductor channel material layer (140) contain the two-dimensional array of pillar semiconductor channels (140). The method of claim 18, further comprising: depositing an intermediate metal electrode material layer (142) over the ferroelectric dielectric layer (130), wherein the semiconductor channel material layer (140) is deposited on the intermediate metal electrode material layer (142); and structuring the intermediate metal electrode material layer (142) into a two-dimensional array of intermediate metal electrodes (142) using the two-dimensional array of etch mask material sections as an etch mask. A method according to any one of claims 15 to 19, further comprising: depositing a gate electrode material layer (160) over the gate dielectric layer (150); applying and structuring a photoresist layer over the gate electrode material layer (160) to provide multiple structured photoresist strips that lie over a respective slit of pillar semiconductor channels (140); and etching unmasked sections of the gate electrode material layer (160), wherein remaining sections of the gate electrode material layer (160) contain the gate electrode strips (160).

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