Multi-gate device structure

Abstract

Semiconductor device comprising: a first transistor in a first device region (100-1) of a substrate (102), the first transistor comprising: a first source / drain element (136N-1) and a second source / drain element (136N-1), a first plurality of channel portions (1081) sandwiched between the first source / drain element (136N-1) and the second source / drain element (136N-1), a first gate structure (120-1) enclosing each of the first plurality of channel portions (1081), a first source / drain contact (130) disposed above the first source / drain element (136N-1), and a first upper gate spacer (122-1) disposed between the first gate structure (120-1) and the first source / drain contact (130); and a second transistor in a second device region (100-2) of the substrate (102), the second transistor comprising: a third source / drain element (136N-2) and a fourth source / drain element (136N-2), a second plurality of channel portions (1082) sandwiched between the third source / drain element (136N-2) and the fourth source / drain element (136N-2), a second gate structure (120-2) enclosing each of the second plurality of channel portions (1082), a second source / drain contact (132) disposed above the third source / drain element (136N-2), and a second upper gate spacer (122-2) arranged between the second gate structure (120-2) and the second source / drain contact (132), wherein a distance (S2) between the second upper gate spacer (122-2) and the second source / drain contact (132) is greater than a distance (S1) between the first upper gate spacer (122-1) and the first source / drain contact (130), wherein: each of the first plurality of channel parts (1081) extends along a first direction (x), each of the second plurality of channel parts (1082) extends along a second direction (x), the first upper gate spacer (122-1) has a first thickness along the first direction (x), the second upper gate spacer (122-2) has a second thickness along the second direction (x), and the second thickness is greater than the first thickness, wherein the first and second plurality of channel portions originate from a stack of semiconductor layers of interleaved channel layers and sacrificial layers by patterning fin structures therefrom and selectively removing the sacrificial layers.

Description

background

[0001] The IC (semiconductor integrated circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have spawned generations of ICs, with each generation having smaller and more complex circuits than the previous generation. Over the course of IC evolution, feature density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest component or line that can be created using a manufacturing process) has decreased. This process of downsizing generally provides benefits by increasing production output and reducing associated costs. However, this downsizing has also increased the complexity of IC processing and manufacturing.

[0002] For example, as IC technologies move to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, lowering off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device with a gate structure, or a portion thereof, disposed over more than one side of a channel region. Fin field-effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices that have become well-known and promising candidates for high-power and low-leakage applications. A FinFET has a raised channel enclosed by a gate on more than one side (for example, the gate encloses a top and sidewalls of a "fin" of semiconductor material extending from a substrate).An MBC transistor has a gate structure that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. Because its gate structure encloses the channel regions, an MBC transistor can also be referred to as a gate-enclosing transistor (SGT) or a gate-all-around transistor (GAA transistor). The channel region of an MBC transistor can be formed by nanowires, nanosheets, or other nanostructures, and therefore an MBC transistor can also be referred to as a nanowire transistor or a nanosheet transistor.

[0003] Corresponding semiconductor devices are known, for example, from US 9 947 804 B1, which relates to the integration of long- and short-channel nanolayer transistors. US 2019 / 0311969 A1 discloses the provision of FinFETs with self-aligned contacts and FINFETs in which the contacts are spaced apart from gate spacers. US 2015 / 0249036 A1 discloses the integration of regions with smaller gate pitches and regions with larger gate pitches, with the source / drain contacts being spaced apart from the gate spacers in regions with larger gate pitches.

[0004] With a reduction in dimensions enabled by implementations of multi-gate devices, distances between gate structures and source / drain contacts are also reduced, which can increase parasitic capacitance and reduce switching speed. Furthermore, there may be room for improvement in the gate contact breakdown voltage or the source / drain gate breakdown voltage. While conventional multi-gate device structures are generally suitable for their intended purposes, they are still not satisfactory in all respects. The invention provides an improvement in a device according to the respective independent claims. Particular developments arise from the dependent claims. Short description of the drawings

[0005] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale. Indeed, the dimensions of various elements may be arbitrarily exaggerated or reduced for the sake of clarity of explanation. Fig. 1 shows a layout diagram of a first device region of a semiconductor device in various aspects of the present invention. Fig. 2 shows a layout diagram of a second device region of a semiconductor device in various aspects of the present invention. Fig. Figure 3 shows a partial sectional view of the first device region along a cross section A - A' of Fig. 1, in various aspects of the present invention. Fig. Figure 4 shows a partial sectional view of the second device region along a cross section B - B' of Fig. 2, in various aspects of the present invention. The Fig. 5 and Fig. 7 show a partial sectional view of the first device region along a cross section C - C' of Fig. 1, in various aspects of the present invention. The Fig. 6 and Fig. 8 show a partial sectional view of the second device region along a cross section D - D` of Fig. 2, in various aspects of the present invention. Fig. 9 shows a partial cross-sectional view of a third device region of a semiconductor device along an active region, in one or more aspects of the present invention. Fig. 10 shows a layout diagram of a fourth device region of a semiconductor device in one or more aspects of the present invention. Fig. 11 shows a layout diagram of a fifth device region of a semiconductor device in one or more aspects of the present invention. Detailed description

[0006] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] In addition, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] Furthermore, when a number or range of numbers is described with the terms "about," "approximately," and the like, the term is intended to encompass numbers that are within a reasonable range, taking into account variations inherent in manufacturing, as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range that includes the stated number, for example, within ±10% of the stated number, due to known manufacturing tolerances associated with the manufacture of an element having a property associated with the number. For example, a material layer having a thickness of "about 5 nm" may encompass a dimensional range of 4.25 nm to 5.75 nm, where one of ordinary skill in the art understands manufacturing tolerances associated with the deposition of a material layer to be ±15%.Furthermore, reference numerals and / or letters may be repeated throughout the various examples in the present invention. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0009] The present invention relates generally to multi-gate transistors and, more particularly, to source / drain contacts of multi-gate transistors.

[0010] MBC transistors enable aggressive gate length scaling to improve performance and packaging density. To meet diverse design requirements in mobile devices, communication networks, high-performance computing (HPC), artificial intelligence (AI), virtual reality (VR), and big data applications, an IC chip can contain different types of devices that work together. These different types of devices can include high-density devices, high-voltage devices, low-leakage devices, high-power devices, and high-bandwidth devices. Implementing different types of MBC transistors in a single chip requires a holistic solution, not piecemeal optimization.

[0011] The present invention provides embodiments of different types of MBC transistors and a combination thereof for different functionalities and applications. For example, the present invention provides structures of a first MBC transistor having smaller gate lengths and pitches and source / drain contacts fabricated using SAC (Self-Aligned Contact) techniques. The present invention also provides structures of a second MBC transistor having larger gate lengths and pitches and non-SAC contacts. The first MBC transistor can be used for large-scale integrated circuit applications. The second MBC transistor can be used for high-voltage applications, such as drivers and controllers for electronic security devices.

[0012] The various aspects of the present invention are described in more detail below with reference to the figures. Fig. 1 shows a layout diagram of a first device region 100-1 of a semiconductor device 100. Fig. 2 shows a layout diagram of a second device region 100-2 of the semiconductor device 100. Fig. 3 shows a partial sectional view of the first device region 100-1 along a cross section A - A' of Fig. 1, wherein the cross section A - A' passes through a first gate structure 120-1. Fig. 4 shows a partial sectional view of the second device region 100-2 along a cross section B - B' of Fig. 2, wherein the cross section B - B' passes through a second gate structure 120-2. The Fig. 5 and Fig. 7 show a partial sectional view of the first device region 100-1 along a cross section C - C' of Fig. 1, wherein the cross section C - C' passes through a first active region 110-1. The Fig. 6 and Fig. 8 show a partial sectional view of the second device region 100-2 along a cross section D - D` of Fig. 2, wherein the cross section D - D' passes through a third active region 110-3. Fig. 9 shows a partial cross-sectional view of a third device region 100-3 of the semiconductor device 100 along an active region. Fig. 10 shows a layout diagram of a fourth device region 100-4 of the semiconductor device 100. Fig. 11 shows a layout diagram of a fifth device region of the semiconductor device 100. In the Fig. 1 to 11, the x-direction, y-direction, and z-direction are perpendicular to each other and are used throughout. Furthermore, similar reference numerals are used throughout the present invention to designate similar elements.

[0013] Now let’s come to Fig. 1, which shows a semiconductor device 100. The semiconductor device 100 includes and is fabricated on a substrate 102. In one embodiment, the substrate may be a silicon (Si) substrate. In some other embodiments, the substrate 102 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Examples of III-V semiconductor materials include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 102 may also include an insulating layer, such as a silicon oxide layer, to form a silicon-on-insulator (SOI) structure.

[0014] The semiconductor device 100 may include a plurality of well regions on the substrate 102. In some embodiments, Fig. 1 to 4, 10, and 11, the semiconductor device 100 includes an n-well region 102N (or an n-well 102N) and a p-well region 102P (or a p-well 102P) for fabricating transistors of different conductivity types. The n-well 102N and the p-well 102P are each formed from the substrate 102 and have a doping profile. The n-well 102N has a doping profile of an n-dopant, such as phosphorus (P) or arsenic (As). The p-well 102P has a doping profile of a p-dopant, such as boron (B). The doping of the n-well 102N and the p-well 102P can be done by ion implantation or thermal diffusion and can take into account parts of the substrate 102. The n-well 102N and the p-well 102P are also in Fig. 4. As shown in Fig. 1, the first device region 100-1 includes a first n-MBC transistor 1000-1N over the p-well 102P and a first p-MBC transistor 1000-1P over the n-well 102N. In Fig. 2, the second device region 100-2 includes a second n-MBC transistor 1000-2N over the p-well 102P and a second p-MBC transistor 1000-2P over the n-well 102N. The third device region 100-3, shown in Fig. 9, has a third n-MBC transistor 1000-3N over the p-well 102P and a third p-MBC transistor (not shown) over the n-well 102N. As shown in Fig. 10, the fourth device region 100-4 includes a fourth n-MBC transistor 1000-4N over the p-well 102P and a fourth p-MBC transistor 1000-4P over the n-well 102N. As shown in Fig. 11, the fifth device region includes a fourth n-MBC transistor 1000-5N over the p-well 102P and a fifth p-MBC transistor 1000-5P over the n-well 102N. The Fig. 5 and Fig. 7 shows the first n-MBC transistors 1000-1N above the p-well 102P. The Fig. 6 and Fig. 8 shows the second n-MBC transistors 1000-2N above the p-well 102P.

[0015] The semiconductor device 100 has more than one device region, such as the one shown in Fig. 1 shown first device area 100-1, which in Fig. 2 shown second device area 100-2, which in Fig. 9 shown third device area 100-3, which in Fig. 10 shown fourth device area 100-4 and the in Fig. 11. Different device regions of the semiconductor device 100 used here are suitable for different application areas. In some implementations, MBC transistors in the first device region 100-1 are configured to have a high packing density and are suitable for applications with large-scale integrated circuits. MBC transistors in the second device region 100-2 are configured to withstand a high voltage and are suitable for high-voltage applications. MBC transistors in the third device region 100-3 are configured to have a low parasitic capacitance and are suitable for applications with high-frequency circuits.MBC transistors in the fourth device region 100-4 are suitable for low-power applications, and MBC transistors in the fifth device region are configured to have low resistance and are suitable for high-speed circuit applications. Note that the semiconductor device 100 may include other combinations of device regions to meet the design requirements of different specific circuits. For example, the semiconductor device 100 may include a first device region 100-1 and a third device region 100-3 to serve as a parallel-to-serial converter / serial-to-parallel converter circuit operating at a high frequency.For example, the semiconductor device 100 may include a first device region 100-1 and a fourth device region 100-4 (or a fifth device region) to serve as an analog or low-power circuit.

[0016] Let’s get to Fig. 1, in which the first device region 100-1 may include one or more active regions, such as a first active region 110-1 and a second active region 110-2. The first active region 110-1 and the second active region 110-2 may each be formed from a fin structure patterned from a stack of semiconductor layers. Such a stack may include a plurality of channel layers interleaved with a plurality of sacrificial layers. The channel layers and the sacrificial layers may have different semiconductor compositions. In some implementations, the channel layers are formed from silicon (Si), and the sacrificial layers are formed from silicon germanium (SiGe). In these implementations, an additional germanium content in the sacrificial layers allows the sacrificial layers to be selectively removed or recessed without significantly damaging the channel layers.In some embodiments, the sacrificial layers and the channel layers may be deposited using an epitaxial process, such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Any number of sacrificial layers and channel layers may be formed in the stack to meet design requirements. First, second, third, and fourth channel portions 1081, 1082, 1083, and 1084 may be formed from the channel layers, as shown in FIGS. Fig. 3 to 9. In some embodiments, the channel portions may comprise silicon (Si).

[0017] In the Fig. 3 and Fig. 4, the active regions may be isolated from each other by an isolation element 106. The isolation element 106 may also be referred to as an STI element 106 (STI: shallow trench isolation). In some embodiments, the isolation element 106 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. The first gate structure 120-1 in the Fig. 1, Fig. 3, Fig. 5 and Fig. 7, the second gate structure 120-2 in the Fig. 2, Fig. 4, Fig. 6 and Fig. 8, the third gate structure 120-3 in Fig. 9, the fourth gate structure 120-4 in Fig. 10 and the fifth gate structure 120-5 in Fig. 5 may be formed using a gate replacement or gate-last process. In a gate-last process, a dummy gate stack is first formed over channel regions of the active areas as a placeholder for functional gate structures, such as the first gate structure 120-1, the second gate structure 120-2, the third gate structure 120-3, the fourth gate structure 120-4, and the fifth gate structure 120-5. The dummy gate stack includes a dummy dielectric layer and a dummy gate electrode. In some embodiments, the dummy dielectric layer comprises silicon oxide, and the dummy gate electrode comprises polysilicon. After the dummy gate stack is formed, a gate spacer is formed along sidewalls of the dummy gate stack.Since the gate spacer is not disposed between channel portions and is located above the active regions, the gate spacer layer may also be referred to as a top spacer or a top gate spacer. The first device region 100-1 includes a first top spacer 122-1, which is shown in FIGS. Fig. 1, Fig. 3, Fig. 5 and Fig. 7, and the second device portion 100-2 has a second upper spacer 122-2 which is inserted into the Fig. 2, Fig. 4, Fig. 6 and Fig. 8. The third device region 100-3 also includes a first top spacer 122-1. The fourth device region 100-4 and the fifth device region include a second top spacer 122-2. The first top spacer 122-1, the second top spacer 122-2, and a third top spacer may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, porous oxide, and / or combinations thereof. The top spacers may include air gaps.

[0018] Gate structures, such as the first gate structure 120-1, the second gate structure 120-2, the third gate structure 120-3, the fourth gate structure 120-4, and the fifth gate structure 120-5, include a gate dielectric layer and a gate electrode. The gate dielectric layer includes an interface layer and a high-k dielectric layer. High-k dielectrics used and described herein include dielectric materials with a high dielectric constant, for example, greater than that of thermal silicon oxide, which is about 3.9. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. In one embodiment, the high-k dielectric layer may include hafnium oxide.Alternatively, the high-k dielectric layer may comprise other high-k dielectrics, such as titanium oxide (TiO2), hafnium-zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium-silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium-silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium-lanthanum oxide (HfLaO), lanthanum-silicon oxide (LaSiO), aluminum-silicon oxide (AlSiO), hafnium-tantalum oxide (HfTaO), hafnium-titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxide nitride (SiON), combinations thereof or other suitable materials.The gate electrode of the gate structure may be a single layer or, alternatively, a multi-layer structure comprising, for example, various combinations of a metal with a selected work function to improve device performance (work function metal layer), a cap layer, a wetting layer, an adhesion layer, a metal alloy, or a metal silicide. The gate electrode may, for example, comprise titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or a combination thereof.

[0019] In some embodiments, a gate structure may have different work function layers for n-MBC transistors (such as for the first n-MBC transistor 1000-1N, the second n-MBC transistor 1000-2N, the third n-MBC transistor 1000-3N, the fourth n-MBC transistor 1000-4N, or the fifth n-MBC transistor 1000-5N) and for p-MBC transistors (such as the first p-MBC transistor 1000-1P, the second p-MBC transistor 1000-2P, the third p-MBC transistor 1000-3P, the fourth p-MBC transistor 1000-4P, or the fifth p-MBC transistor 1000-5P). Fig. 3 and Fig. 4. An n-MBC transistor may be fabricated over the p-well 102P, and a p-MBC transistor may be fabricated over the n-well 102N. As shown in the Fig. 3 and Fig. 4, the first gate structure 120-1 and the second gate structure 120-2 share an n-MBC transistor and a p-MBC transistor. The first gate structure 120-1 and the second gate structure 120-2 may each have two gate electrode portions to provide desired threshold voltages for both devices. First, in Fig. 3, the first gate structure 120-1 includes a gate dielectric layer 1202, a first gate electrode portion 1204 over the p-well 102P, and a second gate electrode portion 1206 over the n-well 102N. The first gate electrode portion 1204 includes n-type work function layers, and the second gate electrode portion 1206 includes p-type work function layers. The first gate electrode portion 1204 and the second gate electrode portion 1206 have different compositions and are fabricated separately. Similarly, the second gate structure 120-2 includes a gate dielectric layer 1202, a first gate electrode portion 1204 over the p-well 102P, and a second gate electrode portion 1206 over the n-well 102N. Along their longitudinal direction (y-direction), the gate structures may terminate in dielectric gate end elements 140, which are embedded in the Fig. 1 to 4, 10, and 11. In some implementations, the gate end dielectric elements 140 may be made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, porous oxide, and / or combinations thereof. The gate dielectric layer 1202 may have a thickness of about 3 nm to 20 nm. In some embodiments, the gate dielectric layer 1202 has a uniform thickness in the first device region 100-1 and the second device region 100-2. In some alternative embodiments not individually illustrated in the figures, the gate dielectric layer in the second device region 100-2 is about 0.5 nm to about 3 nm thicker than the gate dielectric layer in the first device region 100-1.

[0020] An MBC transistor according to the present invention comprises: two source / drain elements; a plurality of channel portions extending between the two source / drain elements; and a gate structure enclosing each of the channel portions. The plurality of channel portions are stacked or arranged vertically along the z-direction. For example, the gate structure shown in Fig. 5 includes first channel portions 1081 extending between two first n-type source / drain elements 136N-1 (or two first n-type elements 136N-1) along the x-direction. In some embodiments, first n-type elements 136N-1 comprise silicon doped with an n-type dopant, such as phosphorus (P) or arsenic (As). First n-type elements 136N-1 are in contact with first channel portions 1081 but are spaced from first gate structure 120-1 by first internal spacer elements 124-1. First internal spacer elements 124-1 are interleaved with first channel portions 1081. The first inner spacer elements 124-1 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxide carbide, silicon oxide carbonitride, porous oxide, and / or combinations thereof. Similarly, the Fig. 6, the second gate structure 120-2 includes the third channel portions 1083 extending between two second n-type source / drain elements 136N-2 (or two second n-type elements 136N-2) along the x-direction. In some embodiments, the second n-type elements 136N-2 comprise silicon doped with an n-type dopant, such as phosphorus (P) or arsenic (As). The second n-type elements 136N-2 are in contact with the third channel portions 1083 but are spaced from the second gate structure 120-2 by second internal spacer elements 124-2. The second internal spacer elements 124-2 are interleaved with the third channel portions 1083. The second inner spacer elements 124-2 may be similar in composition to the first inner spacer elements 124-1. As explained later, the first inner spacer elements 124-1 and the second inner spacer elements 124-2 have different dimensions.Although not shown individually in the figures, the first device region 100-1 has second channel parts 1082 (which are shown in . Fig. 3) extending between two first p-source / drain elements, and the second device region 100-2 has fourth channel portions 1084 (which are shown in Fig. 4) extending between two second p-type source / drain elements. The p-type source / drain elements may comprise silicon germanium (SiGe) doped with a p-type dopant, such as boron (B).

[0021] The first device region 100-1, the second device region 100-2, the third device region 100-3, the fourth device region 100-4, and the fifth device region include source / drain contacts electrically connected to the source / drain elements. During the fabrication of MBC transistors, the source / drain elements are connected to the channel portions. An interlayer dielectric (ILD) layer may be deposited over the source / drain elements. In some embodiments, to control the etching of the source / drain contact openings, a contact etch stop layer (CESL) is deposited over the source / drain elements before the ILD layer is deposited. The source / drain contacts may be formed using a self-aligned contact (SAC) process or a non-SAC process.In an SAC process, a source / drain contact opening is defined in a region enclosed by dielectric layers with a different etch selectivity. In a non-SAC process, a source / drain contact opening is defined solely with a photolithographic process. Therefore, the SAC process is less dependent on photomask coverage, whereas the non-SAC process relies on sufficient photomask coverage. An exemplary SAC process uses an SAC dielectric layer, such as an SAC gate dielectric layer 150 shown in FIGS. Fig. 3 to 9. As explained later, when SAC source / drain contacts and non-SAC source / drain contacts are formed on the same substrate, SAC dielectric layers may be present when non-SAC processes are used to form some source / drain contacts. A SAC process reduces a distance between a gate structure and a source / drain contact and is suitable for forming contact structures for highly integrated circuit applications where gate pitches are small. A non-SAC process increases the distance between a gate structure and a source / drain contact and is suitable for applications where gate-to-contact capacitance and contact-to-gate breakdown voltage are undesirable.

[0022] Source / drain contacts manufactured using SAC processes are in the Fig. 1, Fig. 5, Fig. 7, Fig. 10 and Fig. 11, while source / drain contacts made with non-SAC processes are shown in the Fig. 2, Fig. 6, Fig. 8 and Fig. 9 are shown. In the Fig. 1, Fig. 5 and Fig. 7, a first source / drain contact 130 is first produced using a SAC process. In the Fig. 1 and Fig. 5, in which no CESL is formed, the first source / drain contact 130 is sandwiched between two first upper spacers 122-1 and between two SAC gate dielectric layers 150. That is, the first source / drain contact 130 is in direct contact with the SAC gate dielectric layers 150 and the first upper spacers 122-1. In the embodiments shown in Fig. 7, in which a first CESL 156 is formed over the first n-type source / drain element 136N-1, the first CESL 156 is disposed between the first source / drain contact 130 and the SAC gate dielectric element 150, and between the first source / drain contact 130 and the first top spacer 122-1. In some embodiments, the first CESL 156 may comprise silicon nitride. As shown in FIGS. Fig. 10 and Fig. 11, a fourth source / drain contact 134 and a fifth source / drain contact 135 may be in contact with the first upper spacers 122-1, either directly or indirectly via a CESL (not shown). As shown in the Fig. 3 to 9, the source / drain contacts are connected to the source / drain elements via a silicide layer 138. In some embodiments, the silicide layer 138 may comprise titanium silicide, cobalt silicide, or nickel silicide.

[0023] In the Fig. 2, Fig. 6 and Fig. 8, a second source / drain contact 132 extends through a first ILD layer 151, which is arranged between two second upper spacers 122-2 and between two SAC gate dielectric layers 150. That is, the second source / drain contact 132 is spaced from the second upper spacer 122-2 by the first ILD layer 151. In the embodiments shown in Fig. 8, in which a second CESL 158 is formed over the second n-type source / drain element 136N-2, the second CESL 158 is disposed between the first ILD layer 151 and the SAC gate dielectric element 150, and between the first ILD layer 151 and the second top spacer 122-2. Like the first CESL 108, the second CESL 158 may comprise silicon nitride. The first ILD layer 151 may comprise low-k dielectric materials, such as TEOS oxide (TEOS: Tetraethylorthosilicate), undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), or the like. As shown in Fig. 9, a third source / drain contact 133 is spaced from the SAC gate dielectric layer 150 by the first ILD layer 151 and the second CESL 158. As not individually illustrated in some embodiments, if the second CESL 158 is not formed, the third source / drain contact 133 may be spaced from the SAC gate dielectric layer 150 and the second top spacer 122-2 only by the first ILD layer 151.

[0024] Although the first CESL 156 and the second CESL 158 may initially have the same thickness when deposited, their final structures have different thicknesses due to different source / drain contact formation processes. While the first CESL 156 undergoes an etching process in the SAC process, the second CESL 158 does not undergo an etching process in the non-SAC process. As a result, a thickness of the second CESL 158 is greater than a thickness of the first CESL 156. In some embodiments, the first CESL 156 may have a thickness along the x-direction of about 0.2 nm to about 3 nm. In some implementations, the second CESL 158 may have a thickness along the x-direction of about 1.2 nm to about 5 nm.

[0025] Gate vias electrically connect the gate structures to a metal layer. Fig. 3, a first gate via 160 extends from the first gate structure 120-1 through the SAC gate dielectric layer 150 and a second ILD layer 152 to connect to metal lines in a first metal layer 200 having an inter-metal dielectric (IMD) layer 154 enclosing the metal lines. Similarly, a second gate via 162 extends from the second gate structure 120-2 through the SAC gate dielectric layer 150 and the second ILD layer 152 to connect to metal lines in the first metal layer 200. The second ILD layer 152 and the IMD layer 154 may have a composition similar to that of the first ILD layer 151.The first source / drain contact 130, the second source / drain contact 132, the first gate via 160, the second gate via 162, and the first metal layer 200 may comprise titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), copper (Cu), aluminum (Al), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), or a combination thereof. In some embodiments, the first source / drain contact 130, the second source / drain contact 132, the first gate via 160, the second gate via 162, and the first metal layer 200 may comprise a plating or barrier layer made of a metal nitride, such as titanium nitride.

[0026] MBC device structures in the first device region 100-1, the second device region 100-2, the third device region 100-3, the fourth device region 100-4 and the fifth device region are described with reference to the Fig. 1 to 11. Here again, reference is made to Fig. 1. The first device region 100-1 has first source / drain contacts 130 formed using an SAC process. Since the first source / drain contacts 130 are in contact with the first upper spacer 122-1, a first distance S1 between the first source / drain contact 130 and the first upper spacer 122-1 is substantially zero. The first gate structures 120-1 each extend in the longitudinal direction along the y-direction and have a first gate length G1. Furthermore, the first gate structures 120-1 in the first device region 100-1 have a first distance P1. The second device region 100-2 in Fig. 2 includes second source / drain contacts 132 formed using a non-SAC process. Due to the presence of the first ILD layer 151 disposed between the second upper spacer 122-2 and the second source / drain contact 132, a second distance S2 between the second source / drain contact 132 and the second upper spacer 122-2 is greater than 5 nm, e.g., about 5 nm to about 50 nm. Since the first distance S1 is substantially zero, a difference between the second distance S2 and the first distance S1 may be about 5 nm to about 50 nm. And since the MBC transistors in the second device region 100-2 are intended for high-voltage circuit applications, a second gate length G2 of the second gate structure 120-2 is greater than the first gate length G1 of the first gate structure 120-1. In some cases, the second gate length G2 is about 1.2 to 1.5 times the first gate length G1.Furthermore, due to the presence of the first ILD layer 151 between the second upper spacer 122-2 and the second source / drain contact 132, the second pitch P2 may be approximately 1.4 to 4 times the first pitch P1. The larger second pitch S2 and the presence of the first ILD layer 151 made of low-k material contribute to reducing gate contact loss or parasitic capacitance between the second gate structure 120-2 and the second source / drain contact 132. The . Fig. 7 and Fig. 8 illustrate embodiments in which the first CESL 156 and the second CESL 158 are fabricated. Since the second CESL 158, which is disposed along sidewalls of the second upper spacer 122-2, is not etched, it has a greater thickness than the first CESL 156, as discussed above.

[0027] Additionally, the non-SAC source / drain contact may be larger than the SAC source / drain contact to reduce resistor-capacitor (RC) delay. For example, the second source / drain contacts 132 included in the Fig. 2, Fig. 6 and Fig. 8, have a second contact dimension C2 that is larger than a first contact dimension C1 of the first source / drain contacts 130 shown in the Fig. 1, Fig. 5 and Fig. 7. In some implementations, a ratio of the second contact dimension C2 to the first contact dimension C1 (C2 / C1) is about 1.2 to about 3. The larger second contact dimension C2 enables larger source / drain vias, which may result in reduced resistance. For example, dimensions of a source / drain via 170 above the second source / drain contact 132 may become larger along the x-direction when the second source / drain contact 132 has a larger second contact dimension C2. In some embodiments, the larger second contact dimension C2 enables the source / drain via 170 to be increased in width or diameter (if circular) by about 1.2 to 4 times compared to the smaller first contact dimension C1.To improve the gate contact breakdown voltage in high-voltage applications, the second upper spacer 122-2 in the second device region 100-2 is thicker than the first upper spacer 122-1 in the first device region 100-1, and the second inner spacer element 124-2 in the second device region 100-2 is thicker than the first inner spacer element 124-1 in the first device region 100-1 along the x-direction. In some cases, a difference between a thickness of the second upper spacer 122-2 and the thickness of the first upper spacer 122-1 is about 0.5 nm to 5 nm. The first upper spacer 122-1 may have a thickness of about 3 nm to about 12 nm. In some cases, a difference between the thickness of the second inner spacer element 124-2 and the thickness of the first inner spacer element 124-1 is about 0.5 nm to 5 nm.The first inner spacer element 124-1 may have a thickness of about 3 nm to about 12 nm. The larger pitch S2 and the larger second contact dimension C2 naturally result in a wider source / drain element along the x-direction. For example, a width of the second n-type source / drain element 136N-2 is greater than a width of the first n-type source / drain element 136N-1.

[0028] In some embodiments, a height of the source / drain elements along the z-direction may vary depending on the manufacturing process for the source / drain contacts. When a SAC process is used to manufacture the first source / drain contact 130, as shown in FIGS. Fig. 5 and Fig. 7, the first n-source / drain element 136N-1 has a first height H1. When a non-SAC process is used to form the second source / drain contact 132, as shown in FIGS. Fig. 6 and Fig. 8, the first n-type source / drain element 136N-1 has a second height H2. To accommodate the SAC process, the first n-type source / drain element 136N-1 is deposited until it is higher than the uppermost first channel portion 1081 to reduce the aspect ratio when creating a contact opening for the first source / drain contact 130. In contrast, the second n-type source / drain element 136N-2 may be coplanar with or deeper than the uppermost third channel portion 1083 to improve the source / drain-gate breakdown voltage. In these embodiments, the first height H1 is greater than the second height H2.

[0029] Now let’s get to the Fig. 3 and Fig. 4. To accommodate the lower hole mobility in the channel portions and provide improved CMOS (complementary metal oxide semiconductor) transistor performance, the first channel portions 1081, the second channel portions 1082, the third channel portions 1083, and the fourth channel portions 1084 may have different channel widths along the y-direction. As shown in Fig. 3, in the first device region 100-1, the first channel portions 1081 may each have a first channel width W1, and the second channel portions 1082 may each have a second channel width W2. In some embodiments, the second channel width W2 for the p-MBC transistor above the n-well 102N is larger than the first channel width W1 for the n-MBC transistor above the p-well 102P. In some cases, a ratio of the second channel width W2 to the first channel width W1 (W2 / W1) is about 1.05 to about 2. The lower limit of this range accounts for a process variation of about 5%. This means that a ratio W2 / W1 of 1 to 1.05 may not indicate that the second channel width W2 should be larger than the first channel width W1.This ratio W2 / W1 must not be greater than about 2, since such a width difference may require significant overetching to expose the channel portions having the second channel width W2, and this overetching may undesirably reduce the thickness of the channel portions having the first channel width W1. As shown in . Fig. 4, in the first device region 100-1, the third channel parts 1083 may each have a third channel width W3, and the fourth channel parts 1084 may each have a fourth channel width W4.

[0030] In some embodiments, the fourth channel width W4 for the p-MBC transistor above the n-well 102N is larger than the third channel width W3 for the n-MBC transistor above the p-well 102P. In some cases, a ratio of the fourth channel width W4 to the third channel width W3 (W4 / W3) is about 1.05 to about 2. The lower limit of this range accounts for a process variation of about 5%. This means that a ratio W4 / W3 of 1 to 1.05 may not indicate that the fourth channel width W4 should be larger than the third channel width W3. This ratio W4 / W3 must not be larger than about 2, since such a width difference may require a significant overetch to expose the channel portions having the fourth channel width W4, and this overetch may undesirably reduce the thickness of the channel portions having the third channel width W3.Additionally, the channel widths for the second device region 100-2 may be equal to or greater than the channel widths for the first device region 100-1 to accommodate a higher drive current associated with high-voltage applications. In some cases, a ratio of the third channel width W3 to the first channel width W1 may be about 1 to about 3. In some cases, a ratio of the fourth channel width W4 to the second channel width W2 may be about 1 to about 3. A channel width and a spacing between channels along the z-direction for the first channel portions 1081, the second channel portions 1082, the third channel portions 1083, and the fourth channel portions 1084 may be substantially equal.

[0031] MBC transistors in the first device region 100-1 or in the second device region 100-2 may be combined with MBC transistors of other structures in a third device region 100-3, which is Fig. 9, a fourth device area 100-4, which in Fig. 10, or a fifth device area shown in Fig. 11. For ease of reference, MBC transistors in the first device region 100-1 may be referred to as first MBC transistors, MBC transistors in the second device region 100-2 may be referred to as second MBC transistors, MBC transistors in the third device region 100-3 may be referred to as third MBC transistors, MBC transistors in the fourth device region 100-4 may be referred to as fourth MBC transistors, and MBC transistors in the fifth device region may be referred to as fifth MBC transistors. As stated above, the first, second, third, fourth, and fifth MBC transistors may be n-type or p-type transistors.

[0032] Now let’s come to Fig. 9, which shows a layout diagram of the third device region 100-3. The third MBC transistors in the third device region 100-3 are intended for applications with high-frequency circuits that are sensitive to parasitic capacitance between gate structures and source / drain contacts. As shown in Fig. As shown in Figure 9, the third MBC transistor includes third channel portions 1083 extending between two second n-type source / drain elements 136N-2. A third gate structure 120-3 encloses each of the third channel portions 1083. A third source / drain contact 133 is disposed above the second n-type source / drain element 136N-2. The third source / drain contact 133 is formed using a non-SAC process and is spaced apart from the third gate structure 120-3 by a third distance S3. The third source / drain contact 133 has a third contact dimension C3 along the x-direction. The third gate structures 120-3 have a third gate length G3 and a third distance P3. Since the third MBC transistors are not intended for high-voltage applications, the third gate length G3 is smaller than the second gate length G2 and can be similar to the first gate length G1. In some cases, the ratio of the second gate length G2 to the third gate length G3 can be about 1.2 to about 2.To increase the gate contact pitch, the third pitch P3 may be similar to the second pitch P2. The third pitch S3 may be similar to the second pitch S2. In some cases, the third pitch S3 is greater than 5 nm, e.g., about 5 nm to about 50 nm. The third contact dimension C3 is larger than the first contact dimension C1. In some implementations, a ratio of the third contact dimension C3 to the first contact dimension C1 may be greater than 1.4, e.g., about 1.4 to about 2.

[0033] As in Fig. 10, the fourth MBC transistor includes a fourth gate structure 120-4 disposed between two fourth source / drain contacts 134. The fourth source / drain contact 134 is formed using a SAC process and contacts a fourth upper spacer 122-4. That is, the fourth source / drain contact 134 is spaced from the fourth upper spacer 122-4 by a first distance S1, which is substantially zero. The fourth source / drain contact 134 has a fourth contact dimension C4 along the x-direction. The fourth gate structures 120-4 have a fourth gate length G4 and a fourth pitch P4. The fourth MBC transistors are intended for low-power circuit applications. The fourth gate length G4 is greater than the first gate length G1. In some embodiments, a ratio of the fourth gate length G4 to the first gate length G1 may be about 1.1 to about 1.5.Similarly, a ratio of the fourth distance P4 to the first distance P1 may be about 1.1 to 1.5. When the ratio of the fourth distance P4 to the first distance P1 is less than 1.1 (i.e., when there is a difference of 10%), an increase in a source reverse current (I. soff ) may be insignificant and does not justify implementing different gate pitches. However, if the ratio of the fourth pitch P4 to the first pitch P1 is greater than 1.5, a forward current (I on ) decrease too much to meet the design requirements of modern device nodes. The fourth upper spacer 122-4 may be similar to the first upper spacer 122-1.

[0034] As in Fig.As shown in Figure 11, the fifth MBC transistor includes a fifth gate structure 120-5 disposed between two fifth source / drain contacts 135. The fifth source / drain contact 135 is formed using a SAC process and contacts a fifth upper spacer 122-5. That is, the fifth source / drain contact 135 is spaced from the fifth upper spacer 122-5 by the first distance S1, which is substantially zero. The fifth source / drain contact 135 has a fifth contact dimension C5 along the x-direction. The fifth gate structures 120-5 have a fifth gate length G5 and a fifth pitch P5. The fifth MBC transistors are intended for high-speed circuit applications. The fifth gate length G5 may be similar to the first gate length G1. Likewise, a ratio of the fifth distance P5 to the first distance P1 may be approximately 1.1 to 1.5.When the ratio of the fifth distance P5 to the first distance P1 is less than 1.1 (i.e., when there is a difference of 10%), an increase of a source reverse current (I. soff ) may be insignificant and does not justify implementing different gate pitches. However, if the ratio of the fifth pitch P5 to the first pitch P1 is greater than 1.5, a forward current (I on ) decrease too much to meet the design requirements of modern device nodes.

[0035] In some embodiments, the semiconductor device 100 may include first MBC transistors in the first device region 100-1 and third MBC transistors in the third device region 100-3 to serve as a parallel-to-serial converter / serial-to-parallel converter circuit operating at a high frequency. In some further embodiments, the semiconductor device 100 may include first MBC transistors in the first device region 100-1 and fourth MBC transistors in the fourth device region 100-4 (or the fifth device region) to serve as an analog or low-power circuit.

[0036] One or more embodiments of the present invention provide numerous advantages for a semiconductor device and its fabrication. For example, the present invention provides: structures of a first MBC transistor having smaller gate lengths and pitches, and source / drain contacts fabricated using a self-aligned contact (SAC) process; and structures of a second MBC transistor having larger gate lengths and pitches, and non-SAC source / drain contacts. The first MBC transistors enable dense packaging, which is suitable for large-scale integrated circuit applications. The second MBC transistors have a larger gate-to-contact pitch to improve breakdown voltage, which is suitable for high-voltage applications such as drivers and controllers for electronic fuse devices. A larger gate pitch also improves parasitic capacitance.The present invention can also provide third MBC transistors suitable for high frequency applications, fourth MBC transistors suitable for low power applications, and fifth MBC transistors suitable for high speed applications.

Claims

[1] Semiconductor device comprising: a first transistor in a first device region (100-1) of a substrate (102), the first transistor comprising: a first source / drain element (136N-1) and a second source / drain element (136N-1), a first plurality of channel portions (1081) sandwiched between the first source / drain element (136N-1) and the second source / drain element (136N-1), a first gate structure (120-1) enclosing each of the first plurality of channel portions (1081), a first source / drain contact (130) disposed above the first source / drain element (136N-1), and a first upper gate spacer (122-1) disposed between the first gate structure (120-1) and the first source / drain contact (130); and a second transistor in a second device region (100-2) of the substrate (102), the second transistor comprising: a third source / drain element (136N-2) and a fourth source / drain element (136N-2), a second plurality of channel portions (1082) sandwiched between the third source / drain element (136N-2) and the fourth source / drain element (136N-2), a second gate structure (120-2) enclosing each of the second plurality of channel portions (1082), a second source / drain contact (132) disposed above the third source / drain element (136N-2), and a second upper gate spacer (122-2) arranged between the second gate structure (120-2) and the second source / drain contact (132), wherein a distance (S2) between the second upper gate spacer (122-2) and the second source / drain contact (132) is greater than a distance (S1) between the first upper gate spacer (122-1) and the first source / drain contact (130), wherein: each of the first plurality of channel parts (1081) extends along a first direction (x), each of the second plurality of channel parts (1082) extends along a second direction (x), the first upper gate spacer (122-1) has a first thickness along the first direction (x), the second upper gate spacer (122-2) has a second thickness along the second direction (x), and the second thickness is greater than the first thickness, wherein the first and second plurality of channel portions originate from a stack of semiconductor layers of interleaved channel layers and sacrificial layers by patterning fin structures therefrom and selectively removing the sacrificial layers. [2] A semiconductor device according to claim 1, wherein: the first transistor further comprises a first etch stop layer (156) disposed between the first source / drain contact (130) and the first upper gate spacer (122-1), and the second transistor further comprises a second etch stop layer (158) and a low-k dielectric layer (151) disposed between the second source / drain contact (132) and the second upper gate spacer (122-2). [3] The semiconductor device of claim 2, wherein the first etch stop layer (156) is in direct contact with the first source / drain contact (130) and the first upper gate spacer (122-1). [4] The semiconductor device according to claim 2 or 3, wherein the second etch stop layer (158) is in direct contact with the second upper gate spacer (122-2) and the low-k dielectric layer (151). [5] The semiconductor device according to claim 2, 3 or 4, wherein a thickness of the first etch stop layer (156) is smaller than a thickness of the second etch stop layer (158). [6] A semiconductor device according to claim 2, 3, 4 or 5, wherein: the first etch stop layer (156) and the second etch stop layer (158) comprise silicon nitride, and the low-k dielectric layer (151) comprises silicon oxide. [7] A semiconductor device according to any one of the preceding claims, wherein the first source / drain contact (130) has a first contact dimension (C1) and the second source / drain contact (132) has a second contact dimension (C2), the second contact dimension (C2) being larger than the first contact dimension (C1). [8] A semiconductor device according to any one of the preceding claims, wherein: the first device region is a region of a highly integrated circuit and the second device area is an area of a high voltage application. [9] A semiconductor device according to any one of the preceding claims, wherein: the first gate structure (120-1) has a first gate length (G1), and the second gate structure (120-2) has a second gate length (G2) which is greater than the first gate length (G1). [10] Semiconductor device comprising: a first transistor comprising: a first source / drain element (136N-1) and a second source / drain element (136N-1), a first plurality of channel portions (1081) along a first direction (x) layered between the first source / drain element (136N-1) and the second source / drain element (136N-1), a first gate structure (120-1) enclosing each of the first plurality of channel portions (1081) and comprising a gate dielectric layer and a gate electrode, and a first plurality of inner spacer elements (124-1) arranged between the first gate structure (120-1) and the first source / drain element (136N-1); and a second transistor comprising: a third source / drain element (136N-2) and a fourth source / drain element (136N-2), a second plurality of channel portions (1082) along a second direction (x) layered between the third source / drain element (136N-2) and the fourth source / drain element (136N-2), a second gate structure (120-2) enclosing each of the second plurality of channel portions (1082) and comprising a gate dielectric layer and a gate electrode, and a second plurality of inner spacer elements (124-2) arranged between the second gate structure (120-2) and the third source / drain element (136N-2), wherein: each of the first plurality of inner spacer elements (124-1) has a first thickness along the first direction (x), each of the second plurality of inner spacer elements (124-2) has a second thickness along the second direction (x), and the second thickness is greater than the first thickness, wherein the first transistor further comprises: a first source / drain contact (130) above the first source / drain element (136N-1); and a first upper gate spacer (122-1) arranged along sidewalls of the first gate structure (120-1) above the first plurality of channel portions (1081), wherein the second transistor further comprises: a second source / drain contact (132) over the third source / drain element (136N-2); and a second upper gate spacer (122-2) disposed along sidewalls of the second gate structure (120-2) above the second plurality of channel portions (1082), and a distance (S1) between the first source / drain contact (130) and the first upper gate spacer (122-1) is smaller than a distance (S2) between the second source / drain contact (132) and the second upper gate spacer (122-2), wherein the first and second plurality of channel portions originate from a stack of semiconductor layers of interleaved channel layers and sacrificial layers by patterning fin structures therefrom and selectively removing the sacrificial layers. [11] The semiconductor device of claim 10, wherein the first plurality of channel portions (1081) are interlocked with the first plurality of inner spacer elements (124-1). [12] The semiconductor device according to claim 10 or 11, wherein a width of the first source / drain element (136N-1) along the first direction (x) is smaller than a width of the third source / drain element (136N-2) along the second direction (x). [13] The semiconductor device according to claim 10, 11 or 12, wherein a thickness of the first etch stop layer (156) is smaller than a thickness of the second etch stop layer (158). [14] A semiconductor device according to any one of claims 10 to 13, wherein: the first source / drain contact (130) has a third width (W3) along the first direction (x), the second source / drain contact (132) has a fourth width (W4) along the second direction (x), and the fourth width (W4) is greater than the third width (W3). [15] The semiconductor device according to claim 14, wherein a ratio of the fourth width to the third width (W4 / W3) is about 1.2 to 3.

0. [16] Semiconductor device comprising: a high-density transistor that has: a first gate structure (120-1) and a second gate structure (120-1) defining a first intermediate distance (P1), and a first source / drain contact (130) arranged between the first gate structure (120-1) and the second gate structure (120-2) along a first direction (x); and a high-voltage transistor having: a third gate structure (120-2) and a fourth gate structure (120-2) defining a second intermediate distance (P2) that is greater than the first intermediate distance (P1), and a second source / drain contact (132) arranged between the third gate structure (120-2) and the fourth gate structure (120-2) along a second direction (x), where: the first source / drain contact (130) is spaced a first distance from the first gate structure (120-1), and the second source / drain contact (132) is spaced from the third gate structure (120-2) by a second distance that is greater than the first distance, wherein the semiconductor device (100) further comprises a substrate (102), wherein the high-density transistor further comprises: a first plurality of channel parts (1081) stacked along a third direction (z) away from the substrate (102); and a first source / drain element (136N-1) in contact with the first plurality of channel portions (1081), wherein the high-voltage transistor further comprises: a second plurality of channel parts (1082) stacked along the third direction (z); and a second source / drain element (136N-1) in contact with the second plurality of channel portions (1082), the first source / drain element (136N-1) is higher than an uppermost channel part of the first plurality of channel parts (1081) along the third direction (z), and the second source / drain element (136N-1) is substantially flush with an uppermost channel portion of the second plurality of channel portions (1082) along the third direction (z), wherein the first and second plurality of channel portions originate from a stack of semiconductor layers of interleaved channel layers and sacrificial layers by patterning fin structures therefrom and selectively removing the sacrificial layers. [17] A semiconductor device according to claim 16, wherein: the high-density transistor further comprises a first via (170) over the first source / drain contact (130), the high-voltage transistor further comprises a second via (170) over the second source / drain contact (132), and a width of the first via (C1) along the first direction (x) is smaller than a width of the second via (C2) along the second direction (x). [18] A semiconductor device according to claim 16 or 17, wherein: the high-density transistor further comprises a first etch stop layer (156) disposed between the first source / drain contact (130) and the first gate structure (120-1), the high-voltage transistor further comprises a second etch stop layer (158) arranged between the second source / drain contact (132) and the third gate structure (120-2), and a thickness of the second etch stop layer (158) along the second direction (x) is greater than a thickness of the first etch stop layer (156) along the first direction (x). [19] A semiconductor device according to claim 18, wherein: the first etch stop layer (156) is in contact with the first source / drain contact (130), and the second etch stop layer (158) is spaced from the second source / drain contact (132) by an interlayer dielectric layer (151). [20] The semiconductor device of claim 19, wherein the second etch stop layer (158) is in direct contact with a SAC gate dielectric element (150) and the interlayer dielectric layer (151).

Images