FINFET DEVICE AND METHOD FOR ITS MANUFACTURING

Abstract

Device comprising: a substrate (50); a first insulating structure (56) and a second insulating structure (56) above the substrate (50); a semiconductor fin (52) above the substrate (50) and between the first insulating structure (56) and the second insulating structure (56), wherein an upper surface of the semiconductor fin (52) lies above an upper surface of the first insulating structure (56) and an upper surface of the second insulating structure (56); a third insulating structure extending through the semiconductor fin (52) and between the first insulating structure (56) and the second insulating structure (56), wherein the third insulating structure comprises: a first dielectric material (80);and a second dielectric material (84) above the first dielectric material (80), wherein an interface between the first dielectric material (80) and the second dielectric material (84) lies below the top surface of the first insulating structure (56) and the top surface of the second insulating structure (56); a gate stack (96) above the semiconductor fin (52) and adjacent to the third insulating structure, wherein an top surface of the gate stack (96) lies below an top surface of the third insulating structure; and a gate mask (102) directly above the gate stack (96) and between gate spacers (66, 68), wherein a height of an top surface of the gate mask (102) above the semiconductor fin (52) and measured from an top surface of the semiconductor fin (52) is between about 20 nm and about 30 nm.

Description

GENERAL STATE OF THE ART Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of a material onto a semiconductor substrate, and structuring the various material layers using lithography to create circuit components and elements on top of them. The semiconductor industry is increasingly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature sizes decrease, additional problems arise that need to be addressed. Prior art relating to the subject matter of the invention can be found, for example, in US 2019 / 0305099A1 and US 2018 / 0047634A1. The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1 illustrates an example of a FinFET in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B , Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 22A, Fig. 22B, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig.Figures 24B, 25A, 25B, 26A, 26B, 27A, 27B, 28A, 28B, 29A and 29B are cross-sectional views of intermediate stages in the manufacture of a FinFET device according to some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations explained. Furthermore, spatially related terms such as "underlying," "below," "lower," "above," "upper," and the like may be used herein for a more convenient description of the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or with other orientations), and the spatially related descriptors used herein may be interpreted accordingly. Embodiments are described with reference to a specific context, namely a FinFET device and a method for forming it. Various embodiments presented herein are explained in the context of a FinFET device formed using a gate-last process. In other embodiments, a gate-first process may be used. Various embodiments explained herein enable an improvement in the gap-filling performance of the dielectric material for a trench formed during a fin-cutting process, thereby reducing or avoiding problems due to gap and / or void formation in the dielectric material within the trench, reducing or avoiding short circuits between contact plugs, and improving device and yield performance.In some embodiments, the trench formed during the fin-cutting process is filled with a variety of dielectric materials. In some embodiments, the trench-filling process may include filling the trench with a first dielectric material, partially removing the first dielectric material from the trench so that an upper portion of the trench is not filled with a dielectric material, and filling the upper portion of the trench with a second dielectric material. The second dielectric material may be the same as or different from the first dielectric material. Fig. 1 illustrates an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET has a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Insulation regions 56 are arranged in the substrate 50, and the fin 52 projects above and between adjacent STI regions 56. Although the STI regions 56 are described / illustrated as being separated from the substrate 50, the term "substrate" as used herein may refer to the semiconductor substrate only or to a semiconductor substrate including insulation regions. Although the fin 52 is illustrated as a single, continuous material like the substrate 50, the fin 52 and / or the substrate 50 may comprise a single material or a plurality of materials.In this context, fin 52 refers to the section that extends between the adjacent STI areas 56. A gate dielectric layer 92 is located along side walls and over a top surface of the fin 52, and a gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 70 are arranged on opposite sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94. Fig. 1 further illustrates reference cross-sections that will be used in later figures. Cross-section AA is located along a longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to a direction of current flow between the epitaxial source / drain regions 70 of the FinFET. Cross-section BB is perpendicular to cross-section AA and is located along a longitudinal axis of the fin 52 and in a direction of, for example, the current flow between the epitaxial source / drain regions 70 of the FinFET.Cross-section CC is parallel to cross-section AA and extends through the source / drain region 70 of the FinFET. For clarity, the following figures refer to these cross-sections. 2, 3, 4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. Figures 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 23C, 24A, 24B, 25A, 25B, 26A, 26B, 27A, 27B, 28A, 28B, 29A and 29B are cross-sectional views of intermediate stages in the manufacture of a FinFET device according to some embodiments. Figures 2, 3, 4, 5, 6 to 7 illustrate cross-sectional views along the reference cross-section AA, illustrated in Figure 1, with the exception of several fins. Figures 8B-29B and 23C illustrate along the reference cross-section BB, which is shown in Figure 1.Figure 1 illustrates the cross-section CC, except for several gate structures. Figures 10C and 10D illustrate the cross-section CC shown in Figure 1, except for several fins and several source / drain regions. Figures 8A-29A illustrate the cross-section AA shown in Figures 8B-29B. Figure 2 shows a substrate 50. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can also be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed by an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise silicon; germanium; a composite semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In some embodiments, the substrate 50 can have an n-region and a p-region (not shown separately). The n-region is used to form n-devices, such as NMOS transistors, e.g., n-FinFETs. The p-region is used to form p-devices, such as PMOS transistors, e.g., p-FinFETs. The n-region can be physically separated from the p-region, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-region and the p-region. In Fig. 3, fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 in the substrate 50 can be formed by etching grooves in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), a combination thereof, or the like. The etching process can be anisotropic. The fins 52 extend from a top surface 50t of an unstructured section of the substrate 50. The unstructured section of the substrate 50 can be referred to as the substrate. The fins 52 can be formed by any suitable method. For example, the fins 52 can be formed using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, which makes it possible to create structures that, for example, have spacings that are smaller than what can otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can then be used as a mask to form the fins 52. In Fig. 4, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon dioxide, a nitride, a combination thereof, or the like, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to transform it into another material, such as an oxide), a combination thereof, or the like. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon dioxide formed by an FCVD process. An annealing process can be performed after the insulating material has been formed.In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is illustrated as a single layer, some embodiments can use multiple layers. For example, in some embodiments, a lining (not shown) can first be formed along surfaces of the substrate 50 and the fins 52. Then, a filler material, such as those previously described, can be formed over the lining. In Fig. 5, a removal process is applied to the insulation material 54 to remove excess sections of the insulation material 54 above the fins 52. In some embodiments, a planarization process, such as a chemical-mechanical polishing (CMP) process, a back-etching process, combinations thereof, or the like, may be used. The planarization process exposes the fins 52 so that the upper surfaces of the fins 52 and the upper surface of the insulation material 54 are essentially at the same level or coplanar (within process variations) after the planarization process is complete. In Fig. 6, the insulation material 54 (see Fig. 5) is recessed to form shallow trench insulation regions (STI regions) 56. The insulation material 54 is recessed such that the upper sections of the fins 52 project between adjacent STI regions 56. Furthermore, the upper surfaces of the STI regions 56 can have a flat surface, as illustrated, a convex surface, a concave surface (such as moldings), or a combination thereof. The upper surfaces of the STI regions 56 can be formed as flat, convex, and / or concave by suitable etching. The STI areas 56 can be spared using an acceptable etching process, such as an etching process that is selective with respect to the material of the insulation material 54 (e.g., etching the material of the insulation material 54 at a faster rate than the material of the fins 52).For example, chemical oxide removal can be achieved using a suitable etching process with, for example, dilute hydrofluoric acid (dHF). The process described with respect to Figs. 2, 3, 4, 5 to 6 is only one example of how the fins 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins. For example, the fins 52 in Fig.In one embodiment, a material different from the fins 52 can be recessed, and a material different from the fins 52 can be grown epitaxially over the recessed fins 52. In such embodiments, the fins comprise the recessed material as well as the epitaxially grown material arranged over the recessed material. In yet another embodiment, a dielectric layer can be formed over an upper surface of the substrate 50, and grooves can be etched through the dielectric layer. Then, heteroepitaxial structures can be grown epitaxially in the grooves using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins.In some embodiments where homoepitaxial or heteroepitaxial structures are grown epitaxially, the epitaxially grown materials can be doped on-site during growth, which may eliminate the need for prior and subsequent implantations, although on-site doping and implantation doping can be used together. Furthermore, it can be advantageous to epitaxially grow a material in the n-region of the substrate that differs from a material in the p-region of the substrate 50. In various embodiments, upper sections of the fins 52 can be formed from silicon germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming the III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. Furthermore, suitable wells (not shown) can be formed in the fins 52 and / or the substrate 50 as shown in Fig. 6. In some embodiments, a P-well can be formed in the n-region of the substrate 50 and an N-well can be formed in the p-region of the substrate 50. In some embodiments, a P-well or an N-well is formed in both the n-region and the p-region of the substrate 50. In the embodiments with different well types, the different implantation steps for the n-region and the p-region of the substrate 50 can be achieved using a photoresist or other masks (not shown). For example, a first photoresist can be formed over the fins 52 and the STI regions 56 in both the n-region and the p-region of the substrate 50. The first photoresist is structured to expose the p-region of the substrate 50.The first photoresist can be formed using a spin-on technique and can be structured using acceptable photolithography techniques. After the first photoresist is structured, n-impurity implantation is performed in the p-region of substrate 50, while the remaining portion of the first photoresist acts as a mask to essentially prevent n-impurities from being implanted into the n-region of substrate 50. The n-impurities can be phosphorus, arsenic, antimony, or the like, implanted in the region at a dose of 10¹⁵ cm⁻² or less, such as between approximately 10¹² cm⁻² and approximately 10¹⁵ cm⁻². In some embodiments, the n-impurities can be implanted with an implantation energy of approximately 1 keV to approximately 10 keV.After implantation, the initial photoresist is removed, for example by an acceptable ashing process followed by a wet cleaning process. Following the implantation of the p-region of substrate 50, a second photoresist is formed over the fins 52 and the STI regions 56 in both the p-region and the n-region of substrate 50. The second photoresist is structured to expose the n-region of substrate 50. This second photoresist can be formed using a spin-on technique and can be structured using acceptable photolithography techniques. After the second photoresist is structured, p-contamination implantation can be performed in the n-region of substrate 50, while the remaining portion of the second photoresist acts as a mask to essentially prevent p-contamination from being implanted into the p-region of substrate 50. The p-impurities may be boron, BF2, indium or the like, implanted in the area at a dose of 1015cm-2, such as between approximately 1012cm-2 and approximately 1015cm-2.In some embodiments, the p-impurities can be implanted with an implantation energy of approximately 1 keV to approximately 10 keV. After implantation, the second photoresist can be removed, for example by an acceptable ashing process followed by a wet cleaning process. After implanting the n-region and p-region of substrate 50, a annealing process can be performed to activate the implanted p- and / or n-impurities. In some embodiments, the grown epitaxial fin materials can be doped on-site during growth, which may eliminate the need for implantation, although on-site doping and implantation doping can be used together. In Fig. 7, a dummy dielectric layer 60 is formed on the fins 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. Subsequently, a dummy gate layer 62 is formed over the dummy dielectric layer 60. The dummy gate layer 62 can be deposited over the dummy dielectric layer 60 and then planarized using, for example, a CMP process. The dummy gate layer 62 can be a conductive material and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, metals, combinations thereof, and the like.The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques known in the art and used for depositing conductive materials. The dummy gate layer 62 can be made of materials that have a higher etch selectivity than the materials of the STI regions 56. It should be noted that the dummy dielectric layer 60 is shown for illustrative purposes only to cover only the fins 52. In some embodiments, the dummy dielectric layer 60 can be deposited such that it covers the STI regions 56, extending between the dummy gate layer 62 and the STI regions 56. Die Fig. 8A , Fig. 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 13A , Fig. 13B , Fig. 14A , Fig. 14B , Fig. 15A , Fig. 15B , Fig. 16A , Fig. 16B , Fig. 17A , Fig. 17B , Fig. 18A , Fig. 18B , Fig. 19A , Fig. 19B , Fig. 20A , Fig. 20B , Fig. 21A , Fig. 21B , Fig. 22A , Fig. 22B , Fig. 23A , Fig. 23B , Fig. 23C , Fig. 24A , Fig. 24B , Fig. 25A , Fig. 25B , Fig. 26A , Fig. 26B , Fig. 27A , Fig. 27B , Fig. 28A , Fig. 28B , Fig. 29A und Fig. 29B veranschaulichen verschiedene zusätzliche Schritte bei der Herstellung einer FinFET-Vorrichtung gemäß einigen Ausführungsformen. Die Fig. 8A , Fig. 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 13A , Fig. 13B , Fig. 14A , Fig. 14B , Fig. 15A , Fig. 15B , Fig. 16A , Fig. 16B , Fig. 17A , Fig. 17B , Fig. 18A , Fig. 18B , Fig. 19A , Fig. 19B , Fig. 20A , Fig. 20B , Fig. 21A , Fig. 21B , Fig. 22A , Fig.Figures 22B, 23A, 23B, 23C, 24A, 24B, 25A, 25B, 26A, 26B, 27A, 27B, 28A, 28B, 29A, and 29B illustrate features in each of the n-region and p-region of substrate 50. For example, the structures shown in Figures 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, 12A, and 13B can be used to illustrate features in each of the n-region and p-region of substrate 50. 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B , 20A , 20B , 21A , 21B , 22A , 22B , 23A , 23B , 23C , 24A , 24B , 25A , 25B , 26A , Fig. 26B, Fig. 27A, Fig. 27B , Fig. 28A , Fig. 28B , Fig. 29A and Fig. 29B illustrate that this can be applied to both the n-region and the p-region of substrate 50.Differences (if any) regarding the structures of the n-region and the p-region of substrate 50 are described in the text accompanying each figure. In Figures 8A and 8B, the dummy gate layer 62 (see Figure 7) is structured to form dummy gates 64. The dummy gate layer 62 can be structured using acceptable photolithography and etching techniques. In some embodiments, the etching techniques may include one or more anisotropic etching processes, such as RIE, NBE, a combination thereof, or the like. The dummy gates 64 cover the channel regions 58 of the fins 52. The structure of the structured mask can be used to physically separate each dummy gate 64 from adjacent dummy gates 64. The dummy gates 64 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of each of the fins 52. As described in more detail below, the dummy gates 64 are sacrificial gates and are subsequently replaced by substitute gates. Accordingly, the dummy gates 64 can also be referred to as victim gates.In other embodiments, some of the dummy gates 64 are not replaced and remain in the final structure of the resulting FinFET device. The dummy gates 64 have upper surfaces located above the fins 52 at a height H1 measured from the upper surfaces of the fins 52. In some embodiments, the height H1 is between approximately 90 nm and approximately 120 nm. Furthermore, in Figures 8A and 8B, gate seal spacers 66 can be formed on exposed surfaces of the dummy gates 64 and / or the fins 52. Thermal oxidation or deposition followed by anisotropic etching can form the gate seal spacers 66. The gate seal spacers 66 can comprise silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, a combination thereof, or the like. After forming the gate seal spacers 66, implantations for lightly doped source / drain regions (LDD regions) (not explicitly illustrated) can be performed. In embodiments with different device types, similar to the implantations previously described in Figure 6, a mask, such as a photoresist, can be formed over the region, the n-region, while the p-region is exposed, and impurities of a suitable type (e.g.,p-type impurities can be implanted into the exposed fins 52 in the p-region. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-region while the n-region is exposed, and impurities of a suitable type (e.g., n-type) can be implanted into the exposed fins 52 in the n-region. The mask can then be removed. The n-type impurities can be any of the n-type impurities previously described, and the p-type impurities can be any of the p-type impurities previously described. The lightly doped source / drain regions can have a dose of impurities of approximately 10¹² cm⁻² to approximately 10¹⁶ cm⁻². In some embodiments, the suitable impurities can be implanted with an implantation energy of approximately 1 keV to approximately 10 keV.Tempering can be used to activate the implanted impurities. In Figures 9A and 9B, gate spacers 68 are formed on the gate seal spacers 66 along the side walls of the dummy gates 64. The gate spacers 68 can be formed by conformal deposition of an insulating material followed by anisotropic etching of the insulating material. The insulating material of the gate spacers 68 can comprise silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, a combination thereof, or the like. In some embodiments, the gate spacers 68 can have a plurality of layers (not shown) such that the layers have different materials. In some embodiments, the gate spacers 68 and the gate seal spacers 66 can have the same material. In other embodiments, the gate spacers 68 and the gate seal spacers 66 can have different materials. It should be noted that the preceding disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be employed (e.g., the gate seal spacers 66 may not be etched prior to the formation of the gate spacers 68, resulting in "L-shaped" gate seal spacers, spacers may be formed and removed, and / or the like). Furthermore, the n-devices and the p-devices may be formed using different structures and steps. For example, LDD regions for n-devices may be formed prior to the formation of the gate seal spacers 66, while the LDD regions for p-devices may be formed after the formation of the gate seal spacers 66. In Figures 10A and 10B, epitaxial source / drain regions 70 are formed in the fins 52 to apply stress in the respective channel regions 58, thereby improving device performance. The epitaxial source / drain regions 70 are formed in the fins 52 such that each dummy gate 64 is located between adjacent pairs of epitaxial source / drain regions 70. In some embodiments, the epitaxial source / drain regions 70 may extend into the fins 52. In some embodiments, the gate spacers 68 are used to separate the epitaxial source / drain regions 70 from the dummy gates 64 by a suitable lateral distance, so that the epitaxial source / drain regions 70 do not short-circuit subsequently formed gates of the resulting FinFET device. The epitaxial source / drain regions 70 in the n-region of the substrate 50 can be formed by masking the p-region of the substrate 50 and etching the source / drain regions of the fins 52 in the n-region of the substrate 50 to create recesses in the fins 52. The epitaxial source / drain regions 70 are then grown epitaxially in the recesses within the n-region of the substrate 50. The epitaxial source / drain regions 70 can be made of any acceptable material, such as that suitable for n-FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 70 in the n region of the substrate 50 can have materials that exert a tensile stress in the channel region 58, such as silicon, SiC, SiCP, SiP, a combination thereof or the like.The epitaxial source / drain regions 70 in the n-region of the substrate 50 may have surfaces that are raised from the respective surfaces of the fins 52 and may have facets. The epitaxial source / drain regions 70 in the p-region of the substrate 50 can be formed by masking the n-region of the substrate 50 and etching the source / drain regions of the fins 52 in the p-region of the substrate 50 to create recesses in the fins 52. The epitaxial source / drain regions 70 are then grown epitaxially in the recesses within the p-region of the substrate 50. The epitaxial source / drain regions 70 can be made of any suitable material, such as that used for p-FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 70 in the p-region of the substrate 50 can have materials that exert a compressive stress in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, a combination thereof or the like.The epitaxial source / drain regions 70 in the p-region of the substrate 50 may also have surfaces that are raised from the respective surfaces of the fins 52 and may have facets. The epitaxial source / drain regions 70 and / or the fins 52 can be implanted with dopants, similar to the previously described process for forming lightly doped source / drain regions, followed by annealing. The epitaxial source / drain regions 70 can have an impurity concentration of between approximately 10¹⁹ cm⁻³ and approximately 10²⁹ cm⁻³. The n and / or p impurities for the epitaxial source / drain regions 70 can be any of the impurities described previously. In some embodiments, the epitaxial source / drain regions 70 can be doped in place during growth. As a result of the epitaxial processes used to form the epitaxial source / drain regions 70 in the n-region and p-region of the substrate 50, the upper surfaces of the epitaxial source / drain regions exhibit facets that extend laterally beyond the sidewalls of the fins 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 70 of the same FinFET to merge, as illustrated by Fig. 10C. In other embodiments, adjacent epitaxial source / drain regions 70 remain separate after the epitaxial process is complete, as illustrated by Fig. 10D. In the embodiments illustrated in Fig. 10C and Fig. 10D, the gate spacers 68 are formed such that they cover a section of the side walls of the fins 52 that extend above the STI areas 56, thereby blocking epitaxial growth.In other embodiments, the spacer etching used to form the gate spacers 68 can be adapted to remove the spacer material from the side walls of the fins 52 to allow the epitaxially grown area to extend to the area of ​​the STI region 56. In Figures 11A and 11B, an interlayer dielectric (ILD) 74 is deposited over the structure illustrated in Figures 10A and 10B. The ILD 74 can be formed from a dielectric material and can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), FCVD, a combination thereof, or the like. Dielectric materials can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), a combination thereof, or the like. Other insulating materials formed by any acceptable process can also be used. In some embodiments, an etch stop layer (ESL, Etch Stop Layer) 72 is arranged between the ILD 74 and the epitaxial source / drain regions 70 and the gate spacers 68.The ESL 72 may contain a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, a combination thereof or the like, which has a different etch rate than the material of the overlying ILD 74. In Figures 12A and 12B, a planarization process, such as a CMP process, can be performed to bring the top surface of the ILD 74 to the same height as the top surface of the ESL 72. After performing the planarization process, a hard mask layer 76 is formed over the dummy gates 64, the ILD 74, and the ESL 72. In some embodiments, the hard mask layer 76 can comprise one or more layers of silicon oxide, SiN, SiON, a combination thereof, or the like, and can be formed using ALD, CVD, PECVD, a combination thereof, or the like. Figures 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, and 17B illustrate a fin-cutting process performed on the structure of Figures 12A and 12B, according to some embodiments. In Figures 13A and 13B, a structuring process is performed on the hard mask layer 76 to form a trench 78 in the hard mask layer 76 above the dummy gate 64A. The trench 78 exposes the dummy gate 64A. In some embodiments, the hard mask layer 76 is structured using suitable photolithography and etching processes. The etching processes can include one or more wet etching processes, one or more dry etching processes, combinations thereof, or the like. The etching processes can be anisotropic.In some embodiments, the etchants used to etch the hard mask layer 76 may comprise CHxFy (where x is between 1 and 3, where y is between 1 and 3, and where x+y equals 4), O2, Ar, He, a combination thereof, or the like. In some embodiments, the structuring process further removes a section of the dummy gate 64A and sections of the gate seal spacers 66. In such embodiments, the trench 78 extends below a lower surface of the hard mask layer 76. In some embodiments, the trench 78 has inclined side walls such that the width of the trench 78 decreases with its extension towards the dummy gate 64A. In some embodiments, the trench 78 has a width W1 at an upper surface of the hard mask layer 76 and a depth D1 measured from the upper surface of the hard mask layer 76.In some embodiments, the width W1 is between approximately 26 nm and approximately 30 nm. In some embodiments, the depth D1 is between approximately 35 nm and approximately 50 nm. In some embodiments, the ratio D1 / W1 is between approximately 1.17 and approximately 1.92. In Figures 14A and 14B, the dummy gate 64A, which is exposed by the trench 78 (see Figure 13B), has been removed, so that the trench 78 extends towards the substrate 50 and exposes the dummy dielectric layer 60. In some embodiments, the dummy gate 64A is removed by a suitable etching process. For example, the etching process may include a dry etching process using an etchant gas that selectively etches the dummy gate 64A material without etching the gate seal spacers 66 and the dummy dielectric layer 60. In some embodiments, the etchant gases may include CF4, Ar, HBr, O2, He, NF3, H2, a combination thereof, or the like. The dummy dielectric layer 60 can be used as an etch stop layer when the dummy gate 64A is etched.In some embodiments, the etching process for removing the dummy gate 64A can also etch the hard mask layer 76, thus reducing the thickness of the hard mask layer 76. In Figures 15A and 15B, the dummy dielectric layer 60 is removed after the dummy gate 64A has been removed (see Figures 13A and 13B). In some embodiments, the dummy dielectric layer 60 can be removed using one or more suitable etching processes that selectively etch the dummy dielectric layer 60 without etching the gate sealing spacers 66 and the fins 52. The suitable etching processes may be one or more dry etching processes, one or more wet etching processes, combinations thereof, or the like. In some embodiments, the etchants used to etch the dummy dielectric layer 60 may comprise CF4, Ar, He, a combination thereof, or the like. In some embodiments, the etching process for removing the dummy dielectric 60 can also etch the hard mask layer 76, thus further reducing the thickness of the hard mask layer 76. In Figures 16A and 16B, after removal of the dummy dielectric layer 60, exposed sections of the channel areas 58 of the fins 52 are removed, so that the groove 78 extends towards the substrate 50. In some embodiments, the exposed sections of the channel areas 58 of the fins 52 can be removed using one or more suitable etching processes that selectively etch the material of the fins 52 without etching the gate seal spacers 66 and the STI areas 56. In some embodiments, the exposed sections of the channel areas 58 of the fins 52 are removed by an anisotropic dry etching process. In some embodiments, the anisotropic dry etching process is carried out using etchant gases such as cyanide, oxygen, HBr, argon, helium, a combination thereof, or the like.In some embodiments, after the removal of the exposed sections of the channel areas 58 of the fins 52, the trench 78 has a depth D2 measured from an upper surface of the fins 52 and a depth D3 measured from an upper surface of the STI areas 56. In some embodiments, the depth D2 is between approximately 20 nm and approximately 30 nm. In some embodiments, the depth D3 is between approximately 15 nm and approximately 25 nm. In some embodiments, the etching process for removing the exposed sections of the channel areas 58 of the fins 52 can also etch the hard mask layer 76, thus further reducing the thickness of the hard mask layer 76. In Figures 17A and 17B, after the removal of the exposed sections of the channel areas 58 of the fins 52, exposed sections of the fins 52 and sections of the substrate 50 below the exposed sections of the fins 52 are removed, so that the trench 78 extends into the substrate 50. In some embodiments, the removal process may include one or more suitable etching processes that selectively etch the material of the fins 52 without etching the gate seal spacers 66 and the STI areas 56. In some embodiments, the suitable etching processes may include an anisotropic dry etching process. In some embodiments, the anisotropic dry etching process is carried out using etchant gases such as O2, HBr, Ar, He, a combination thereof, or the like.In some embodiments, after removal of the exposed sections of the fins 52 and the sections of the substrate 50 below the exposed sections of the fins 52, the trench 78 has a depth D4 measured from the upper surface 50t of the substrate 50, a depth D5 measured from the upper surface of the hard mask layer 76, and a width W2 at the upper surface of the hard mask layer 76. In some embodiments, the depth D4 is between approximately 30 nm and approximately 50 nm. In some embodiments, the depth D5 is between approximately 250 nm and approximately 300 nm. In some embodiments, the width W2 is between approximately 22 nm and approximately 26 nm. In some embodiments, the aspect ratio of the trench 78, defined as the ratio of the depth D5 to the width W2 (D5 / W2), is between approximately 9.62 and approximately 13.6.In some embodiments, the etching process for removing the exposed sections of the fins 52 and the sections of the substrate 50 below the exposed sections of the fins 52 can also etch the hard mask layer 76, thus further reducing the thickness of the hard mask layer 76. Furthermore, in Figures 17A and 17B, the groove 78 cuts each of the fins 52 into two separate sections. As described in more detail below, the groove 78 is filled with one or more dielectric materials to electrically insulate the separated sections of the fins 52. Accordingly, devices formed from the separated sections of the fins 52 are also electrically insulated. Figures 18A, 18B, 19A, 19B, 20A, 20B, 21A, and 21B illustrate a dielectric gap-filling process carried out on the trench 78 (see Figures 17A and 17B), according to some embodiments. In Figures 18A and 18B, a dielectric material 80 is deposited in the trench 78 (see Figure 17B) and over the hard mask layer 76. In some embodiments, the dielectric material 80 comprises an oxide material (such as silicon oxide or the like), a nitride material (such as silicon nitride or the like), an oxynitride material (such as silicon oxynitride or the like), a combination thereof or the like, and can be formed using ALD, CVD, PECVD, a combination thereof or the like.In some embodiments, due to a large aspect ratio of the trench 78, a joint 82 or a cavity (not shown) can be formed in the dielectric material 80 within the trench 78. In some embodiments, the joint 82 extends below the upper surface of the fins 52. In Figures 19A and 19B, a planarization process is performed on the dielectric material 80 in some embodiments. The planarization process may include a CMP process, a back-etching process, a combination thereof, or the like. In some embodiments, the planarization process exposes the dummy gates 64 such that, after the planarization process is complete, the top surface of the dielectric material 80, the top surfaces of the dummy gates 64, and the top surface of the ILD layer 74 are substantially at the same level (within process variations). In such embodiments, the planarization process removes the hard mask layer 76 and portions of the ESL 72 above the dummy gates 64. In some embodiments, the planarization process further removes portions of the dummy gates 64, the gate seal spacers 66, the gate spacers 68, and the ILD 74.In such embodiments, after the planarization process, the dummy gates 64 have upper surfaces located above the fins 52 at a height H2 measured from the upper surfaces of the fins 52. In some embodiments, the height H2 is less than the height H1 (see Fig. 8B). In some embodiments, the height H2 is between approximately 80 nm and approximately 90 nm. In Figures 20A and 20B, in some embodiments, the dielectric material 80 is recessed below the upper surfaces of the fins 52. In the illustrated embodiment, after the recession of the dielectric material 80, an upper surface of the dielectric material 80 lies below a lower surface of the adjacent epitaxial source / drain regions 70. In other embodiments, the upper surface of the dielectric material 80 may lie above the lower surface of the adjacent epitaxial source / drain regions 70. In some embodiments, the dielectric material 80 is recessed below the upper surface of the fin 52 to a depth D6. In some embodiments, the depth D6 is between approximately 150 nm and approximately 170 nm. In some embodiments, the dielectric material 80 is recessed below the upper surface of the STI regions 56 to a depth D7.In some embodiments, the depth D7 is between approximately 120 nm and approximately 150 nm. In some embodiments, the recession process comprises a suitable etching process that selectively etches the dielectric material 80 without substantially etching the gate sealing spacers 66, the dummy gates 64, the ESL 72, and the ILD 74. The suitable etching process may comprise a dry etching process, a wet etching process, a combination thereof, or the like. In some embodiments, the etching process for recessing the dielectric material 80 is carried out using etchants such as NF3, HF, NH3, a combination thereof, or the like. In some embodiments, leaving a portion of the dielectric material 80 in the trench 78 reduces the aspect ratio of the unfilled portion of the trench 78. The unfilled portion of the trench 78 has a width W3 at a top of the trench 78 and a depth D8 measured from the top surfaces of the dummy gates 64. In some embodiments, the depth D8 is between approximately 200 nm and approximately 250 nm. In some embodiments, the aspect ratio of the unfilled portion of the trench 78, defined as the ratio of the depth D8 to the width W3 (D8 / W3), is between approximately 9 and approximately 12. In some embodiments, the recession process of the dielectric material 80 can also recess the ILD 74, such that the top surface of the ILD 74 lies below the top surfaces of the dummy gates 64.In some embodiments, the ILD 74 is recessed to a depth D9 below the upper surfaces of the dummy gates 64. In some embodiments, the depth D9 is between approximately 15 nm and approximately 30 nm. In some embodiments, the recessing process also removes sections of the dummy gates 64, the gate seal spacers 66, the gate spacers 68, and the ESL 72. In such embodiments, after the recessing process, the dummy gates 64 have upper surfaces located above the fins 52 at a height H3 measured from the upper surfaces of the fins 52. In some embodiments, the height H3 is less than the height H2 (see Fig. 19B). In some embodiments, the height H3 is between approximately 70 nm and approximately 75 nm. In Figures 21A and 21B, a dielectric material 84 is deposited in the trench 78 (see Figure 20B) and above the ILD 74 and the dummy gates 64. In some embodiments, the dielectric material 84 comprises an oxide material (such as silicon oxide or the like), a nitride material (such as silicon nitride or the like), an oxynitride material (such as silicon oxynitride or the like), a combination thereof, or the like, and can be formed using ALD, CVD, a combination thereof, or the like. In some embodiments, the dielectric material 80 and the dielectric material 84 comprise different materials. In other embodiments, the dielectric material 80 and the dielectric material 84 comprise the same material. In some embodiments, by reducing the aspect ratio of the unfilled portion of the trench 78, as previously described with reference to Figures 20A and 21B, the dielectric material 84 can be reduced.As described in Fig. 20B, the formation of a gap or cavity within the trench 78 can be reduced. In some embodiments, by reducing the aspect ratio (D8 / W3) of the unfilled section of the trench 78 to between approximately 9 and approximately 12, a gap 86 can be formed in the dielectric material 84 within the trench 78 (see Fig. 20B) such that the gap 86 does not extend below the upper surfaces of the fins 52. In some embodiments, a lowest section of the gap 86 is located above the fins 52 at a height H4 measured from the upper surfaces of the fins 52. In some embodiments, the height H4 is between approximately 20 nm and approximately 35 nm. In some embodiments, a planarization process is performed on the dielectric material 84. The planarization process may include a CMP process, a back-etching process, a combination thereof, or the like. The planarization process exposes the dummy gates 64 such that the upper surfaces of the dummy gates 64 and the upper surface of the dielectric material 84 are substantially at the same level (within process variations) after the planarization process is complete. Sections of the dielectric material 80 and 84 arranged within the trench 78 (see Fig. 20B) may also be referred to as an insulating structure. In some embodiments, the planarization process also removes sections of the dummy gates 64, the gate seal spacers 66, the gate spacers 68, and the ESL 72.In such embodiments, after the planarization process, the dummy gates 64 have upper surfaces located above the fins 52 at a height H5 measured from the upper surfaces of the fins 52. In some embodiments, the height H5 is less than the height H3 (see Fig. 20B). In some embodiments, the height H5 is between approximately 50 nm and approximately 65 nm. In Figures 22A and 22B, the dummy gates 64 and the corresponding dummy dielectric layers 60 (see Figures 21A and 21B) are removed in one or more etching steps, forming openings 88. In some embodiments, the dummy gates 64 are removed by a suitable etching process. For example, the etching process may be a dry etching process using reactive gas(es) that selectively etches the dummy gates 64 without etching the ILD 74 or the gate spacers 68. The etching process may be anisotropic. Each opening 88 exposes channel regions 58 of respective fins 52. Each channel region 58 is located between adjacent pairs of epitaxial source / drain regions 70. During removal, the dummy dielectric layers 60 can be used as an etch stop layer when the dummy gates 64 are etched. Subsequently, the dummy dielectric layers 60 are removed by a suitable etching process. In some embodiments, the processes for removing the dummy gates 64 and the dummy dielectric layers 60 can also remove sections of the dielectric material 84, the gate seal spacers 66, the gate spacers 68, and the ESL 72. In such embodiments, the thickness of the dielectric material 84 above the ILD 74 is reduced so that an upper surface of the dielectric material 84 is located above the fins 52 at a height H6 measured from the upper surfaces of the fins 52. In some embodiments, the height H6 is less than the height H5 (see Fig. 21B). In some embodiments, the height H6 is between approximately 50 nm and approximately 60 nm. In Figures 23A and 23B, interface layers 90, gate dielectric layers 92, and gate electrodes 94 are formed in the openings 88 (see Figures 22A and 22B) to form replacement gate stacks 96. Figure 23C illustrates a detailed view of a region 98 from Figure 23B. In some embodiments, the interface layers 90 are formed in the openings 88 (see Figures 22A and 22B). The interface layers 90 may contain silicon oxide and may be formed using a chemical deposition process, such as ALD, CVD, PECVD, or the like, or using an oxidation process. In some embodiments, where the interface layers 90 are formed using a deposition process, the interface layers 90 extend along exposed surfaces of the fins 52, the STI areas 56 and the gate sealing spacers 66.In some embodiments, where the interface layers 90 are formed using an oxidation process, the interface layers 90 extend along exposed surfaces of the fins 52 and do not extend along exposed surfaces of the STI areas 56 and the gate sealing spacers 66. In some embodiments, the gate dielectric layers 92 are deposited over the interface layers 90 in the openings 88 (see Fig. 22A and Fig. 22B). In some embodiments, the gate dielectric layers 92 may comprise silicon oxide, silicon nitride, or multiple layers thereof, or the like. In some embodiments, the gate dielectric layers 92 may comprise a high-k dielectric material, and in these embodiments, the gate dielectric layers 92 may have a k-value greater than approximately 7.0 and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, or the like. The gate dielectric layers 92 may be formed using ALD, CVD, or the like. Furthermore, in Figs. 23A and 23B, the gate electrodes 94 are deposited over the gate dielectric layers 92 and fill the remaining portions of the openings 88 (see Figs. 22A and 22B). Although single-layer gate electrodes 94 are illustrated in Fig. 23B, each of the gate electrodes 94 can have any number of lining layers 94A, any number of output function matching layers 94B, and a conductive filler layer 94C, as illustrated by Fig. 23C. The lining layers 94A can comprise TiN, TiO, TaN, TaC, combinations thereof, multiple layers thereof, or the like, and can be formed using PVD, CVD, ALD, a combination thereof, or the like.In the n-region of substrate 50, the output work matching layers 94B can comprise Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, multiple layers thereof, or the like, and can be formed using PVD, CVD, ALD, a combination thereof, or the like. In the p-region of substrate 50, the output work matching layers 94B can comprise TiN, WN, TaN, Ru, Co, combinations thereof, multiple layers thereof, or the like, and can be formed using PVD, CVD, ALD, a combination thereof, or the like. In some embodiments, the conductive filler layer 94C may comprise Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, multiple layers thereof or the like, and may be formed using PVD, CVD, ALD, a combination thereof or the like. After filling the openings 88 (see Fig. 22A and Fig. 22B), a planarization process, such as a CMP process, can be performed to remove the excess sections of the gate dielectric layers 92, the gate electrodes 94, and / or the interface layers 90, the excess sections being located above the top surface of the dielectric material 84. The remaining sections of the gate electrodes 94, the gate dielectric layers 92, and the interface layers 90 thus form substitute gate stacks 96 of the resulting FinFETs. The gate stacks 96 can extend along sidewalls of the channel regions 58 of the fins 52. In some embodiments, the planarization process can also remove sections of the dielectric material 84, the gate seal spacers 66, the gate spacers 68, and the ESL 72.In such embodiments, after the planarization process, the gate stacks 96 have upper surfaces located above the fins 52 at a height H7 measured from the upper surfaces of the fins 52. In some embodiments, the height H7 is less than the height H6 (see Fig. 22B). In some embodiments, the height H7 is between approximately 40 nm and approximately 50 nm. The formation of the gate dielectric layers 92 in the n-region and the p-region of the substrate 50 can occur simultaneously, so that the gate dielectric layers 92 in each region are formed from the same materials. In other embodiments, the gate dielectric layers 92 in each region can be formed by different processes, so that the gate dielectric layers 92 in different regions can be formed from different materials. The formation of the conductive filler layers 94C in the n-region and the p-region of the substrate 50 can occur simultaneously, so that the conductive filler layers 94C in each region are formed from the same materials. In other embodiments, the conductive filler layers 94C in each region can be formed by different processes, so that the conductive filler layers 94C in different regions can be formed from different materials.Different masking steps can be used to mask and reveal suitable areas when different processes are used. In Figures 24A and 24B, the gate stacks 96 are recessed, forming recesses 100 directly above the gate stacks 96 and between opposing sections of the gate sealing spacers 66. In some embodiments, the recessing process includes a suitable etching process that selectively etches the materials of the gate stacks 96 without substantially etching the gate sealing spacers 66. The suitable etching process may include a dry etching process, a wet etching process, a combination thereof, or the like. In some embodiments, the etching process for recessing the gate stacks 96 is carried out using etchants such as CF4, CHF3, HBr, N2, H2, O2, a combination thereof, or the like.In other embodiments, the etching process for leaving out the gate stack 96 is carried out using etching agents such as deionized water (DI water) with dissolved ozone (DIO3), H2SO4, NH4OH, a combination thereof or the like. In some embodiments, after the recessing process, the gate stacks 96 have upper surfaces located above the fins 52 at a height H8 measured from the upper surfaces of the fins 52. In some embodiments, the height H8 is less than the height H4 (see Fig. 21B). In some embodiments, the height H8 is between approximately 10 nm and approximately 20 nm. In some embodiments, the recession process can also remove sections of the dielectric material 84, the gate seal spacer 66, the gate spacer 68, and the ESL 72. In such embodiments, the thickness of the dielectric material 84 above the ILD 74 is further reduced, so that an upper surface of the dielectric material 84 is located above the fins 52 at a height H9 measured from the upper surfaces of the fins 52. In some embodiments, the height H9 is less than the height H7 (see Fig. 23B). In some embodiments, the height H9 is between approximately 30 nm and approximately 40 nm. In Figures 25A and 25B, gate masks 102, comprising one or more layers of a dielectric material such as silicon nitride, silicon oxynitride, a combination thereof, or the like, are filled into the recesses 100 (see Figures 24A and 24B), followed by a planarization process to remove excess sections of the dielectric material extending over the ILD 74. The planarization process may include a CMP process, an etching process, a combination thereof, or the like. In some embodiments, gaps 104 may be formed in the gate masks 102 within the recesses 100 (see Figures 24A and 24B). In some embodiments, the planarization process may also remove sections of the ILD 74, the gate seal spacer 66, the gate spacer 68, and the ESL 72.In such embodiments, after the planarization process, the gate masks 102 have upper surfaces located above the fins 52 at a height H10 measured from the upper surfaces of the fins 52. In some embodiments, the height H10 is less than the height H9 (see Fig. 24B). In some embodiments, the height H10 is between approximately 25 nm and approximately 35 nm. In Figures 26A and 26B, the ILD 74 and the ESL 72 (see Figures 25A and 25B) are patterned to form openings 106 that expose the epitaxial source / drain regions 70. The patterning process exposes the epitaxial source / drain regions 70 and the gate spacers 68. In some embodiments, the patterning process includes one or more suitable etching processes that selectively etch the materials of the ILD 74 and the ESL 72. The suitable etching processes may include a dry etching process, a wet etching process, a combination thereof, or the like. In some embodiments, the structuring process comprises a first etching process to structure the ILD 74 followed by a second etching process to structure the ESL 72. In some embodiments, the first etching process is carried out using etchants such as C4F6, C4F8, O2, CO, a combination thereof, or the like.In some embodiments, the second etching process is carried out using etchants such as HF, NH3, NF3, a combination thereof or the like. In Figures 27A and 27B, silicide layers 108 are formed over the epitaxial source / drain regions 70 through the openings 106. In some embodiments, a metal material is deposited over the epitaxial source / drain regions 70. The metal material may comprise Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, a combination thereof, or the like, and may be formed using PVD, ALD, CVD, a combination thereof, or the like. Subsequently, an annealing process is carried out to form the silicide layers 108. In some embodiments where the epitaxial source / drain regions 70 contain silicon, the annealing process causes the metal material to react with silicon to form a silicide of the metal material at interfaces between the metal material and the epitaxial source / drain regions 70.After the formation of the silicide layers 108, sections of the metal material that have not reacted are removed using a suitable removal process, such as a suitable etching process. In Figures 28A and 28B, source / drain contacts 114 are formed in the openings 106 (see Figures 27A and 27B). In some embodiments, the source / drain contacts 114 are formed by forming a lining 110 and a conductive material 112 in the openings 106. The lining 110 can be a diffusion barrier layer, an adhesion layer, or the like. The lining 110 can comprise titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or the like, and can be formed using PVD, sputtering, plating, a combination thereof, or the like. The conductive material 112 can include copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, a combination thereof or the like, and can be formed using PVD, CVD, sputtering, plating, a combination thereof or the like.In some embodiments, sections of the lining 110 and the conductive material 112 can penetrate the joint 86 (see Fig. 27B). However, since the joint 86 does not extend below the upper surfaces of the fins 52, the amount of material penetrated is reduced. In some embodiments, a planarization process, such as a CMP process, can be performed to remove excess sections of the lining 110 and the conductive material 112, exposing the upper surfaces of the gate masks 102. The remaining sections of the lining 110 and the conductive material 112 form the source / drain contacts 114. The source / drain contacts 114 are electrically coupled to the respective epitaxial source / drain regions 70 by the silicide layers 108. In some embodiments, the upper surfaces of the gate masks 102 and the upper surfaces of the source / drain contacts 114 are substantially at the same level or are coplanar (within process variations) after the planarization process is complete. In some embodiments, the planarization process also removes sections of the gate masks 102, the gate sealing spacers 66, the gate spacers 68, and the dielectric material 84, so that the joint 86 (see Fig. 27B) in the dielectric material 84 is completely removed. In some embodiments, removing the joint 86 (see Fig. 27B) also removes sections of the conductive material that may have penetrated the joint 86 during the formation of the source / drain contacts 114. Accordingly, short-circuiting of the source / drain contacts 114, which are arranged on opposite sides of the dielectric material 84, is avoided. In some embodiments, after the planarization process, the gate masks 102 have upper surfaces located above the fins 52 at a height H11 measured from the upper surfaces of the fins 52.In some embodiments, the height H11 is less than the height H10 (see Fig. 25B). In some embodiments, the height H11 is equal to or less than the height H4 (see Fig. 21B). In some embodiments, the height H11 is between approximately 20 nm and approximately 30 nm. In Figures 29A and 29B, an ILD 116 is deposited over the gate stack 96 and the source / drain contacts 114 after the planarization process. In some embodiments, the ILD 116 can be formed using similar materials and methods to the ILD 74 previously described with reference to Figures 11A and 11B, and this description is not repeated here. In some embodiments, the ILD 74 and the ILD 116 are made of the same material. In other embodiments, the ILD 74 and the ILD 116 are made of different materials. After forming the ILD 116, openings for the gate contacts 118 are created through the ILD 116 and the gate masks 102. The openings can be formed using acceptable photolithography and etching techniques. Subsequently, the gate contacts 118 are formed in the openings. In some embodiments, the gate contacts 118 are formed using similar materials and a similar process as the source / drain contacts 114 previously described with reference to Figures 28A and 28B, and the description is not repeated here. Various embodiments can offer advantages. Several embodiments, described herein, enable the improvement of the gap-filling performance of the dielectric material for a trench formed during a fin-cutting process, thereby reducing or avoiding problems due to gap and / or void formation in the dielectric material within the trench, reducing or avoiding short circuits between contact plugs, and improving device and yield performance. In some embodiments, the trench formed during the fin-cutting process is filled with a variety of dielectric materials.In some embodiments, the trench-filling process may include filling the trench with a first dielectric material, partially removing the first dielectric material from the trench so that an upper section of the trench is not filled with dielectric material, and filling the upper section of the trench with a second dielectric material. The second dielectric material may be the same as or different from the first dielectric material. According to one embodiment, a device comprises a substrate, a first insulating structure and a second insulating structure above the substrate, a semiconductor fin above the substrate and between the first and second insulating structures, and a third insulating structure extending through the semiconductor fin and between the first and second insulating structures. An upper surface of the semiconductor fin lies above an upper surface of the first insulating structure and an upper surface of the second insulating structure. The third insulating structure comprises a first dielectric material and a second dielectric material above the first dielectric material. An interface between the first dielectric material and the second dielectric material lies below the upper surface of the first insulating structure and the upper surface of the second insulating structure.In one embodiment, the first dielectric material extends below a lower surface of the first insulating structure and a lower surface of the second insulating structure. In another embodiment, the second dielectric material extends along the upper surface and side walls of the first insulating structure and is in physical contact with them. In another embodiment, an upper surface of the third insulating structure lies above the upper surface of the first insulating structure and the upper surface of the second insulating structure. In yet another embodiment, an upper surface of the third insulating structure lies above the upper surface of the semiconductor fin. In yet another embodiment, the device further comprises a gate stack above the semiconductor fin and adjacent to the third insulating structure, with an upper surface of the gate stack lying below an upper surface of the third insulating structure.In one embodiment, the first dielectric material differs from the second dielectric material. According to another embodiment, a device comprises a substrate, a semiconductor fin extending from an upper surface of the substrate, a gate stack extending along an upper surface and from side walls of the semiconductor fin, a source / drain region extending into the semiconductor fin adjacent to the gate stack, and an insulating structure extending into the semiconductor fin adjacent to the source / drain region. The source / drain region is inserted between the insulating structure and the gate stack. The insulating structure includes a first dielectric material and a second dielectric material above the first dielectric material. An interface between the first dielectric material and the second dielectric material is located below the upper surface of the semiconductor fin. In one embodiment, the first dielectric material differs from the second dielectric material.In one embodiment, the first dielectric material extends into the substrate. In another embodiment, the interface between the first dielectric material and the second dielectric material is located above the upper surface of the substrate. In yet another embodiment, an upper surface of the second dielectric material is located above an upper surface of the gate stack. In yet another embodiment, the interface between the first dielectric material and the second dielectric material is located below a lower surface of the source / drain region. In yet another embodiment, the device further comprises a spacer structure extending along a side wall of the insulation structure, the spacer structure being in physical contact with the second dielectric material. According to yet another embodiment, a method comprises forming a semiconductor fin over a substrate. A dummy gate structure is formed over the semiconductor fin. Spacers are formed on opposite side walls of the dummy gate structure. The dummy gate structure is removed to form a trench between the spacers. The trench exposes the semiconductor fin. An etching process is performed on the semiconductor fin to extend the trench into the semiconductor fin. The trench is filled with a first dielectric material. The first dielectric material is back-etched. A second dielectric material is deposited in the trench and over the first dielectric material. In one embodiment, the etching process extends the trench further into the substrate.In one embodiment, an upper surface of the first dielectric material lies below an upper surface of the semiconductor fin after etching back the first dielectric material. In another embodiment, the first dielectric material differs from the second dielectric material. In another embodiment, the second dielectric material has a gap within the groove. In yet another embodiment, the gap is removed.

Claims

Device comprising: a substrate (50); a first insulating structure (56) and a second insulating structure (56) above the substrate (50); a semiconductor fin (52) above the substrate (50) and between the first insulating structure (56) and the second insulating structure (56), wherein an upper surface of the semiconductor fin (52) lies above an upper surface of the first insulating structure (56) and an upper surface of the second insulating structure (56); a third insulating structure extending through the semiconductor fin (52) and between the first insulating structure (56) and the second insulating structure (56), wherein the third insulating structure comprises: a first dielectric material (80);and a second dielectric material (84) above the first dielectric material (80), wherein an interface between the first dielectric material (80) and the second dielectric material (84) lies below the top surface of the first insulating structure (56) and the top surface of the second insulating structure (56); a gate stack (96) above the semiconductor fin (52) and adjacent to the third insulating structure, wherein an top surface of the gate stack (96) lies below an top surface of the third insulating structure; and a gate mask (102) directly above the gate stack (96) and between gate spacers (66, 68), wherein a height of an top surface of the gate mask (102) above the semiconductor fin (52) and measured from an top surface of the semiconductor fin (52) is between about 20 nm and about 30 nm. Device according to claim 1, wherein the first dielectric material (80) extends below a lower surface of the first insulation structure (56) and a lower surface of the second insulation structure (56). Device according to claim 1 or 2, wherein the second dielectric material (84) extends along the upper surface and side walls of the first insulation structure (56) and is in physical contact with them. Device according to one of the preceding claims, wherein an upper surface of the third insulation structure is located above the upper surface of the first insulation structure (56) and the upper surface of the second insulation structure (56). Device according to one of the preceding claims, wherein an upper surface of the third insulation structure is located above the upper surface of the semiconductor fin (52). Device according to one of the preceding claims, wherein the first dielectric material (80) differs from the second dielectric material (84). Device comprising: a substrate (50); a semiconductor fin (52) extending from an upper surface of the substrate (50); a gate stack (96) extending along an upper surface and from side walls of the semiconductor fin (50); a source / drain region (70) extending into the semiconductor fin (52) adjacent to the gate stack (96); an insulating structure extending into the semiconductor fin (52) adjacent to the source / drain region (70), wherein the source / drain region (70) is inserted between the insulating structure and the gate stack (96), the insulating structure comprising: a first dielectric material (80); and a second dielectric material (84) above the first dielectric material (80), wherein an interface between the first dielectric material (80) and the second dielectric material (84) lies below the upper surface of the semiconductor fin (52);a gate mask (102) directly above the gate stack (96) and between gate spacers (66, 68), wherein the height of an upper surface of the gate mask (102) above the semiconductor fin (52) and measured from the upper surface of the semiconductor fin (52) is between about 20 nm and about 30 nm. Device according to claim 7, wherein the first dielectric material (80) differs from the second dielectric material (84). Device according to claim 7 or 8, wherein the first dielectric material (80) extends into the substrate (50). Device according to any one of the preceding claims 7 to 9, wherein the interface between the first dielectric material (80) and the second dielectric material (84) is located above the upper surface of the substrate (50). Device according to any one of the preceding claims 7 to 10, wherein an upper surface of the second dielectric material (84) is located above an upper surface of the gate stack (96). Device according to any one of the preceding claims 7 to 11, wherein the interface between the first dielectric material (80) and the second dielectric material (84) is located below a lower surface of the source / drain region (70). Device according to any one of the preceding claims 7 to 12, further comprising a spacer structure extending along a side wall of the insulation structure, wherein the spacer structure is in physical contact with the second dielectric material (84). The method comprises: forming a semiconductor fin (52) over a substrate (50); forming a dummy gate structure (64) over the semiconductor fin (52); forming spacers (66, 68) on opposite side walls of the dummy gate structure (64); removing the dummy gate structure (64) so ​​that a trench (78) is formed between the spacers (66, 68), the trench (78) exposing the semiconductor fin (52); performing an etching process on the semiconductor fin (52) so that the trench (78) is extended into the semiconductor fin (52); filling the trench (78) with a first dielectric material (80); and etching back the first dielectric material (80). and depositing a second dielectric material (84) in the trench (78) and above the first dielectric material (80), wherein the second dielectric material (84) has a joint (86) within the trench (78);Forming a gate stack (96) extending along a top surface and side walls of the semiconductor fin (52), between gate spacers (66, 68) and adjacent to the first (80) and second dielectric material (84); forming a gate mask (102) directly above the gate stack (96) and between the gate spacers (66, 68); and removing the joint (86) by a planarization process that removes a section of the gate mask (102), a section of the gate spacers (66, 68), and a section of the second dielectric material (84). Method according to claim 14, wherein the etching process further extends the trench (78) into the substrate (50). Method according to claim 14 or 15, wherein an upper surface of the first dielectric material (80) lies below an upper surface of the semiconductor fin (52) after etching back the first dielectric material (80). Method according to any one of the preceding claims 14 to 16, wherein the first dielectric material (80) differs from the second dielectric material (84).

Images