HETEROGENIC BOND STRUCTURE AND METHOD FOR ITS PREPARATION

Abstract

Method comprising the following steps: Manufacturing a first package component comprising the following steps: Creating (204) a first plurality of openings (44, 46) in a first dielectric layer (42), Depositing (206) a first metallic material into the first plurality of openings (44, 46), Performing (208) a planarization process on the first metallic material and the first dielectric layer (42) to produce a first plurality of metal pads (54') in the first dielectric layer (42), and selectively depositing (210) a second metallic material onto the first plurality of metal pads (54') to produce a first plurality of bond pads (54), wherein the first plurality of bond pads (54) comprises the first plurality of metal pads (54') and corresponding portions of the second metallic material;and bonding (212) of the first package component to a second package component, wherein the first plurality of bond pads (54) is bonded to the second package component, the selective deposition (210) of the second metallic material comprising: depositing a first sublayer (58A) comprising a first metal; and depositing a second sublayer (58B) over the first sublayer (58A), wherein the second sublayer (58B) comprises a second metal that is different from the first metal.;

Description

Priority claim and cross-reference

[0001] The present application claims priority over the provisional US patent application filed on January 28, 2021, with file number 63 / 142,543 and entitled “New Heterogeneous Bonding Structure for SoIC Application”, which is incorporated by reference into the present application. background

[0002] In wafer-to-wafer bonding technology, various methods have been developed to bond two package components (such as wafers) together. Available bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, and the like. In hybrid bonding, metal pads from two wafers are bonded together using direct metal-to-metal bonding, where an oxide surface of one of the two wafers is bonded to an oxide or silicon surface of the other wafer.

[0003] Wafer-wafer bonding places high demands on the coplanarity of the wafer bonding surfaces. For example, the bonding surfaces of the metal pads must be coplanar with the bonding surfaces of dielectric layers to achieve metal-to-metal direct bonding and fusion bonding. However, coplanarity is difficult to achieve. For instance, the top surfaces of the wafers are typically planarized using CMP processes (chemical-mechanical polishing), which, however, are prone to dishing problems (dishing: depressions). List of characters

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1 to Fig. Figure 13 shows sectional views of intermediate stages in the manufacture of a package component by wafer-wafer bonding according to some exemplary embodiments. Fig. Figure 14 is a sectional view of a package component manufactured by die-wafer bonding, according to some exemplary embodiments. The Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17, Fig. 18A and Fig. Figure 18B shows enlarged views of bond pads during bonding processes according to some exemplary embodiments. Fig. Figure 19 shows a process flow for manufacturing a package according to some embodiments. Detailed description

[0005] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] A package and various methods for its fabrication are provided. According to some embodiments of the present invention, a package component is fabricated comprising a dielectric surface layer and metal pads within the dielectric surface layer. A planarization process is performed to level the top surfaces of the dielectric surface layer and the metal pads. A conductive filler layer is selectively deposited on the metal pads to fill any voids in the metal pads, thus ensuring improved bonding when the package component is subsequently bonded to another package component.The embodiments discussed herein are intended to provide examples of manufacturing or using the subject matter of the present invention, and a person skilled in the art should readily recognize modifications that can be made without deviating from the intended scope of protection of other embodiments. In all illustrations and explanatory embodiments, similar reference numerals are used to designate similar elements. While some method embodiments may be discussed as being carried out in a particular sequence, other method embodiments may be carried out in any logical sequence.

[0008] The Fig. 1 to Fig. Figure 13 shows sectional views of intermediate stages in the fabrication of a package component by wafer-wafer bonding according to some embodiments. The respective steps are also schematically indicated in the process flow 200, which is presented in Fig. 19 is shown.

[0009] Fig. Figure 1 shows a sectional view during the production of a package component 2. The corresponding step is indicated as step 202 in process flow 200, which is described in Fig. Figure 19 shows that, according to some embodiments of the present invention, the package component 2 is a device wafer with active devices 22, such as transistors and / or diodes, and optionally passive devices, such as capacitors, inductors, resistors, or the like. The package component 2 can have a plurality of chips 4, only one of which is shown. The chips 4 are referred to below alternatively as dies or device dies. In some embodiments of the present invention, a device die 4 is a logic die, which can be a CPU die (CPU: main processor), an MCU die (MCU: microcontroller unit), an input / output die (I / O die), a baseband die (BB die), an application processor die (AP die), or the like. The device die 4 can also be a memory die, such as a DRAM die (DRAM: dynamic random access memory) or an SRAM die (SRAM: static random access memory).

[0010] In alternative embodiments of the present invention, the package component 2 is an interposer wafer that does not have any active devices but may or may not have passive devices. While a device wafer is discussed below as the exemplary package component 2, the embodiments of the present invention can also be used for other types of package components, such as interposer wafers. Furthermore, the package component 2 can be a newly configured wafer that includes discrete device dies encapsulated in an encapsulation material, such as a molding compound.

[0011] According to some embodiments of the present invention, the wafer 2 comprises a semiconductor substrate 20. The semiconductor substrate 20 can be made of crystalline silicon, crystalline germanium, crystalline silicon germanium, and / or a III-V compound semiconductor, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and the like. The semiconductor substrate 20 can also be a solid silicon substrate or a silicon-on-insulator (SOI) substrate. STI regions (not shown; STI: shallow trench insulation) can be fabricated in the semiconductor substrate 20 for isolating the active regions. Although not shown, vias can be fabricated to extend into the semiconductor substrate 20, the vias serving to electrically connect structural elements on opposite sides of the wafer 2.

[0012] According to some embodiments of the present invention, the wafer 2 has integrated circuit devices 22 that are fabricated on the top surface of the semiconductor substrate 20. Exemplary integrated circuit devices 22 are CMOS transistors (CMOS: complementary metal oxide semiconductor), resistors, capacitors, diodes, and / or the like. Details of the integrated circuit devices 22 are not shown here. In alternative embodiments, the wafer 2 is used to fabricate interposers, in which the substrate 20 can be a semiconductor substrate or a dielectric substrate.

[0013] An interlayer dielectric (ILD) 24 is produced over the semiconductor substrate 20, filling a space between gate stacks of transistors (not shown) in the integrated circuit devices 22. According to some embodiments, the ILD 24 is made of phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), silicon dioxide, or the like. The ILD 24 can be produced by spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like.

[0014] In the ILD 24, contact pins 28 are manufactured, which are used for electrically connecting the integrated circuit devices 22 to conductive structural elements located above them. In some embodiments of the present invention, the contact pins 28 are made of a conductive material from the group consisting of tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers. The contact pins 28 can be manufactured as follows: creating contact openings in the ILD 24; filling the contact openings with one or more conductive materials; and performing a planarization process (such as a CMP process) to bring the top surfaces of the contact pins 28 to the same level as the top surface of the ILD 24.

[0015] An interconnect structure 30 is fabricated above the ILD 24 and the contact pins 28. The interconnect structure 30 comprises dielectric layers 32, as well as metal conductors 34 and vias 36 fabricated within the dielectric layers 32. The dielectric layers 32 are alternatively referred to below as intermetal dielectric (IMD) layers 32. In some embodiments of the present invention, at least the lower dielectric layers 32 are fabricated from a low-k dielectric material having a dielectric constant (k-value) lower than approximately 3.0 or approximately 2.5. The dielectric layers 32 can be fabricated from Black Diamond® (registered trademark of Applied Materials), a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like.In alternative embodiments of the present invention, all or some of the dielectric layers 32 are made of non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or the like. In some embodiments of the present invention, the production of the dielectric layers 32 comprises depositing a porous dielectric material and subsequently performing a curing process to drive out the porous material, leaving the remaining dielectric layers 32 porous. Etch-stop layers (not shown), for example made of silicon carbide, silicon nitride, or the like, are produced between the IMD layers 32; these are not shown for simplicity.

[0016] The metal conductors 34 and the vias 36 are fabricated in the dielectric layers 32. The metal conductors 34 on the same layer are hereinafter collectively referred to as a metal layer. In some embodiments of the present invention, the interconnect structure 30 has a plurality of metal layers connected to one another by the vias 36. The metal conductors 34 and the vias 36 can be made of copper, aluminum, silver, or alloys thereof, but they can also be made of other metals. Single- and dual-damascene processes can be used for fabrication. In a single-damascene process, a trench is first created in the corresponding dielectric layers 32, which is then filled with a conductive material.A planarization process, such as a CMP process, is then performed to remove excess conductive material that extends above the top of the IMD layer, leaving a metal conductor in the trench. In a dual-damascene process, a trench and a via hole are created within an IMD layer, with the via hole positioned below and connected to the trench. Conductive material is then filled into the trench and via hole to create a metal conductor and a via, respectively. The conductive material may include a diffusion barrier and a copper-containing metallic material above the diffusion barrier. The diffusion barrier may consist of titanium, titanium nitride, tantalum, tantalum nitride, or similar materials.

[0017] The metal conductors 34 are metal conductors in an upper metal layer. The respective dielectric layer 32 (designated 32A) in which the upper metal layer is located can be made of a non-low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or the like. The dielectric layer 32A can also be made of a low-k dielectric material, which can be selected from similar materials to those used for the underlying IMD layers 32.

[0018] In some embodiments of the present invention, dielectric layers 38, 40, and 42 are produced above the upper metal layer. The dielectric layers 38 and 42 can be made of silicon oxide, silicon nitride, silicon carbide, or the like. The dielectric layer 40 is made of a different material than the dielectric layer 42. For example, the dielectric layer 42 can be made of a silicon-containing dielectric material such as silicon oxide, silicon nitride, silicon carbide, or the like.

[0019] In Fig. 2. Through-holes 44 and grooves 46 are created. The corresponding step is specified as step 204 in process flow 200, which is described in Fig. Figure 19 shows that photoresists (not shown) and / or hard masks (not shown) can be fabricated and structured over the dielectric layer 42 to create the via holes 44 and the trenches 46. In some embodiments of the present invention, an anisotropic etching process is performed to create the trenches 46, with the etching ending on the etch stop layer 40. Then, a further anisotropic etch is performed to create the via holes 44 by etching the exposed etch stop layer 40 and the deeper portions of the dielectric layer 38. In some embodiments of the present invention, the etch stop layer 40 is not fabricated, and the via holes 44 and the trenches 46 are created in a single dielectric layer.The etching can be carried out by time control so that the etching (to create the trenches 46) can be terminated at an intermediate level between a top and a bottom of the single dielectric layer.

[0020] Fig. Figure 3 shows the filling of conductive materials. The corresponding step is indicated as step 206 in process flow 200, which is described in Fig. Figure 19 shows that a conductive diffusion barrier 48 is first fabricated. In some embodiments of the present invention, the diffusion barrier 48 is made of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The diffusion barrier 48 can be fabricated, for example, by atomic layer deposition (ALD), physical vapor deposition (PVD), or the like. The diffusion barrier 48 has first parts above the dielectric surface layer 42 and second parts on the undersides and side walls of the grooves 46 and the via opening 42.

[0021] A metallic material 50 is then deposited, for example, by electrochemical plating (ECP). The metallic material 50 fills the remaining portions of the grooves 46 and the via openings 44. The metallic material 50 also has some portions above the top surface of the dielectric surface layer 42. The metallic material 50 can comprise copper or a copper alloy, tungsten, aluminum, silver, alloys thereof, or other metallic materials that can diffuse in a subsequent tempering process, thus creating a metal-to-metal direct bond.

[0022] As in Fig. As shown in Figure 4, a planarization process, such as a CMP process, is then carried out to remove excess parts of the metallic material 50 and the diffusion barrier 48 until the dielectric layer 42 is exposed. The corresponding step is indicated as step 208 in the process flow 200, which is shown in Figure 4. Fig. Figure 19 shows the remaining parts of the diffusion barrier 48 and the metallic material 50. These are vias 52 and metal pads 54'. Throughout this description, the metal pads 54' are also referred to as bond pads 54'.

[0023] The planarization process is intended to produce a planar top surface, with the top surfaces of the bond pads 54' and the top surface of the dielectric layer 42 being coplanar. However, various process factors, such as a structure-charging effect and a difference between the etching rates and the mechanical polishing rates for the bond pads 54' and the dielectric layer 42, as well as their different reactions to the slurry, can result in non-planar surfaces. Fig. Figure 4 shows a dishing effect that occurs during the CMP process, resulting in pits 55 that extend into the metal pads 54'. Additionally, micro-pits (roughness) can form on the top surfaces of the bond pads 54'. The roughness of the top surfaces of the bond pads 54' can be greater than approximately 1 µm, which is greater than the maximum permissible roughness for wafer-wafer bonding. Accordingly, in some embodiments, to reduce the problems of non-coplanarity and roughness, an additional layer is deposited on the surfaces of the bond pads 54', as shown in the Fig. 15A, Fig. 15B, Fig. 16A and Fig. 16B is shown.

[0024] Fig. Figure 15A shows an enlarged sectional view of parts of the bond pads 54' and the corresponding dielectric layer 42 according to some embodiments of the present invention. The bond pads 54' (and the underlying vias 52, which are shown in Fig. Figure 4 shows the diffusion barrier 48 and the metallic material 50 enclosed by the diffusion barrier 48. The metallic material 50 can have edge portions and a middle portion between the edge portions, the middle portion having a top surface that is lower than the top surfaces of the edge portions, thus creating the recesses 55. The recesses 55 can have a depth D1 of more than about 0.1 µm, and the depth D1 can range from about 0.1 µm to about 3 µm. Fig. 15B shows a similar structure, except that instead of the one in Fig. The dishing micro-recesses 55 shown in Figure 15A are formed. It should be noted that the dishing and the micro-recesses 55 can occur simultaneously and on the same structure, with the recessed surface also exhibiting micro-recesses.

[0025] In Fig. 16A Conductive filler layers 58 are selectively deposited on the bond pads 54'. The conductive filler layers 58 can be made of one or more metals and are alternatively referred to as filler metal layers 58. Throughout this description, the bond / metal pads 54' and the respective filler metal layers 58 located above them are collectively referred to as bond pads 54. The respective wafer 2 is in Fig. 5 shown, with details of the bond pads 54 in Fig. 16A. In some embodiments, the filler metal layers 58 are deposited using a selective deposition process such as plating, which may be ECP, electroless plating, or the like. Accordingly, the filler metal layers 58 are selectively deposited on the metallic materials, such as the bond pads 54', but not on the dielectric materials, such as the dielectric layer 42. In some embodiments, the current density used for the plating process may be approximately 0.1 A / dm². 2 up to approximately 5.0 A / dm³ 2 be.

[0026] The amount of filler metal layers 58 deposited on each of the bond pads 54 is controlled such that the filler metal layers 58 fill the recesses 55 ( Fig. 15A) with as little excess as possible. The highest point TMP of the filler metal layers 58 can be higher than the top of the dielectric surface layer 42. To keep the volume of the filler metal layers 58 within the volume of the corresponding recesses 55, the lowest point LMP of the top of the filler metal layers 58 can be lower than the top 42T of the dielectric surface layer 42. In other words, the recesses 55 can have small portions that are not filled with the filler metal layers 58, and the excess portions of the filler metal layers 58 that are higher than the top 42T can compensate for the unfilled portions. The corresponding volume of the filler metal layers 58 can be determined by ascertaining the dimensions of the recesses 55 and the dimensions of the bond pads 54.

[0027] The filler metal layers 58 can be made of, or comprise, materials selected from the group consisting of Cu, Sn, In, Ag, SnAg, or the like, alloys thereof, and / or composite layers thereof. In some embodiments, the materials for the filler metal layers 58 are selected to match the material for the bond pads 54, such that the coefficient of thermal expansion (CTE) CTE58 of the filler metal layers 58 is close to the CTE CTE54' of the bond pads 54'. For example, the ratio |(CTE58 - CTE54')| / CTE58 can be less than about 0.2 and less than about 0.1, where the value |(CTE58 - CTE54')| is the absolute value of (CTE58 - CTE54'). Furthermore, the CTE difference |(CTE58 - CTE54')| at 20 °C can be less than about 10 x 10⁻⁵ / K. When the CTEs CTE58 and CTE54' are close together, the resulting bond structure is less susceptible to problems caused by a CTE discrepancy, such as cracking, layer delamination, or the like.

[0028] In some embodiments of the present invention, the melting point of the filler metal layers 58 is lower than the melting point of the bond pads 54'. For example, if the metal pads 54' are made of or contain copper, the filler metal layers 58 may be made of or contain Sn, In, Ag, or the like, or alloys thereof. In some embodiments, the melting point difference (MP54' - MP58) is greater than about 100 °C, greater than about 200 °C, or greater than about 500 °C, wherein the melting points MP54' and MP58 are the melting points of the bond pads 54' and the filler metal layers 58, respectively. The melting point difference (MP54' - MP58) may also range from about 100 °C to about 800 °C.

[0029] In some embodiments, the filler metal layers 58 are made of a homogeneous material. In alternative embodiments, each of the filler metal layers 58 can be a composite layer with two or more sublayers, wherein the sublayers are made of different materials. As in Fig. As shown in Figure 16A, for example, each filler layer 58 can comprise a sublayer 58A and a sublayer 58B made of different materials. In some embodiments of the present invention, the sublayer 58A is a diffusion barrier layer that can be made of or comprise Ti, Ta, TiN, TaN, Ni, or the like. The sublayer 58B can be made of Cu, Sn, In, Ag, SnAg, or the like, or alloys thereof. In alternative embodiments, the sublayers 58A and 58B are made of different materials, and they can diffuse into each other in a subsequent bonding process by solid-liquid diffusion. For example, the sublayer 58A can be made of In or Cu, while the sublayer 58B can be made of Cu (if the sublayer 58A is made of In) or of In (if the sublayer 58A is made of Cu).

[0030] Fig. Figure 16B shows the filler metal layer 58, which in some embodiments completely or partially fills the recesses 55, wherein the recesses are micro-recesses rather than dishing. The in Fig. Although the sublayers 58A and 58B shown in Figure 16B are not shown individually, they can also be produced.

[0031] In Fig. 5 are the bond pads 54 shown, which are the bond pads 54' (not shown; see Fig. 16A) and the corresponding filler metal layers 58 located above it.

[0032] Fig. Figure 6 shows the fabrication of a wafer 100 in which device dies 112 are fabricated. In some embodiments of the present invention, the device dies 112 are logic dies, such as CPU dies, MCU dies, I / O dies, baseband dies, AP dies, or the like. The device dies 112 can also be memory dies. The wafer 100 has a semiconductor substrate 114, which can be a silicon substrate. Silicon vias (TSVs) 116, sometimes also referred to as semiconductor vias or vias, are fabricated to extend into the semiconductor substrate 114. The TSVs 116 are used to connect the devices and metal traces fabricated on a front side (the bottom side shown) of the semiconductor substrate 114 to a back side, as shown in later figures.Furthermore, the device dies 112 feature interconnect structures 130 for connecting to the active and (optionally) passive devices in the device dies 112. The interconnect structures 130 include metal traces and vias (not shown).

[0033] The wafer 100 can have dielectric layers 138 and 142 and an etch stop layer 140 between the dielectric layers 138 and 142. Bond pads 154 are produced in the layers 138, 140, and 142. The corresponding step is specified as step 210 in the process flow 200, which is described in Fig. Figure 19 shows that the materials and manufacturing processes for the dielectric layers 138 and 142, the etch stop layer 140, the bond pads 154 and the vias 152 may be similar to their corresponding parts in the device die 4, and therefore the details are not repeated here.

[0034] Fig. Figure 17 shows an enlarged view of the bond pads 154 according to some embodiments. The bond pads 154 have a diffusion barrier 148 and a metallic material 150. The structures, materials, and manufacturing processes for the bond pads 154 and the vias 152 can be similar to those for the bond pads 54 and the vias 52 described in Fig. Figure 16A shows the bond pads 154 having metal pads 154' and filler metal layers 158 on the metal pads 154'. The manufacturing processes and corresponding materials for the filler metal layers 158 may be similar to those for the filler metal layers 58, and they are not repeated. In alternative embodiments, the bond pads 154 have metal pads 154', but no filler metal layers 158. In alternative embodiments, the filler metal layers 158 are produced on the metal pads 154', while no filler metal layers are deposited on the metal pads 54'.

[0035] In the Fig. 6 and Fig. In step 17, wafer 100 is pressed against wafer 2, aligning the bond pads 154 with the corresponding bond pads 54. Wafer 100 is pressed against wafer 2, which in Fig. 17 is represented by an arrow 60. Wafers 2 and 100 are heated, which in Fig. Figure 17 is represented by curved lines 62. In some embodiments, the pressure is less than approximately 1000 kp / cm². 2 This pressure is lower than that used in conventional wafer-to-wafer bonding processes. The reduction in pressure is achieved by using filler metal layers 58 and 158 with lower melting points. Furthermore, the wafer temperature in this process can range from approximately 100 °C to approximately 200 °C. The bonding time can be approximately 1 to 2 hours.

[0036] As in Fig. As shown in Figure 7, wafer 100 is then bonded to wafer 2 by hybrid bonding. The bond pads 154 are bonded to their respective bond pads 54 by metal-to-metal bonding, whereby the bond pads 154 are bonded to the bond pads 54 by interdiffusion. The dielectric surface layer 142 in wafer 100 is bonded, for example, to the dielectric surface layer 42 in wafer 2 by fusion bonding, forming Si-O-Si bonds between the dielectric surface layer 142 and the dielectric surface layer 42.

[0037] Fig. Figure 18A shows an enlarged view of the bonding processes. The bonding processes create interdiffusion zones 59. Parts of the filler metal layers 58 and / or 158 may or may not remain. In some embodiments, the wafer temperature during the bonding process is equal to or higher than the melting point of the filler metal layers 58 and / or 158. This leads to at least partial or complete melting of the filler metal layers 58 and / or 158. Throughout this description, the term "partial melting" means that the corresponding layers contain mixed molten and unmelted portions.

[0038] As explained above, the filler metal layers 58 and 158 can be individual layers made of the same material, such as Cu, Sn, In Ag, SnAg, or the like. Accordingly, during partial melting, the filler metal layers 58 (or 158) diffuse into one another and are bonded together. In alternative embodiments, the filler metal layers 58 and 158 are individual layers made of different materials. The different materials thus diffuse into one another and form an alloy. Fig. Figure 17 shows that the dashed line between sublayers 58A and 58B indicates that layer 58 can comprise a single layer made of a homogeneous material or multiple layers, and the dashed line between sublayers 158A and 158B indicates that layer 158 can comprise a single layer made of a homogeneous material or multiple layers. In further embodiments, one of the materials in one of the filler metal layers 58 and 158 is indium, which has a melting point of approximately 156 °C. Thus, indium melts completely or partially during the bonding process and diffuses into the other material (e.g., copper) by solid-liquid diffusion, forming an alloy, which can be an InxCuy alloy. The InxCuy alloy can have a melting point greater than approximately 600 °C, which is higher than the melting point of indium.This makes the resulting alloy more stable and allows it to undergo subsequent thermal processes without melting or breaking.

[0039] In Fig. In 18A, the resulting metal layers are designated as metal layers 59 / 58 / 158 to indicate that the layers between the metal pads 54' and the corresponding overlying metal pads 154' may be alloy regions 59, or that they may contain the bonded filler metal layers 58 and 158 (which are separate layers that may form a recognizable interface) if no alloy is formed. The metal layers 59 / 58 / 158 may also contain the alloy regions 59 and unmelted / unalloyed portions of the filler metal layers 58 and 158.

[0040] Fig. Figure 18B shows embodiments in which micro-recesses are created, and thus the filler metal layers 58 and 158 also have the shapes of the micro-recesses. Here, too, the filler metal layers 58 and 158 can form an alloy 59 or remain as separate layers (made of different materials) with a recognizable interface. The metal pads 54 and 154 can be in contact with each other, as shown in Figure 18B. Fig. 18B is shown, or they can be spaced apart by the filler metal layers 58 and 158 (if they are not alloyed) or the alloy area 59.

[0041] In some embodiments, where the filler metal layers 58 and / or 158 each consist of a composite layer, the different sublayers in the filler metal layers 58 and 158 can diffuse into one another, forming an alloy. For example, in some embodiments, an upper sublayer of the filler metal layer 58 is made of In, and a lower sublayer of the filler metal layer 158 is made of Cu, which can form an alloy during the bonding process. Additionally, there can be a diffusion barrier that is not melted and alloyed. Fig. In embodiment 18A, the resulting bonded areas, for example, have a diffusion layer 58A and a diffusion layer 158A, with the metal layers 59 / 58 / 158 in between (where 58 / 158 are actually 58B / 158B). In alternative embodiments, where each of the diffusion layers 58 and 158 is a single layer and alloy regions 59 are formed, the alloy regions 59 can be in contact with the top surfaces of the bond pad 54' and the bottom surfaces of the bond pad 154'.

[0042] In some embodiments, some parts of the metal pads 54' and 154' are in physical contact with each other and are bonded together. As in Fig. As shown in Figure 18A, for example, the edge portions of the metal pads 54' and 154' are bonded together, forming interfaces. The interface formed between a pair of metal pads 54' and 154' can form a ring in a top view of the bond structure, with the ring enclosing the metal layers 59 / 58 / 158. In other embodiments, the metal pads 54' and 154' are completely spaced apart by the metal layers 59 / 58 / 158 and are not in contact with each other. It is understood that, due to process variations, some of the metal pads 54' and 154' on the same bonded wafer and in the same resulting package may be in physical contact with each other and bonded together, while some other metal pads 54' and 154' are completely spaced apart by the metal layers 59 / 58 / 158.

[0043] In alternative embodiments, one of the filler metal layers 58 and 158 is used for the corresponding wafers 2 and 100 ( Fig. 6) is produced, and the other is not produced. Accordingly, the filler metal layers 58 and 158 both fill the recesses in the metal pads 54' and 154'.

[0044] In Fig. 8 In some embodiments, back-side grinding can be performed after the bonding process to thin the wafer 100 until the vias 116 are exposed. Then in Fig. Nine redistribution lines (RDLs) 72 and a dielectric layer 74 were produced. The corresponding step is specified as step 212 in the process flow 200, which is described in Fig. Figure 19 shows that in some embodiments of the present invention, the dielectric layer 74 is made from an oxide, such as silicon oxide, a nitride, such as silicon nitride, or the like. The RDLs 72 can be produced using a Damascene process comprising the following steps: etching the dielectric layer 74 to create openings; depositing a conductive barrier layer in the openings; cladding with a metallic material, such as copper or a copper alloy; and performing planarization to remove excess portions of the metallic material.

[0045] Fig. Figure 10 shows the fabrication of passivation layers, metal pads, and higher-level dielectric layers. It is understood that the higher-level structures may take on different forms than those shown, and the structure depicted is merely an example. The corresponding step is specified as step 214 in process flow 200, which is described in Fig. Figure 19 shows that a passivation layer 76 (occasionally also referred to as Passivation-1) is fabricated above the dielectric layer 74, and vias 78 are fabricated in the passivation layer 76 for electrical connection to the RDLs 72. Metal pads 80 are fabricated above the passivation layer 76 and are electrically connected to the RDLs 72 via the vias 78. The metal pads 80 can be aluminum pads or aluminum-copper pads, but other metallic materials can also be used.

[0046] As also in Fig. As shown in Figure 10, a passivation layer 82 (occasionally also referred to as passivation-2) is produced above the passivation layer 76. The passivation layers 76 and 82 can each be a single layer or a composite layer and can be made of a non-porous material. In some embodiments of the present invention, the passivation layers 76 and / or 82 are each a composite layer with a silicon oxide layer and a silicon nitride layer (not shown separately) above the silicon oxide layer. The passivation layers 76 and 82 can also be made of other non-porous dielectric materials, such as USG, silicon nitride oxide, and / or the like.

[0047] The passivation layer 82 is then structured such that some parts of the passivation layer 82 cover the edge portions of the metal pads 80, while some parts of the metal pads 80 are exposed through the openings in the passivation layer 82. A polymer layer 84 is then produced and structured to expose the metal pads 80. The polymer layer 84 can be made from a polyimide, polybenzoxazole (PBO), or the like.

[0048] In Fig. 11. Post-passivation interconnects (PPIs) 86 are fabricated. The fabrication process may include the fabrication of a metallic seed layer and a structured mask layer (not shown) over the metallic seed layer; and the plating of the PPIs 86 in the structured mask layer. The structured mask layer and the portions of the metallic seed layer covered by the structured mask layer are then removed by etching processes. A polymer layer 88, for example made of PBO, a polyimide, or the like, is then fabricated.

[0049] In Fig. 12 Metallizations are produced below the contact mounds (UBMs) 90 and electrical connecting elements 92. The UBMs 90 and the electrical connecting elements 92 extend into the polymer layer 88 to be connected to the PPIs 86. In some embodiments of the present invention, the UBMs 90 each have a barrier layer (not shown) and a seed layer (not shown) above the barrier layer. The barrier layer can be a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, or a layer made of a titanium alloy or a tantalum alloy. Copper or a copper alloy can be used as the material for the seed layer. Other metals, such as silver, gold, aluminum, palladium, nickel, nickel alloys, tungsten alloys, chromium, chromium alloys, and combinations thereof, can also be included in the UBMs 90.

[0050] A manufacturing process for producing the UBMs 90 and the electrical connectors 92 may include depositing a UBM protective layer and fabricating and structuring a mask (which may be a photoresist; not shown), wherein portions of the UBM protective layer are exposed through the opening in the mask. After fabrication of the UBMs 90, the illustrated package is placed in a plating solution (not shown), and a plating process is performed to fabricate the electrical connectors 92 onto the UBMs 90. In some embodiments of the present invention, the electrical connectors 92 have solderless portions (not shown) that are not melted in the subsequent remelting processes. The solderless portions may be made of copper and are therefore referred to below as copper contact mounds, but they may also be made of other solderless materials.The electrical connecting elements 92 may also each have one or more capping layers (not shown) selected from the group consisting of nickel, nickel alloy, palladium, gold, silver, or multiple layers thereof. The one or more capping layers are produced over the copper contact mounds. The electrical connecting elements 92 may also have solder caps made of a Sn-Ag alloy, an Sn-Cu alloy, an Sn-Ag-Cu alloy, or the like, and may be lead-free or lead-containing.

[0051] The structure produced in the preceding steps is referred to as a newly configured wafer 94. A die sawing step (single-out step) is then performed on the newly configured wafer 94 to separate it into a plurality of packages 96. The corresponding step is specified as step 222 in the process flow 200, which is described in Fig. 19 is shown. Fig. 13 is one of the packages shown in 96.

[0052] The in Fig. The package shown in Figure 13 is manufactured using a wafer-to-wafer bonding process. In alternative embodiments, the wafers and bond pads manufactured according to the embodiments of the present invention can also be used in die-to-wafer or die-to-die bonding processes. For example, Figure 13 shows... Fig. 14 a package that is manufactured by a die-wafer bonding process. In the respective manufacturing process, device dies 112 are first sawn from the respective wafer into discrete dies, which are then bonded to the wafer 2 by die-wafer bonding. Subsequently, gap-filling materials 160 and 162 are deposited to fill gaps between the device dies 112. In some embodiments, the gap-filling material 160 comprises silicon nitride, and the gap-filling material 162 comprises an oxide, such as silicon oxide. After the bonding process, a planarization process is carried out to remove excess gap-filling materials 160 and 162 and to expose the vias 116. Then, vias 170 are created for electrical connection to some of the bond pads 54. It is understood that these bond pads 54 are the ones described in Fig. The structures shown in Figure 16A can have metal pads 54' made of a first material and filler metal layers 58 made of a second material different from the first. The vias 170 are in contact with the bond pads 54, and they can be in contact with the filler metal layers 58 and / or the metal pads 54', as shown in Figure 16A. Fig. Figure 16A shows this process. In subsequent processes, the RDLs 72, the dielectric layer 74, and the structural elements located above them are manufactured to produce the newly configured wafer 94. Then, a singulation process can be carried out to saw the newly configured wafer 94 into individual packages 96.

[0053] In the embodiments described above, some processes and structural elements according to some embodiments of the present invention for manufacturing a three-dimensional package (3D package) have been discussed. Other processes and structural elements can also be used. For example, test structures can be used to assist in the verification testing of a 3D encapsulation or 3D IC devices. The test structures can, for example, include test pads fabricated in a redistribution layer or on a substrate, enabling the testing of the 3D encapsulation or 3D IC devices, the use of probes and / or probe cards, and the like. The verification test can be performed on intermediate structures as well as on the final structure.Furthermore, the structures and procedures disclosed here can be used in conjunction with testing methodologies that include intermediate verification of proven good dies to increase yield and reduce costs.

[0054] The embodiments of the present invention can have several advantages. By selectively producing conductive filler layers on bond pads, recesses in the bond pads can be filled, and the corresponding bonding processes have a higher quality.

[0055] According to some embodiments of the present invention, a method comprises manufacturing a first package component by the following steps: generating a first plurality of openings in a first dielectric layer; depositing a first metallic material into the first plurality of openings; performing a planarization process on the first metallic material and the first dielectric layer to produce a first plurality of metal pads in the first dielectric layer; and selectively depositing a second metallic material on the first plurality of metal pads to produce a first plurality of bond pads, wherein the first plurality of bond pads comprises the first plurality of metal pads and corresponding portions of the second metallic material.The method further comprises bonding the first package component to a second package component, wherein the first plurality of bond pads is bonded to the second package component. In one embodiment, the second package component comprises: a second dielectric layer, wherein the first dielectric layer is bonded to the second dielectric layer; and a second plurality of bond pads in the second dielectric layer, wherein the second plurality of bond pads is bonded to the first plurality of bond pads. In one embodiment, the first plurality of metal pads and the second metallic material in the first plurality of bond pads are in contact with the second plurality of bond pads. In one embodiment, during the deposition of the first metallic material, the first metallic material is not deposited on exposed surfaces of the first dielectric layer.In one embodiment, the selective deposition of the second metallic material comprises: depositing a first sublayer comprising a first metal; and depositing a second sublayer over the first sublayer, wherein the second sublayer comprises a second metal different from the first metal.In one embodiment, the method further comprises fabricating a second package component by the following steps: creating a second plurality of openings in a second dielectric layer; depositing a third metallic material into the second plurality of openings; performing a further planarization process on the third metallic material and the second dielectric layer to produce a second plurality of metal pads in the second dielectric layer; and selectively depositing a fourth metallic material onto the second plurality of metal pads to produce a second plurality of bond pads, wherein the first plurality of bond pads is bonded to the second plurality of bond pads. In one embodiment, the second metallic material is at least partially melted during the bonding process.In one embodiment, during bonding, the second metallic material forms an alloy with a material from a second plurality of bond pads in the second package component. In another embodiment, the second metallic material has a first melting point that is lower than the second melting point of the material from the second plurality of bond pads. In another embodiment, the selective deposition of the second metallic material includes a plating process. In yet another embodiment, bonding is performed at a temperature of both the first and second package components that is lower than approximately 200 °C, with the second metallic material being melted during bonding.

[0056] According to some embodiments of the present invention, a package comprises a first package component comprising: a first dielectric layer; a first metal pad in the first dielectric layer, the first metal pad comprising a first metallic material; and a filler metal layer extending from a top surface of the first dielectric layer into the first metal pad, the filler metal layer comprising a second metallic material different from the first metallic material. In one embodiment, the first metallic material has a first melting point, and the second metallic material has a second melting point lower than the first melting point. In one embodiment, the second melting point is lower than about 200 °C. In another embodiment, the package further comprises a diffusion barrier between the filler metal layer and the first metal pad.In one embodiment, the package further comprises a second package component comprising: a second dielectric layer bonded to the first dielectric layer; and a second metal pad in the second dielectric layer bonded to the first metal pad, the filler metal layer also extending into the second metal pad.

[0057] According to some embodiments of the present invention, a package comprises a first package component and a second package component. The first package component comprises: a first dielectric layer; and a first metal pad in the first dielectric layer, wherein the first metal pad comprises a first metallic material. The second package component comprises: a second dielectric layer bonded to the first dielectric layer; a second metal pad in the second dielectric layer, wherein the second metal pad comprises a second metallic material; and a metal layer extending into the first metal pad, wherein the metal layer comprises an alloy, the alloy comprising a third metallic material different from the first metallic material, and the metal layer being arranged between the first metal pad and the second metal pad.In one embodiment, the first metal pad has a dishing recess, the metal layer extending into the dishing recess. In one embodiment, the first metal pad is physically connected to the second metal pad. In another embodiment, the first metal pad is physically separated from the second metal pad by the metal layer.

[0058] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. It should be clear to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent designs do not deviate from the fundamental concept and scope of protection of the present invention and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present invention.

Claims

[1] Procedure with the following steps: Create a first package component with the following steps: Creating a first plurality of openings in a first dielectric layer, Depositing a first metallic material into the first plurality of openings, Performing a planarization process on the first metallic material and the first dielectric layer to produce a first plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the first plurality of metal pads to form a first plurality of bond pads, wherein the first plurality of bond pads comprises the first plurality of metal pads and corresponding portions of the second metallic material; and Bonding the first package component to a second package component, wherein the first plurality of bond pads are bonded to the second package component. [2] The method of claim 1, wherein the second package component comprises: a second dielectric layer, wherein the first dielectric layer is bonded to the second dielectric layer; and a second plurality of bond pads in the second dielectric layer, wherein the second plurality of bond pads are bonded to the first plurality of bond pads. [3] The method of claim 2, wherein the first plurality of metal pads and the second metallic material in the first plurality of bond pads are in contact with the second plurality of bond pads. [4] A method according to any one of the preceding claims, wherein in depositing the first metallic material, the first metallic material is not deposited on exposed surfaces of the first dielectric layer. [5] A method according to any one of the preceding claims, wherein the selective deposition of the second metallic material comprises: Depositing a first sublayer comprising a first metal; and Depositing a second sublayer over the first sublayer, wherein the second sublayer comprises a second metal different from the first metal. [6] Method according to one of the preceding claims, further comprising manufacturing the second package component with the following steps: Creating a second plurality of openings in a second dielectric layer; depositing a third metallic material into the second plurality of openings; Performing a further planarization process on the third metallic material and the second dielectric layer to form a second plurality of metal pads in the second dielectric layer; and selectively depositing a fourth metallic material on the second plurality of metal pads to form a second plurality of bond pads, wherein the first plurality of bond pads are bonded to the second plurality of bond pads. [7] Method according to one of the preceding claims, wherein the second metallic material is at least partially melted during the bonding. [8] A method according to any one of the preceding claims, wherein during the bonding, the second metallic material forms an alloy with a material of a second plurality of bond pads in the second package component. [9] The method of claim 8, wherein the second metallic material has a first melting point that is lower than a second melting point of the material of the second plurality of bond pads. [10] A method according to any one of the preceding claims, wherein the selective deposition of the second metallic material comprises a plating process. [11] A method according to any one of the preceding claims, wherein the bonding is performed at a temperature of the first package component and the second package component that is lower than about 200°C, wherein the second metallic material is melted during the bonding. [12] Package with a first package component comprising: a first dielectric layer; a first metal pad in the first dielectric layer, the first metal pad comprising a first metallic material; and a fill metal layer extending from a top surface of the first dielectric layer into the first metal pad, the fill metal layer comprising a second metallic material different from the first metallic material. [13] The package of claim 12, wherein the first metallic material has a first melting point and the second metallic material has a second melting point lower than the first melting point. [14] The package of claim 13, wherein the second melting point is lower than about 200°C. [15] The package of any one of claims 12 to 14, further comprising a diffusion barrier between the fill metal layer and the first metal pad. [16] Package according to one of claims 12 to 15, further comprising a second package component comprising: a second dielectric layer bonded to the first dielectric layer; and a second metal pad in the second dielectric layer bonded to the first metal pad, wherein the fill metal layer further extends into the second metal pad. [17] Package with: a first package component that has the following: a first dielectric layer, and a first metal pad in the first dielectric layer, the first metal pad comprising a first metallic material; and a second package component that has the following: a second dielectric layer bonded to the first dielectric layer, and a second metal pad in the second dielectric layer, the second metal pad comprising a second metallic material, a metal layer extending into the first metal pad, the metal layer comprising an alloy, the alloy comprising a third metallic material different from the first metallic material, and the metal layer being disposed between the first metal pad and the second metal pad. [18] The package of claim 17, wherein the first metal pad has a dishing recess, the metal layer extending into the dishing recess. [19] The package of claim 17 or 18, wherein the first metal pad is physically connected to the second metal pad. [20] The package of claim 17 or 18, wherein the first metal pad is physically separated from the second metal pad by the metal layer.