Semiconductor device

Abstract

Semiconductor device (100), comprising: a semiconductor substrate having a drift layer (1) of a first conductivity type between a first principal surface and a second principal surface opposite the first principal surface; and an IGBT region (10) and a diode region (20) arranged adjacent to each other in the semiconductor substrate, wherein: the IGBT area (10) exhibits: a base layer (15) of a second conductivity type, which is arranged in the semiconductor substrate on the side of the first main surface; a source layer (13) of the first conductivity type, which is selectively arranged on the base layer (15) on the side of the first main surface; a gate (11) of an active trench, which contains a gate electrode (11a) of the active trench, arranged such that it faces the drift layer (1) via an insulating film (11b), and to which a gate voltage is applied, in each of a plurality of active trenches, which are configured to be aligned in a first direction along the first main surface of the semiconductor substrate and pass through the source layer (13) and the base layer (15); and a collector layer (16) of the second conductivity type, which is arranged in the semiconductor substrate on the side of the second main surface; the diode area (20) includes: an anode layer (25) of the second conductivity type, which is arranged in the semiconductor substrate on the side of the first main surface; a cathode layer (26) of the first conductivity type, which is arranged in the semiconductor substrate on the side of the second main surface; and a gate (21) of a dummy trench, which contains a gate electrode (21a) of the dummy trench, which is opposite the drift layer (1) via an insulating film (21b) and to which the gate voltage is not applied, in each of a plurality of dummy trenches which are configured to be oriented in the first direction of the semiconductor substrate and which pass through the anode layer (25); and the semiconductor device (100) further comprises: a boundary trench which, at a position where the IGBT area (10) and the diode area (20) are adjacent in plan view, has a bottom surface (51c) positioned in the drift layer (1) such that it is lower than the active trench or the dummy trench, and has one side wall (51d) and another side wall (51d) that are opposite each other and connect the bottom surface (51c) and the first main surface; and a gate electrode (51a) of the boundary trench, which is opposite the base layer (15), the anode layer (25) and the drift layer (1) via an insulating film (51b) of the boundary trench and is arranged from the side of one side wall (51d) to the side of the other side wall (51d) of the boundary trench via an area opposite the drift layer (1) in the boundary trench in which the bottom surface (51c), one side wall (51d) and the other side wall (51d) are covered with the insulating film (51b) of the boundary trench, wherein the bottom surface (51c) of the boundary ditch is deeper than a bottom surface of an active ditch and is at the same depth as a bottom surface of the dummy ditch.

Description

Background of the inventionArea

[0001] The present disclosure relates to a semiconductor device. background

[0002] In recent years, small-sized inverter devices have been demanded for energy conservation in the automotive, industrial machinery, and consumer appliance sectors. For example, in JP 2008-103590 A, to downsize an inverter device, a semiconductor device is proposed in which an insulated-gate bipolar transistor (IGBT) and a diode are formed on a semiconductor substrate.

[0003] However, in the semiconductor device of JP 2008-103590 A, electron holes, which are minority carriers, flow from an IGBT region to a diode region. Therefore, there is a problem in that the recovery current increases at the time of recovery operation and the breakdown resistance of the diode decreases compared to when an IGBT and a diode, which are separate parts, are connected in parallel. Other semiconductor devices are known from JP 2017-098359 A, US 2016 / 0 336 404 A1, DE 101 60 118 A1, DE 11 2011 105 319 T5, and DE 11 2011 105 681 T5. Summary

[0004] The present disclosure has been made to solve the above-mentioned problems, and its object is to provide a semiconductor device which suppresses the inflow of electron holes from an IGBT region into a diode region and whose breakdown resistance at the time of recovery operation is improved.

[0005] This problem is solved by the features of the independent claims. The subclaims contain advantageous embodiments of the invention.

[0006] The features and advantages of the present disclosure can be summarized as follows.

[0007] According to a first aspect of the present disclosure, a semiconductor device includes a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite the first main surface; and an IGBT region and a diode region arranged adjacent to each other in the semiconductor substrate, wherein the IGBT region includes a base layer of a second conductivity type arranged on a front layer of the semiconductor substrate on the first main surface side; an emitter layer of a first conductivity type selectively arranged on a front layer of the base layer on the first main surface side;an active trench gate including an active trench gate electrode disposed to oppose the drift layer via an insulating film and to which a gate voltage is applied, in each of a plurality of active trenches formed to be aligned in a first direction along the first main surface of the semiconductor substrate and to pass through the emitter layer and the base layer; and a collector layer of a second conductivity type disposed on a front layer of the semiconductor substrate on the second main surface side; the diode region includes an anode layer of a second conductivity type disposed on the front layer of the semiconductor substrate on the first main surface side; a cathode layer of a first conductivity type disposed on the front layer of the semiconductor substrate on the second main surface side;and a dummy trench gate having a dummy trench gate electrode, which faces the drift layer via an insulating film and to which the gate voltage is not applied, in each of a plurality of dummy trenches formed to align in the first direction of the semiconductor substrate and pass through the anode layer; and the semiconductor device further includes a boundary trench formed at a position where the IGBT region and the diode region are adjacent to each other in plan view, a bottom surface positioned in the drift layer to be deeper than the active trench or the dummy trench, and a side wall and another side wall, which face each other and connect the bottom surface and the first main surface.and a gate electrode of a boundary trench, which faces the base layer, the anode layer, and the drift layer via an insulating film of the boundary trench and is arranged from the one sidewall side to the other sidewall side of the boundary trench over a region facing the drift layer in the boundary trench in which the bottom surface, one sidewall, and the other sidewall are covered with the insulating film of the boundary trench;

[0008] Other and further objects, features and advantages of the disclosure will appear more fully from the following description. Short description of the drawings Fig. 1 is a plan view illustrating a semiconductor device according to a first embodiment. Fig. 2 is a plan view illustrating a semiconductor device having another configuration according to the first embodiment. Fig. 3 is a partially enlarged plan view illustrating the configuration of the IGBT region of the semiconductor device according to the first embodiment. Fig. 4 and Fig. 5 are cross-sectional views illustrating the configuration of the IGBT region and the semiconductor device according to the first embodiment. Fig. 6 is a partially enlarged plan view illustrating the configuration of the diode region of the semiconductor device according to the first embodiment. Fig. 7 and Fig. 8 are cross-sectional views illustrating the configurations of the diode region of the semiconductor device according to the first embodiment. Fig. 9 is a partially enlarged cross-sectional view illustrating the configuration of the boundary between the IGBT region and the diode region of the semiconductor device according to the first embodiment. Fig. 10 and Fig. 11 are cross-sectional views illustrating the configuration of the boundary between the IGBT region and the diode region of the semiconductor device according to the first embodiment. Fig. 12A to Fig. 17B illustrates the manufacturing method of the semiconductor device according to the first embodiment. Fig. 18 schematically illustrates the movement of electron holes at the time of diode operation of the semiconductor device of the comparative example. Fig. 19 schematically illustrates the movement of electron holes at the time of recovery operation of the semiconductor device of the comparative example. Fig. 20 and Fig. 21 schematically illustrate an effect of suppressing the inflow of electron holes of the semiconductor device according to the first embodiment. Fig. 22 is a cross-sectional view illustrating the semiconductor device according to the second embodiment. Fig. 23 is a cross-sectional view illustrating the semiconductor device according to the third embodiment. Fig. 24 is a cross-sectional view illustrating the semiconductor device according to the fourth embodiment. Fig. 25 is a cross-sectional view illustrating the semiconductor device according to the fifth embodiment. Description of the embodiments

[0009] Embodiments will be described below with reference to the drawings. The drawings are schematically illustrated, and therefore the interrelationships between sizes and positions may be changed. In the following description, the same or corresponding components may be denoted by the same reference numerals, and repeated descriptions may be omitted.

[0010] In the following description, terms meaning predetermined positions and directions such as "upper," "lower," and "lateral" may be used; however, these terms are used for convenience to facilitate understanding of the details of the embodiments and do not limit the positions and directions when the embodiments are carried out.

[0011] In the following description, n and p indicate the conductivity types of a semiconductor. In the present disclosure, the first conductivity type is described as n-type, and a second conductivity type is described as p-type. Furthermore, (n-) indicates that the impurity concentration is lower than n, and (n+) indicates that the impurity concentration is higher than n. Similarly, (p-) indicates that the impurity concentration is lower than p, and (p+) indicates that the impurity concentration is higher than p. First embodiment

[0012] Fig. 1 is a plan view illustrating a semiconductor device according to a first embodiment, and illustrates a semiconductor device that is a reverse conducting IGBT (RC-IGBT). Fig. Fig. 2 is a plan view illustrating a semiconductor device having a different configuration according to the first embodiment, and illustrates a semiconductor device that is an RC-IGBT having the different configuration. Fig. In the semiconductor device 100 illustrated in Figure 1, IGBT regions 10 and diode regions 20 are arranged so as to be aligned in a stripe shape, and the semiconductor device 100 may simply be referred to as a “stripe type.” In a Fig. In the semiconductor device 101 illustrated in Figure 2, a plurality of diode regions 20 are arranged in the longitudinal direction and the transverse direction, and the IGBT region 10 is arranged around the diode region 20. The semiconductor device 101 may be referred to as an "island type." In the description below, a description will be made using the stripe type; however, the present disclosure may be applied to any of the stripe type and the island type.

[0013] In Fig. 1, the semiconductor device 100 includes the IGBT regions 10 and the diode regions 20 in one semiconductor device. The IGBT regions 10 and the diode regions 20 extend from one end to the other end of the semiconductor device 100 and are arranged alternately in a strip shape in a direction orthogonal to the extension direction of the IGBT regions 10 and the diode regions 20. In Fig. 1 illustrates three IGBT regions 10 and two diode regions, and illustrates a configuration in which all the diode regions 20 are arranged between the IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to the above. The number of IGBT regions 10 may be three or more, or three or less, and the number of diode regions 20 may also be two or more, or two or less. The positions of the IGBT regions 10 and the diode regions 20 in Fig. 1 can be interchanged, and all the IGBT regions 10 can be arranged between the diode regions 20. An IGBT region 10 and a diode region 20 can be provided or arranged adjacent to each other.

[0014] As in Fig. As illustrated in Figure 1, a pad region 40 is arranged adjacent to the IGBT region 10 on the lower side of the sheet. The pad region 40 is a region in which control pads 41 for controlling the semiconductor device 100 are arranged. The IGBT regions 10 and the diode regions 20 are collectively referred to as a cell region. A termination region 30 is arranged around a region obtained by combining the cell region and the pad region 40 to maintain the withstand voltage of the semiconductor device 100. In the termination region 30, a well-known withstand voltage maintaining structure can be selected and arranged as necessary.In the withstand voltage sustaining structure, for example, a field limiting ring (FLR) in which the cell region is surrounded by a p-type termination well layer of a p-type semiconductor, and a variation of lateral doping (VLD) in which the cell region is surrounded by a p-type well layer with a concentration gradient can be arranged on the first main surface side, which is the front surface side of the semiconductor device 100. The number of annular p-type termination well layers used in the FLR and the concentration distribution used in the VLD can be selected as appropriate according to the withstand voltage design of the semiconductor device 100. The p-type termination well layer can be provided over almost the entire area of ​​the pad region 40, and an IGBT cell and a diode cell can be provided in the pad region 40.

[0015] The control pads 41 may be, for example, a current detection pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and pads 41d and 41e for a temperature sensing diode. The current detection pad 41a is a control pad for detecting a current flowing through the cell region of the semiconductor device 100 and is a control pad electrically connected to some IGBT cells or diode cells of the cell region, so that when current flows through the cell region of the semiconductor device 100, a current that is a fraction to several ten-thousandths of the current flowing through the entire cell region flows therethrough.

[0016] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied to control the ON / OFF of the semiconductor device 100. The Kelvin emitter pad 41 is electrically connected to a p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to an electrode of a gate trench of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected to each other via a (p+)-type contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to an anode and a cathode of a temperature sensing diode provided in the semiconductor device 100.The temperature detection diode pads 41d and 41e measure the voltage between the anode and the cathode of the temperature detection diode (not shown) provided in the cell region, thereby measuring the temperature of the semiconductor device 100.

[0017] Fig. 3 is a partially enlarged plan view illustrating the configuration of the IGBT region of the semiconductor device according to the first embodiment, and illustrates the configuration of the IGBT region of the semiconductor device which is an RC-IGBT. Fig. 4 and Fig. 5 are cross-sectional views illustrating the configuration of the IGBT region of the semiconductor device according to the first embodiment, and illustrate the configuration of the IGBT region of the semiconductor device which is an RC-IGBT. Fig. Figure 3 illustrates an enlarged view of an area defined by a dashed line 82 in the Fig. 1 illustrated semiconductor device 100 or the one in Fig. 2 illustrated semiconductor device 101. Fig. 4 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along a Fig. 3 illustrated dashed line AA, and Fig. 5 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along a Fig. 3 illustrated by the dashed line BB.

[0018] As in Fig. 3, in the IGBT region 10, gates 11 of active trenches and gates 12 of dummy trenches are provided in a stripe shape. In the semiconductor device 100, the gates 11 of active trenches and the gates 12 of dummy trenches extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is the longitudinal direction of the gates 11 of active trenches and the gates 12 of dummy trenches. Meanwhile, in the semiconductor device 101, the left-right direction on the sheet may be the longitudinal direction of the gates 11 of active trenches and the gates 12 of dummy trenches, or the up-down direction on the sheet may be the longitudinal direction of the gates 11 of active trenches and the gates 12 of dummy trenches.

[0019] The active trench gate 11 includes a gate trench electrode 11a formed in a trench formed in the semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 includes a dummy trench electrode 12a formed in a trench formed in the semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode arranged on a first main surface of the semiconductor device 100 or the semiconductor device 101. In other words, a gate drive voltage can be applied to the gate 11 of an active trench, but the gate drive voltage cannot be applied to the gate 12 of a dummy trench.

[0020] On both sides of the active trench gate 11 in the width direction, n+-type source layers 13 are provided to contact the gate trench insulating film 11b. The n+-type source layers 13 are provided along the extension direction of the active trench gate 11 to alternate with p+-type contact layers 14. The p+-type contact layer 14 is also arranged between two adjacent dummy trench gates 12.

[0021] As in Fig. 3, in the IGBT region 10 of the semiconductor device 100 or the semiconductor device 101, three gates 12 of dummy trenches are aligned next to the three aligned gates 11 of active trenches, and three gates 11 of active trenches are aligned next to the three aligned gates 12 of dummy trenches. The IGBT region 10 has a configuration in which one set of the gates 11 of active trenches and one set of the gates 12 of dummy trenches are alternately aligned as above. The number of the gates 11 of active trenches included in one set of the gates 11 of active trenches is Fig. 3 three; but the number must be one or more. The number of dummy trench gates 12 included in a set of dummy trench gates 12 can be one or more, or the number of dummy trench gates 12 can be zero. In other words, all the trenches arranged in the IGBT region 10 can be active trench gates 11.

[0022] Fig. 4 is a line drawn along a dashed line AA in Fig. 3 shows a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 and illustrates a cross-sectional view of the IGBT region 10. The semiconductor device 100 or the semiconductor device 101 has an (n-) type drift layer 1 formed by a semiconductor substrate. Fig. 4, the semiconductor substrate extends from the source layers 13 of the (n+) type and the contact layer 14 of the (p+) type to a collector layer 16 of the p-type. In Fig. 4, the upper ends of the n+-type source layers 13 and the p+-type contact layer 14 on the sheet are referred to as the first main surface of the semiconductor substrate, and a lower end of the p-type collector layer 16 on the sheet is referred to as a second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is a main surface of the front surface side of the semiconductor device 100, and the second main surface of the semiconductor substrate is a main surface of a back surface side of the semiconductor device 100. The semiconductor device 100 has the n-type drift layer 1 between the first main surface and the second main surface opposite the first main surface in the IGBT region 10, which is a cell region.

[0023] As in Fig. 4, in the IGBT region 10, an n-type carrier accumulation layer 2, in which the concentration of the n-type impurity is higher than that of the (n-)-type drift layer 1, is arranged on the side of the first main surface of the (n-)-type drift layer 1. In the semiconductor device 100 or the semiconductor device 101, the (n-)-type drift layer 1 may be arranged without disposing the n-type carrier accumulation layer 2 in the region of the Fig. 4 may also be arranged. By disposing the n-type carrier accumulation layer 2, the conduction loss when current flows through the IGBT region 10 can be reduced. The n-type carrier accumulation layer 2 and the (n-)-type drift layer 1 may be collectively referred to as the drift layer.

[0024] The n-type carrier accumulation layer 2 is formed by implanting ions of an n-type impurity into the semiconductor substrate constituting the (n-)-type drift layer 1 and allowing the implanted n-type impurity to diffuse in the semiconductor substrate constituting the (n-)-type drift layer 1 by subsequent annealing.

[0025] On the first main surface side of the n-type carrier accumulation layer 2, a p-type base layer 15 is disposed. The p-type base layer 15 is in contact with insulating films 11b of gate trenches of the gates 11 of active trenches. On the first main surface side of the p-type base layer 15, n+-type source layers 13 are disposed to contact the insulating films 11b of gate trenches of the gates 11 of active trenches, and the p+-type contact layer 14 is disposed in the remaining region. The n+-type source layers 13 and the p+-type contact layer 14 constitute the first main surface of the semiconductor substrate. The p+-type contact layer 14 is a region where the concentration of the p-type impurity is higher than that of the p-type base layer 15.If the p+-type contact layer 14 and the p-type base layer 15 need to be distinguished from each other, the p+-type contact layer 14 and the p-type base layer 15 may be referred to individually. The p+-type contact layer 14 and the p-type base layer 15 may be referred to collectively as the p-type base layer.

[0026] In the semiconductor device 100 or the semiconductor device 101, an n-type buffer layer 3, in which the concentration of the n-type impurity is higher than that of the (n-)-type drift layer 1, is disposed on the second main surface side of the (n-)-type drift layer 1. The n-type buffer layer 3 is provided to suppress the punch-through of a depletion layer extending from the p-type base layer 15 to the second main surface side when the semiconductor device 100 or the semiconductor device 101 is in an OFF state. The n-type buffer layer 3 can be formed, for example, by implanting phosphorus (P) or protons (H+), or can be formed by implanting both phosphorus (P) and protons (H+). In the semiconductor device 100 or the semiconductor device 101, the (n-) type drift layer 1 may be formed without arranging the n type buffer layer 3 in the region of Fig. 4 may also be arranged. The n-type buffer layer 3 and the (n-)-type drift layer 1 may be collectively referred to as the drift layer.

[0027] In the semiconductor device 100 or the semiconductor device 101, the p-type collector layer 16 is disposed on the second main surface side of the n-type buffer layer 3. In other words, the p-type collector layer 16 is disposed between the n-type drift layer 1 and the second main surface. The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 is disposed not only in the IGBT region 10 but also in the termination region 30, and the part of the p-type collector layer 16 disposed in the termination region 30 forms a termination p-type collector layer. The p-type collector layer 16 may be disposed such that a part of it bulges from the IGBT region 10 to the diode region 20.

[0028] As in Fig. As illustrated in Fig. 4, in the semiconductor device 100 or the semiconductor device 101, trenches are formed that pass through the p-type base layer 15 from the first main surface of the semiconductor substrate and reach the (n-)-type drift layer 1. The gates 11 of active trenches are formed by disposing the electrodes 11a of gate trenches in the trenches via the insulating films 11b of gate trenches. The electrodes 11a of gate trenches face the (n-)-type drift layer 1 via the insulating films 11b of gate trenches. The gates 12 of dummy trenches are formed by disposing the electrodes 12a of dummy trenches in the trenches via the insulating films 12b of dummy trenches. The electrodes 12a of dummy trenches are opposed to the (n-) type drift layer 1 via the insulating films 12b of dummy trenches.The gate trench insulating films 11b of the active trench gates 11 are in contact with the p-type base layer 15 and the n+-type source layers 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0029] As in Fig. As illustrated in Figure 4, an interlayer insulating film 4 is disposed on the gate trench electrodes 11a of the gates 11 of the active trenches. A barrier metal 5 is formed on the interlayer insulating film 4 and on a region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not disposed. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), may be, for example, titanium nitride, or may be TiSi obtained by alloying titanium and silicon (Si).

[0030] As in Fig. As illustrated in Figure 4, the barrier metal 5 is in ohmic contact with the n+-type source layers 13, the p+-type contact layer 14, and the dummy trench electrodes 12a, and is electrically connected to the n+-type source layers 13, the p+-type contact layer 14, and the dummy trench electrodes 12a. An emitter electrode 6 is disposed on the barrier metal 5. For example, the emitter electrode 6 may be formed using an aluminum alloy such as an aluminum-silicon alloy (AlSi alloy), and may be an electrode formed by a plurality of layers of metal films in which a plating film is formed by electroless plating or electroplating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electroplating may, for example, be a plating film made of nickel (Ni).

[0031] When the width of a contact hole 19 disposed on the interlayer insulating film 4 is narrow and sufficient embedding with the emitter electrode 6 cannot be obtained, tungsten having a more satisfactory embedding property than the emitter electrode 6 can be positioned on the contact hole 19, and the emitter electrode 6 can be disposed on the tungsten. The emitter electrode 6 can be disposed without disposing the barrier metal 5 on the n+-type source layers 13, the p+-type contact layer 14, and the dummy trench electrodes 12a. It is possible to provide the barrier metal 5 only on n-type semiconductor layers such as the n+-type source layers 13. The barrier metal 5 and the emitter electrode 6 can be referred to collectively as an emitter electrode.

[0032] In Fig. 4 illustrates a configuration in which the contact holes 19 are arranged on the electrodes 12a of dummy trenches of the gates 12 of dummy trenches without providing the interlayer insulating film 4. However, the interlayer insulating film 4 may be formed on the electrodes 12a of dummy trenches of the gates 12 of dummy trenches. When the interlayer insulating film 4 is formed on the electrodes 12a of dummy trenches of the gates 12 of dummy trenches, only the emitter electrode 6 and the electrodes 12a of dummy trenches need to be electrically connected to each other at a different cross section.

[0033] A collector electrode 7 is arranged on the second main surface side of the p-type collector layer 16. Like the emitter electrode 6, the collector electrode 7 can be formed using an aluminum alloy or using an aluminum alloy and a plating film. The collector electrode 7 can have a different configuration from that of the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0034] Fig. 5 is a line drawn along the dotted line BB in Fig. 3 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 and is a cross-sectional view of the IGBT region 10. Fig. 5 differs from that in Fig. 4, taken along a dashed line AA in that the source layers 13 of the (n+) type arranged on the side of the first main surface of the semiconductor substrate so as to be in contact with the gates 11 of active trenches are shown in the cross section taken along the dashed line BB of Fig. 5 are not apparent. In other words, as in Fig. 3, the n+-type source layers 13 are selectively arranged on the first main surface side of the p-type base layers. The p-type base layers referred to here are the p-type base layers, which collectively refer to the p-type base layer 15 and the p+-type contact layer 14.

[0035] Fig. 6 is a partially enlarged plan view illustrating the configuration of the diode region of the semiconductor device according to the first embodiment, and illustrates the configuration of the diode region of the semiconductor device which is an RC-IGBT. Fig. 7 and Fig. 8 are cross-sectional views illustrating the configurations of the diode region of the semiconductor device according to the first embodiment, and illustrate the configurations of the diode region of the semiconductor device which is an RC-IGBT. Fig. Figure 6 illustrates, on an enlarged scale, the area enclosed by a dashed line 83 in the Fig. 1 illustrated semiconductor device 100 or the semiconductor device 101. Fig. 7 is one along a in Fig. 6 illustrates a cross-sectional view of the semiconductor device 100 taken along dashed line CC. Fig. 8 is one along a in Fig. 6 illustrates a cross-sectional view of the semiconductor device 100 taken along dashed line DD.

[0036] Diode trench gates 21 extend from one end of the diode region 20, which is a cell region, along the first main surface of the semiconductor device 100 or the semiconductor device 101 to the other end opposite thereto. Each of the diode trench gates 21 has a diode trench electrode 21a in a trench formed in the semiconductor substrate of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a faces the n-type drift layer 1 via the diode trench insulating film 21b. A p+-type contact layer 24 and a p-type anode layer 25 are disposed between two adjacent diode trench gates 21. The (p+)-type contact layer 24 and the p-type anode layer 25 are alternately arranged in the longitudinal direction of the gate 21 of diode trenches.

[0037] Fig. 7 is a line drawn along a dotted line CC in Fig. 6 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 and is a cross-sectional view of the diode region 20. The semiconductor device 100 or the semiconductor device 101 has the (n-)-type drift layer 1 formed by a semiconductor substrate in the diode region 20 as well as in the IGBT region 10. The (n-)-type drift layer 1 in the diode region 20 and the (n-)-type drift layer 1 in the IGBT region 10 are continuously integrally formed and are formed by the same semiconductor substrate. Fig. 7, the semiconductor substrate extends from the contact layer 24 of the (p+)-type to a cathode layer 26 of the (n+)-type. In Fig. 7, the upper end of the p+-type contact layer 24 on the sheet is referred to as the first main surface of the semiconductor substrate, and the lower end of the n+-type cathode layer 26 on the sheet is referred to as the second main surface of the semiconductor substrate. The first main surface in the diode region 20 and the first main surface in the IGBT region 10 are the same surface, and the second main surface in the diode region 20 and the second main surface in the IGBT region 10 are the same surface.

[0038] As in Fig. As illustrated in Fig. 7, as in the IGBT region 10, in the diode region 20, the n-type carrier accumulation layer 2 is disposed on the first main surface side of the (n-)-type drift layer 1, and the n-type buffer layer 3 is disposed on the second main surface side of the (n-)-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. The n-type carrier accumulation layer 2 may not necessarily be provided in the IGBT region 10 and the diode region 20. Even if the n-type carrier accumulation layer 2 is arranged in the IGBT region 10, it is possible not to provide the n-type carrier accumulation layer 2 in the diode region 20.As with the IGBT region 10, the (n-)-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be referred to collectively as a drift layer.

[0039] On the first main surface side of the n-type carrier accumulation layer 2, the p-type anode layer 25 is disposed. The p-type anode layer 25 is provided between the n-type drift layer 1 and the first main surface. In the p-type anode layer 25, the concentration of the p-type impurity may be the same as that of the p-type base layer 15 in the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. The p-type anode layer 25 and the p-type base layer 15 may be formed at the same depth in the direction toward the second main surface.The concentration of the p-type impurity in the p-type anode layer 25 can be set to be lower than the concentration of the p-type impurity in the p-type base layer 15 in the IGBT region 10, thereby reducing the amount of electron holes flowing into the diode region 20 at the time of diode operation. By reducing the amount of electron holes flowing in at the time of diode operation, the recovery current at the time of diode operation can be reduced.

[0040] On the first main surface side of the p-type anode layer 25, the p+-type contact layer 24 is disposed. The concentration of the p-type impurity in the p+-type contact layer 24 may be the same as or different from the concentration of the p-type impurity in the p+-type contact layer 14 in the IGBT region 10. The p+-type contact layer 24 forms the first main surface of the semiconductor substrate. The p+-type contact layer 24 is a region where the concentration of the p-type impurity is higher than that of the p-type anode layer 25. When the p+-type contact layer 24 and the p-type anode layer 25 need to be distinguished from each other, the p+-type contact layer 24 and the p-type anode layer 25 may be referred to individually. The (p+)-type contact layer 24 and the p-type anode layer 25 may be referred to together as the p-type anode layer.

[0041] In the diode region 20, the n+-type cathode layer 26 is provided on the second main surface side of the n-type buffer layer 3. The n+-type cathode layer 26 is disposed between the n-type drift layer 1 and the second main surface. The n+-type cathode layer 26 is disposed in a part or the entirety of the diode region 20. The n+-type cathode layer 26 forms the second main surface of the semiconductor substrate. Although not shown, as described above, a p-type impurity may be further selectively implanted into a region where the n+-type cathode layer 26 is formed, and the p-type cathode layer may be disposed by using a part of the region where the n+-type cathode layer 26 is formed as a p-type semiconductor.

[0042] As in Fig. As illustrated in Figure 7, trenches are formed in the diode region 20 of the semiconductor device 100 or the semiconductor device 101, passing through the p-type anode layer 25 from the first main surface of the semiconductor substrate and reaching the n-type drift layer 1. Diode trench gates 21 are formed by disposing diode trench electrodes 21a in the trenches of the diode region 20 via diode trench insulating films 21b. The diode trench electrodes 21a face the n-type drift layer 1 via the diode trench insulating films 21b.

[0043] As in Fig. As illustrated in Figure 7, the barrier metal 5 is disposed on the electrodes 21a of diode trenches and the p+-type contact layer 24. The barrier metal 5 is in ohmic contact with the electrodes 21a of diode trenches and the p+-type contact layer 24 and is electrically connected to the electrodes of diode trenches and the p+-type contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. The emitter electrode 6 is disposed on the barrier metal 5. The emitter electrode 6 disposed in the diode region 20 is formed to be continuous with the emitter electrode 6 disposed in the IGBT region 10. As in the IGBT region 10, the electrodes 21a of diode trenches and the (p+) type contact layer 24 and the emitter electrode 6 can be brought into ohmic contact with each other without providing the barrier metal 5.

[0044] In Fig. 7 illustrates a configuration in which the contact holes 19 are arranged on the diode trench electrodes 21a of the diode trenches 21 without providing the interlayer insulating film 4; however, the interlayer insulating film 4 may be formed on the diode trench electrodes 21a of the diode trenches 21. When the interlayer insulating film 4 is formed on the diode trench electrodes 21a of the diode trenches 21, the emitter electrode 6 and the diode trench electrodes 21a only need to be electrically connected at a different cross section.

[0045] The collector electrode 7 is arranged on the second main surface side of the n+-type cathode layer 26. As with the emitter electrode 6, the collector electrode 7 in the diode region 20 is formed so that it is continuous with the collector electrode 7 arranged in the IGBT region 10. The collector electrode 7 is in ohmic contact with the n+-type cathode layer 26 and is electrically connected to the n+-type cathode layer 26.

[0046] Fig. 8 is a line drawn along a dashed line DD in Fig. 6 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 and is a cross-sectional view of the diode region 20. Fig. 8 differs from that in Fig. 7, taken along a dashed line CC, in that the (p+)-type contact layer 24 is not disposed between the p-type anode layer 25 and the barrier metal 5, and that the p-type anode layer 25 forms the first main surface of the semiconductor substrate. In other words, the Fig. 7 is selectively arranged on the first main surface side of the p-type anode layer 25.

[0047] Fig. 9 is a partially enlarged cross-sectional view illustrating the configuration of the boundary between the IGBT region and the diode region of the semiconductor device according to the first embodiment, and illustrates the configuration of the boundary between the IGBT region and the diode region of the semiconductor device which is an RC-IGBT. Fig. Figure 9 illustrates an enlarged view of an area surrounded by a dashed line 84 in the Fig. 1 illustrated semiconductor device 100 or the semiconductor device 101. As in Fig. 9, the IGBT region 10 and the diode region 20 are arranged adjacent to each other, and a gate 51 of a boundary trench is arranged between the gate 11 of an active trench in the IGBT region 10 and the gate 21 of a dummy trench in the diode region 20.

[0048] In the region surrounded by the dashed line 84 in the semiconductor device 100, the gate 51 of a boundary trench extends in the left-right direction on the sheet, which is the longitudinal direction of the gate 11 of an active trench in the IGBT region 10 and the gate 21 of a dummy trench in the diode region 20, and the longitudinal direction of the gate 11 of an active trench in the IGBT region 10 and the gate 21 of a dummy trench in the diode region 20 is the longitudinal direction of the gate 51 of a boundary trench.Meanwhile, in the area surrounded by the dashed line 84 in the semiconductor device 101, the gate 51 of a boundary trench extends in the left-right direction on the sheet, which is the longitudinal direction of the gate 11 of an active trench in the IGBT region 10 and the gate 21 of a dummy trench in the diode region 20, and the longitudinal direction of the gate 11 of an active trench in the IGBT region 10 and the gate 21 of a dummy trench in the diode region 20 is the longitudinal direction of the gate 51 of a boundary trench.

[0049] The barrier trench gate 51 includes a barrier trench gate electrode 51a in a trench formed in the semiconductor substrate via a gate trench insulating film 51b. On one side of the barrier trench gate 51 in the width direction, in other words, the IGBT region 10 side, n+-type source layers 13 are arranged to contact the gate trench insulating film 51b. On the other side of the barrier trench gate 51 in the width direction, in other words, the diode region 20 side, p-type anode layers 25 are arranged to contact the gate trench insulating film 51b. At a location in the IGBT region 10 between the gate 51 of a boundary trench and the gate 11 of an active trench, source layers 13 of the (n+) type are provided so as to alternate with the contact layers 14 of the (p+) type along the extension direction of the gate 51 of a boundary trench.At a location in the diode region 20 between the gate 51 of a boundary trench and the diode trench 21, p-type anode layers 25 are provided so as to alternate with (p+)-type contact layers 24 along the extension direction of the gate 51 of a boundary trench.

[0050] Fig. 10 is a cross-sectional view illustrating the configuration of the boundary between the IGBT region and the diode region of the semiconductor device according to the first embodiment, and illustrates a boundary taken along a dashed line GG in Fig. 9. The boundary trench gate 51 includes the boundary trench gate electrode 51a, the gate trench insulating film 51b, a bottom surface 51c, and a sidewall 51d. The boundary trench gate 51 includes the boundary trench gate bottom surface 51c and the boundary trench gate sidewall 51d. The boundary trench gate sidewall 51d is formed to connect the bottom surface 51c and the first main surface.

[0051] An active trench of the active trench gate 11 includes an active trench gate bottom surface 11c and an active trench gate sidewall 11d. The active trench gate sidewall 11d is formed to connect the active trench gate bottom surface 11c and the first main surface. A dummy trench of the dummy trench gate 21 includes a dummy trench gate bottom surface 21c and a dummy trench gate sidewall 21d. The dummy trench gate sidewall 21d is formed to connect the dummy trench gate bottom surface 21c and the first main surface.

[0052] As in Fig. As illustrated in FIG. 10, the boundary between the IGBT region 10 and the diode region 20 is a position where the gate 51 of a boundary trench is disposed with the bottom surface 51c deeper than the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side and the bottom surfaces 21c of the gates of dummy trenches on the diode region 20 side. The p-type collector layer 16 disposed on the second main surface side of the IGBT region 10 is disposed to be in contact with the (n+)-type cathode layer 26 at the boundary between the IGBT region 10 and the diode region 20.The p-type collector layer 16 and the n+-type cathode layer 26 have manufacturing defects, and therefore only one or more sets of the p-type collector layer 16 and the n+-type cathode layer 26 need be arranged, wherein a part of the p-type collector layer 16 and a part of the n+-type cathode layer 26 are in contact with each other at the boundary between the IGBT region 10 and the diode region 20.

[0053] Fig. 11 is a cross-sectional view illustrating the configuration of the boundary between the IGBT region and the diode region of the semiconductor device according to the first embodiment, and illustrates a boundary taken along a dashed line HH in Fig. 9 taken cross-sectional view. Fig. 11 is from the Fig. 10 illustrated cross-sectional view taken along a dashed line GG in that the (n+)-type source layer 13 arranged on the side of the first main surface of the semiconductor substrate in the cross-section taken along the dashed line HH of Fig. 11 is not visible and is replaced by the (p+)-type contact layer 14, and insofar as the (p+)-type contact layer 24 is arranged between the p-type anode layer 25 and the barrier metal 5 and forms the first main surface of the semiconductor substrate.

[0054] Next, a manufacturing method of the semiconductor device according to the first embodiment will be described. In the description of the manufacturing method below, the manufacturing method of the cell region will be described, and the manufacturing methods of the termination region 30, the pad region 40, and the like, which are formed by freely selected structures, will be omitted.

[0055] Fig. 12 to Fig. 17 illustrates the manufacturing method of the semiconductor device according to the first embodiment, and illustrates the manufacturing method of the semiconductor device which is an RC-IGBT. Fig. 12 to Fig. 15 illustrate a step of forming the front surface side of the semiconductor device 100 or the semiconductor device 101, and Fig. 16 and Fig. 17 illustrates a step of forming the back surface side of the semiconductor device 100 or the semiconductor device 101.

[0056] As in Fig. As illustrated in Figure 12A, first, the semiconductor substrate forming the n-type drift layer 1 is prepared. For the semiconductor substrate, for example, a so-called FZ wafer manufactured by a floating zone (FZ) method or a so-called MCZ wafer manufactured by a Czochralski applied magnetic field (MCZ) method may be used, and the semiconductor substrate may be an n-type wafer containing an n-type impurity. The concentration of the n-type impurity contained in the semiconductor substrate is selected as appropriate according to the withstand voltage of the manufactured semiconductor device. For example, in a semiconductor device whose withstand voltage is 1200 V, the concentration of the n-type impurity is adjusted so that the resistivity of the n-type drift layer 1 forming the semiconductor substrate ranges from about 40 to 120 Ω cm. As shown in Fig. 12A, in the step of preparing the semiconductor substrate, the entire semiconductor substrate is the (n-)-type drift layer 1; however, the semiconductor device 100 or the semiconductor device 101 is manufactured by forming a p-type or n-type semiconductor layer by implanting p-type or n-type impurity ions from the first main surface side or the second main surface side of the semiconductor substrate as above, and then diffusing the p-type or n-type impurity ions in the semiconductor substrate by heat treatment and the like.

[0057] As in Fig. As illustrated in Fig. 12A, the semiconductor substrate forming the (n-)-type drift layer 1 includes a region serving as the IGBT region 10 and the diode region 20. Although not shown, a region serving as the termination region 30 is included around the region serving as the IGBT region 10 and the diode region 20. The manufacturing method of the configuration of the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101 will be mainly described below, but the termination region 30 of the semiconductor device 100 or the semiconductor device 101 can be manufactured by a publicly known manufacturing method.For example, when an FLR having a p-type termination well layer in the termination region 30 is formed as the withstand voltage maintaining structure, the FLR may be formed by implanting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101, or may be formed by implanting p-type impurity ions simultaneously when implanting p-type impurity ions in the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0058] As in Fig. Next, as illustrated in FIG. 12B, the n-type carrier accumulation layer 2 is formed by implanting an n-type impurity such as phosphorus (P) from the second main surface side of the semiconductor substrate. The p-type base layer 15 and the p-type anode layer 25 are formed by implanting a p-type impurity such as boron (B) from the first main surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by diffusing impurity ions through heat treatment after implanting impurity ions in the semiconductor substrate.The ions of the n-type impurity and the p-type impurity are implanted after a mask process is applied to the first main surface of the semiconductor substrate, and are therefore selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type termination well layer in the termination region 30. The mask process refers to a process of forming a mask on the semiconductor substrate by applying a resist to the semiconductor substrate and forming openings in a predetermined region of the resist using photolithography and lithography, respectively, to perform etching and ion implantation in predetermined regions of the semiconductor substrate via the openings.

[0059] The p-type base layer 15 and the p-type anode layer 25 can be formed by simultaneously implanting p-type impurity ions therein. In this case, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 are the same, and the same configurations are obtained. By configuring as above, ion implantation can be performed simultaneously, and therefore, the productivity of the semiconductor device can be improved. The depths of the p-type base layer 15 and the p-type anode layer 25 are the same, and therefore, the concentration of an electric field can be weakened and a decrease in withstand voltage can be suppressed.By implanting ions of a p-type impurity into the p-type base layer 15 and the p-type anode layer 25 separately through the mask process, the depths and the p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 can be made different from each other.

[0060] As in Fig. Next, as illustrated in FIG. 13A, the n+-type source layer 13 is formed by selectively implanting an n-type impurity on the first main surface side of the p-type base layer 15 in the IGBT region 10 through the mask process. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P).

[0061] As in Fig. Next, as illustrated in Figure 13B, trenches 8 are formed, which penetrate through the p-type base layer 15 and the p-type anode layer 25 from the first main surface side of the semiconductor substrate and reach the n-type drift layer 1. In the IGBT region 10, the sidewalls of the trenches 8, which penetrate through the n+-type source layer 13, form a part of the n+-type source layer 13. The trenches 8 can be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, then forming openings in portions of the oxide film in which the trenches 8 are to be formed by the mask process, and etching the semiconductor substrate using the oxide film in which the openings are formed as a mask. Fig. 13B, the pitches or center-to-center distances between the trenches 8 in the IGBT region 10 and the diode region 20 are the same; however, the center-to-center distances between the trenches 8 may differ between the IGBT region 10 and the diode region 20. The structure or pattern of the center-to-center distances between the trenches 8 in plan view may be changed as necessary according to the mask structure of the mask process.

[0062] Through the mask process, the center-to-center distance of trenches may be changed so that the interval between the plurality of gates 21 of dummy trenches in the diode region 20 is changed to be wider than the interval between the plurality of gates 11 of active trenches in the IGBT region 10, or the center-to-center distance of trenches may be changed so that the interval between the plurality of gates 21 of dummy trenches in the diode region 20 becomes narrower than the interval between the plurality of gates 11 of active trenches in the IGBT region 10.

[0063] As in Fig. As illustrated in Fig. 13B, by performing etching twice, a trench 8a positioned in the boundary between the IGBT region 10 and the diode region 20 can be a trench whose bottom surface is deeper than the trenches 8 in the IGBT region 10 and the diode region 20. The trench 8a is a boundary trench that forms the gate 51 of a boundary trench. A deep trench can be formed by etching by making the width of the trench 8a wide through the mask process. The etching rate at the time of trench etching changes according to the opening width of the trench. Therefore, a deep trench can be formed by changing the opening width for only the trench to be deeper in a direction in which the etching rate becomes faster. The structure of the trench widths in plan view can be changed as necessary according to the mask structure of the mask process.By increasing the center-to-center distance of trenches as with the trench width, a deep trench can be partially formed without adding a step.

[0064] In the description below, ditch 8a, which is the boundary ditch, and the other ditches 8 may not be distinguished from each other, and the description of the ditches 8 may include ditch 8a.

[0065] As in Fig. Next, as illustrated in Fig. 14A, the semiconductor substrate is heated in an oxygen-containing atmosphere to thereby form an oxide film 9 on inner walls of the trenches 8 and 8a and the first main surface of the semiconductor substrate. The inner walls of the trenches 8 and 8a have bottom surfaces and sidewalls, and are, for example, the bottom surface 51c and sidewall 51d of the trench 8a, which is the boundary trench, the bottom surface 11c and sidewall 11d of the active trench on the IGBT side, and the bottom surface 21c and sidewall 21d of the dummy trench on the diode side. Of the oxide film 9 formed on the inner walls of the trenches 8 and 8a, the oxide film 9 formed in the trenches 8 in the IGBT region 10 serves as the insulating films 11b of the gate trenches of the gates 11 of the active trenches and the insulating films 12b of the dummy trenches of the gates 12 of the dummy trenches. The oxide film 9 formed in the trenches 8 in the diode region 20 serves as the insulating films 21b of the diode trenches.The oxide film 9 formed in the trench 8a, which is the boundary trench, serves as the boundary trench insulating film 51b of the boundary trench gate 51. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a later step.

[0066] As in Fig. Next, as illustrated in Fig. 14B, polysilicon doped with an n-type or p-type impurity is deposited by chemical vapor deposition (CVD) and the like in the trenches 8 and 8a having inner walls on which the oxide film 9 is formed, to thereby form the electrodes 11a of gate trenches, the electrodes 12a of dummy trenches, the electrodes 21a of diode trenches, and the gate electrode 51a of a boundary trench.

[0067] As in Fig. Next, as illustrated in FIG. 15A, after the interlayer insulating films 4 are formed on the gate trench electrodes 11a of the gates 11 of active trenches in the IGBT region 10, the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 may be SiO2, for example. Contact holes are then formed in the deposited interlayer insulating film 4 by the mask process. The contact holes are formed on the n+-type source layers 13, the p+-type contact layer 14, the p+-type contact layers 24, the dummy trench electrodes 12a, the diode trench electrodes 21a, and the gate electrode 51a of a boundary trench.

[0068] As in Fig. Next, as illustrated in Fig. 15B, the barrier metal 5 is formed on the interlayer insulating film 4 and the first main surface of the semiconductor substrate, and the emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by forming a film of titanium nitride using physical vapor deposition (PVD) or CVD.

[0069] The emitter electrode 6 can be formed, for example, by depositing an aluminum-silicon alloy (Al-Si alloy) on the barrier metal 5 using PVD such as sputtering or vapor deposition. The emitter electrode 6 can be obtained by further forming a nickel alloy (Ni alloy) on the formed aluminum-silicon alloy by electroless plating or electroplating. When the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6. Therefore, the heat capacity of the emitter electrode 6 can be increased and its heat resistance can be improved.Further, when a nickel alloy is formed by the plating process after forming the emitter electrode 6 formed by an aluminum-silicon alloy by PVD, the plating process for forming the nickel alloy may be performed after performing the processing of the second main surface side of the semiconductor substrate.

[0070] As in Fig. Next, as illustrated in Figure 16A, the second main surface side of the semiconductor substrate is ground, and the semiconductor substrate is thinned to a predetermined design thickness. The thickness of the semiconductor substrate after grinding may range from 80 µm to 200 µm, for example.

[0071] As in Fig. Next, as illustrated in FIG. 16B, the n-type buffer layer 3 is formed by implanting an n-type impurity from the second main surface side of the semiconductor substrate. The p-type collector layer 16 is further formed by implanting a p-type impurity from the second main surface side of the semiconductor substrate. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30, or may be formed in only the IGBT region 10 or the diode region 20.

[0072] The n-type buffer layer 3 can be formed, for example, by implanting phosphorus (P-) ions. The n-type buffer layer 3 can be formed by implanting protons (H+). The n-type buffer layer 3 can also be formed by implanting both protons and phosphorus. Protons can be implanted into a deep location from the second main surface of the semiconductor substrate with relatively low acceleration energy. By changing the acceleration energy, the depth at which the protons are implanted can be changed relatively easily.Therefore, when the n-type buffer layer 3 is formed by protons, the n-type buffer layer 3, which is wider in the thickness direction of the semiconductor substrate compared with a case where the n-type buffer layer 3 is formed by phosphorus, can be formed by performing the implantation a plurality of times while changing the acceleration energy.

[0073] The activation rate of phosphorus as the n-type impurity can be higher than that of protons. Therefore, even for the semiconductor substrate that is thinned, the punch-through of the depletion layer can be more reliably suppressed by forming the n-type buffer layer 3 using phosphorus. To further thin the semiconductor substrate, it is preferable that the n-type buffer layer 3 be formed by implanting both protons and phosphorus. In this case, protons are implanted at a position deeper than phosphorus from the second main surface.

[0074] The p-type collector layer 16 can be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region serves as the termination p-type collector layer. By performing laser annealing by irradiating the second main surface after ion implantation with a laser beam from the second main surface side of the semiconductor substrate, the implanted boron is activated, and the p-type collector layer 16 is formed. At this time, phosphorus for the n-type buffer layer 3, which is implanted at a position relatively shallow from the second main surface of the semiconductor substrate, is simultaneously activated. Meanwhile, protons are activated at a relatively low annealing temperature, such as a temperature of 380°C to 420°C.Therefore, care must be taken to ensure that the entire semiconductor substrate does not reach a temperature higher than 380°C to 420°C in any step other than the proton activation step after the protons are implanted. It is possible to raise the temperature of only a location near the second main surface of the semiconductor substrate to a high temperature through laser annealing, and therefore, laser annealing can be used to activate the n-type impurity and the p-type impurity even after the protons are implanted.

[0075] As in Fig. 17A, the n+-type cathode layer 26 is next formed on the diode region 20. The n+-type cathode layer 26 can be formed, for example, by implanting phosphorus (P). As shown in Fig. As illustrated in Figure 17A, phosphorus is selectively implanted from the second main surface side by the mask process so that the boundary between the p-type collector layer 16 and the (n+)-type cathode layer 26 is established at the position of the boundary between the IGBT region 10 and the diode region 20. The implantation amount of the n-type impurity for forming the (n+)-type cathode layer 26 may be larger than the implantation amount of the p-type impurity for forming the p-type collector layer 16. Fig. 17A, the depths of the p-type collector layer 16 and the n+-type cathode layer 26 are illustrated as being equal from the second main surface; however, the depth of the n+-type cathode layer 26 may be equal to or greater than the depth of the p-type collector layer 16. The region where the n+-type cathode layer 26 is formed must become the n-type semiconductor by implanting an n-type impurity in the region where a p-type impurity is implanted, and therefore, the concentration of the implanted p-type impurity is caused to be higher than the concentration of the n-type impurity in all the regions where the n+-type cathode layer 26 is formed.

[0076] As in Fig. Next, as illustrated in FIG. 17B, the collector electrode 7 is formed on the second main surface side of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the IGBT region 10, the diode region 20, and the second main surface termination region 30. The collector electrode 7 may be formed over the entire surface of the second main surface of the n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum-silicon alloy (Al-Si alloy), titanium (Ti), and the like by means of PVD such as sputtering and vapor deposition, or may be formed by laminating a variety of metals such as an aluminum-silicon alloy, titanium, nickel, or gold.The collector electrode 7 can be obtained by further forming a metal film by electroless plating or electroplating on a metal film formed by PVD.

[0077] The semiconductor device 100 or the semiconductor device 101 is manufactured through the steps as above. A plurality of the semiconductor devices 100 or the semiconductor devices 101 are manufactured in a matrix form in an n-type wafer, and therefore, the semiconductor devices 100 or the semiconductor devices 101 are completed by cutting and dividing the n-type wafer into individual semiconductor devices 100 or semiconductor devices 101 by dicing with a laser or dicing with a knife.

[0078] Next, the operation of the semiconductor device according to the first embodiment will be described.

[0079] First, a semiconductor device of a comparative example will be described. Then, the semiconductor device according to the first embodiment will be described. Fig. 18 schematically illustrates the movement of electron holes at the time of diode operation of the semiconductor device of the comparative example. The semiconductor device of the comparative example differs from the semiconductor device 100 or the semiconductor device 101 of the first embodiment in that a gate of a boundary trench having a bottom surface deeper than the bottom surfaces of the gates 11 of active trenches on the IGBT region 10 side and the bottom surfaces of the gates 21 of dummy trenches on the diode region 20 side is not provided in the semiconductor device of the comparative example.

[0080] The diode operation of the semiconductor device of the comparative example will be described. During diode operation, a positive voltage is applied to the emitter electrode 6 compared to the collector electrode 7. When the positive voltage is applied, electron holes h flow from the anode layer 25 and the base layer 15 into the drift layer 1, and the inflowing electron holes h move toward the cathode layer 26. In addition to the electron holes h from the anode layer 25, the electron holes h from the IGBT region 10 also flow into the diode region 20 near the boundary with the IGBT region 10. As a result, the diode region 20 near the boundary with the IGBT region 10 is in a state where the density of electron holes h is higher than in the diode region 20 far from the IGBT region 10. At the time of diode operation, a reverse current flows from the emitter electrode 6 toward the collector electrode 7.

[0081] A recovery operation of the semiconductor device of the comparative example will be described. Fig. Figure 19 schematically illustrates the movement of the electron holes at the time of recovery operation of the semiconductor device of the comparative example. At the time of recovery operation, a negative voltage is applied to the emitter electrode 6 compared to the collector electrode 7. The electron holes h, which were moving toward the cathode layer 26 at the time of diode operation, move toward the anode layer 25 while changing the direction of movement. At the time of recovery operation, the electron holes h flow out of the semiconductor device via the anode layer 25 and the emitter electrode 6.

[0082] Compared with the anode layer 25 in the diode region 20 far from the IGBT region 10, a larger number of electron holes h pass through the anode layer 25 in the diode region 20 near the boundary with the IGBT region 10, where the density of electron holes h is high during diode operation. Some of the electron holes h present in the IGBT region 10 flow out of the semiconductor device via the base layer 15 and the emitter electrode 6. During recovery operation, the recovery current flows from the collector electrode 7 toward the emitter electrode 6.

[0083] Next, with reference to Fig. 20 and Fig. 21, the operation of the semiconductor device according to the first embodiment is described. Fig. 20 schematically illustrates an effect of suppressing the inflow of electron holes of the semiconductor device according to the first embodiment, and schematically illustrates the movement of electron holes at the time of diode operation. Fig. 21 schematically illustrates the effect of suppressing the inflow of electron holes of the semiconductor device according to the first embodiment, and schematically illustrates the movement of the electron holes at the time of the recovery operation.

[0084] The semiconductor device according to the first embodiment suppresses the electron holes h flowing from the IGBT region 10 into the diode region 20. As shown in Fig. 20, at the time of diode operation, the electron holes h flow from the p-type base layer 15 into the drift layer 1 in the diode region 20. At this time, by disposing the gate 51 of a boundary trench having a bottom surface deeper than the bottom surfaces of the gates 11 of active trenches on the IGBT region 10 side and the bottom surfaces of the gates 21 of dummy trenches on the diode region 20 side at the boundary between the IGBT region 10 and the diode region 20, the moving distance of the electron holes h from the p-type base layer 15 to the diode region 20 becomes longer, and the inflow of the electron holes h can be suppressed.

[0085] As in Fig. 21, at the time of the recovery operation, the recovery current can be suppressed and the breakdown resistance at the time of the recovery operation can be improved compared with the semiconductor device of the comparative example, wherein the gate 51 of a boundary trench having a bottom surface deeper than the bottom surfaces of the gates 11 of active trenches on the IGBT region 10 side and the bottom surfaces of the gates 21 of dummy trenches on the diode region 20 side is not provided at the boundary between the IGBT region 10 and the diode region 20.

[0086] In the semiconductor device according to the first embodiment, the bottom surface 51c of the gate of a boundary trench has a bottom surface at a deeper position than the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side or the bottom surfaces 21c of the gates of dummy trenches on the diode region 20 side. By configuring as above, the inflow of electron holes from the IGBT region 10 to the diode region 20 can be suppressed and the recovery current of a diode can be reduced without disposing an inactive region between the IGBT region 10 and the diode region 20.

[0087] The gate electrode 51a of a boundary trench of the gate 51 of a boundary trench may be electrically connected to the gate pad 41c or may be electrically connected to the emitter electrode arranged on the first main surface of the semiconductor device 100 or the semiconductor device 101. Second embodiment

[0088] The configuration of a semiconductor device according to a second embodiment will be described with reference to Fig. 22 described. Fig. Fig. 22 is a cross-sectional view illustrating the semiconductor device according to the second embodiment. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0089] As in Fig. 22, the bottom surface 51c of the gate of a boundary trench and the bottom surfaces 21c of the gates of dummy trenches on the diode region 20 side are positioned at the same depth, and the bottom surface 51c of the gate of a boundary trench and the bottom surfaces 21c of the gates of dummy trenches on the diode region 20 side are deeper than the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side. By configuring as above, the concentration of an electric field in the drift layer near the bottom surfaces 21c of the gates of dummy trenches on the diode region 20 side can be alleviated, and the decrease in withstand voltage can be suppressed.

[0090] Therefore, in the second embodiment, since the bottom surface 51c of the gate of a boundary trench and the bottom surfaces 21c of the gates of dummy trenches on the diode side are arranged at the same depth, and the bottom surface 51c of the gate of a boundary trench and the bottom surfaces 21c of the gates of dummy trenches on the diode side are deeper than the bottom surfaces 11c of the gates of active trenches on the IGBT side, the concentration of an electric field can be alleviated and the decrease in withstand voltage can be suppressed, while the recovery current is suppressed and the breakdown resistance at the time of recovery operation is improved.

[0091] The trench width of the gate 51 of a boundary trench and the trench widths of the gates 21 of dummy trenches on the diode side can be wider than the trench widths of the gates 11 of active trenches on the IGBT side. By configuring as described above, deep trenches can be partially formed without adding a step. Third embodiment

[0092] The configuration of a semiconductor device according to the third embodiment will be described with reference to Fig. 23 described. Fig. 23 is a cross-sectional view illustrating the semiconductor device according to the third embodiment. In the third embodiment, the same components as those described in the first embodiment and the second embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0093] As in Fig. 23, the bottom surface 51c of the gate of a boundary trench is positioned at the same depth as the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side, and the bottom surface 51c of the gate of a boundary trench and the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side are deeper than the bottom surfaces 21c of the gates of dummy trenches on the diode region 20 side. By configuring as above, the concentration of an electric field in the drift layer near the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side can be alleviated, and the decrease in withstand voltage can be suppressed. The bottom surface 51c of the gate of a boundary trench and the bottom surfaces 11c of the gates of active trenches on the side of the IGBT region 10 are arranged at the same depth.Therefore, while the inflow of electron holes h from the p-type base layer 15 to the diode region 20 can be more suppressed, the electron holes h can be accumulated in the drift layer 1 on the IGBT region 10 side. As a result, the injection gain (IE) effect can be increased and the on-voltage can be reduced.

[0094] Therefore, in the third embodiment, the bottom surface 51c of the gate of a boundary trench and the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side are arranged at the same depth, and the bottom surface 51c of the gate of a boundary trench and the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side are deeper than the bottom surfaces 21c of the gates of dummy trenches on the diode region 20 side. As a result, the concentration of an electric field can be alleviated and the decrease in withstand voltage can be suppressed, while the recovery current is suppressed and the breakdown resistance at the time of recovery operation is improved. The bottom surface 51c of the gate of a boundary trench and the bottom surfaces 11c of the gates of active trenches on the IGBT region 10 side are positioned at the same depth.Therefore, the effect of injection gain (IE) can be increased and the on-voltage can be reduced.

[0095] The trench width of the gate 51 of a boundary trench and the trench widths of the gates 11 of active trenches on the IGBT side can be wider than the trench widths of the gates 21 of dummy trenches on the diode side. By configuring as described above, deep trenches can be partially formed without adding a step. Fourth embodiment

[0096] The configuration of a semiconductor device according to a fourth embodiment will be described with reference to Fig. 24 described. Fig. 24 is a cross-sectional view illustrating the semiconductor device according to the fourth embodiment. In the fourth embodiment, the same components as those described in the first embodiment to the third embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0097] As in Fig. 24, the interval between the gate 11 of an active trench on the IGBT region 10 side closest to the gate 51 of a barrier trench and the gate 51 of a barrier trench is narrower than the interval between the gate 21 of a dummy trench on the diode region 20 side closest to the gate 51 of a barrier trench and the gate 51 of the barrier trench. As described above, by forming the gate 51 of a barrier trench, which suppresses the inflow of electron holes from the IGBT region 10 to the diode region 20, to be close to the IGBT region 10, the flow of electron holes can be easily blocked. As a result, the distance over which the electron holes pass between the p-type base layer 15 and the cathode layer 26 can be lengthened.

[0098] Therefore, in the fourth embodiment, by providing a configuration in which the interval between the gate 11 of an active trench on the IGBT side, which is closest to the gate 51 of a barrier trench, and the gate 51 of a barrier trench is narrower than the interval between the gate 21 of a dummy trench on the diode side, which is closest to the gate 51 of a barrier trench, and the gate 51 of a barrier trench, the movement of electron holes from the p-type base layer 15 in the IGBT region 10 to the cathode layer 26 in the diode region 20 can be more suppressed. As a result, the recovery current can be suppressed, and the breakdown resistance at the time of recovery operation can be improved. Fifth embodiment

[0099] The configuration of the semiconductor device according to a fifth embodiment will be described with reference to Fig. 25 described. Fig. 25 is a cross-sectional view illustrating the semiconductor device according to the fifth embodiment. In the fifth embodiment, the same components as those described in the first embodiment to the fourth embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0100] As in Fig.As illustrated in Fig. 25, a dummy trench gate 52 on the back surface is provided so as to pass through the p-type collector layer 16 and the n+-type cathode layer 26 from the second main surface toward the first main surface. The dummy trench gate 52 on the back surface has a trench electrode 52a on the back surface in a trench formed in the semiconductor substrate via a trench insulation film 52b on the back surface. The dummy trench gate 52 on the back surface is arranged at a position opposite to the p-type collector layer 16, the n+-type cathode layer 26, and the n-type drift layer 1, at the boundary between the IGBT region 10 and the diode region 20.The back-surface dummy trench gate 52 has a back-surface trench bottom surface 52c at a position opposite to the barrier trench gate bottom surface 51c, and includes a back-surface trench sidewall 52d at a position connecting the bottom surface 52c and the second main surface. By configuring as above, the inflow of electron holes can also be suppressed by the back-surface dummy trench gate 52 in addition to the barrier trench gate 51, which suppresses the inflow of electron holes from the IGBT region 10 to the diode region 20.

[0101] Therefore, in the fifth embodiment, by providing the gate 52 of a dummy trench on the back surface in addition to the gate 51 of a boundary trench, the movement of electron holes from the p-type base layer 15 in the IGBT region 10 to the cathode layer 26 in the diode region 20 can be more suppressed. As a result, the recovery current can be suppressed and the breakdown resistance at the time of recovery operation can be improved.

[0102] According to the semiconductor device according to the present disclosure, by disposing the boundary trench having a bottom surface deeper than the bottom surface of the trench in the IGBT region and the bottom surface of the trench in the diode region between the IGBT region and the diode region adjacent to the IGBT region, the inflow of electron holes to the diode region can be suppressed and the breakdown resistance at the time of recovery operation can be improved.

Claims

[1] A semiconductor device (100) comprising: a semiconductor substrate having a drift layer (1) of a first conductivity type between a first main surface and a second main surface opposite the first main surface; and an IGBT region (10) and a diode region (20) arranged adjacent to each other in the semiconductor substrate, wherein: the IGBT area (10) has: a base layer (15) of a second conductivity type arranged in the semiconductor substrate on the side of the first main surface; a source layer (13) of the first conductivity type selectively disposed on the base layer (15) on the side of the first main surface; an active trench gate (11) including an active trench gate electrode (11a) arranged to oppose the drift layer (1) via an insulating film (11b) and to which a gate voltage is applied, in each of a plurality of active trenches formed to be aligned in a first direction along the first main surface of the semiconductor substrate and passing through the source layer (13) and the base layer (15); and a collector layer (16) of the second conductivity type arranged in the semiconductor substrate on the side of the second main surface; the diode area (20) comprises: an anode layer (25) of the second conductivity type arranged in the semiconductor substrate on the side of the first main surface; a cathode layer (26) of the first conductivity type arranged in the semiconductor substrate on the side of the second main surface; and a dummy trench gate (21) including a dummy trench gate electrode (21a) facing the drift layer (1) via an insulating film (21b) and to which the gate voltage is not applied, in each of a plurality of dummy trenches formed to be aligned in the first direction of the semiconductor substrate and passing through the anode layer (25); and the semiconductor device (100) further comprises: a boundary trench having, at a position where the IGBT region (10) and the diode region (20) are adjacent to each other in plan view, a bottom surface (51c) positioned in the drift layer (1) to be deeper than the active trench or the dummy trench, and a side wall (51d) and another side wall (51d) opposite each other and connecting the bottom surface (51c) and the first main surface; and a gate electrode (51a) of the boundary trench, which is opposite to the base layer (15), the anode layer (25) and the drift layer (1) via an insulating film (51b) of the boundary trench and is arranged from the side of one side wall (51d) to the side of the other side wall (51d) of the boundary trench over a region opposite to the drift layer (1) in the boundary trench, in which the bottom surface (51c), one side wall (51d) and the other side wall (51d) are covered with the insulating film (51b) of the boundary trench, wherein the bottom surface (51c) of the boundary trench is deeper than a bottom surface of an active trench and is at the same depth as a bottom surface of the dummy trench. [2] The semiconductor device (100) according to claim 1, wherein the collector layer (16) and the cathode layer (26) are at least partially in contact with each other at a position opposite to the bottom surface (51c). [3] The semiconductor device (100) according to claim 1 or 2, wherein the base layer (15) and the anode layer (25) are at an equal depth in a direction toward the second main surface from the first main surface. [4] The semiconductor device (100) according to any one of claims 1 to 3, further comprising, at a position where a depth from the first main surface is deeper than the base layer (15), a carrier accumulation layer (2) of the first conductivity type opposed to the base layer (15). [5] A semiconductor device (100), comprising: a semiconductor substrate having a drift layer (1) of a first conductivity type between a first main surface and a second main surface opposite the first main surface; and an IGBT region (10) and a diode region (20) arranged adjacent to each other in the semiconductor substrate, wherein: the IGBT area (10) has: a base layer (15) of a second conductivity type arranged in the semiconductor substrate on the side of the first main surface; a source layer (13) of the first conductivity type selectively disposed on the base layer (15) on the side of the first main surface; an active trench gate (11) including an active trench gate electrode (11a) disposed to oppose the drift layer (1) via an insulating film (11b) and to which a gate voltage is applied, in each of a plurality of active trenches formed to be aligned in a first direction along the first main surface of the semiconductor substrate and to pass through the source layer (13) and the base layer (15); and a second conductivity type collector layer (16) disposed in the semiconductor substrate on the second main surface side; the diode area (20) comprises: an anode layer (25) of the second conductivity type arranged in the semiconductor substrate on the side of the first main surface; a cathode layer (26) of the first conductivity type arranged in the semiconductor substrate on the side of the second main surface; and a dummy trench gate (21) including a dummy trench gate electrode (21a) facing the drift layer (1) via an insulating film (21b) and to which the gate voltage is not applied, in each of a plurality of dummy trenches formed to be aligned in the first direction of the semiconductor substrate and passing through the anode layer (25); and the semiconductor device (100) further comprises: a boundary trench having, at a position where the IGBT region (10) and the diode region (20) are adjacent to each other in plan view, a bottom surface (51c) positioned in the drift layer (1) to be deeper than the active trench or the dummy trench, and a side wall (51d) and another side wall (51d) opposite each other and connecting the bottom surface (51c) and the first main surface; and a gate electrode (51a) of the boundary trench, which is opposite to the base layer (15), the anode layer (25) and the drift layer (1) via an insulating film (51b) of the boundary trench and is arranged from the side of one side wall (51d) to the side of the other side wall (51d) of the boundary trench over a region opposite to the drift layer (1), in the boundary trench in which the bottom surface (51c), one side wall (51d) and the other side wall (51d) are covered with the insulating film (51b) of the boundary trench, wherein: the boundary trench is positioned between the dummy trench and the active trench; and an interval between the boundary ditch and the active ditch is narrower than an interval between the boundary ditch and the dummy ditch. [6] The semiconductor device (100) according to any one of claims 1 to 5, wherein a trench width of the boundary trench and a trench width of the active trench are wider than a trench width of the dummy trench. [7] The semiconductor device (100) according to any one of claims 1 to 5, wherein a trench width of the boundary trench and a trench width of the dummy trench are wider than a trench width of the active region. [8] The semiconductor device (100) according to any one of claims 1 to 7, further comprising a back surface dummy trench comprising: a back surface dummy trench bottom surface (52c) at a position opposite to the boundary trench bottom surface (51c); and a back surface dummy trench side wall (52d) connecting the back surface dummy trench bottom surface (52c) and the second main surface, the back surface dummy trench facing the collector layer (16), the cathode layer (26), and the drift layer (1). [9] A semiconductor device (100) according to any one of claims 1 to 8, wherein: a plurality of dummy trenches and active trenches are arranged; and an interval between the plurality of dummy trenches is wider than an interval between the plurality of active trenches. [10] A semiconductor device (100) according to any one of claims 1 to 8, wherein: a plurality of dummy trenches and active trenches are arranged; and an interval between the plurality of active trenches is wider than an interval between the plurality of dummy trenches.

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