Semiconductor devices and methods for their manufacture

Abstract

Semiconductor device comprising: a first active region located on a first side of a GAA-FET device extending along a first lateral direction; a second active region located on the first side extending along the first lateral direction, wherein the first active region has a first conductivity type and the second active region has a second conductivity type opposite to the first conductivity type; and a first interconnect structure formed on a second side of the GAA-FET device opposite the first side, comprising: a first section extending along the first lateral direction and arranged vertically below the first active region; and a second section extending along a second lateral direction, wherein the first lateral direction is perpendicular to the second lateral direction.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over preliminary US application No. 63 / 142,034, filed on January 27, 2021, entitled “SYSTEMS AND METHODS FOR LAYOUT DESIGNS HAVING A BACK SIDE SIGNAL LINE”, which is hereby incorporated by reference in full and for all purposes into the present text. BACKGROUND

[0002] The integrated semiconductor (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to generations of ICs, each featuring smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be formed through a manufacturing process) has decreased. This miniaturization process generally delivers benefits by increasing production efficiency and reducing manufacturing costs.Such miniaturization has also increased the complexity of IC structures (for example, three-dimensional transistors) and processing, and to realize these advances, similar developments in IC processing and manufacturing are necessary. For example, device performance (such as the degradation of device performance due to various defects) and the manufacturing costs of field-effect transistors become a greater challenge as devices become increasingly smaller. Although the methods for addressing such a challenge have generally been adequate, they have not been entirely satisfactory. List of characters

[0003] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1 illustrates, according to some embodiments, a perspective view of a non-planar transistor device containing rear-side power lines and signal lines. Fig. Figure 2 illustrates, according to some embodiments, a layout design of a semiconductor device that includes rear-facing power lines and signal lines. Fig. 3A, Fig. 3B and Fig. Figure 3C illustrates various embodiments of the layout of a rear-side signal line according to some embodiments. Fig. Figure 4 illustrates a circuit diagram of an exemplary AOI logic circuit according to some embodiments. Fig. 5A, Fig. 5B and Fig. Figure 5C illustrates different layout levels of a cell, based on the exemplary AOI logic circuit of Fig. 4 corresponds to, according to some embodiments. Fig. 6A, Fig. 6B and Fig. Figure 6C illustrates different layout levels of another cell, which corresponds to the exemplary AOI logic circuit of Fig. 4 corresponds to, according to some embodiments. Fig. Figure 7 illustrates a layout layer of a cell corresponding to an exemplary OAI logic circuit according to some embodiments. Fig. Figure 8 illustrates a layout layer of another cell corresponding to the exemplary OAI logic circuit, according to some embodiments. Fig. Figure 9 illustrates a circuit diagram of an exemplary SDF circuit according to some embodiments. Fig. 10A, Fig. 10B, Fig. 10C and Fig. Figure 10D illustrates different layout levels of a cell, corresponding to the exemplary SDF circuit of Fig. 9 corresponds, according to some embodiments. Fig. Figure 11 illustrates a layout plane of a cell corresponding to an exemplary inverter circuit according to some embodiments. Fig. Figure 12 illustrates a layout design of a semiconductor device containing multiple backside metallization layers, according to some embodiments. Fig. Figure 13 illustrates a cross-sectional view of a reference semiconductor device according to some embodiments. Fig. Figure 14 illustrates a flowchart of a process for manufacturing a semiconductor device according to some embodiments. Fig. Figure 15 illustrates a block diagram of a system for creating an IC layout design according to some embodiments. Fig. Figure 16 illustrates a block diagram of an IC manufacturing system and an associated IC manufacturing flow according to some embodiments. Fig. Figure 17 illustrates a flowchart of an exemplary method for manufacturing a non-planar transistor device according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0006] Semiconductor IC design typically employs standard cell methodologies for designing semiconductor devices on a single chip (or wafer). These methodologies utilize standard cells as abstract representations of specific functions to integrate millions or billions of devices onto a single chip. As ICs continue to miniaturize, more and more devices are integrated onto a single chip. This miniaturization process generally delivers benefits by increasing production efficiency and reducing manufacturing costs.

[0007] In modern semiconductor device manufacturing processes, each cell can contain a specific number of semiconductor devices, such as field-effect transistors (FETs). Non-planar transistor device architectures, such as fin-based transistors (usually referred to as FinFETs), can offer higher device density and performance than planar transistors. Some more advanced non-planar transistor device architectures, such as nanolayer transistors (or nanowire transistors), can further improve performance compared to FinFETs. In contrast to the FinFET, where the channel is partially surrounded (for example, bridged) by a gate structure, the nanolayer transistor generally incorporates a gate structure that can wrap around the entire perimeter of one or more nanolayers to better control the channel current flow.For example, in the case of a FinFET and a nanolayer transistor with similar dimensions, the nanolayer transistor can drive a larger current (I. on ) and a smaller subthreshold leakage current (I off ) etc. Such a transistor, which has a gate structure that wraps around its channel, is usually referred to as a gate all-around transistor (GAA transistor) or GAA-FET.

[0008] With such a gate structure surrounding the channel, at least some of the interconnect structures, which are typically formed on the front side of the chip in the FinFET configuration, can be formed on the back side of the chip, further reducing the area (e.g., cell height) of a corresponding cell. However, in existing technologies, these interconnect structures typically extend in a one-dimensional direction and function solely as power rails (sometimes referred to as power grids or power lines). This can potentially limit the flexibility and scalability of the layout design of an integrated circuit using the GAA transistor architecture.

[0009] The present disclosure provides various embodiments of a semiconductor device (or integrated circuit) that can be represented by (or formed on the basis of) a number of standard cells. Each of the cells, as disclosed herein, comprises a number of GAA transistors, although it is understood that any of various other transistor architectures, allowing the formation of interconnect structures on the back side, can be included in each of the cells. For example, the cell can comprise a number of transistors configured in a complementary field-effect transistor (CFET) configuration, where two active regions in different conductor types (for example, n-type and p-type) are arranged on two vertically aligned planes.

[0010] According to various embodiments, some of the cells may have one or more rear interconnect structures that are permitted to extend in more than one direction. Such rear interconnect structures may be configured to carry not only power supply voltages (for example, VDD, VSS) but also signals. As disclosed herein, a rear interconnect structure configured to carry a signal other than a power supply voltage and permitted to extend in more than one direction may sometimes be referred to as a "multidimensional (MD) signal line." For example, some of the cells, which have a relatively short cell height, may have one or more of these MD signal lines. Other rear interconnect structures may still be configured to carry power supply voltages.It is possible to allow such backside interconnect structures, configured to carry power supply voltages, to extend in a single direction. As disclosed herein, a backside interconnect structure configured to carry a power supply voltage, and which is not permitted to extend in more than one direction, may sometimes be referred to as a "single-dimensional (SD) power line." For example, some of the cells, which have a relatively large cell height, may have one or more of these SD signal lines. The disclosed single-dimensional (MD) signal lines can significantly increase the flexibility in the design of an integrated circuit, and thus further extend the scalability of the integrated circuit.

[0011] Fig. Figure 1 illustrates a perspective view of an exemplary GAA-FET device 100, which includes one or more multidimensional (MD) signal lines and one or more one-dimensional (SD) power lines, according to various embodiments. It should be noted that the Fig. The GAA-FET device 100 shown is inverted, so that the MD signal line and the SD power line are arranged on the top side of a formed GAA transistor. For example, the GAA-FET device 100 has a number of semiconductor layers (for example, nanolayers, nanowires, or other nanostructures) 102 that are vertically separated from each other and can collectively function as a channel (conductor channel) of the GAA-FET device 100. The channel can extend along a first direction (for example, the X-axis). The GAA-FET device 100 has a (for example, metallic) gate structure 104 that surrounds each of the semiconductor layers 102 (for example, around one circumference of each of the semiconductor layers 102). The gate structure 104 can extend in a second direction perpendicular to the first direction (for example, the Y-axis).The GAA-FET device 100 has source / drain structures arranged on opposite sides of the gate structure 104 (along the direction of extension of the channel); one such source / drain structure 106 is shown, for example, in . Fig. Figure 1 shows that the GAA-FET device 100 has an interlayer dielectric (ILD) 108 over the source / drain structure 106 when Fig. 1 is turned upside down.

[0012] Above the back of the GAA-FET device 100 (for example, the top of Fig. Figure 1) shows an SD power line 110 and an MD signal line 112. The SD power line 110 can extend along the X-axis. The MD signal line 112 can have multiple sections, one or more of which can extend along the X-axis, and one or more of which can extend along the Y-axis. As discussed (and shown) below, the SD power line 110, configured to carry a power supply voltage (for example, VDD, VSS), can be electrically coupled to one or more source / drain structures via one or more backside vias. Such a power supply voltage is sometimes referred to as a current signal.The MD signal line 112, configured to carry a signal other than the power supply voltage, can be electrically coupled to one or more source / drain structures via one or more backside vias. Such a signal, which is not the power supply voltage, is sometimes referred to as a non-current signal.

[0013] The in Fig. The GAA-FET device shown has been simplified, and it is therefore understood that one or more features of a complete GAA-FET device in Fig. 1 may not be shown. For example, the other source / drain structure opposite the gate structure 104 as seen from the source / drain structure 110, and the ILD arranged above such a source / drain structure, a gate spacer between the gate structure 104 and the source / drain structure 106, an inner spacer between the source / drain structure 106 and each semiconductor layer 102, and the backside via structures connecting the MD signal lines / SD power lines are not shown in Figure 1. Fig. 1 not shown. Furthermore, it is understood that the spatial configurations between the SD power line 110, the MD signal line 112 and other structures of the GAA-FET device 100, which are in Fig. The figures shown in 1 are for illustrative purposes only and should not be limited to them.

[0014] Fig. Figure 2 illustrates an exemplary layout design 200 according to various embodiments of the present disclosure. The layout design 200 can be used to fabricate at least one section of a semiconductor device (for example, an integrated circuit with a number of interconnected circuits). However, not all of the illustrated components are required, and some embodiments of the present disclosure may include additional components that are described in Fig. 2 are not shown. Variations in the arrangement and type of components are permissible without departing from the scope of protection of this disclosure as set forth herein. Additional, different, or fewer components may be included.

[0015] The semiconductor device corresponding to layout design 200 can be fabricated based on the formation of a number of transistor features / structures (for example, channel structures, source structures, drain structures) along one or more active regions on the front face of a substrate. Although layout design 200 in Fig. Since Layout Design 200 has a number of structural forms, each forming a number of features / structures on the back side of a substrate, it is understood that Layout Design 200 can also have a number of structural forms, each forming a number of features / structures on the front side of the substrate, which will be discussed below. It should be noted that Layout Design 200 is viewed from its back side, which is why in Fig. 2 the structural forms for forming the rear features / structures are located on the structural forms for forming the front features / structures.

[0016] Layout design 200 comprises a number of cell rows 201 and 203 arranged (for example, laid out) with respect to a space, grid, or plan for the design of an integrated circuit. Such a plan may, in some embodiments, correspond to a substrate on which the semiconductor device is fabricated. The cell rows of layout design 200 may have at least two distinct row heights, cell heights, or heights. As shown, cell rows 201 may have a first row height, and cell rows 203 may have a second row height, the first row height being greater than the second row height. As a non-limiting example, the first row height may be between about 10 nanometers (nm) and about 85 nm, and the second row height may be between about 10 nm and about 40 nm.In the following, cell rows 201 and 203 may sometimes be referred to as tall cell rows (TC rows) and short cell rows (SC rows), respectively. The row height may correspond to the cell height of a cell to be placed within it (sometimes referred to as a standard cell). In the illustrated example of... Fig. 2. The cell rows 201 and 203 are arranged alternately with each other, but it is understood that the cell rows with different row heights can also be arranged in any other configuration (for example, 2 SC rows adjacent to 1TC row) without exceeding the scope of protection of the present disclosure.

[0017] Each of the TC / SC series features a number of active region structural shapes extending along the X-axis. As a non-restrictive example, the TC series 201 features active region structural shapes 202 and 204, and the SC series 203 features active region structural shapes 206 and 208. Active region structural shapes 202, 204, 206, and 208 are each configured to form an active region above the substrate, referred to below as "active region 202," "active region 204," "active region 206," and "active region 208," respectively. In some embodiments, active regions 202 through 208 are formed above the front face of the substrate.

[0018] The active regions in each cell row can be characterized by opposite conduction types. For example, in TC row 201, active region 202 can be characterized by a first conduction type (e.g., n-type), and active region 204 can be characterized by a second conduction type (e.g., p-type); and in SC row 203, active region 206 can be characterized by a first conduction type (e.g., p-type), and active region 208 can be characterized by a second conduction type (e.g., n-type).

[0019] In a non-restrictive example where layout design 200 is used to form GAA-FETs, the active region 202 can have one or more nanolayers stacked on top of each other over the substrate to form a number of n-transistors; the active region 204 can have one or more nanolayers stacked on top of each other over the substrate to form a number of p-transistors; the active region 206 can have one or more nanolayers stacked on top of each other over the substrate to form a number of p-transistors; and the active region 208 can have one or more nanolayers stacked on top of each other over the substrate to form a number of n-transistors.

[0020] In one embodiment, the cell height can correspond to the width along the Y-axis of an active region contained therein. For example, the SC array and the TC array can each have a number of active regions, with the active regions of the TC array having a greater width than the active regions of the SC array. In another embodiment, the cell height can correspond to the number of bottommost interconnect structures arranged therein, for example, Mo traces (as explained further below). For example, the SC array and the TC array can each have a number of Mo traces, with the number of Mo traces in the TC array being greater than the number of Mo traces in the SC array. In yet another embodiment, the cell height can correspond to the number of active regions contained therein.For example, the SC series may have a smaller number of active regions, while the TC series may have a larger number of active regions.

[0021] According to various embodiments of the present disclosure, each of the TC series can have a number of first structural forms extending along the X-axis to form first interconnect structures on the back side; each of the SC series can have a number of second structural forms to form second interconnect structures on the back side, each of which is configured as a pad adjacent to one of the first interconnect structural forms in the TC series; and each of the SC series can further have a number of third structural forms to form third interconnect structures on the back side. Some of the third interconnect structural forms can have multiple sections, some of which extend along the X-axis and some of which extend along the Y-axis.

[0022] As an illustrative example in Fig. 2 The TC series 201 features interconnect structural shapes 210 and 212 extending along the X-axis. In some embodiments, the interconnect structural shapes 210 and 212 may extend almost completely across the plan view of the layout design 200. In this respect, the interconnect structural shapes 210 and 212 may completely overlap the active regions (structural shapes) 202 and 204, respectively. The SC series 203 includes the interconnect structural shapes 214 and 216, which are configured as a pad or segment, and an interconnect structural shape 218, which has some sections extending along the X-axis and one section extending along the Y-axis. In some embodiments, the interconnect structural shapes 214 and 216 may not extend completely across the plan view of the layout design.In particular, the interconnect structural forms 214 and 216 can adjoin one of the fully extending interconnect structural forms 210 and 212 in an adjacent TC row. In some embodiments, the interconnect structural form 218 need not extend completely across the plan view of the layout design. In this respect, the interconnect structural forms 214 and 216 can partially overlap the active regions (structures) 206 and 208, respectively, and the interconnect structural form 218 can partially overlap both active regions (structures) 206 and 208. In particular, the interconnect structural form 218 can have three sections 218A, 218B, and 218C, which are located in . Fig. 3A are easier to see.

[0023] In Fig. In 3A, section 218A extends along the X-axis at a certain distance (for example, less than the width of the plan along the X-axis). Section 218C extends along the X-axis at a certain distance (for example, less than the width of the plan along the X-axis) and is laterally offset from section 218A along the X-axis. In some embodiments, sections 218A and 218C can overlap the active regions 206 and 208, respectively. Section 218B, which has two ends, each connected to sections 218A and 218C, extends along the Y-axis. Thus, each of sections 218A and 218C, together with section 218B, can form an L-shaped profile.By extending along a different direction than the extension direction of the active regions 206 and 208, section 218B can connect the active regions 206 and 208 through a number of through-contact structures 219 (as discussed further below).

[0024] Fig. 3B and Fig. Figures 3C each show different embodiments of the interconnect structural form 218. Fig. In 3B, the interconnect structure shape 218 extends along the Y-axis to overlap a section of the active region 206 and a section of the active region 208, thereby coupling the active regions 206 and 208 via a number of through-hole structures 219 (as discussed further below). Fig. In 3C, the interconnect structure 218 extends along a direction between the X-axis and the Y-axis to overlap a section of the active region 206 and a section of the active region 208, thereby coupling the active regions 206 and 208 via a number of via structures 219 (as discussed further below). In such an embodiment, the interconnect structure 218 can be inclined with respect to an edge of either the active region 206 or 208.

[0025] We return to Fig. 2. Interconnect structural forms 210 and 212 are each configured to form a first type of the disclosed SD power line across the back of the substrate (hereinafter referred to as “SD power line 210” and “SD power line 212” respectively); interconnect structural forms 214 and 216 are each configured to form a second type of the disclosed SD power line across the back of the substrate (hereinafter referred to as “SD power line 214” and “SD power line 216” respectively); and interconnect structural form 218 is configured to form a type of the disclosed MD signal line across the back of the substrate (hereinafter referred to as “MD signal line 218”).

[0026] Each of the SD power lines and MD signal lines can be coupled (for example, electrically) to an active region via a via structure, as mentioned above. As in Fig. As shown in Figure 2, the layout design 200 can include a number of structures 219 configured to form such via structures (hereinafter referred to as "via structure 219"). In some embodiments, the via structure 219 is formed on the back side of the substrate to electrically couple each of the SD power lines and MD signal lines to one or more sections of a corresponding active region.

[0027] For example, the SD power line 210 can be electrically coupled to the active region 202 via a number of via structures 219, for example 219-1; the SD power line 212 can be electrically coupled to the active region 204 via a number of via structures 219, for example 219-2; the SD power line 214 can be electrically coupled to the active region 206 via a number of via structures 219, for example 219-3; the SD power line 216 can be electrically coupled to the active region 208 via a number of via structures 219, for example 219-4; and the MD signal line 218 can each be electrically coupled to the active regions 206 and 208 via a number of via structures, for example 219-5 and 219-6, respectively.

[0028] Layout design 200 can have a number of cells arranged above one or more of the cell rows. For example, layout design 200 has in Fig. 2. The cells 220, 230, 240, 250, 260, 270, 280, and 290. Cell 220 is arranged above a single row of cells (for example, an SC row 203); cell 230 is arranged above a single row of cells (for example, an SC row 203); cell 240 is arranged above a single row of cells (for example, an SC row 210); cell 250 is arranged above three rows of cells (for example, two TC rows 201 and one SC row 203); cell 260 is arranged above two rows of cells (for example, a TC row 201 and an SC row 203); cell 270 is arranged above a single row of cells (for example, an SC row 203); cell 280 is arranged above a single row of cells (for example, an SC row 203); and cell 290 is arranged above a single row of cells (for example, a TC row 201).

[0029] Each cell can correspond to a circuit (for example, a logic gate or a logic circuit). For example, cell 220 can correspond to a single-stage inverter; cell 230 can correspond to a multi-stage NAND gate; cell 240 can correspond to a multi-stage inverter; cell 250 can correspond to another multi-stage inverter; cell 260 can correspond to a flip-flop circuit; cell 270 can correspond to an AND-OR-invert logic circuit (AOI logic circuit); cell 280 can correspond to an OR-AND-invert logic circuit (OAI logic circuit); and cell 290 can correspond to another AND-OR-invert logic circuit (AOI logic circuit).

[0030] Each cell can correspond to at least one layout that has a number of structural shapes overlapping one or more of the active regions in the corresponding row of cells. Some of the structural shapes can be configured to form features / structures on the front of the substrate (referred to here as "front-facing structural shapes"), while some of the structural shapes can be configured to form features / structures on the back of the substrate (referred to here as "back-facing structural shapes"). The layout of each cell occupying a section of the floor plan of Layout Design 200 can thus represent a section of one or more of the features described in Fig. exhibit the two structural forms shown.

[0031] In the following explanations, cell 260 (corresponding to a flip-flop circuit placed over a single SC row and a single TC row), cell 270 (corresponding to an AOI logic circuit placed over a single SC row) and cell 290 (corresponding to an AOI logic circuit placed over a single TC row) are selected as representative examples to illustrate both their respective front- and back-side structural forms, while cell 250 (corresponding to a multi-stage inverter) and cell 280 (corresponding to an OAI logic circuit placed over a single SC row) are selected as representative examples to illustrate their respective back-side structural forms.

[0032] In Fig. Figure 4 shows a circuit diagram of an example integrated circuit 400. The integrated circuit 400 features an AND-OR inverting logic circuit (AOI logic circuit). The AOI logic circuit is generally constructed from a combination of one or more AND gates followed by a NOR gate. As shown in Fig. As shown in Figure 4, the circuit 400 has four inputs: A1, A2, B1, and B2; and one output ZN, configured to perform the following Boolean function: (A1 ∩ A2) ∩ (B1 ∩ B2). To perform this function, the circuit 400 can include eight transistors 402, 404, 406, 408, 410, 412, 414, and 416, electrically coupled to each other and between the supply voltages VDD and VDD. Transistors 402 through 408 can each be implemented as a p-type transistor; and transistors 410 through 416 can each be implemented as an n-type transistor. However, it is understood that each of transistors 402 through 416 can also be implemented as one of various other line types of transistors.

[0033] Fig. 5A-5B and Fig. 5C illustrates a layout design 500 of a cell that corresponds to the AOI logic circuit 400 ( Fig. 4) corresponds to the cell to be placed above the SC row (the short cell row) 203, for example cell 270 of Fig. 2. Fig. 6A-6B and Fig. Figure 6C illustrates a layout design 600 of a cell that corresponds to the AOI logic circuit 400 ( Fig. 4) corresponds to the cell to be placed above the TC row (the long row of cells) 201, for example cell 290 of Fig. 2.

[0034] The layout design 500 of the Fig. Figure 5A-C shows different layout levels of cell 270, two of which have structural forms for creating structures / features on the front of the substrate, and one of which has structural forms for creating structures / features on the back of the substrate. Similarly, layout design 600 shows... Fig. 6A-C different layout levels of cell 290, two of which have structural forms for forming structures / features on the front of the substrate and one of which has structural forms for forming structures / features on the back of the substrate. It should be noted that layout designs 500 and 600, which are in the Fig. 5A-C and Fig. Figures 6A-C are shown from above, which is why they are located in the Fig. 5A-C and Fig. 6A-C the structural forms for forming the front features / structures are located on the top side of the structural forms for forming the back features / structures.

[0035] We turn first Fig. 5A, where a first layout level 500A of the layout design 500, which has a number of structural forms for forming a number of active regions and a number of interconnect structures on the front of the substrate, is shown according to various embodiments.

[0036] As shown, the first layout layer 500A comprises the active regions (structure shapes) 206 and 208, with a number of structure shapes 501A, S01B, 501C, 501D, S01E, and 501F extending along the Y-axis so that they intersect the active regions 206 and 208. Structure shapes 501A through 501F are configured to form gate structures, referred to below as "Gate Structure 501A", "Gate Structure 501B", "Gate Structure 501C", "Gate Structure S01D", "Gate Structure S01E", and "Gate Structure 501F", respectively. The gate structure 501A can be arranged along or above a first boundary of the layout design 500 (or the cell), and the gate structure 501F can be arranged along or above a second boundary of the layout design 500 (or the cell).Gate structures 501A and 501F do not need to provide an electrical or conductive path and can prevent or at least reduce / minimize leakage current at the components between which gate structures 501A and 501F are located. Gate structures 501A and 501F may include dummy polysilicon traces, sometimes referred to as PODEs. Each of the remaining gate structures 501B to 501E, formed from one or more conductive materials (for example, one or more types of polysilicon or metals), may be positioned over corresponding portions of active regions 206 and 208 to connect one or more of the transistors 402-416 (in ). Fig. 4 shown). As a representative example, the gate structure 501B can define a gate of transistor 412, and the sections of active region 208, which are arranged on the left and right sides of the gate structure 501B, can define a source and a drain of transistor 412, respectively.

[0037] The first layout level 500A features the feature types 502A, 502B, 502C, 502D, 502E, 502F, 502G, 502H, 502I, and 502J. Feature types 502A through 502J can each extend along the Y-direction and be configured to form a source / drain interconnect structure (for example, MDs), hereinafter referred to as "MD 502A", "MD 502B", "MD 502C", "MD 502D", "MD 502E", "MD 502F", "MD 502G", "MD 502H", "MD 502I", and "MD 502J". Each of the MDs 502A through 502J can be electrically coupled to the source or drain of a corresponding transistor.

[0038] The first layout layer 500A features the structural forms 503A, 503B, 503C, 503D, 503E, 503F, 503G, and 503H. Structural forms 503A through 503H can be configured to form through-hole interconnect structures (VDs), referred to below as "VD 503A", "VD 503B", "VD 503C", "VD 5030", "VD 503E", "VD 503F", "VD 503G", and "VD 503H". Each of the VDs 503A through 503H can extend along a vertical direction (for example, a direction perpendicular to the X-axis and the Y-axis) by a certain height to electrically couple a corresponding MD to an interconnect structure.

[0039] The first layout layer 500A features the structural forms 504A, 504B, 504C, and 504D. Structural forms 504A through 504D can be configured to form through-hole interconnect structures (VGs), referred to below as "VG 504A," "VG 504B," "VG 504C," and "VG 504D." Each VG 504A through 504D can extend along a vertical direction (for example, a direction perpendicular to the X-axis and the Y-axis) by a certain height to electrically couple a corresponding gate structure to an interconnect structure.

[0040] The first layout layer 500A features the structural forms 505A, 505B, 505C, 505D, and 505E. Structural forms 505A to 505E can each extend along the X-axis and be configured to form an interconnect structure in a bottom metallization layer above the front surface of the substrate (for example, a Mo layer). In this text, structural forms 505A to 505E are referred to as "Mo trace 505A", "Mo trace 505B", "Mo trace 505C", "Mo trace 505D", and "Mo trace 505E", respectively.

[0041] In some embodiments, the Mo trace 505A, which is arranged along or above a third boundary of the layout design (the cell), can be configured to carry a supply voltage (for example, VDD) and act as a shielding metal trace. The Mo trace 505E, which is arranged along or above a fourth boundary of the layout design (the cell), can be configured to carry a supply voltage (for example, VSS) and act as a shielding metal trace. In some embodiments, such shielding metal traces need not be connected to any of the active regions. To connect the transistors in the Fig. In the manner shown in Figure 4, some of the Mo traces can be "cut" into multiple sections by one or more Mo sectioning structures. For example, Mo trace 505B can be cut into a number of sections by sectioning structures 506A and 506C; and Mo trace 505C can be cut into a number of sections by sectioning structure 506B.

[0042] We will turn next Fig. 5B, where a second layout layer 500B of the layout design 500, which has a number of structural forms for forming a number of interconnect structures on the front of the substrate, is shown according to various embodiments. For reference purposes, the Mo conductor tracks 505A to 505E ( Fig. 5A) in Fig. 5B shown again.

[0043] The second layout layer 500B features the structural forms 506A, 506B, 506C, 506D, and 506E. Structural forms 506A to 506E can each extend along the Y-axis and be configured to form an interconnect structure on the next higher metallization layer (for example, an Mi layer). In this text, structural forms 506A to 506E are referred to as "M1 trace 506A", "M1 trace 506B", "Mi trace 506C", "M1 trace 506D", and "M1 trace 506E", respectively.

[0044] Each of the Mi conductor tracks 506A to 506E can be electrically coupled to at least one Mo conductor track via a through-hole structure (for example Vo) to carry either one of the input signals A1, A2, B1 and B2 ( Fig. 4) to receive or the output signal ZN ( Fig. 4) to provide. For example, the Mi trace 506A is electrically coupled via a via structure 507A (hereinafter "Vo 507A") to a cut section of the Mo trace 505B to receive the input signal A2; the Mi trace 506B is electrically coupled via a via structure 507B (hereinafter "Vo 507B") to a cut section of the Mo trace 505C to receive the input signal A1; the Mi trace 506C is electrically coupled via a via structure 507C (hereinafter "Vo 507C") to a cut section of the Mo trace 505B to provide the output signal ZN; The Mi conductor track 506D is electrically coupled to a cut section of the Mo conductor track 505C via a via 507D (hereinafter referred to as “Vo 507D”) to receive the input signal B1;and the Mi conductor 506E is electrically coupled via a via structure 507E (hereinafter referred to as "Vo 507E") to a cut section of the Mo conductor 505B to receive the input signal B2.

[0045] We now turn Fig. 5C, where a third layout layer 500C of layout design 500, which has a number of structural forms for forming a number of interconnect structures on the back side of the substrate, is shown according to various embodiments. For reference purposes, the gate structures 501A to 501F and those on the front side ( Fig. 5A) formed active regions 206 to 208 in Fig. 5C was shown again.

[0046] The third layout level 500C features structure forms 508, 510, 512, and 514. Structure forms 508, 510, and 514 can each be an example of interconnect structure form 214 or 216; and structure form 512 can be an example of interconnect structure form 218, which is found in Fig. Figure 2 shows that the structural features 508 to 514 can each be configured to form an interconnect structure at the lowest metallization layer above a back side of the substrate (for example, a BMo layer). In this text, the structural features 508 to 514 are referred to as "BMo trace 508", "BMo trace 510", "BMo trace 512", and "BMo trace 514", respectively. In some embodiments, the BMo traces 508 and 514 can each carry a first power supply voltage (for example, VSS), and the BMo trace 510 can carry a second power supply voltage (for example, VDD), while the BMo trace 512 can carry a signal other than one of the power supply voltages.The BMo conductor tracks 508, 510 and 514 can each be an implementation of the SD power line 214 or 216, and the BMo conductor track 512 can be an implementation of the MD signal line 218, as per the layout design 200 of . Fig. 2 discussed.

[0047] The BMo conductor track 508 can be electrically connected to a section of the active region 208 (for example, a source of transistor 412) via a backside via-hole structure formed by a structural form 513A (hereinafter referred to as "BVo 513A"). Fig. 4) be coupled; the BMo conductor track 510 can be electrically connected to a section of the active region 206 (for example, the respective sources of transistors 402 and 406 of) via a backside via-hole plating structure formed by a structural form 513B (hereinafter referred to as “BVo 513B”). Fig. 4) be connected; and the BMo conductor track 514 can be electrically connected to a section of the active region 208 (for example, a source of transistor 416 of) via a backside via-hole structure formed by a structural form 513E (hereinafter referred to as “BVo 513E”). Fig. 4) be connected. In this respect, each of the BMo conductor tracks 508, 510 and 514 can, according to the circuit design, either feed VDD or VSS into the corresponding nodes or otherwise provide it.

[0048] The BMo conductor track 512 can connect a section of the active region 208 (for example, the respective drains of transistors 410 and 414, as in Fig. 4) via a backside via-hole structure formed by a 513C feature (hereinafter “VB 513C”) and a backside via-hole structure formed by a 513D feature (hereinafter “VB 513D”), electrically connected to a section of the active region 206 (for example, the respective drains of transistors 404 and 408, as shown in Fig. (shown in Figure 4). More precisely, the BMo conductor 512 has three sections: 512A, 512B, and 512C. Section 512A overlaps active region 208 by extending in the same direction, and VB 513C is further located between active region 208 and section 512A; and section 512C overlaps active region 206 by extending in the same direction, and VB 513D is further located between active region 206 and section 512C. Section 512B, extending in a different direction, can, according to the circuit design, connect sections 512A and 512C to couple the corresponding (internal) nodes.

[0049] We now turn Fig. 6A, where a first layout level 600A of the layout design 600, which has a number of structural forms for forming a number of active regions and a number of interconnect structures on the front of the substrate, is shown according to various embodiments.

[0050] As shown, the first layout layer 600A comprises the active regions (structure shapes) 202 and 204, with a number of structure shapes 601A, 601B, 601C, 601D, 601E, and 601F extending along the Y-axis so that they intersect the active regions 202 and 204. Structure shapes 601A through 601F are configured to form gate structures, referred to below as "Gate Structure 601A", "Gate Structure 601B", "Gate Structure 601C", "Gate Structure 601D", "Gate Structure 601E", and "Gate Structure 601F", respectively. The gate structure 601A can be arranged along or above a first boundary of the layout design 600 (or the cell), and the gate structure 601F can be arranged along or above a second boundary of the layout design 600 (or the cell).Gate structures 601A and 601F do not need to provide an electrical or conductive path and can prevent or at least reduce / minimize leakage current at the components between which gate structures 601A and 601F are located. Gate structures 601A and 601F may include dummy polysilicon traces, sometimes referred to as PODEs. Each of the remaining gate structures 601B to 601E, formed from one or more conductive materials (for example, one or more types of polysilicon or metals), may be positioned over corresponding sections of active regions 202 and 204 to connect one or more of the transistors 402-416 (in ). Fig. 4 shown). As a representative example, the gate structure 601B can define a gate of transistor 412, and the sections of active region 204, which are arranged on the left and right sides of the gate structure 601B, can define a source and a drain of transistor 412, respectively.

[0051] The first layout level 600A features the feature types 602A, 602B, 602C, 602D, 602E, 602F, 602G, 602H, 602I, and 602J. Feature types 602A through 602J can each extend along the Y-direction and be configured to form a source / drain interconnect structure (for example, MDs), hereinafter referred to as "MD 602A", "MD 602B", "MD 602C", "MD 602D", "MD 602E", "MD 602F", "MD 602G", "MD 602H", "MD 602I", and "MD 602J". Each of the MDs 602A through 602J can be electrically coupled to the source or drain of a corresponding transistor.

[0052] The first layout layer 600A features the structural forms 603A, 603B, 603C, 603D, 603E, 603F, 603G, and 603H. Structural forms 603A through 603H can be configured to form through-hole interconnect structures (VDs), referred to below as "VD 603A," "VD 603B," "VD 603C," "VD 603D," "VD 603E," "VD 603F," "VD 603G," and "VD 603H." Each VD 603A through 603H can extend along a vertical direction (for example, a direction perpendicular to the X-axis and the Y-axis) by a certain height to electrically couple a corresponding MD to an interconnect structure.

[0053] The first layout layer 600A features the structural forms 604A, 604B, 604C, and 604D. Structural forms 604A through 604D can be configured to form through-hole interconnect structures (VGs), hereinafter referred to as "VG 604A," "VG 604B," "VG 604C," and "VG 604D." Each VG 604A through 604D can extend along a vertical direction (for example, a direction perpendicular to the X-axis and the Y-axis) by a certain height to electrically couple a corresponding gate structure to an interconnect structure.

[0054] The first layout layer 600A features the structural forms 605A, 605B, 605C, 605D, 605E, and 605F. Structural forms 605A to 605F can each extend along the X-axis and be configured to form an interconnect structure in a bottom metallization layer above the front surface of the substrate (for example, a Mo layer). In this text, structural forms 605A to 605F are referred to as "Mo conductor 605A", "Mo conductor 605B", "Mo conductor 605C", "Mo conductor 605D", "Mo conductor 605E", and "Mo conductor 605F", respectively.

[0055] In some embodiments, the Mo trace 605A, which is arranged along or above a third boundary of the layout design (the cell), can be configured to carry a supply voltage (for example, VDD) and act as a shielding metal trace. The Mo trace 605F, which is arranged along or above a fourth boundary of the layout design (the cell), can be configured to carry a supply voltage (for example, VSS) and act as a shielding metal trace. In some embodiments, such shielding metal traces need not be connected to any of the active regions. To connect the transistors in the Fig. In the manner shown in Figure 4, some of the Mo traces can be "cut" into multiple sections by one or more Mo cutting structures. For example, Mo traces 605C and 605E can each be cut into a number of sections by cutting structures 606A; Mo trace 605D can be cut into a number of sections by cutting structure 606B; and Mo trace 605E can be cut into a number of sections by cutting structure 606C.

[0056] We will turn next Fig. 6B, where a second layout layer 600B of layout design 600, which has a number of structural forms for forming a number of interconnect structures on the front side of the substrate, is shown according to various embodiments. For reference purposes, the Mo conductor tracks 605A to 605F ( Fig. 6A) in Fig. 6B was shown again.

[0057] The second layout layer 600B features the structural forms 606A, 606B, 606C, 606D, and 606E. Structural forms 606A to 606E can each extend along the Y-axis and be configured to form an interconnect structure on the next higher metallization layer (for example, an Mi layer). In this text, structural forms 606A to 606E are referred to as "M1 trace 606A", "M1 trace 606B", "M1 trace 606C", "M1 trace 606D", and "M1 trace 606E", respectively.

[0058] Each of the Mi conductor tracks 606A to 6o6E can be electrically coupled to at least one Mo conductor track via a through-hole structure (for example Vo) to either one of the input signals A1, A2, B1 and B2 ( Fig. 4) to receive or the output signal ZN ( Fig. 4) to provide. For example, the M1 conductor 606A is electrically coupled via a via structure 607A (hereinafter “Vo 607A”) to a cut section of the Mo conductor 605C to receive the input signal A2; the Mi conductor 606B is electrically coupled via a via structure 607B (hereinafter “Vo 607B”) to a cut section of the Mo conductor 605D to receive the input signal A1; the Mi conductor 606C is via via structures 607C (hereinafter “Vo 607C”) and 607C (hereinafter “Vo 607C”) respectively.607D (hereinafter referred to as "Vo 607D") is electrically coupled to a cut section of the Mo conductor 605C and a cut section of the Mo conductor 605E to provide the output signal ZN; the Mi conductor 606D is electrically coupled to a cut section of the Mo conductor 605D via a via structure 607E (hereinafter referred to as "Vo 607E") to receive the input signal B1; and the Mi conductor 606E is electrically coupled to a cut section of the Mo conductor 605B via a via structure 607F (hereinafter referred to as "Vo 607F") to receive the input signal B2.

[0059] We now turn Fig. 6C, where a third layout level 600C of layout design 600, which has a number of structural forms for forming a number of interconnect structures on the back side of the substrate, is shown according to various embodiments. For reference purposes, the gate structures 601A to 601F and those on the front side ( Fig. 6A) formed active regions 202 to 204 in Fig. 6C was shown again.

[0060] The third layout level 600C features structural forms 608 and 610. Structural forms 608 and 610 can each be an example of a section of the... Fig. The interconnect structures shown in Figure 2 are 210 or 212. Structures 608 and 610 can each be configured to form an interconnect structure at the lowest metallization layer above a back side of the substrate (for example, a BMo layer). Structures 608 to 610 are referred to in this text as "BMo trace 608" and "BMo trace 610," respectively. In some embodiments, BMo trace 608 can carry a first power supply voltage (for example, VDD), and BMo trace 610 can carry a second power supply voltage (for example, VSS). BMo traces 608 and 610 can each be an implementation of SD power line 210 or 212, as shown in the layout design 200 of Figure 200. Fig. 2 discussed.

[0061] The BMo conductor track 608 can be electrically connected to a section of the active region 204 (for example, the respective sources of transistors 402 and 406 of) via a backside via-hole plating structure formed by a structural form 613A (hereinafter “VB 613A”). Fig. 4) be coupled; and the BMo conductor track 610 can be connected to a section of the active region 202 (for example, a source of transistor 412 of) via a backside via-hole structure formed by a structural form 613B (hereinafter referred to as “VB 513B”). Fig. 4) and via a backside through-hole structure formed by a 613C structure (hereinafter referred to as “VB 613C”), with a section of the active region 202 (for example, a source of transistor 416 of Fig. 4) be electrically coupled. Therefore, each of the BMo conductor tracks 608 and 610 can, according to the circuit design, either supply VDD or VSS to the corresponding nodes or provide it in another way.

[0062] Fig. Figure 7 illustrates a layout design 700 of a cell corresponding to the OAI logic circuit to be placed above the SC series (short cell series) 203, for example cell 290 of Fig. 2. Fig. Figure 8 illustrates a layout design 800 of a cell corresponding to the OAI logic circuit to be placed above the TC row (the tall cell row) 201. The OAI logic circuit is similar to the AOI logic circuit, which in terms of Fig. As discussed in section 4, except that the internal connection between the p-transistors is replaced by an internal connection between the n-transistors, which does not significantly alter the structural forms used to create the front-side structural forms / features. Thus, in the Fig. 7 and Fig. 8 Layout designs 700 and 800 each include a layout layer showing structural shapes for forming the rear interconnect structures, while structural shapes for forming active regions and gate structures are present on the front side for reference purposes.

[0063] We turn first Fig. 7. If active regions 206-208 and gate structures 701A to 701F are present, then layout design (level) 700 has structure forms 702, 704, 706, and 708. Structure forms 702, 704, and 708 can each be an example of interconnect structure form 214 or 216; and structure form 706 can be an example of interconnect structure form 218, which is described in Fig. Figure 2 shows that the structural forms 702 to 708 can each be configured to form an interconnect structure at the lowest metallization layer above a back side of the substrate (for example, a BMo layer). In this text, the structural forms 702 to 708 are referred to as "BMo trace 702", "BMo trace 704", "BMo trace 706", and "BMo trace 708", respectively. In some embodiments, the BMo trace 702 can carry a first power supply voltage (for example, VSS), and the BMo traces 704 and 708 can each carry a second power supply voltage (for example, VDD), while the BMo trace 706 can carry a signal other than one of the power supply voltages.The BMo conductor tracks 702, 704 and 708 can each be an implementation of the SD power line 214 or 216, and the BMo conductor track 706 can be an implementation of the MD signal line 218, as per the layout design 200 of . Fig. 2 discussed.

[0064] The BMo trace 702 can be electrically coupled to a section of active region 208 via a backside via structure formed by a 709A feature (hereinafter "VB 709A"); the BMo trace 704 can be electrically coupled to a section of active region 206 via a backside via structure formed by a 709B feature (hereinafter "VB 709B"); and the BMo trace 708 can be electrically coupled to a section of active region 206 via a backside via structure formed by a 709E feature (hereinafter "VB 709E"). Thus, each of the BMo traces 702, 704, and 708 can, according to the circuit design, either supply or otherwise provide VDD or VSS to the corresponding nodes.

[0065] The BMo conductor 706 can electrically connect a section of the active region 206 to a section of the active region 208 via a back-side via formed by a 709C feature (hereinafter "VB 709D") and a back-side via formed by a 709D feature (hereinafter "VB 709D"). More precisely, the BMo conductor 706 has three sections 706A, 706B, and 706C. Section 706A overlaps the active region 208 by extending along the same direction, and VB 709D is furthermore located between the active region 208 and section 706A. and section 706C overlaps active region 206 by extending along the same direction, and VB 709C is furthermore located between active region 206 and section 706C.According to the circuit design, section 706B, which extends in a different direction, can connect sections 706A and 706C to couple the corresponding (internal) nodes.

[0066] We now turn Fig. 8. If active regions 202-204 and gate structures 801A to 801F are present, then layout design (level) 800 has structure forms 802 and 804. Structure forms 802 and 804 can each be an example of a section of the in Fig. The interconnect structures shown in Figure 2 are 210 or 212. Structures 802 and 804 can each be configured to form an interconnect structure at the lowest metallization layer above a back side of the substrate (for example, a BMo layer). Structures 802 and 804 are referred to in this text as "BMo trace 802" and "BMo trace 804," respectively. In some embodiments, BMo trace 802 can carry a first power supply voltage (for example, VDD), and BMo trace 804 can carry a second power supply voltage (for example, VSS). BMo traces 802 and 804 can each be an implementation of SD power line 210 or 212, as shown in the layout design 200 of Figure 200. Fig. 2 discussed.

[0067] The BMo trace 802 can be electrically coupled to a section of active region 204 via a backside via formed by a feature shape 805A (hereinafter "VB 805A") and to a section of active region 204 via a backside via formed by a feature shape 805C (hereinafter "VB 805C"); and the BMo trace 804 can be electrically coupled to a section of active region 202 via a backside via formed by a feature shape 805B (hereinafter "VB 805B"). Thus, each of the BMo traces 802 and 804 can, according to the circuit design, either supply or otherwise provide VDD or VSS to the corresponding nodes.

[0068] In Fig. Figure 9 shows a circuit diagram of an exemplary integrated circuit 900. The integrated circuit 900 features a scan-D flip-flop circuit or a D flip-flop circuit with a scan input (hereinafter referred to as the "SDF" circuit). The SDF circuit is generally constructed from a combination of a number of transistors, as shown in Fig. Figure 9 shows that the SDF circuit features a D flip-flop with a multiplexer (MUX) that has one input designated as a function input "D" and another input designated as a "Scan-In Input (SI Input)." "Scan / Test Enable (SE / TE)" is used to control a selection bit of the MUX. A clock signal is also supplied via the "CP" input, and the SDF circuit has an output "Q." To perform a function of the SDF circuit (for example, a D flip-flop allowing its input signal to come from an alternative source), the transistors are electrically coupled to each other and between the supply voltages VDD and VDD. As shown in Fig. As shown in Figure 9, some of the transistors can be implemented as p-type transistors, and some of the transistors can be implemented as n-type transistors. However, it is understood that each of the transistors can also be implemented as one of various other conduction types of transistors.

[0069] Fig. 10A, Fig. 10B, Fig. 10C and Fig. Figure 10D illustrates a layout design of 1000 of a cell, which corresponds to the SDF circuit 900 ( Fig. 9) corresponds to being placed above the SC row (the short cell row) 203 and the TC row (the long cell row) 201, for example cell 260 of Fig. 2. The layout design 1000 of the Fig. Figures 10A-D show different layout levels of cell 260, three of which have structural forms for creating structures / features on the front of the substrate, and one of which has structural forms for creating structures / features on the back of the substrate. It should be noted that layout design 1000, which is shown in the Fig. 10A-D is shown, viewed from above, which is why in the Fig. 10A-D the structural forms for forming the front features / structures are located on the top side of the structural forms for forming the back features / structures.

[0070] We turn first Fig. 10A to, where a first layout level 1000A of the layout design 1000, which has a number of structural forms for forming a number of active regions and a number of interconnect structures on the front of the substrate, is shown according to various embodiments.

[0071] As shown, the first layout layer 1000A has the active regions (structure shapes) 202-204 (of the tall cell row 201) and 206-208 (of the short cell row 203), with a number of structure shapes 1001A, 1001B, 1001C, 1001D, 1001E, 1001F, 1001G, 1001H, 1001I, 1001J and 1001K extending along the Y-axis, such that the active regions 202 to 208 are crossed. The structural forms 1001A to 1001K are configured to form gate structures, hereinafter referred to as "Gate structure 1001A", "Gate structure 1001B", "Gate structure 1001C", "Gate structure 1001D", "Gate structure 1001E", "Gate structure 1001F", "Gate structure 1001G", "Gate structure 1001H", "Gate structure 1001I", "Gate structure 1001J" and "Gate structure 1001K".

[0072] The gate structure 1001A can be arranged along or above a first boundary of the layout design 1000 (or the cell), and the gate structure 1001K can be arranged along or above a second boundary of the layout design 1000 (or the cell). The gate structures 1001A and 1001K do not need to provide an electrical or conductive path and can prevent or at least reduce / minimize leakage current at the components between which the gate structures 1001A and 1001K are located. The gate structures 1001A and 1001K can include dummy polysilicon conductors, sometimes referred to as PODEs. Each of the remaining gate structures 1001B to 1001J, formed from one or more conductive materials (for example, one or more types of polysilicon or metals), can be located over corresponding sections of the active regions 202 and 208 to connect the transistors of the SDF circuit 900 (in Fig. 9 shown) to define.

[0073] The first layout layer 1000A has a number of structure forms 1003. The structure forms 1003 can each extend along the Y direction and be configured to form a source / drain interconnect structure (for example, MD), hereinafter referred to as "MD 1003". Each of the MDs can be electrically coupled to the source or drain of a corresponding transistor, for example, the section of each of the active regions 202 to 208 over which there is no gate structure.

[0074] The first layout layer 1000A has a number of structure shapes 1005. Each structure shape 1005 can be configured to form a via interconnect structure (for example, VD), hereinafter referred to as "VD 1005". Each VD 1005 can extend along a vertical direction (for example, a direction perpendicular to the X-axis and the Y-axis) by a certain height to electrically couple a corresponding MD to an interconnect structure.

[0075] The first layout layer 1000A has a number of structure forms 1007. Each structure form 1007 can be configured to form a via interconnect structure (for example, VG), hereinafter referred to as "VG 1007". Each VG 1007 can extend along a vertical direction (for example, a direction perpendicular to the X-axis and the Y-axis) by a certain height to electrically couple a corresponding gate structure to an interconnect structure.

[0076] We will turn next Fig. 10B, where a second layout layer 1000B of layout design 1000, which has a number of structural forms for forming a number of interconnect structures on the front side of the substrate, is shown according to various embodiments. For reference purposes, the gate structures 1001A to 1001K ( Fig. 10A) in Fig. 10B was shown again.

[0077] The second layout level 1000B features the structural forms 1010A, 1010B, 1010C, 1010D, 1010E, 1010F, 1010G, 1010H, 1010I, and 1010J. Structural forms 1010A to 1010J can each extend along the X-axis and be configured to form an interconnect structure in a bottom metallization layer above the front surface of the substrate (for example, a Mo layer). The structural forms 1010A to 1010J are referred to in this text as “Mo conductor 1010A”, “Mo conductor 1010B”, “Mo conductor 1010C”, “Mo conductor 1010D”, “Mo conductor 1010E”, “Mo conductor 1010F”, “Mo conductor 1010G”, “Mo conductor 1010H”, “Mo conductor 1010I” and “Mo conductor 1010J”.

[0078] In some embodiments, the Mo trace 1010A, which is arranged along or above a third boundary of the layout design (the cell), can be configured to carry a supply voltage (for example, VDD) and act as a shielding metal trace. The Mo trace 1010J, which is arranged along or above a fourth boundary of the layout design (the cell), can be configured to carry a supply voltage (for example, VSS) and act as a shielding metal trace. In some embodiments, such shielding metal traces need not be connected to any of the active regions. To connect the transistors in the Fig. To connect in the manner shown in Figure 9, some of the Mo conductor tracks can be “cut” into several sections by one or more Mo section structure shapes, for example 1011.

[0079] We will turn next Fig. 10C, where a third layout level 1000C of layout design 1000, which has a number of structural forms for forming a number of interconnect structures on the front side of the substrate, is shown according to various embodiments. For reference purposes, the gate structures 1001A to 1001K ( Fig. 10A) in Fig. 10C was shown again.

[0080] The third layout level 1000C features the structural forms 1012A, 1012B, 1012C, 1012D, 1012E, 1012F, 1012G, 1012H, 1012I, 1012J, and 1012K. Structural forms 1012A to 1012K can each extend along the Y-axis and be configured to form an interconnect structure on the next higher metallization layer (for example, an M1 layer). The structural forms 1012A to 1012K are referred to in this text as "M1 conductor 1012A", "M1 conductor 1012B", "M1 conductor 1012C", "M1 conductor 1012D", "M1 conductor 1012E", "Mi conductor 1012F", "M1 conductor 1012G", "Mi conductor 1012H", "M1 conductor 1012I", "M1 conductor 1012J" or "Mi conductor 1012K".

[0081] Each of the Mi conductor tracks 1012A to 1012K can be electrically coupled to at least one Mo conductor track via a through-hole structure (for example Vo) to carry either one of the input signals SI, D, SE and CP ( Fig. 9) to receive or the output signal Q ( Fig. 9) to provide. For example, the Mi trace 1012A is electrically coupled via a via structure 1013A (hereinafter referred to as "1013A") to a cut section of the Mo trace 1010C to receive the input signal SI; the Mi trace 1012B is electrically coupled via a via structure 1013B (hereinafter referred to as "1013B") to a cut section of the Mo trace 1010I to provide the output signal Q; the Mi trace 1012D is electrically coupled via a via structure 1013C (hereinafter referred to as "1013C") to a cut section of the Mo trace 1010C to receive the input signal D; The Mi conductor track 1012E is electrically coupled to a cut section of the Mo conductor track 1010E via a via structure 1013D (hereinafter referred to as "1013D") to receive the input signal SE;and the Mi conductor 1012K is electrically coupled via a through-hole structure 1013E (hereinafter referred to as "1013E") to a cut section of the Mo conductor 1010H to receive the input signal CP.;

[0082] We now turn Fig. Figure 10D shows a fourth layout layer 1000D of layout design 1000, which has a number of structural forms for forming a number of interconnect structures on the back side of the substrate, according to various embodiments. For reference, the gate structures 1001A to 1001K and those on the front side ( Fig. 10A) formed active regions 202 to 208 in Fig. 10D shown again.

[0083] The fourth layout level 1000D has the structure forms 1014, 1016, 1018, 1020, 1022, 1024, 1026, and 1028. Structure forms 1014, 1018, 1022, and 1024 can each be an example of the interconnect structure form 214 or 216; structure forms 1016 and 1020 can each be an example of the interconnect structure 218; and structure forms 1026 and 1028 can each be an example of a section of the interconnect structure form 210 or 212, which is in Fig. Figure 2 shows that the structural forms 1014 to 1028 can each be configured to form an interconnect structure on the lowest metallization layer above a back side of the substrate (for example, a BMo layer). In this text, the structural forms 1014 to 1028 are referred to as "BMo conductor 1014", "BMo conductor 1016", "BMo conductor 1018", "BMo conductor 1020", "BMo conductor 1022", "BMo conductor 1024", "BMo conductor 1026", and "BMo conductor 1028", respectively. BMo conductors 1022 and 1024 can each be connected to BMo conductor 1026, as shown in Figure 2. Fig. Figure 10D shows that in some embodiments, BMo traces 1022, 1024, and 1026 can each carry a first power supply voltage (for example, VSS), and BMo traces 1014, 1018, and 1028 can carry a second power supply voltage (for example, VDD), while BMo traces 1016 and 1020 can each carry a signal other than one of the power supply voltages. BMo traces 1014, 1018, 1022, 1024, 1026, and 1028 can each be an implementation of the SD power line 214 or 216, and BMo traces 1016 and 1020 (which even extend along a single direction) can be an implementation of the MD signal line 218, as shown in layout design 200. Fig. 2 discussed.

[0084] The BMo conductor 1014 can be electrically coupled to a section of the active region 206 via a backside via structure formed by a feature 1031A (hereinafter referred to as "VB 1031A"); the BMo conductor 1018 can be electrically coupled to a section of the active region 206 via a backside via structure formed by a feature 1031D (hereinafter referred to as "VB 1031D"); the BMo conductor 1022 can be electrically coupled to a section of the active region 208 via a backside via structure formed by a feature 1031E (hereinafter referred to as "VB 1031E"). The BMo conductor track 1024 can be electrically coupled to a section of the active region 208 via a backside via-hole structure formed by a structural form 1031H (hereinafter referred to as “VB 1031H”);The BMo conductor track 1026 can be electrically coupled to a number of sections of the active region 202 via a backside via structure formed by a structure form 1031I (hereinafter referred to as "VB 1031I"), a backside via structure formed by a structure form 1031J (hereinafter referred to as "VB 1031J"), or a backside via structure formed by a structure form 1031K (hereinafter referred to as "VB 1031K");and the BMo conductor 1028 can be electrically coupled to a number of sections of the active region 204 via a back-side via structure formed by a structure shape 1031L (hereinafter "VB 1031L"), a back-side via structure formed by a structure shape 1031M (hereinafter "VB 1031M"), or a back-side via structure formed by a structure shape 1031N (hereinafter "VB 1031N"). In this respect, each of the BMo conductors 1014, 1018, 1022, 1024, 1026, and 1028 can, according to the circuit design, either supply or otherwise provide VDD or VSS to the corresponding nodes.

[0085] The BMo conductor 1016 can electrically connect a section of active region 206 to a section of active region 206 via a backside via formed by a feature 1031B (hereinafter "VB 1031B") and a backside via formed by a feature 10310 (hereinafter "VB 1031C"). The BMo conductor 1020 can electrically couple a section of active region 208 to another section of active region 208 via a backside via formed by a feature 1031F (hereinafter "VB 1031F") and a backside via formed by a feature 1031G (hereinafter "VB 1031G"). According to the circuit design, the BMo conductor tracks 1016 and 1020 can each couple different sections of an active region to couple the corresponding (internal) nodes together.

[0086] Fig. Figure 11 illustrates a layout design 1100 of a cell corresponding to the multi-stage inverter to be placed above a single SC series 203 and two TC series 201, for example the cell 250 of Fig. 2. The Layout Design 1100 features a layout layer that shows structural shapes for forming the rear interconnect structures, while structural shapes for forming active regions and gate structures are present on the front side for reference purposes.

[0087] As shown, active region 204 from one of the TC series 201 (for example, the upper TC series 201) and active region 206 from SC series 203 merge to form a first wider active region in layout design 1100. Similarly, active region 202 from the other TC series 201 (for example, the lower TC series 201) and active region 208 from SC series 203 merge to form a second wider active region in layout design 1100. When active regions 202 and 204 are merged with active regions 206 and 208, and gate structures 1101A to 1101F are present, the layout design (layer) 1100 has structure forms 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, and 1120. Structure forms 1102 to 1120 can each be configured to form an interconnect structure at the bottom metallization layer above a back side of the substrate (for example, a BMo layer).The structural forms 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118 and 1120 are referred to in this text as “BMo conductor rail 1102”, “BMo conductor rail 1104”, “BMo conductor rail 1106”, “BMo conductor rail 1108”, “BMo conductor rail 1110”, “BMo conductor rail 1112”, “BMo conductor rail 1114”, “BMo conductor rail 1116”, “BMo conductor rail 1118” and “BMo conductor rail 1120”, respectively.

[0088] In some embodiments, BMo traces 1102, 1112, 1114, 1116, and 1118 can each carry a first power supply voltage (for example, VSS), and BMo traces 1104, 1106, 1108, 1110, and 1120 can carry a second power supply voltage (for example, VDD). In some embodiments, BMo traces 1106, 1108, and 1100 can each be adjacent to Mo trace 1104, and BMo traces 1112, 1114, and 1116 can each be adjacent to Mo trace 1118, as shown. The BMo conductor tracks 1102 to 1120 can each be an implementation of the SD power line 210 or 212, as shown in the layout design 200. Fig. 2 discussed.

[0089] The adjacent sections of the BMo conductor tracks 1104 and 1106, 1104 and 1108, and 1104 and 1110 can be electrically coupled to the respective sections of the fused active regions 204 and 206 via a number of backside vias, each formed by structural forms 1109A (hereinafter "VB 110gA"), 1109B (hereinafter "VB 1109B") and 11090 (hereinafter "VB 11090"). The adjacent sections of the BMo conductor tracks 1118 and 1112, 1118 and 1114, and 1118 and 1116 can be electrically coupled to respective sections of the fused active regions 208 and 202 via a number of backside vias, each formed by structural forms 1109D (hereinafter “VB 110gD”), 1109E (hereinafter “VB 1109E”) and 1109F (hereinafter “VB 110gF”).Therefore, each of the BMo conductor tracks 1102 to 1120 can, according to the design of the circuit, either feed VDD or VSS into the corresponding nodes or provide it in another way.

[0090] Although the layout designs, as discussed above, illustrate the bottom metallization layer (BMo layer) over the back of the substrate, it is understood that each of the layout designs can have any number of metallization layers arranged over the back of the substrate. Fig. Figure 12 illustrates a layout design 1200, which has a number of structural forms for creating backside interconnect structures on the BMo layer. Layout design 1200 can be a section of layout design 200 ( Fig. 2) be. For example, the layout design comprises 1200 in Fig. 12 a single SC series 203, which is sandwiched between two TC series 201, and a number of BMo conductor tracks 210 to 218.

[0091] Furthermore, the Layout Design 1200 includes the structural forms 1210A, 1210B, 1210C, 1210D, 1210E, 1210F, 1210G, 1210H, 1210I and 1210J. Structural forms 1210A to 1210J can each be configured to form an interconnect structure on the next higher metallization layer relative to the BMo layer (for example, a BM1 layer). The structural forms 1210A, 1210B, 1210C, 1210D, 1210E, 1210F, 1210G, 1210H, 1210I and 1210J are referred to in this text as “BM1 conductor 1210A”, “BM1 conductor 1210B”, “BM1 conductor 1210C”, “BM1 conductor 1210D”, “BM1 conductor 1210E”, “BM1 conductor 1210F”, “BM1 conductor 1210G”, “BM1 conductor 1210H”, “BM1 conductor 1210I” and “BM1 conductor 1210J”.In some embodiments, the BM1 traces 1210A to 1210J can each extend along a direction (for example, the Y-axis) that is perpendicular to the direction of extension of the BMo traces configured to carry the power supply voltage, for example, BMo traces 210 and 212. In some embodiments, the BM1 traces 1210A, 1210C, 1210E, 1210G, and 1210I can each carry a first power supply voltage (for example, VDD), and the BM1 traces 1210B, 1210D, 1210F, 1210H, and 1210J can carry a second power supply voltage (for example, VSS). Each of the BM1 conductors can be electrically connected to one or more of the BMo conductors via one or more backside via structures (for example VBo) formed by structural features 1213 (hereinafter referred to as “VBo 1213”).

[0092] Fig. Figure 13 illustrates a cross-sectional view of a semiconductor device 1300 exhibiting the features / structures described above. The cross-sectional view of Fig. 13 is cut along the longitudinal direction of a channel of the semiconductor device 1300, which is implemented as a GAA-FET device. Fig. Figure 13 has been simplified to illustrate relatively spatial configurations of the structures discussed above, and therefore it is understood that one or more features / structures of a finished GAA-FET device in Fig. 13 may not be shown.

[0093] On the front side of a substrate (which is surrounded by a dashed line, as it was removed during the formation of the backside interconnect structures), the semiconductor device 1300 has an active region 1302 comprising sections configured as channels 1304 and sections configured as source / drain structures 1306. The channel 1304 has one or more nanostructures (for example, nanolayers, nanowires) that are vertically spaced apart in various embodiments. The semiconductor device 1300 has a number of (for example, metallic) gate structures 1308, each of which surrounds the nanostructures of a corresponding channel 1304. Above the source / drain structure 1306, the semiconductor device 1300 has a number of MDs 1310, some of which are coupled to VDs 1312 formed on them. Above the gate structure 1308, the semiconductor device 1300 has a number of VGs 1314.The VD 1312 can couple the MD 1310 to a first Mo trace 1316. The VG 1314 can couple the gate structure 1308 to a second Mo trace 1316. Above the Mo trace 1316, the semiconductor device 1300 has a number of Vos 1318 to couple the Mo traces 1316 to a number of Mi traces 1320. On the back side of the substrate, the semiconductor device 1300 has a number of VBs 1322, each of which can couple the source / drain structure 1306 to a BMo trace 1324. Furthermore, the semiconductor device 1300 has a number of VBos 1326 above the BMo conductor track 1324, each of which can couple the BMo conductor track 1324 with a BM1 conductor track 1328.

[0094] Fig. Figure 14 is a flowchart of a method 1400 for forming or manufacturing a semiconductor device according to some embodiments. It is understood that additional operations may be performed before, during, and / or after the process described in Figure 14. Fig. The methods shown in Figure 14 can be carried out using Method 1400. In some embodiments, Method 1400 can be used to form a semiconductor device according to various layout designs disclosed in this text.

[0095] In operation 1410 of procedure 1400, a layout design of a semiconductor device (for example, layout design 200 of Fig. 2) created. Operation 1410 is performed by a processing device (for example, the 1502 processor from Fig. 15) is performed, which is configured to execute instructions for creating a layout design. In one approach, the layout design is created by placing layout designs of one or more standard cells through a user interface. In another approach, the layout design is created automatically by a processor that executes a synthesis tool that converts a logic design (for example, Verilog) into a corresponding layout design. In some embodiments, the layout design is rendered in a Graphic Database System file format (GDSII file format).

[0096] In operation 1420 of method 1400, a semiconductor device is fabricated based on the layout design. In some embodiments, operation 1420 of method 1400 comprises fabricating at least one mask based on the layout design and fabricating the semiconductor device based on the at least one mask. A number of exemplary fabrication operations of operation 1420 are described below with reference to method 1700. Fig. 17 discussed.

[0097] Fig. Figure 15 is a schematic view of a system 1500 for designing and manufacturing an IC layout design according to some embodiments. The system 1500 creates or places one or more IC layout designs as described in this text. In some embodiments, the system 1500 fabricates one or more semiconductor devices based on the one or more IC layout designs as described in this text. The system 1500 comprises a hardware processor 1502 and a non-transient, computer-readable storage medium 1504, which is encoded with and stores computer program code 1506, for example, a set of executable instructions. The computer-readable storage medium 1504 is configured to be connected to manufacturing machines for producing the semiconductor device. The processor 1502 is electrically coupled to the computer-readable storage medium 1504 via a bus 1508.The processor 1502 is also electrically coupled to an I / O interface 1510 via the bus 1508. A network interface 1512 is likewise electrically connected to the processor 1502 via the bus 1508. The network interface 1512 is connected to a network 1514, enabling the processor 1502 and the computer-readable storage medium 1504 to connect to external elements via the network 1514. The processor 1502 is configured to execute the computer program code 1506 encoded in the computer-readable storage medium 1504 in order to make the system 1500 usable for the complete or partial execution of the operations described in the procedure 1400.

[0098] In some embodiments, the 1502 processor is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0099] In some embodiments, the computer-readable storage medium 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or such device or apparatus). For example, the computer-readable storage medium 1504 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In some embodiments operating with optical disks, the computer-readable storage medium 1504 includes a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disc (DVD).

[0100] In some embodiments, the storage medium 1504 stores the computer program code 1506, which is configured to cause the system 1500 to execute the method 1400. In some embodiments, the storage medium 1504 also stores information required for executing the method 1100, as well as information generated during the execution of the method 1100, such as the layout design 1516, the user interface 1518, the manufacturing unit 1520, and / or a set of executable instructions for carrying out the process of the method 1100.

[0101] In some embodiments, the storage medium 1504 stores instructions (for example, the computer program code 1506) for connecting to manufacturing machines. The instructions (for example, the computer program code 1506) enable the processor 1502 to generate manufacturing instructions that can be read by the manufacturing machines to effectively implement the method 300 during a manufacturing process.

[0102] The System 1500 includes the I / O interface 1510. The I / O interface 1510 is coupled to external circuitry. In some embodiments, the I / O interface 1510 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor keys for transmitting information and commands to the processor 1502.

[0103] System 1500 also includes the network interface 1512, which is coupled to the processor 1502. The network interface 1512 enables System 1500 to communicate with the network 1514, to which one or more other computer systems are connected. The network interface 1512 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or wired network interfaces such as Ethernet, USB, or IEEE-13154. In some embodiments, the method 1400 is implemented in two or more Systems 1500, and information such as the layout design, user interface, and manufacturing unit is exchanged between different Systems 1500 via the network 1514.

[0104] The System 1500 is configured to receive layout design information via the I / O interface 1510 or the network interface 1512. This information is transmitted via the bus 1508 to the processor 1502 to determine a layout design for manufacturing an IC. The layout design is then stored on the computer-readable medium 1504 as layout design 1516. The System 1500 is also configured to receive user interface information via the I / O interface 1510 or the network interface 1512. This information is stored on the computer-readable medium 1504 as user interface 1518. Finally, the System 1500 is configured to receive manufacturing unit information via the I / O interface 1510 or the network interface 1512. This information is stored on the computer-readable medium 1504 as manufacturing unit 1520.In some embodiments, the manufacturing unit 1520 contains manufacturing information that is used by the system 1500.

[0105] In some embodiments, Method 1400 is implemented as a standalone software application for execution by a processor. In some embodiments, Method 1400 is implemented as a software application that is part of an additional software application. In some embodiments, Method 1400 is implemented as a plug-in to a software application. In some embodiments, Method 1400 is implemented as a software application that is a section of an EDA tool. In some embodiments, Method 1400 is implemented as a software application that is used by an EDA tool. In some embodiments, the EDA tool is used to create a layout design of the integrated circuit. In some embodiments, the layout design is stored on a non-transient, computer-readable medium.In some embodiments, the layout design is created using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout creation tool. In some embodiments, the layout design is generated based on a netlist created from the schematic design. In some embodiments, Method 1400 is implemented by a fabrication device to produce an integrated circuit using a set of masks produced based on one or more layout designs created by System 1500. In some embodiments, System 1500 includes a fabrication device (for example, the fabrication tool 1522) for producing an integrated circuit using a set of masks produced based on one or more layout designs of the present disclosure.In some embodiments, the system creates 1500 of . Fig. 15 layout designs for an IC that are smaller than those of other approaches. In some embodiments, the system creates 1500 of Fig. 15 layout designs for a semiconductor device that take up less space than other approaches.

[0106] Fig. Figure 16 is a block diagram of a manufacturing system 1600 for integrated circuits (ICs) / semiconductor devices and an associated IC manufacturing flow according to at least one embodiment of the present disclosure.

[0107] In Fig. The IC manufacturing system 1600 comprises entities such as a design house 1620, a mask house 1630, and an IC manufacturer / fabricator (“fab”) 1640, which interact with each other in the design, development, and manufacturing cycles and / or in the services related to the manufacture of an IC device (semiconductor device) 1660. The entities in the system 1600 are connected via a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a multitude of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from them.In some embodiments, two or more of the Design House 1620, the Mask House 1630, and the IC-Fab 1640 are owned by a single company. In some embodiments, two or more of the Design House 1620, the Mask House 1630, and the IC-Fab 1640 exist side-by-side in a shared facility and utilize common resources.

[0108] Design House (or Design Team) 1620 creates an IC design layout 1622. The IC design layout 1622 contains various geometric structures designed for the IC device 1660. These geometric structures correspond to structures of metal, oxide, or semiconductor layers that comprise the various components of the IC device 1660 to be manufactured. The different layers combine to form various IC features. For example, a section of the IC design layout 1622 includes various IC features, such as an active region, gate structures, source / drain structures, interconnect structures, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers arranged on the semiconductor substrate. Design House 1620 implements a suitable design process to create the IC design layout 1622.The design process comprises one or more steps, including a logical design, a physical design, and placement and routing. The IC design layout 1622 is presented in one or more files containing information about the geometric structures. For example, the IC design layout 1622 can be expressed in a GDSII file format or a DFII file format.

[0109] The mask house 1630 comprises the data preparation 532 and the mask fabrication 534. The mask house 1630 uses the IC design layout 2422 to fabricate one or more masks, which are to be used in fabricating the various layers of the IC device 1660 according to the IC design layout 2422. The mask house 1630 performs the mask data preparation 1632, in which the IC design layout 1622 is translated into a representative data file (RDF). The mask data preparation 1632 transmits the RDF to the mask fabrication 1634. The mask fabrication 1634 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticule) or a semiconductor wafer. The design layout is processed by the mask data preparation 1632 in such a way that it meets certain properties of the mask writer and / or requirements of the IC-Fab 1640. Fig. Figure 16 illustrates the mask data preparation 1632 and the mask production 1634 as separate elements. In some embodiments, the mask data preparation 1632 and the mask production 1634 can be referred to together as the mask data preparation.

[0110] In some embodiments, the mask data preparation 1632 includes optical proximity correction (OPC), which uses lithography optimization techniques to compensate for image defects, such as those caused by diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 1622. In some embodiments, the mask data preparation 1632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0111] In some embodiments, the mask data preparation 1632 includes a mask rule checker (MRC) that verifies the IC design layout, which has undergone processes in the OPC, against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 534 that may undo some of the modifications made by the OPC to comply with mask generation rules.

[0112] In some embodiments, the mask data preparation 1632 includes a lithography process checking (LPC) that simulates processing implemented by the IC-Fab 1640 to manufacture the IC fixture 1660. The LPC simulates this processing using the IC design layout 1622 to generate a simulated manufactured fixture, such as the IC fixture 1660. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as intermediate image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated manufactured device has been produced by the LPC, if the simulated device does not have the shape accurately enough to comply with design rules, OPC and / or MRC are repeated to further refine the IC design layout 1622.

[0113] It is understood that the above description of mask data preparation 1632 has been simplified for clarity. In some embodiments, mask data preparation 1632 includes additional features, such as a logic operation (LOP) for modifying the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1622 during mask data preparation 1632 can be performed in a variety of different sequences.

[0114] Following mask data preparation 1632 and during mask fabrication 1634, a mask or a group of masks are fabricated according to the modified IC design layout. In some embodiments, an electron beam (E-beam) or a mechanism consisting of multiple E-beams is used to form a structure on a mask (photomask or reticulum) according to the modified IC design layout. The mask can be formed using various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask structure has opaque and transparent regions. A beam, such as an ultraviolet beam (UV beam), used to expose the image-sensitive material layer (for example, the photoresist) deposited on a wafer, is blocked by the opaque region and transmitted through the transparent regions.In one example, a binary mask comprises a transparent substrate (for example, quartz glass) and an opaque material (for example, chromium) that is deposited in the opaque regions of the mask. In another example, the mask is formed using phase-shift technology. In the phase-shift mask (PSM), various features in the structure formed on the mask are configured to have the correct phase difference to increase resolution and image quality. In different examples, the phase-shift mask can be a damped PSM or an alternating PSM. The one or more masks generated by the 534 mask fabrication process are used in a variety of different processes.For example, these one or more masks are used in an ion implantation process to form different doped regions in the semiconductor wafer, in an etching process to form different etched regions in the semiconductor wafer, and / or in other suitable processes.

[0115] The IC-Fab 1640 is an IC manufacturing entity comprising one or more manufacturing facilities for producing a variety of different IC products. In some embodiments, the IC-Fab 1640 is a semiconductor foundry. For example, there may be a first manufacturing facility for the front-end manufacturing of several IC products (e.g., source / drain structures, gate structures), while a second manufacturing facility may handle the middle-end manufacturing for interconnecting the IC products (e.g., MDs, VDs, VGs), and a third manufacturing facility may handle the back-end manufacturing for interconnecting and encapsulating the IC products (e.g., Mo traces, Mi traces, BMo traces, BM1 traces), and a fourth manufacturing facility may provide other services to the foundry entity.

[0116] The IC Fab 1640 uses the one or more masks produced by the Mask House 1630 to fabricate the IC Device 1660. Thus, the IC Fab 1640 uses, at least indirectly, the IC Design Layout 1622 to fabricate the IC Device 1660. In some embodiments, a semiconductor wafer 1642 is fabricated by the IC Fab 1640 using the mask(s) to form the IC Device 1660. The semiconductor wafer 1642 has a silicon substrate or other suitable substrate on which layers of material are formed. The semiconductor wafer further comprises one or more of various doped regions, dielectric features, multi-layer interconnects, and the like (which are formed in subsequent fabrication steps).

[0117] System 1600 is shown such that the Design House 1620, the Mask House 1630, and the IC Fab 1640 are separate components or entities. However, it is understood that one or more of the Design House 1620, the Mask House 1630, or the IC Fab 1640 can also be part of the same component or entity.

[0118] Fig. Figure 17 is a flowchart illustrating an exemplary process 1700 for manufacturing a semiconductor device having the disclosed rear-side SD power lines and / or rear-side MD signal lines, according to various aspects of the present disclosure. Process 1700 can be part of operation 1420 of process 1400 ( Fig. 14). In this respect, the semiconductor device can be manufactured on the basis of at least one section of the layout design disclosed in the present text.

[0119] At least some operations of Method 1700 can be used to form a semiconductor device in a non-planar transistor configuration. For example, the semiconductor device may include one or more gate-all-around transistors (GAA transistors). However, it is understood that the transistors of the semiconductor device may each be configured in any other type of transistor, such as a CFET, without exceeding the scope of protection of this disclosure. It should be noted that Method 1700 is merely an example and that there is no intention to limit this disclosure. Accordingly, it is understood that additional operations may be performed before, during, and / or after Method 1700, and that some other operations may only be briefly described in this text.The following discussions of Procedure 1700 may relate to one or more components of the . Fig. Refer to 1-16.

[0120] In brief, Method 1700 begins with Operation 1702, which involves providing a semiconductor substrate. Method 1700 proceeds to Operation 1704, which involves forming a number of GAA transistors on a front side of the semiconductor substrate. Method 1700 proceeds to Operation 1706, which involves forming a number of first interconnect structures on the front side. Method 1700 proceeds to Operation 1708, which involves forming a number of second interconnect structures on a back side of the semiconductor substrate. The second interconnect structures may include the disclosed SD power lines and MD signal lines.

[0121] According to Operation 1702, the semiconductor substrate can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (for example, with a p-type or n-type dopant) or undoped. The substrate can be a wafer, such as a silicon wafer. In general, an SOI substrate has a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is placed on a substrate, usually a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, can also be used.In some embodiments, the semiconductor material of the substrate may include silicon, germanium, a composite semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof.

[0122] According to Operation 1704, a number of GAA transistors are formed on the front face of the semiconductor substrate. The GAA transistors can each be formed by at least some of the following process steps: forming a fin structure projecting from the substrate, wherein the fin structure has a number of first semiconductor nanostructures and a number of second semiconductor nanostructures stacked alternately on top of each other; forming a dummy gate structure extending over the fin structure; forming gate spacers arranged along opposite sidewalls of the dummy gate structure; omitting portions of the fin structure over which there is no dummy gate structure (and no gate spacer); replacing respective end portions of each second semiconductor nanostructure with a dielectric material to form a number of inner spacers;Forming source / drain structures in the fin structure, arranged on opposite sides of the dummy gate structure; removing the dummy gate structure; removing the remaining second semiconductor nanostructures; and forming an active gate structure (for example, a metal gate structure) that wraps around each of the first semiconductor nanostructures. In some embodiments, the first semiconductor nanostructures can be collectively referred to as a channel of the GAA transistor, and the second semiconductor nanostructures that are replaced by the active gate structure can be referred to as sacrificial nanostructures.

[0123] According to Operation 1706, the first interconnect structures are formed on the front face of the semiconductor substrate. These first interconnect structures can include a number of middle-end-of-line (MEOL) interconnect structures (e.g., MDs, VDs, VGs) and a number of back-end-of-line (BEOL) interconnect structures (e.g., Mo traces, Vos, Mi traces, etc.), as described above. In some embodiments, the MEOL and BEOL interconnect structures can each extend in a single direction. For example, the MDs can all extend along a first lateral direction parallel to the gate structures; the Mo traces can all extend along a second lateral direction perpendicular to the first lateral direction (parallel to a longitudinal direction of the channel); and the Mi traces can all extend along the first lateral direction.Each of the first interconnect structures arranged on the front side can incorporate one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru) or combinations thereof.

[0124] According to Operation 1708, the second interconnect structures are formed on the back side of the substrate. In some embodiments, the second interconnect structure can function as a current line (carrying a current signal) or as a signal line (carrying a non-current signal), with the current line extending along the first or the second direction, while the signal line can extend in more than one direction.The second interconnect structures can be formed by at least some of the following process steps: flipping the semiconductor substrate; thinning the semiconductor substrate from the back side until the undersides of the source / drain structures (or the undersides of dielectric layers beneath the source / drain structures, formed prior to epitaxial growth of the source / drain structures) are exposed; forming a number of vias (e.g., VBs) coupled to each of the source / drain structures; and forming the second interconnect structures (e.g., various BMo traces, as discussed above). Each of the second interconnect structures located on the back side can incorporate one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof.

[0125] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device has a first active region located on a first side of a substrate, extending along a first lateral direction. The semiconductor device has a second active region located on the first side, extending along the first lateral direction. The first active region has a first conductivity type, and the second active region has a second conductivity type opposite to the first conductivity type.The semiconductor device has a first interconnect structure formed on a second side of the substrate opposite the first side, comprising: a first section extending along the first lateral direction and arranged vertically beneath the first active region; and a second section extending along a second lateral direction. The first lateral direction is perpendicular to the second lateral direction.

[0126] In another aspect of the present disclosure, an integrated circuit is disclosed. The integrated circuit has a first row extending along a first direction and a first height extending along a second direction, perpendicular to the first direction. The first row has a first active region formed on a first side of a substrate. The integrated circuit has a second row extending along the first direction and a second height extending along the second direction. The second height is greater than the first height, and the second row has a second active region formed on the first side of the substrate. The integrated circuit has a signal line structure formed on a second side of the substrate opposite the first side. The signal line structure is arranged within the first row.The integrated circuit has a first power conduction structure formed on the second side of the substrate. The first power conduction structure is arranged within the second row.

[0127] In a further aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method comprises forming several transistors on a first side of a substrate. The method comprises coupling the several transistors by forming, on the first side, several first interconnect structures extending either along a first lateral direction or a second lateral direction, the first and second lateral directions being perpendicular to each other. The method comprises forming, on a second side of the substrate opposite the first side, several third interconnect structures. At least one of the third interconnect structures comprises a first section and a second section extending along the first and second lateral directions, respectively.The process involves forming, on the second side, several conductor rail structures that extend along the first lateral direction.

[0128] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 142034

[0001]

Claims

[1] Semiconductor device comprising: a first active region located on a first side of a substrate, extending along a first lateral direction; a second active region located on the first side, extending along the first lateral direction, wherein the first active region exhibits a first conductivity type and the second active region exhibits a second conductivity type opposite to the first conductivity type; and a first interconnect structure formed on a second side of the substrate opposite the substrate, comprising: a first section extending along the first lateral direction and arranged vertically below the first active region; and a second section extending along a second lateral direction, the first lateral direction being perpendicular to the second lateral direction. [2] Semiconductor device according to claim 1, wherein the first interconnect structure is configured to transport a non-current signal. [3] Semiconductor device according to claim 1 or 2, wherein a first end of the second section of the first interconnect structure is connected to the first section of the first interconnect structure. [4] Semiconductor device according to one of the preceding claims, wherein the first interconnect structure has a third section extending along the first lateral direction and arranged vertically below the second active region. [5] Semiconductor device according to claim 4, wherein a second end of the second section of the first interconnect structure is connected to the third section of the first interconnect structure. [6] Semiconductor device according to any one of the preceding claims, further comprising: a third active region located on the first side, extending along the first lateral direction, wherein the third active region has the first conduction type; a fourth active region located on the first side, extending along the first lateral direction, wherein the fourth active region has the second conduction type; several second interconnect structures formed on the first side above the first to fourth active regions, extending along the first lateral direction; a third interconnect structure formed on the second side, extending along the first lateral direction and positioned vertically below the third active region; and a fourth interconnect structure formed on the second side, extending along the first lateral direction and positioned vertically below the fourth active region. [7] Semiconductor device according to claim 6, wherein the number of a first subset of the third interconnect structures electrically coupled to the first and second active regions is less than the number of a second subset of the third interconnect structures electrically coupled to the third and fourth active regions. [8] Semiconductor device according to claim 6 or 7, wherein each of the third and fourth interconnect structures is configured to carry a current signal. [9] Semiconductor device according to one of the preceding claims, further comprising several fourth interconnect structures formed on the second side, each arranged vertically between either the first or the second active region and the second interconnect structure. [10] Semiconductor device according to any of the preceding claims, wherein each of the first and second active regions comprises multiple nanostructures that are vertically separated from each other. [11] Integrated circuit comprising: a first row extending along a first direction and having a first height along a second direction perpendicular to the first direction, wherein the first row has a first active region formed on a first side of a substrate; a second row extending along the first direction and having a second height along the second direction, the second height being greater than the first height, and the second row comprising a second active region formed on the first side of the substrate; a signal transmission structure formed on a second side of the substrate opposite the first side, wherein the signal transmission structure is arranged within the first row; and a first electrical conduction structure formed on the second side of the substrate, wherein the first electrical conduction structure is arranged within the second row. [12] Integrated circuit according to claim 11, wherein the signal line structure partially overlaps the first active region and the first power line structure completely overlaps the second active region. [13] Integrated circuit according to claim 11 or 12, wherein the signal line structure has a first section extending along the first direction and a second section extending along the second direction. [14] Integrated circuit according to claim 13, wherein the first section overlaps the first active region and the second section does not overlap the first active region. [15] Integrated circuit according to claim 13 or 14, wherein respective ends of the first and second sections are connected to each other in such a way that they form an L-shaped profile. [16] Integrated circuit according to one of claims 11 to 15, further comprising a second current conduction structure on the second side of the substrate, wherein the second current conduction structure is adjacent to the first current conduction structure. [17] Integrated circuit according to any one of claims 11 to 16, wherein each of the first and second active regions comprises multiple nanostructures that are vertically separated from each other. [18] Method for manufacturing a semiconductor device comprising: Forming multiple transistors on one side of a substrate; Coupling the multiple transistors by forming, on the first side, multiple first interconnect structures extending either along a first lateral direction or a second lateral direction, with the first and second lateral directions being perpendicular to each other; Forming, on a second side of the substrate opposite the first side, several third interconnect structures, wherein at least one of the third interconnect structures comprises a first section and a second section extending along the first and second lateral directions, respectively; and Forming, on the second side, several conductor rail structures extending along the first lateral direction. [19] Method according to claim 18, wherein the at least one third interconnect structure is configured to carry a non-current signal. [20] Method according to claim 18 or 19, wherein each of the multiple transistors comprises a gate all-around transistor.