Semiconductor package and method for manufacturing a semiconductor package

Abstract

Semiconductor package comprising: a first chip (110), wherein the first chip (110) comprises first bond pads; a second chip (120) arranged above the first chip (110), wherein the second chip (120) has second bond pads, the first bond pads being bonded to the second bond pads, the second chip (120) having a substrate (121) and a plurality of vias (124) extending through the substrate (121), the second chip (120) having a plurality of alignment marks (126), wherein the distance between any two adjacent alignment marks (126) is different from the distance between any two adjacent vias (124); an encapsulation material (130) arranged above the first chip (110), wherein the encapsulation material (130) laterally encapsulates the second chip (120);and a redistribution structure (140) arranged above the second chip (120) and the encapsulation material (130), wherein the redistribution structure (140) has conductive features, the conductive features being electrically connected to corresponding vias (124), wherein the second chip (120) further comprises an insulating layer (125) arranged between the substrate (121) of the second chip (120) and the redistribution structure (140), wherein the plurality of vias (124) extends through the insulating layer (125), and wherein the plurality of alignment markers (126) extends from an upper surface of the insulating layer (125) facing the redistribution structure (140) towards the substrate (121).

Description

PRIORITY

[0001] This application claims priority over US Provisional Application No. 63 / 136,761, entitled “Package and Method of Fabricating the Same”, filed on January 13, 2021, which is hereby incorporated in full by reference. BACKGROUND

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. The various layers are then patterned using lithography to create circuit components and elements. Many integrated circuits are typically fabricated on a single semiconductor wafer. The wafer's chips can be processed and packaged at the wafer level, and various wafer-level packaging technologies have been developed. List of characters

[0003] Aspects of the present disclosure are best understood from the following detailed description when considered in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily increased or decreased to enhance clarity. Fig. 1 to Fig. 10 illustrate cross sectional views of intermediate stages in the manufacturing of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 11 shows a schematic view of alignment markings of a semiconductor package according to some embodiments of the present disclosure. Fig. 12 to Fig. Figure 16 shows schematic top views of various alignment markings according to some embodiments of the present disclosure. Fig. Figure 17 shows a schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 18 shows a schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 19 shows a schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 20 shows a schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 21 shows a schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 22 shows a schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 23 shows a schematic cross-sectional view and enlarged partial views of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 24 shows a schematic cross-sectional view and enlarged partial views of a semiconductor package according to some embodiments of the present disclosure. Fig. 25 to Fig. Figure 26 shows cross-sectional views of intermediate stages in the manufacture of a semiconductor package according to some embodiments of the present disclosure. Fig. 27 to Fig. Figure 28 shows cross-sectional views of intermediate stages in the manufacture of a semiconductor package according to some embodiments of the present disclosure. Fig. 29 to Fig. Figure 32 shows cross-sectional views of intermediate stages in the manufacture of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 33 shows a partial top view of a chip of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 34 shows a schematic top view and an enlarged partial view of a chip of a semiconductor package according to some embodiments of the present disclosure. Fig. Figure 35 shows a schematic top view and an enlarged partial view of a chip of a semiconductor package according to some embodiments of the present disclosure. Fig. 36 to Fig. Figure 37 shows cross-sectional views of intermediate stages in the manufacture of a semiconductor package according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples of the implementation of various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features do not have to be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself represent a relationship between the various designs and / or configurations discussed.

[0005] Furthermore, to simplify the description, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like can be used to describe the relationship of one element or feature to another, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative terms used here can be interpreted accordingly.

[0006] A semiconductor package and the method for fabricating a semiconductor package are provided according to various exemplary embodiments. In some embodiments, the semiconductor package can be a System on Integrated Chip (SoIC) package, and the intermediate stages of forming the SoIC package are shown according to some embodiments. Some variations of certain embodiments are discussed. In the various views and illustrative embodiments, the same reference numbers are used to denote the same elements. Although the formation of SoIC packages is used as an example to explain the concept of the embodiments of this disclosure, the embodiments of this disclosure are readily applicable to package structures and packaging methods in which the orientation markers and vias (substrate) are formed on one of the chips.

[0007] Fig. 1 to Fig. Figure 10 shows cross-sectional views of intermediate stages in the fabrication of a semiconductor package according to some embodiments of the present disclosure. According to some embodiments of the present disclosure, the fabrication process of a semiconductor package may comprise the following steps. Referring to Fig. 1. A first chip 110 is provided, and a second chip 120 is bonded to the first chip 110. In some embodiments, the first chip 110 and the second chip 120 can each be an application-specific integrated circuit (ASIC), a system-on-chip (SoC), an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, a logic chip such as a central processing unit (CPU) chip, a micro control unit (MCU) chip, a baseband (BB) chip, an application processor (AP) chip, or a memory chip such as a dynamic random access memory (DRAM) chip or a static random access memory (SRAM) chip, or other types of chips. The first chip 110 and the second chip 120 can be the same type of chip or different types of chips, and the types of chips are not limited in the disclosure.Various suitable joining techniques can be used to connect the first chip 110 and the second chip 120. For example, the second chip 120 can be joined to the first chip 110 by hybrid bonding, fusion bonding, or similar methods, or combinations thereof. Although the figures show one chip 110 and one chip 120, the number of chips 110 and 120 is not limited in the disclosure.

[0008] In some embodiments, the first die 110 can be a chip contained in a semiconductor wafer at the present stage. Although one die 110 is shown, it is understood that the semiconductor wafer has a plurality of dies 110, each located within a die region of the wafer and separated from one another by scribble regions. The singulation of the dies 110 can be carried out in subsequent processes. The second die 120 can be a chip that has been singulated from another semiconductor wafer and mounted over the first die 110 by pick-and-place processes. In some embodiments, the first chip 110 and the second chip 120 can have similar structures, and the detailed structure of the dies is described below.

[0009] In some embodiments, the first chip 110 comprises a semiconductor substrate 111, at least one integrated circuit element 1131, an interconnect structure 113, and a plurality of conductive pads 112. The integrated circuit device 1131 may include transistors and / or diodes, passive devices (e.g., capacitors, inductors, resistors, or the like), or the like. For brevity, the integrated circuit device 1131 is omitted from the following drawings. According to some embodiments of the present disclosure, the first chip 110 is a logic chip, which may be a central processing unit (CPU) chip, a micro control unit (MCU) chip, an input-output (IO) chip, a baseband (BB) chip, an application processor (AP) chip, or the like. In some embodiments, the first chip 110 may also be a memory chip, such as... For example, a DRAM chip (Dynamic Random Access Memory), an SRAM chip (Static Random Access Memory), or similar.In accordance with some embodiments of the present disclosure, the first chip 110 can be an interposer wafer that is free of active components such as transistors and / or diodes. In some embodiments, the first chip 110 can be free of passive components such as capacitors, inductors, resistors or the like, or it can include passive components.

[0010] According to some embodiments of the present disclosure, the semiconductor substrate 111 can be formed from crystalline silicon, crystalline germanium, crystalline silicon-germanium, and / or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and the like. In some embodiments, the semiconductor substrate 111 can also have other features such as various doped regions, buried layer(s), and / or epitaxial layer(s). The semiconductor substrate 111 can also be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or silicon on sapphire, or the like. Shallow trench isolation (STI) regions (not shown) can be formed in the semiconductor substrate 111 to isolate the active regions within the semiconductor substrate 111.Although not shown, a variety of vias can be formed extending into the semiconductor substrate 111, and the vias can be used to electrically couple the conductive features (e.g. conductive pads 112) on opposite sides of the first chip 110.

[0011] According to some embodiments of the present disclosure, the first chip 110 comprises at least one integrated circuit device 1131 formed on the upper surface of the semiconductor substrate 111. The integrated circuit device 1131 may comprise a CMOS transistor (complementary metal-oxide semiconductor), a resistor, a capacitor, a diode, a photodiode, a fuse, or the like, or combinations thereof. For brevity, the details of the integrated circuit device 1131 are not shown here. In accordance with some embodiments, the first chip 110 is used to form intermediate switches, wherein the semiconductor substrate 111 may be a semiconductor substrate or a dielectric substrate.

[0012] In some embodiments, the first chip 110 may also include an interconnection structure 113 (represented abstractly as a layer for simplicity) formed on top of the semiconductor substrate 111 to electrically connect the various integrated circuit devices 1131 and form a functional circuit. The interconnection structure 113 may include metallization structures (e.g., conductive traces and vias) embedded in one or more dielectric layers, such as the dielectric intermediate layers (ILDs) and the dielectric intermediate metal layers (IMDs). The ILD is formed on top of the semiconductor substrate 111 and fills the space between the gate stacks of the transistors (not shown) in the integrated circuit device 1131.In accordance with some embodiments, the ILD may be formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. In some embodiments, the ILD may be formed by spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like. In some embodiments, a plurality of contact channels are formed in the ILD, which are used for the electrical connection of integrated circuits 1131 to overlying metal conductors and channels.

[0013] The IMD layers are located above the ILD. According to some embodiments of this disclosure, some of the IMD layers (e.g., the lower IMD layers) are formed from a low-k dielectric material having a dielectric constant (k-value) of less than about 3.0 or about 2.5. The IMD layers may be formed from Black Diamond® (a registered trademark of Applied Materials), a low-k carbon dielectric material, Hydrogen SilsesQuioxane (HSQ), Methyl SilsesQuioxane (MSQ), or the like. According to some embodiments of this disclosure, some or all of the IMD layers are formed from non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbononitrile (SiCN), silicon oxycarbonitrile (SiOCN), or the like.

[0014] In some embodiments, the metallization structures comprise a variety of conductive features interconnected and embedded within one or more dielectric layers. The conductive features may include multiple layers of conductive lines, conductive vias, and conductive contacts. The conductive contacts may be formed within the integrated circuit devices (ILDs) to electrically connect the conductive lines to the integrated circuit elements 1131, and the conductive vias may be formed within the integrated circuit devices (IMDs) to electrically connect the conductive lines in different layers. The conductive features of the metallization structures may be made of metal, a metal alloy, or a combination thereof. For example, the conductive features may be tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof.In some embodiments, the uppermost conductive features of the metallization structure have upper surfaces that are essentially coplanar (e.g., within process variations) with an upper surface of the dielectric structure, but the disclosure is not limited thereto.

[0015] In some embodiments, the conductive pads 112 are formed in the dielectric surface layer of the interconnect structure 113. According to some embodiments of the present disclosure, the conductive pads 112 are formed by a single damascus process and may also include barrier layers and a copper-containing material formed over the respective barrier layers. In accordance with alternative embodiments of the present disclosure, the conductive pads 112 are formed by a dual damascus process. The top-side dielectric layer and the conductive pads 112 are planarized such that their top surfaces are coplanar within process variations that may arise due to the CMP during the formation of the conductive pads 112. The conductive pads 112 are configured for bonding to other device chips (e.g., the second chip 120).

[0016] In some embodiments, which still refer to Fig. Referring to the first chip 110, the second chip 120 comprises a structure that may be similar to that of the first chip 110. For example, the second chip 120 comprises a substrate 121, at least one integrated circuit device 1231, an interconnection structure 123 (represented abstractly as a layer for simplicity), and a plurality of bond pads 122 connected to the conductive pads 112 of the first chip 110. The interconnection structure 123 is formed on top of the substrate 121 to electrically connect the various integrated circuit components 1231 and form a functional circuit.The materials and configurations of the substrate 121, the integrated circuit device 1231, the interconnect structure 123 and the bond pads 122 of the second chip 120 may be substantially similar and formed using similar processes and / or materials as described above in relation to the first chip 110, which are not described again here.

[0017] According to some embodiments of the present disclosure, the second chip die 120 may comprise a logic die, such as a central processing unit (CPU) die, a micro control unit (MCU) die, an input-output (IO) die, a baseband (BB) die, an application processor (AP) die, or the like. In some embodiments, the second chip 120 may also comprise a memory chip, such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, or the like. Furthermore, a plurality of second chips 120 may be bonded via the first chip 110, and the second chips 120 may be different types of chips selected from those listed above. In addition, one of the second chips 120 may be a digital circuit chip, while the other may be an analog circuit chip.In some embodiments, the first chip 110 can be a logic die, while the second chip 120 can be a memory die, and the chips 110 and 120 function together as a system. Distributing the functions and circuitry of a system across different chips, such as chips 110 and 120, can optimize the manufacturing of these chips and reduce production costs.

[0018] In some embodiments, the second chip 120 also comprises a plurality of vias (substrate) 124 formed in the substrate 121, which may be electrically connected to conductive features in the interconnect structure 123 and the bond pads 122. In some embodiments, the vias 124, sometimes also referred to as semiconductor vias or substrate vias, are configured to penetrate the semiconductor substrate 121. The vias 124 are used to connect the integrated circuit components 1231 and the metal conductors formed on the front (the underside shown) of the substrate 121 to the back. In some embodiments, the vias 124 may extend into the interconnect structure 123 to be in physical and electrical contact with the conductive features of the interconnect structure 123.In some embodiments, the vias 124 may have one or more linings (not shown) to cover their surface. The lining is arranged between the via 124 and the substrate 121 to separate the via 124 from the substrate 121. The lining may surround the side walls and / or the top surface of the via 124. The via 124 may comprise copper, copper alloys, aluminum, aluminum alloys, Ta, TaN, Ti, TiN, CoW, or combinations thereof. The lining may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or combinations thereof.

[0019] In some embodiments, the second chip 120 is connected to the first chip 110 by a hybrid bonding process, and the hybrid bonding comprises at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding, such as dielectric-to-dielectric bonding. In other words, the bond pads 122 of the second chip 120 are each in direct contact with the conductive pads 112 of the first chip 110. In some embodiments, the bonding pads 122 of the second chip 120 are connected to the conductive pads 112 of the first chip 110 by metal-to-metal bonding, while the dielectric layer of the second chip 120 is connected to the dielectric layer of the first chip 110 by dielectric-to-dielectric bonding. According to some embodiments of the present disclosure, the metal-on-metal bonding may include direct copper-on-copper bonding.Furthermore, dielectric-to-dielectric bonding can include fusion bonding. In some embodiments, the bonding process can include the following steps. First, the surfaces to be joined of the second chip 120 and the first chip 110 can be prepared to avoid the occurrence of unbonded areas (i.e., interface bubbles) so that the bonding surface is sufficiently clean and smooth. Then, the second chip 120 can be removed and placed onto the first chip 110. In some embodiments, the first chip 110 and the second chip 120 are aligned and brought into physical contact at room temperature with slight pressure to initiate an adhesive process. Afterward, a thermal treatment, such as…An annealing process is carried out to effect the interdiffusion of the metals in the conductive pads 112 of the first chip 110 and the corresponding bond pads 122 above them of the second chip 120, and to convert the chemical bonds into covalent bonds. The bond pads 122 can be larger, equal to, or smaller than the size of the respective conductive pads 112.

[0020] Through hybrid bonding, the bond pads 122 are connected to the corresponding conductive pads 112 by direct metal-to-metal bonding caused by metal interdiffusion. The dielectric layer of the second chip 120 is also connected to the dielectric layer of the first chip 110, with bonds forming between them. For example, the atoms (e.g., oxygen atoms) in one of the dielectric layers of the second chip 120 form chemical or covalent bonds with the atoms (e.g., silicon atoms) in one of the dielectric layers of the first chip 110. The resulting bonds between the dielectric layers of the first chip 110 and the second chip 120 are dielectric-to-dielectric bonds. In other words, a bonding interface exists between the first chip 110 and the second chip 120.In some embodiments, the bonding interface is a hybrid bonding interface comprising a metal-to-metal bonding interface between the conductive pads 112 and the bonding pads 122 and a dielectric-to-dielectric bonding interface between the dielectric layers of the first chip 110 and the second chip 120.

[0021] In some embodiments, the second chip 120 is bonded to the first chip 110 in a face-to-face configuration. That is, the front (active) surface of the second chip 20 faces the front surface of the first chip 110. However, the disclosure is not limited to this. In some embodiments, the second chip 120 may be bonded to the first chip 110 in a face-to-back configuration. In other words, the front of the second chip 120 may face the back of the first chip 110. Throughout this description, a "front surface" of a chip refers to a surface that has the components (e.g., the integrated circuit device 1131 / 1231) or is located near the conductive pads (e.g., the conductive pads 112 / 122) and may also be referred to as an active surface.A "back surface" of a chip is a surface that faces the front surface and can be a surface of the substrate, which can also be referred to as the back surface.

[0022] Although two device chips 110 and 120 are shown, hybrid bonding can be performed at the wafer level, and a plurality of device chip groups identical or similar to the chip group shown (comprising device chips 110 and 120) are pre-bonded and arranged in rows and columns. In some embodiments, hybrid bonding can also be a die-to-wafer bonding process. The disclosure is not limited to this.

[0023] With reference to Fig. 2 In some embodiments, after the second chip 120 is connected to the first chip 110, a back-side grinding process can be performed to thin the second chip 120 and expose the vias 124. As shown in Fig. As shown in Figure 2, in some embodiments the vias 124 can extend through the substrate 121 and be exposed from the top surface (e.g., the back) of the second chip 120, the top surfaces of the vias 124 being substantially coplanar with the top surface (e.g., the back) of the substrate 121 within process variations. In some embodiments, the vias 124 cannot be exposed at this time, and the back-side grinding is stopped when a thin layer of the substrate 121 covers the vias 124. In some embodiments, the back-side grinding process can be skipped. In some embodiments, the vias 124 can be exposed in the Fig. 2 or Fig. The 3 steps shown will be exposed.

[0024] As in Fig. As shown in Figure 2, an encapsulation material 130 is provided over the first chip 110 to cover the sidewalls and the top surface of the second chip 120. In some embodiments, the encapsulation material 130 can be a molding compound, a mold underfill, an epoxy, a resin, or the like, or a combination thereof. In such embodiments, the encapsulation material 130 can be formed by a molding process, a molding underfilling (MUF) process, or the like. In some embodiments, the encapsulation material 130 can comprise silicon oxide or TEOS, while other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxycarbonnitride, PSG, BSG, BPSG, or the like can also be used. In such embodiments, the encapsulation material 130 can be produced by CVD, high-density plasma chemical vapor deposition (HDPCVD), flowable CVD, spin-on coating, or the like.

[0025] In some embodiments, the top surface of the encapsulation material 130 may initially be higher than the back surface of the second chip 120, meaning that the encapsulation material 130 covers the back surface of the second chip 120. A planarization process is then performed to remove a portion of the encapsulation material 130 above the top surface of the second chip 120, so that the encapsulation material 130 laterally encapsulates the second chip 120. The planarization process may include a chemical-mechanical polishing (CMP) process. In some embodiments, where the vias 124 are located in the step of Fig. If 1 is not exposed, the planarization process can continue to remove part of the substrate 121 above the top of the vias 124 to expose the vias 124.

[0026] In some embodiments, multiple planarization processes can be performed. For example, in some embodiments, a first planarization process can be performed on the in Fig. The structure shown in Figure 1 is used to first thin the second chip 120. After this first planarization process, the vias 124 can remain covered by the substrate 121. Following this first planarization, the encapsulation material 130 can be formed, and then a second planarization process can be performed to remove excess encapsulation material 130 and further thin the substrate 121 to expose the vias 124.

[0027] After the formation of the encapsulation material 130 and the execution of one or more planarization processes, the encapsulation material 130 covers a portion of the top surface of the first chip 110 and the sidewalls of the second chip 120. In some embodiments, the top surface of the encapsulation material 130 is substantially coplanar with the top surface of the second chip 120 within process variations. In one embodiment, the top surface of the encapsulation material 130 is substantially coplanar with the top surface (e.g., the back surface) of the substrate 121 and the top surface of the vias 124 of the second chip 120 within process variations. In some embodiments, the encapsulation material 130 can also be described as a gap-filling dielectric layer, an insulating structure, or a dielectric structure.

[0028] Referring to Fig. 3 In some embodiments, a rear portion of the substrate 121 of the second chip 120 is removed, so that the vias 124 protrude from the rear of the substrate 121 and recesses RC are formed transversely across the substrate 121. In some embodiments, the encapsulation material 130 and the vias 124 define the sidewalls of the recesses RC. In some embodiments, the removal of the rear portion of the substrate 121 is achieved by further thinning of the substrate 121. For example, the rear portion of the substrate 121 can be removed laterally adjacent to the vias 124 by an etching process, e.g., a wet etching process, a dry etching process, or a combination thereof. The etching process can exhibit a high etch selectivity ratio between the substrate 121 and other adjacent materials (e.g., the encapsulation material), the vias 124, etc.In some embodiments, the encapsulation material 130 cannot be substantially removed by the etching process, but the disclosure is not limited thereto. In some embodiments, a portion of the encapsulation material 130 can also be removed by the etching process. After the thinning process (e.g., by etching) has been performed, the top surface of the substrate 121 is lower than the top surface of the vias 124 and the top surface of the encapsulation material 130. In other words, the vias 124 have a portion that protrudes from the top surface of the substrate 121. In some embodiments, the recesses RC can have a depth in the range of about 0.5 µm to about 2 µm.

[0029] With reference to Fig. 4. An insulating layer 125 is provided over the substrate 121 of the second chip 120 and the encapsulation material 130 to cover the top surface of the substrate 121. In some embodiments, the insulating layer 125 can also cover the top surfaces of the vias 124 and the top surface of the encapsulation material 130. In some embodiments, the insulating layer 125 is a conformal layer, i.e., the insulating layer 125 has a substantially uniform thickness extending along the area on which the insulating layer 125 is formed.The insulating layer 125 can consist of a dielectric material such as silicon nitride (SiN), HDP OX(SiO2), TEOS OX(SiO2), silicon oxide, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), oxygen-doped silicon carbide, nitrogen-doped silicon carbide, a polymer which may be a photosensitive material such as PBO, polyimide or BCB, a dielectric material with a low K-value such as PSG, BPSG, FSG, SiO. x C ySOG, spin-on polymers, silicon-carbon materials, compounds thereof, composites thereof, combinations thereof, or the like may also be used for the insulating layer 125. The insulating layer 125 may be formed by a suitable deposition process, such as CVD, atomic layer deposition (ALD), or the like. In some embodiments, the insulating layer 125 is configured to have a thickness that is at least equal to the height of the recesses RC (i.e., the thickness of the portion of the vias 124 that protrudes from the substrate 121). In other words, the insulating layer 125 completely fills the recesses RC.

[0030] A planarization process is then performed to remove a portion of the insulating layer 125 above the top surface of the vias 124, exposing the vias 124 and forming an insulating layer 125. Thus, the vias 124 extend through the insulating layer 125. The planarization process may include a CMP process. The insulating layer 125 is located on the substrate 121 and laterally encapsulates the portions of the vias 124 that protrude from the substrate 121. In some embodiments, the insulating layer 125 is located laterally between the vias 124 and the encapsulation material 130. The top surface of the insulating layer 125 may be substantially coplanar with the top surfaces of the vias 124 and the top surface of the encapsulation material 130, depending on the process. In some embodiments, the formation of the Fig. 3 to Fig. The insulating layer 125 shown in Figure 4 is omitted. In some embodiments, the insulating layer can be formed before the encapsulation material 130 is formed, and the insulating layer can extend along the top surface and sidewalls of the second chip 120 and the top surface of the first chip 110. In some embodiments, the insulating layer can extend further to cover the top surface of the encapsulation material 130. In some embodiments, the insulating layer 125 can have a thickness in the range of about 0.5 µm to about 2 µm.

[0031] With reference to Fig. 5 and Fig. 6. A plurality of alignment marks 126 are formed on the second chip 120. In some embodiments, the formation of the alignment marks 126 may comprise the following steps. First, a mask layer PR is provided over the top surface of the second chip 120 (e.g., the insulating layer 125). The mask layer PR may comprise photosensitive material, including organic materials, and may be a positive or negative photosensitive material. The mask layer PR is deposited over the insulating layer 125, e.g., by a spin-deposition process. After deposition, the mask layer PR may be exposed to a structured energy source (e.g., a structured light source) to induce a chemical reaction in the portions of the mask layer PR exposed to the structured light source.A developer is then applied to the exposed mask layer PR to exploit the physical changes and, depending on the desired pattern, selectively remove either the exposed or the unexposed part of the mask layer PR to create the desired pattern (e.g., openings on the mask layer PR) for the alignment marks 126. Other masking materials can be used instead of or in addition to the photosensitive material.

[0032] After the mask layer PR has been structured, the pattern of the mask layer PR is transferred to the insulation layer 125 (and optionally the substrate 121 of the second chip 120) by an etching process. That is, the etching process is carried out to form a multitude of openings OP on the insulation layer 125. The etching process is anisotropic, so that the openings in the mask layer PR extend through the insulation layer 125 and have approximately the same size (or are slightly smaller) in the insulation layer 125 as in the mask layer PR.

[0033] The alignment markings 126 are then formed within the openings OP. In one embodiment, the alignment markings 126 are formed by filling the openings OP with a material that differs from the surrounding material. In some embodiments, the alignment markings consist of a conductive material that is easily distinguishable from the surrounding material. For example, the alignment markings 126 may comprise one or more conductive materials such as copper, tungsten, other conductive metals, or the like, and may be formed, for example, by electroplating, electroless plating, or similar processes. The conductive material of the alignment markings 126 may be the same as that of the vias 124.In some embodiments, the conductive material of the alignment markers 126 may differ from the conductive material of the vias 124, as they are formed by different processes in separate steps. In other embodiments, the alignment markers 126 are formed by filling the openings OP with dielectric material, as described below. Subsequently, the mask layer PR can be removed by a suitable removal method, such as an ashing process. In one embodiment, a plasma ashing process can be used to remove the mask layer PR, whereby the temperature of the mask layer PR can be increased until it undergoes thermal decomposition and can be removed. Alternatively, however, any other suitable method, such as wet etching, can be used.In some embodiments, a planarization process can be performed on the top surfaces of the insulating layer 125, the vias 124, and the alignment marks 126. The planarization process may include a grinding process. The resulting structure is shown in . Fig. Figure 6 shows that, due to the planarization process, the top surfaces of the vias 124 are essentially flat with the top surfaces of the alignment marks 126 and essentially flat with the top surface of the insulating layer 125. In some embodiments, the alignment marks 126 can have a thickness in the range of about 0.3 µm to about 3 µm.

[0034] Fig. Figure 11 shows a schematic view of orientation markings of a semiconductor package according to some embodiments of the present disclosure. Referring to Fig. 6 and Fig. 11 According to some embodiments of the disclosure, since the alignment markings 126 and the vias 124 are formed by different processes in separate steps, the distance P2 between two adjacent alignment markings 126 may differ from the distance P1 between two adjacent vias 124. In some embodiments, the sizes (e.g., diameter, depth) of the alignment markings 126 may also differ from those of the vias 124. In some embodiments, the distance P2 of the alignment markings 126 is significantly smaller than the distance P1 of the vias 124. In some embodiments, the alignment markings 126 may have a different set of distances P21, P22, P23, P24, as shown in Fig. Figure 11 shows. In some embodiments, the alignment markings 126 can be composed of a plurality of subsets of alignment markings 1261, 1262, 1263, 1264, and the corresponding divisions P21, P22, P23, P24 of the subsets of alignment markings 1261, 1262, 1263, 1264 are different from each other. For example, the divisions P21 and the diameters of the alignment marks 1261 can be in a range of about 7µm to about 9µm (e.g. 8µm), the divisions P22 and the diameters of the alignment marks 1262 can be in a range of about 1µm to about 2µm (e.g. 1.6µm), the spacings P23 and the diameters of the alignment marks 1263 can be in a range of about 0.5µm to about 0.8µm (e.g. 1.15µm), and the spacings P24 and the diameters of the alignment marks 1264 can be in a range of about 8µm to about 10µm (e.g. 8.8µm).In some embodiments, the spacing P1 of the vias 124 can be approximately 2 µm to approximately 6 µm, and the diameter of each via 124 can be approximately 2 µm. However, the dimensions and figures listed above are for illustrative purposes only, and the disclosure is not limited thereto. Accordingly, the flexibility in the design of the alignment markers 126 is increased, and the alignment markers 126 are able to meet a fine pitch requirement (at least less than or approximately equal to 2 µm) for improved resolution. In some embodiments, the spacing P2 between two adjacent alignment markers 126 can be 0.4 µm or less. In some embodiments, the total length L1 of the alignment markers 126 (including the lengths of the alignment markers 1261, 1262, 1263, 1264) is approximately 800 µm to 830 µm (e.g.,822µm), and a width W1 of the alignment marks 126 is about 50µm to about 70µm (e.g. 60µm), but the disclosure is not limited to this.

[0035] According to some embodiments of the disclosure, the alignment markers 126 enable the identification of a correct orientation of the chip. In some embodiments, the alignment markers 126 are dummy structures in the sense that the alignment markers 126 are not electrically coupled to the bond pads 122 or the vias 124. In some embodiments, the alignment markers 126 can be electrically coupled to the bond pads 122 and subsequently formed by the vias 124. In some embodiments, the alignment markers 126 can be grounded. The alignment markers 126 can include a photoalignment marker, a scanning electron microscope (SEM) marker, and other alignment markers. The alignment markers 126 can serve as an alignment feature during photolithographic processing, testing, inspection, or measurement.

[0036] With reference to Fig. 7 and Fig. 8 will be a redistribution structure 140 (see Fig. 8) formed over the second chip 120 (e.g., the insulating layer 125) and the encapsulation material 130. Thus, the insulating layer 125 is arranged between the substrate 121 of the second chip 120 and the redistribution structure 140, and the alignment markings 126 extend from an upper surface of the insulating layer 125 facing the redistribution structure 140 and extend towards the substrate 121 of the second chip 120. Fig. Figure 7 illustrates the formation of the first layer 142 of the redistribution structure 140. In detail, for example, one or more dielectric layers, referred to for illustration as dielectric layer 1423, can be formed over the second chip 120 and the encapsulation material 130 to cover the top surfaces of the second chip 120 (e.g., the insulating layer 125) and the encapsulation material 130. The dielectric layer 1423 can be an oxide, such as silicon oxide, a nitride, such as silicon nitride, USG, or similar, or combinations thereof. The dielectric layer 1423 can be formed by a suitable deposition method, such as CVD. Subsequently, a plurality of the through-hole dielectric vias 1421 and the redistribution layer 1422 are formed, for example, by a single / double damascus process.In some embodiments, the alignment markers 126 can be used during the formation of the redistribution structure 140 to identify and align the relative position between the chip 120 and the features of the redistribution structure 140 (e.g., the dielectric vias and redistribution layers). In some embodiments, the alignment markers 126 do not overlap with conductive layers (e.g., dielectric vias and redistribution layers) of the redistribution structure 140 when viewed from above, so that the alignment markers 126 are not blocked during the alignment process.

[0037] In some embodiments, a structuring process is performed to form a multitude of vias and a multitude of trenches in the dielectric layer 1423. During the structuring process, a portion of the dielectric layer 1423 is removed to expose the top surfaces of the vias 124 of the second chip 120. The structuring process may include several photolithography and / or etching processes. The sidewalls of the vias and trenches may be straight or inclined. The vias and trenches are then filled with conductive material to provide the necessary connectivity. Fig. The conductive material comprises a suitable metallic material, such as copper or a copper alloy. In some embodiments, the method for forming the conductive material may include a plating process, such as an electroplating or electrochemical plating process, or a suitable deposition process, such as CVD, PVD, or the like. Subsequently, a planarization process, such as a CMP process, may be performed to remove excess portions of the conductive material until the dielectric layer 1423 is exposed. In some embodiments, after the planarization process, the top surfaces of the dielectric vias 1421 and the redistribution layer 1422 are substantially coplanar with the top surface of the dielectric layer 1423 within process variations.

[0038] With reference to Fig. In some embodiments, a passivation layer 1443 is formed over the dielectric layer 1423, and vias 1441 are formed in the passivation layer 1443 to establish an electrical connection with the redistribution layer 1422. A redistribution layer (or conductive pads) 1442 is then formed over the passivation layer 1443 and the vias 1441 and electrically connected to the redistribution layer 1422 via the vias 1441. The material of the redistribution layer (or conductive pads) 1442 and the vias 1441 can each comprise a suitable metallic material, such as aluminum, copper, alloys thereof, or combinations thereof. In some embodiments, the conductive pads 1442 can be aluminum pads or aluminum-copper pads, but other metallic materials can also be used.The vias 1441 and the conductive pads 1442 can be configured separately with an interface in between or simultaneously without an interface in between.

[0039] In some embodiments, a passivation layer 1445 can be formed over the passivation layer 1443 to encapsulate the conductive pads 1442, at least laterally. The passivation layers 1443 and 1445 can each be a single layer or a composite layer and can be formed from a non-porous material. In some embodiments, each of the passivation layers 1443 and 1445 can comprise silicon oxide, silicon nitride, or a combination thereof. In some embodiments, one or both of the passivation layers 1443 and 1445 are a composite layer comprising a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) over the silicon oxide layer. The passivation layers 1443 and 1445 can also be formed from other non-porous dielectric materials such as undoped silicate glass (USG), silicon oxynitride, and / or the like, or combinations thereof.Then a planarization process, such as a CMP process, can be performed to remove excess portions of the passivation layer 1445 until the conductive pads 1442 are exposed. In some embodiments, after the planarization process, the top surfaces of the conductive pads 1442 are essentially coplanar with the top surface of the passivation layer 1445.

[0040] At this stage, the resulting package structure can be in the form of a wafer and can then be mounted onto a dicing tape (e.g., a frame). Subsequently, the package structure can be singulated or diced (e.g., along dicing lines), forming a multitude of semiconductor packages, each substantially identical or similar to the one in Fig. The semiconductor package shown in 8 can be 100.

[0041] With reference to Fig. 9 and Fig. 10 According to some embodiments of the disclosure, the semiconductor package 100 described above can be applied to an integrated fan-out (InFO) package method to create a Fig. The package-on-package structure shown in Figure 10 is formed. In detail, some embodiments can be described, now with reference to… Fig. 8 and Fig. 9, which in Fig. The semiconductor package 100 shown in Figure 8 is provided on a support C1 such that a back face of the semiconductor substrate 111 of the first chip 110 is attached to the support C1. In some embodiments, the support C1 can be a glass support, a ceramic support, or the like. An adhesive layer AD, such as a light-to-heat-conversion (LTHC) release coating or the like, can be arranged on the support C1. In some embodiments, a dielectric layer 400 can optionally be arranged over the support C1 (e.g., on the adhesive layer AD).

[0042] When placing the semiconductor package 100, the alignment marks 126 are used to align the position of the semiconductor package 100 (e.g., the second chip 120 of the semiconductor package 100) to ensure that the semiconductor package 100 is placed in the desired location and that it does not shift or rotate from its intended position and orientation. The alignment is achieved by determining the relative position of the semiconductor package 100 with respect to the positions of the alignment marks 126.

[0043] In some embodiments, the vias 500 can be pre-formed and then placed on the substrate C1. In other embodiments, the vias 500 can be formed, for example, by an electroplating process. The electroplating of the vias 500 can be performed before the placement of the semiconductor package 100 and can include the formation of a seed layer (not shown) over the substrate C1, the formation and structuring of a photoresist layer (not shown), and the electroplating of the vias 500 on the portions of the seed layer exposed by the photoresist layer. The photoresist layer and the portions of the seed layer covered by the photoresist layer can then be removed. The semiconductor package 100 can then be placed over the substrate C1.The material of the through-hole vias 500 can be copper, aluminum, or similar. Accordingly, the lower ends of the through-hole vias 500 are essentially at the same level as the back of the semiconductor package 100. In some embodiments, the through-hole vias 500 can be provided after the semiconductor package 100 has been placed.

[0044] Subsequently, the semiconductor package 100 and the interlayer vias 500 on the substrate C1 are encapsulated with an encapsulation material 200. In other words, the encapsulation material 200 is provided over the substrate C1 to encapsulate the semiconductor package 100 (e.g., the first chip 110, the encapsulation material 130, and the in Fig. 8 redistribution structure 140) and the interlayer vias 500 to encapsulate at least the sides. In some embodiments, the encapsulation material 200 fills the gaps between the semiconductor package 100 and the interlayer vias 500. Thus, the interlayer vias 500 extend through the encapsulation material 200. The encapsulation material 200 can be a molding compound, an epoxy, or a resin, etc. In some embodiments, an upper surface of the encapsulation material 200 can initially be higher than the upper ends of the interlayer vias 500 and the upper surface of the semiconductor package 100 (e.g., the upper surface of the in Fig. (Redistribution structure 140 shown in Figure 8). The encapsulation material 200 covers the top ends of the vias 500 and the top surface of the semiconductor package 100. A thinning process, which may be a grinding process, is then performed to thin the encapsulation material 200 until the top ends of the vias 500 and the top surfaces of the conductive pads 1442 of the semiconductor package 100 are exposed. Due to the thinning process, the top ends of the vias 500 are essentially flush with the top surfaces of the encapsulation material 200.

[0045] Then a redistribution structure 300 is placed over the semiconductor package 100 (e.g., the encapsulation material 130 and the one in Fig. The redistribution structure 300 is formed by the redistribution structure 140 shown in Figure 8 and the encapsulation material 200. The redistribution structure 300 is electrically connected to the semiconductor package 100 and the through-hole vias 500. In some embodiments, the conductive features of the redistribution structure 300 are electrically connected to the conductive pads 1442 of the semiconductor package 100 and the through-hole vias 500. In some embodiments, the redistribution structure 300 can also connect the conductive pads 1442 and the through-hole vias 500 to each other.

[0046] The redistribution structure 300 can be formed, for example, by first depositing a dielectric layer (not shown separately) onto the encapsulation material 130, the interlayer vias 500, and the semiconductor package 100. In some embodiments, the dielectric layer is formed from a photosensitive material such as PBO, polyimide, BCB, or the like, which can be patterned using a lithography mask. The dielectric layer can be formed by spin coating, lamination, CVD, or a combination thereof. The dielectric layer is then patterned to create openings that expose portions of the interlayer vias 500 and / or the conductive pads 1442 of the semiconductor package 100. The patterning can be performed by an acceptable method, e.g.,by exposing and developing the dielectric layer, if the dielectric layer is a photosensitive material, or by etching, e.g. with an anisotropic etching process.

[0047] Subsequently, a metallization pattern is formed over the dielectric layer. The metallization pattern comprises conductive elements that extend along the main surface of the dielectric layer and through the dielectric layer to establish a physical and electrical connection with the vias 500 and / or the conductive pads 1442 of the semiconductor package 100. To form the metallization pattern 126, for example, a seed layer is formed over the dielectric layer and in the openings extending through the dielectric layer. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer with a plurality of sublayers of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may, for example, be a metal layer.The nucleation layer can be formed, for example, using PVD or similar processes. A photoresist is then formed and patterned on the nucleation layer. The photoresist can be formed by spin coating or similar methods and exposed to light for patterning. The pattern of the photoresist corresponds to a desired metallization pattern. The structuring process creates openings through the photoresist to expose the nucleation layer. A conductive material is then formed in the openings of the photoresist and on the exposed parts of the nucleation layer. The conductive material can be formed by electroplating, such as electroless plating or similar processes. The conductive material can consist of a metal such as copper, titanium, tungsten, aluminum, or similar. The combination of the conductive material and the underlying parts of the nucleation layer forms the metallization pattern.The photoresist and portions of the nucleation layer where the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or peeling process, e.g., using an oxygen plasma or similar method. Once the photoresist is removed, exposed portions of the nucleation layer are removed, e.g., by an acceptable etching process, such as wet or dry etching. This process can be repeated one or more times to form the redistribution structure 300. In some embodiments, a simple / dual damascus process can be used.

[0048] Still referring to Fig. 9. In some embodiments, a plurality of electrical connectors 310 are arranged on the redistribution structure 300 in accordance with some exemplary embodiments. In some embodiments, the plurality of electrical connectors 310 may comprise an under bump metallurgy (UBM) layer formed on the redistribution structure 300 by sputtering, vapor deposition, or electroless coating, etc. The formation of the electrical connectors 310 may include the application of solder balls to the redistribution structure 300 (or to the UBM layer) and subsequent melting of the solder balls. In alternative embodiments, the formation of the electrical connectors 310 may include performing a plating process to form solder areas on the redistribution structure 300 and subsequent melting of the solder areas.The electrical connector 310 can also have conductive pillars or conductive pillars with solder caps, which can also be formed by electroplating. In some embodiments, at least one integrated passive device (IPD) can also be arranged on the redistribution structure 300. The IPD can be manufactured using standard wafer fabrication technologies, such as thin-film and photolithography processing, and can be mounted on the redistribution structure 300, for example, by flip-chip bonding or wire bonding, etc.

[0049] With reference to Fig. 9 and Fig. 10. The carrier C1 can be removed. In some embodiments, the carrier C1 is detached from the overlying structure (hereinafter referred to as the packing structure PK) by the adhesive layer AD losing or reducing its adhesion. The adhesive layer AD is then removed together with the carrier C1. For example, the adhesive layer AD can be irradiated with UV light so that the adhesive layer AD loses or reduces its adhesion, and thus the carrier C1 and the adhesive layer AD can be removed from the packing structure PK. After the removal of the carrier C1, the lower ends of the interlayer vias 500 are exposed. In the illustrated structure, the lower ends of the interlayer vias 500 lie on the same plane as the lower surface of the semiconductor package 100 and the lower surface of the encapsulation material 200.In embodiments where the dielectric layer 400 is omitted, a grinding process can optionally be performed to lightly grind the back of the semiconductor package 100 (e.g., the back of the first chip 110) and the lower ends of the interlayer vias 500.

[0050] In embodiments with the dielectric layer 400, a structuring process can then be carried out on the dielectric layer 400 to form a plurality of openings. The openings are located at the through-vias 500 to expose the lower ends of the through-vias 500. In some embodiments, the openings can be formed by a photolithography process, a laser drilling process, etc.

[0051] Still referring to Fig. 10. A plurality of electrical connections 610 can be formed on the package structure PK to be electrically connected to the interlayer vias 500. In some embodiments, the electrical connections 610 are arranged in the openings of the dielectric layer 400 to be connected to the interlayer vias 500. Then, another package structure 600 is arranged on the package structure PK and electrically connected to the interlayer vias 500 via the electrical connections 610. The package structure 600 is mounted on the package structure PK. Accordingly, the resulting structure is a package-on-package structure 600, as shown in Fig. Figure 10 illustrates this. In some embodiments, the package structure 600 may consist of packages, device cubes, passive components, and / or the like. In some embodiments, the package-on-package structure 600 may vertically combine discrete memory and logic packages, but the disclosure is not limited thereto. In some embodiments, bonding between the package structure PK and the package structure 600 may be effected using flip-chip bonding through the electrical terminals 610, which may, for example, include solder. In some embodiments, an underfill 620 may be formed between the package structure PK and the package structure 600 to encapsulate the electrical terminals 610.

[0052] It is understood that the component chips in the package structure 600 can be arranged differently than in the exemplary embodiments shown. In some embodiments, the device chips are encapsulated by the encapsulation material. Then the wafer-level package can be sawn into a plurality of independent package-on-package structures 10, each of which comprises a package structure 600 connected to a package structure PK.

[0053] Fig. 12 to Fig. Figure 16 shows schematic top views of various alignment markings according to some embodiments of the present disclosure. Since the alignment markings 126 are formed by a different process in separate steps than the vias 124, the design of the alignment markings 126 can be more flexible. For example, the cross-sectional shape of one of the alignment markings 126 can differ from the cross-sectional shape (e.g., circular) of one of the vias 124 (shown in Figure 16). Fig. 8) distinguish. Fig. 12 to Fig. Figure 16 merely illustrates some of the possible embodiments of the alignment markings 126, but the disclosure is not limited thereto.

[0054] First, to Fig. 12: In one embodiment, each of the alignment markings 126a can have a rectangular shape in the top view. That is, each of the alignment markings 126a can be a rectangular bar. For example, the width of one of the alignment markings 126a can be about 4 µm to 6 µm (e.g., 5 µm), while the length of one of the alignment markings 126a can be about 12 µm to 14 µm (e.g., 13.5 µm). In one embodiment, the alignment markings 126a can comprise two groups of alignment markings 1261a, 1262a, and one longitudinal direction of the alignment markings 1261a is substantially perpendicular to a longitudinal direction of the alignment markings 1262a, and the alignment markings 1261a, 1262a can be arranged in an alternative manner, as shown in Fig. Figure 12 shows. In one embodiment, the total length of the alignment markings 126 (including the alignment markings 1261a, 1262a) is in a range of about 50 µm to about 70 µm (e.g., 60 µm), and the total width of the alignment markings 126 (including the alignment markings 1261a, 1262a) is in a range of about 50 µm to about 70 µm (e.g., 60 µm), but the disclosure is not limited thereto.

[0055] With reference to Fig. 13 In some embodiments, the alignment markings 126b may be rectangular (e.g., square) rings arranged concentrically in plan view. For example, the alignment markings 126b may comprise a first alignment marking 1261b and a second alignment marking 1262b located within the first alignment marking 1261b, as shown in Fig. Figure 13 shows that in some embodiments, the width / length of the first alignment mark 1261b may be in a range of about 4 µm to about 6 µm (e.g., 5 µm), while the width / length of the second alignment mark 1262b may be in a range of about 2 µm to about 3 µm (e.g., 2.5 µm). In one embodiment, the width / length of the alignment marks 126b may be in a range of about 50 µm to about 70 µm (e.g., 60 µm), but the disclosure is not limited thereto.

[0056] With reference to Fig. 14. In some embodiments, the shapes of the alignment markings 126c may vary. For example, the alignment markings 126c may comprise two groups of alignment markings 1261c and 1262c, with the cross-sectional shape of each of the alignment markings 1261c being circular and the cross-sectional shape of each of the alignment markings 1262c being rectangular. The alignment markings 1261c and 1262c may be arranged in an alternative manner, as shown in Fig. Figure 14 shows that in some embodiments, the width of the rectangular alignment mark 1262c may be approximately 4 µm to 6 µm (e.g., 5 µm), while the length of the rectangular alignment mark 1262c may be approximately 12 µm to 15 µm (e.g., 13.5 µm). Some of the circular alignment marks 1261c are arranged along a longitudinal direction of the rectangular alignment mark 1262c. In some embodiments, the total length / width of the alignment marks 126c (including the alignment marks 1261c and 1262c) may be in a range of approximately 50 µm to approximately 70 µm (e.g., 60 µm), but the disclosure is not limited thereto.

[0057] With reference to Fig. 15 In some embodiments, the shapes of the alignment markers 126d can vary. For example, the alignment markers 126c can comprise two types of alignment markers 1261d and 1262d, and in a top view, the alignment marker 1262d can be a rectangular (e.g., square) ring defining a closed region, with the alignment markers 1261d arranged within that closed region. In some embodiments, the alignment markers 1261d can be a plurality of vias arranged in a cross pattern within the closed region defined by the alignment marker 1262d, as shown in Fig. Figure 15 shows that in some embodiments the overall width / length of the alignment markings 126d may be in a range of about 50 µm to about 70 µm (e.g. 60 µm), but the disclosure is not limited thereto.

[0058] With reference to Fig. 16. In some embodiments, the alignment markers 126e can comprise two types of alignment markers 1261e and 1262e, and the alignment markers 1261e are a plurality of vias surrounding an area in which the alignment marker 1262e is located. In some embodiments, the alignment markers 1261e can surround a rectangular (e.g., square) area, and the alignment marker 1262e located within the rectangular area has a cross shape. In some embodiments, the width of the cross-shaped alignment marker 1262e can be about 2 µm to 3 µm (e.g., 2.5 µm), while the length of the cross-shaped alignment marker 1262e can be in a range of about 8 µm to about 12 µm (e.g., 10 µm). In some embodiments, the overall width / length of the alignment mark 126e is in a range of approximately 50µm to approximately 70µm (e.g.60µm), but the disclosure is not limited thereto. It is noted that the embodiments in the examples are related to . Fig. 12 to Fig. The dimensions and figures mentioned in point 16 are for illustrative purposes only and do not limit the disclosure.

[0059] Fig. Figure 17 shows a schematic cross-sectional view of an intermediate stage in the fabrication of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. The semiconductor package shown in 17 has many identical or similar features to the semiconductor package disclosed in the preceding embodiments (e.g., the one shown in Fig. 6 semiconductor package shown). For clarity and simplicity, the detailed description of identical or similar features can be omitted, and identical or similar reference numbers denote identical or similar components.

[0060] Referring to Fig. 17 In accordance with some embodiments of the disclosure, the depth d2 of each of the alignment markings 126 differs from the depth d1 of each of the vias 124. In some embodiments, the depth d2 of each of the alignment markings 126 is substantially smaller than the depth d1 of each of the vias 124. In embodiments such as those described in Fig. As shown in Figure 6, the alignment markings 126 extend through the insulating layer 125. In some embodiments, the alignment markings 126 extend further into the substrate 121 of the second chip 120, but not completely through the substrate 121 of the second chip 120, as shown in Figure 6. Fig. 17 shown. That is, the depth d2 of each of the alignment marks 126 is greater than the thickness of the insulating layer 125.

[0061] Fig. Figure 18 shows a schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. The semiconductor package shown in 18 has many features that are similar to those of the semiconductor package disclosed in the previous embodiments (e.g., the one in Fig. The semiconductor package shown in section 6 is identical or similar. For clarity and simplicity, the detailed description of identical or similar features can be omitted, and identical or similar reference numbers denote identical or similar components.

[0062] With reference to Fig. 18 According to some embodiments of the disclosure, the depth of each of the alignment markings 126 can be approximately equal to the depth of each of the vias 124. In some embodiments, the alignment markings 126 can extend through the insulating layer 125 and the substrate 121 of the second chip 120 and further into the interconnect structure 123, but the alignment markings 126 are not electrically connected to the integrated circuit device (e.g., the one in Fig. The integrated circuit device 1231 shown in Figure 1 is connected in the interconnect structure 123. That is, the depth of the alignment mark 126 is greater than the sum of the thickness of the insulating layer 125 and the thickness of the substrate 121 and can be substantially equal to the depth of each of the vias 124. In some embodiments, the depth of the alignment mark 126 can be approximately equal to the depth of the vias 124, while the spacing of the alignment mark 126 differs from the spacing of the vias 124.

[0063] Fig. Figure 19 shows a schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. The semiconductor package shown in 19 has many features that are similar to those of the semiconductor package disclosed in the previous embodiments (e.g., the one in ). Fig. The semiconductor package shown in section 6 is identical or similar. For clarity and simplicity, the detailed description of identical or similar features can be omitted, and identical or similar reference numbers denote identical or similar components.

[0064] Referring to Fig. 19 In accordance with some embodiments of the disclosure, the depth of each of the alignment markings 126 differs from the depth d1 of each of the vias 124. In some embodiments, the depth of each of the alignment markings 126 is less than the depth of each of the vias 124. In some embodiments, the alignment markings 126 extend from the upper surface of the insulating layer 125, but not completely through the insulating layer 125. That is, the depth of the alignment marking 126 is less than the thickness of the insulating layer 125.

[0065] Fig. Figure 20 shows a schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. The semiconductor package shown in Figure 20 has many features that are identical or similar to the semiconductor package disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and identical or similar reference numbers denote identical or similar components.

[0066] Referring to Fig. According to some embodiments of the disclosure, at least one of the conductive layers of the redistribution structure 140 comprises an alignment pattern 1424 that overlaps with the alignment markings 126 in a top view. In some embodiments, the conductive layer, including the redistribution layer 1422, can also have the alignment pattern 1424. That is, the alignment pattern 1424 is located on the same plane (layer) as the redistribution layer 1422 and can be formed in the same step (simultaneously) with the redistribution layer 1422. In some embodiments, the alignment pattern 1424 is aligned with the alignment markings 126 from a top view, which allows for the identification of a correct orientation of the redistribution structure 140. In some embodiments, the alignment pattern 1424 is electrically isolated from the redistribution layer 1422.In some embodiments, the alignment pattern 1424 may have the same pattern as the alignment markings 126. In some embodiments, the alignment pattern 1424 may have a pattern that differs from the alignment markings 126.

[0067] Fig. Figure 21 shows a schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. The semiconductor package shown in Figure 21 comprises many features that are identical or similar to those disclosed in the previous embodiments. For clarity and simplicity, the detailed description of identical or similar features can be omitted, and identical or similar reference numbers denote identical or similar components.

[0068] Referring to Fig. According to some embodiments of the disclosure, at least one of the conductive layers of the redistribution structure 140 comprises an alignment pattern that overlaps with the alignment markings 126 in the top view. In some embodiments, the conductive layer, including the redistribution layer (or conductive pads) 1442, may, in addition to the alignment pattern 1424 described above, have the alignment pattern 1444, which overlaps with the alignment markings 126 in the top view. That is to say, in such an embodiment, the redistribution structure 140 comprises the alignment pattern 1424, which is on the same plane (layer) as the redistribution layer 1422, and the alignment pattern 1444, which is on the same plane (layer) as the conductive pads 1442.In some embodiments, the alignment pattern 1424 and the alignment pattern 1444 are each aligned with the alignment markings 126 from a top view, which allows identification of the correct orientation of the redistribution structure 140. In some embodiments, the alignment pattern 1424 is electrically isolated from the redistribution layer 1422, while the alignment pattern 1444 is electrically isolated from the conductive pads 1442. In some embodiments, the alignment patterns 1424 and 1444 may each have the same pattern as the alignment markings 126. In some embodiments, the alignment patterns 1424 and 1444 may each have a pattern that differs from the alignment markings 126.

[0069] Fig. Figure 22 shows a schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. The semiconductor package shown in Figure 22 comprises many features that are identical or similar to the semiconductor package disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers refer to the identical or similar components.

[0070] Referring to Fig. According to some embodiments of the disclosure, at least one of the conductive layers of the redistribution structure 140 comprises an alignment pattern that overlaps with the alignment markings 126 in a top view. In some embodiments, the conductive layer, including the redistribution layer (or conductive pads) 1442, may also have the alignment pattern 1444. That is, the alignment pattern 1444 is located on the same plane (layer) as the conductive pads 1442 and can be formed with the conductive pads 1442 in the same step (simultaneously). In some embodiments, the alignment pattern 1444 is aligned with the alignment markings 126 in a top view, which allows for the identification of a correct orientation of the redistribution structure 140. In some embodiments, the conductive layer, including the redistribution layer 1442, does not overlap with the alignment markings 126 in a top view.This means that the conductive layer, including the redistribution layer 1422, does not have an alignment pattern that is aligned with the alignment markers 126. In some embodiments, the alignment pattern 1444 is electrically isolated from the conductive pads 1442. In some embodiments, the alignment pattern 1444 may have the same pattern as the alignment markers 126. In some embodiments, the alignment pattern 1444 may have a pattern that differs from the alignment markers 126.

[0071] Fig. Figure 23 shows a schematic cross-sectional view and enlarged partial views of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. The semiconductor package shown in Figure 23 has many features that are identical or similar to those of the semiconductor packages disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers refer to the identical or similar components.

[0072] With reference to Fig. 23 In some embodiments, the material filling the openings OP of the alignment marks 126 can be a composite layer. That is, the alignment marks 126 can comprise a plurality of layers filling the openings OP of the alignment marks 126. In some embodiments, the alignment marks 126 can have a barrier layer 1266, such as a titanium nitride (TiN) layer, covering the sidewalls of the openings OP, and a conductive layer 1265, such as a copper (Cu) layer, filling the remaining part of the openings OP. In some embodiments, the formation of the alignment marks 126 can comprise the following steps. First, a plurality of openings OP are etched through a mask layer (e.g., the one described in the following) by the etching process. Fig. A mask layer PR (shown in Figure 5) is formed over the upper surface of the second chip 120 (e.g., the insulating layer 125). Accordingly, the pattern of the mask layer PR is transferred to the insulating layer 125 (and possibly to the substrate 121 of the second chip 120) by the etching process. Subsequently, the barrier layer 1266 can be formed over the insulating layer 125 and cover the sidewall of the openings OP. In some embodiments, the barrier layer 1266 can be formed from materials such as TaN, TiN, or similar. The barrier layer 1266 can have a thickness in the range of approximately 500 angstroms to approximately 750 angstroms. The barrier layer 1266 can be formed by various deposition techniques such as ALD, PVD, CVD, or other suitable techniques. Subsequently, the conductive layer 1265 can be formed over the barrier layer 1266 to fill the remaining portion of the openings OP.The conductive layer 1265 can, for example, comprise conductive material such as copper, tungsten, other conductive metals, or the like, and can be formed, for example, by electroplating, electroless deposition, or the like. The conductive layer 1265 can have a thickness in the range of approximately 1 µm to approximately 2 µm. The conductive material of the alignment markers 126 can be the same as that of the vias 124. In some embodiments, the conductive material of the alignment markers 126 can differ from the conductive material of the vias 124 because they are formed by different processes in separate steps. Subsequently, the mask layer can be removed using a suitable removal process, such as an ashing process. After that, a planarization process, such as…A CMP process is performed to remove excess portions of the conductive layer 1265 and the barrier layer 1266 until the insulating layer 125 is exposed. The use of a composite layer is related to the alignment markings of . Fig. Figure 23 is shown for illustration. In some embodiments, the [details omitted] Fig. The composite layer shown in 23 can be used in other alignment marker configurations, including those mentioned above with reference to the Fig. 17-19 were discussed.

[0073] Fig. Figure 24 shows a schematic cross-sectional view and partially enlarged views of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. The semiconductor package shown in Figure 24 has many identical or similar features to the semiconductor package disclosed in the previous embodiments. For clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers refer to the identical or similar components.

[0074] With reference to Fig. 24. According to some embodiments of the disclosure, the material filling the openings OP of the alignment markings 126 can be a dielectric material. In some embodiments, the dielectric material of the redistribution structure 140 fills the openings OP of the alignment markings 126. For example, the dielectric layer 1423 can fill the openings OP to form the alignment markings 126, as shown in the enlarged partial view on the left in Figure 24. Fig. Figure 24 illustrates this. The dielectric material of the redistribution structure 140 can comprise silicon nitride (SiN), HDP OX(SiO2), TEOS OX(SiO2), silicon oxide, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), oxygen-doped silicon carbide, nitrogen-doped silicon carbide, USG, or the like. It should be noted that the dielectric material filling the openings OP is different from the material of the insulating layer 125. In some embodiments, the formation of the alignment marks 126 can comprise the following steps. First, a plurality of openings OP are etched through a mask layer (e.g., the one shown in Figure 24) by the etching process. Fig. The mask layer PR (shown in Figure 5) is formed over the top surface of the second chip 120 (e.g., the insulating layer 125). Accordingly, the pattern of the mask layer PR is transferred to the insulating layer 125 (and possibly to the substrate 121 of the second chip 120) by the etching process. The mask layer can then be removed by a suitable removal process, such as an ashing process. The dielectric layer 1423 can then be formed over the second chip 120 and the encapsulation material 130 to cover the top surfaces of the second chip 120 (e.g., the insulating layer 125) and the encapsulation material 130 and to fill the openings OP to form the alignment marks 126. The dielectric layer 1423 can be formed by a suitable deposition process such as CVD or the like.

[0075] In some embodiments, the dielectric material filling the openings OP of the alignment marks 126 can be a composite layer. That is, a plurality of dielectric layers can fill the openings OP of the alignment marks 126, as shown in the enlarged partial view on the right in Figure 1. Fig. Figure 24 shows that in some embodiments, the alignment markers 126 may include a water-resistant layer 1267, such as a silicon nitride (SiN) layer, covering the sidewalls of the openings OP, and the dielectric material (e.g., the dielectric layer 1423) of the redistribution structure 140, filling the remaining portion of the openings OP. In some embodiments, the water-resistant layer 1267 may cover the entire top surface of the second chip (e.g., the top surface of the insulating layer 125 and the sidewalls of the openings OP) and the top surface of the encapsulation material 130, thus providing water-resistant properties to the second chip 120 and the encapsulation material 130. For example, the water-resistant layer 1267 may have a thickness between approximately 500 angstroms and approximately 750 angstroms. The water-resistant layer 1267 may be formed by a CVD process.The dielectric material of the redistribution structure 140 can comprise a silicon oxide layer (SiOx) or the like. The silicon oxide layer can comprise tetraethoxysilane (TEOS) or fused silica. The silicon oxide layer can have a thickness in the range of about 1 µm to about 2 µm. It is noted that the dielectric material filling the openings OP can be different from the material of the insulating layer 125. In some embodiments, the formation of the alignment marks 126 can comprise the following steps. First, a plurality of openings OP are etched through a mask layer (e.g., the one described in [reference]) by the etching process. Fig. The mask layer PR (shown in Figure 5) is formed over the top surface of the second chip 120 (e.g., the insulating layer 125). Accordingly, the pattern of the mask layer PR is transferred to the insulating layer 125 (and possibly to the substrate 121 of the second chip 120) by the etching process. The mask layer can then be removed by a suitable removal process, such as an ashing process. The water-repellent layer 1267 can then be formed over the top surface of the insulating layer 125 (and the top surface of the encapsulation material 130) and cover the sidewall of the openings OP. In some embodiments, the water-repellent layer 1267 can be formed from materials such as silicon nitride (SiN) or similar. The water-repellent layer 1267 can have a thickness in the range of approximately 500 angstroms to approximately 750 angstroms.The water-repellent layer 1267 can be formed by various deposition techniques such as ALD, PVD, CVD, or other suitable techniques. The dielectric layer 1423 can then be formed over the second chip 120 and the encapsulation material 130 to cover the upper surfaces of the second chip 120 (e.g., the insulating layer 125) and the encapsulation material 130, and to fill the remaining portion of the openings OP to form the alignment marks 126. The dielectric layer 1423 can be formed by a suitable deposition process such as CVD or similar.

[0076] Fig. 25 to Fig. Figure 26 shows cross-sectional views of intermediate stages in the manufacture of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. 25 to Fig. The manufacturing process shown in Figure 26 and the semiconductor packing exhibit many identical or similar features to the semiconductor packing disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers refer to the identical or similar components.

[0077] Referring to Fig. 25 In some embodiments, a redistribution layer 1422' can be in contact with the vias 124 without the dielectric vias (e.g., those in Fig. The dielectric vias 1421 shown in Figure 24 are located between the two components. The dielectric layer 1423 can, for example, be formed over the second chip 120 and the encapsulation material 130 to cover the upper surfaces of the second chip 120 (e.g., the insulating layer 125) and the encapsulation material 130. The dielectric layer 1423 can comprise an oxide, such as silicon oxide, a nitride, such as silicon nitride, USG, or the like, or combinations thereof. The dielectric layer 1423 can be formed by a suitable deposition process, such as CVD. Subsequently, the redistribution layer (tracks) 1422' is formed in the dielectric layer 1423, for example, by a Damascus process. In some embodiments, the alignment markings 126 do not overlap with the redistribution layer (tracks) 1422' in the top view, so that the alignment markings 126 are not blocked during the alignment process.However, the revelation is not limited to that.

[0078] In some embodiments, a patterning process is performed to form a multitude of trenches in the dielectric layer 1423. In some embodiments, the trenches extend through the dielectric layer 1423. The patterning process removes a portion of the dielectric layer 1423 to expose the top surfaces of the vias 124 of the second chip 120. The patterning process may include several photolithography and / or etching processes. The sidewalls of the trenches may be straight or inclined. Subsequently, the trenches are filled with conductive material to facilitate the connection of the Fig. to form the redistribution layer 1422' shown in Figure 25. The conductive material comprises a suitable metallic material, such as copper or a copper alloy. In some embodiments, the method for forming the conductive material may include a plating process, such as an electroplating or electrochemical plating process, or a suitable deposition process, such as CVD, PVD, or the like. Subsequently, a planarization process, such as a CMP process, may be carried out to remove excess portions of the conductive material until the dielectric layer 1423 is exposed. In some embodiments, after the planarization process, the upper surfaces of the redistribution layer 1422' are substantially coplanar with the upper surface of the dielectric layer 1423.

[0079] Then, in some embodiments (see Fig. 26) The passivation layer 1443 is formed over the dielectric layer 1423, and the vias 1441 are formed in the passivation layer 1443 to establish an electrical connection with the redistribution layer 1422'. Then the redistribution layer (or conductive pads) 1442 is formed over the passivation layer 1443 and the vias 1441 and electrically connected to the redistribution layer 1422'. The material of the redistribution layer (or conductive pads) 1442 and the vias 1441 can each comprise a suitable metallic material, such as aluminum, copper, alloys thereof, or combinations thereof. In some embodiments, the conductive pads 1442 can be aluminum pads or aluminum-copper pads, but other metallic materials can also be used.The vias 1441 and the redistribution layer 1442 can be formed separately with an interface between them or simultaneously without an interface between them. In some embodiments, the alignment markings 126 do not overlap with the redistribution layer 1442 in the top view, so that the alignment markings 126 would not be blocked during the alignment process. However, the disclosure is not limited to this.

[0080] In some embodiments, the passivation layer 1445 can be formed over the passivation layer 1443 to encapsulate the conductive pads 1442, at least laterally. The passivation layers 1443 and 1445 can each be a single layer or a composite layer and can be formed from a non-porous material. In some embodiments, each of the passivation layers 1443 and 1445 can comprise silicon oxide, silicon nitride, or a combination thereof. In some embodiments, one or both of the passivation layers 1443 and 1445 are a composite layer comprising a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) over the silicon oxide layer. The passivation layers 1443 and 1445 can also be formed from other non-porous dielectric materials such as undoped silicate glass (USG), silicon oxynitride, and / or the like, or combinations thereof.Then a planarization process, such as a CMP process, can be performed to remove excess portions of the passivation layer 1445 until the conductive pads 1442 are exposed. In some embodiments, after the planarization process, the top surfaces of the conductive pads 1442 are essentially coplanar with the top surface of the passivation layer 1445.

[0081] Fig. 27 to Fig. Figure 28 shows cross-sectional views of intermediate stages in the manufacture of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. 27 to Fig. The manufacturing process shown in Figure 28 and the semiconductor packing exhibit many identical or similar features to the semiconductor packing disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers refer to the identical or similar components.

[0082] Referring to Fig. 27 According to some embodiments of the disclosure, the material filling the openings OP of the alignment markings 126 can be a dielectric material. In some embodiments, the dielectric material of the redistribution structure 140 fills the openings OP of the alignment markings 126. For example, the dielectric layer 1423 can fill the openings OP to form the alignment markings 126, as described in Fig. 27 is shown. Furthermore, in some embodiments, the redistribution layer 1422' can be in (direct) contact with the vias 124 without the dielectric vias (e.g., those in Fig. The dielectric vias 1421 shown in Figure 24 are located between the two chips. After the openings of the alignment marks 126 have been formed by an etching process, the dielectric layer 1423 can be formed, for example, over the second chip 120 and the encapsulation material 130 to cover the upper surfaces of the second chip 120 (e.g., the insulating layer 125) and the encapsulation material 130 and to fill the openings of the alignment marks 126. The dielectric layer 1423 can be formed by a suitable deposition method such as CVD or similar. Then the redistribution layer (tracks) 1422' is formed in the dielectric layer 1423, e.g., by a damascus process. In some embodiments, the alignment markings 126 do not overlap with the redistribution layer (tracks) 1422' in the top view, so that the alignment markings 126 would not be blocked during the alignment process.However, the disclosure is not limited thereto. In other embodiments, the redistribution layer (tracks) 1422' may further have an alignment pattern that overlaps (aligns) with the alignment markings 126.

[0083] In some embodiments, a structuring process is carried out to form a multitude of trenches in the dielectric layer 1423. In some embodiments, the trenches extend through the dielectric layer 1423. The trenches are then filled with conductive material to facilitate the connection of the dielectrics in the dielectric layer 1423. Fig. 27 to form the redistribution layer 1422' shown. The conductive material comprises a suitable metallic material, such as copper or a copper alloy. In some embodiments, the method for forming the conductive material may include a plating process, such as an electroplating or electrochemical plating process, or a suitable deposition process, such as CVD, PVD, or the like. Subsequently, a planarization process, such as a CMP process, may be carried out to remove excess portions of the conductive material until the dielectric layer 1423 is exposed.

[0084] In some embodiments, the passivation layer 1443 is formed over the dielectric layer 1423, and the vias 1441 are formed in the passivation layer 1443 to establish an electrical connection with the redistribution layer 1422'. The redistribution layer (or conductive pads) 1442 is then formed over the passivation layer 1443 and the vias 1441 and electrically connected to the redistribution layer 1422'. In some embodiments, the alignment markings 126 do not overlap with the redistribution layer 1442 in plan view, so that the alignment markings 126 would not be blocked during the alignment process. However, the disclosure is not limited to this. In other embodiments, the redistribution layer 1442 may also have an alignment pattern that overlaps (is aligned) with the alignment markings 126.

[0085] In some embodiments, the passivation layer 1445 can be formed over the passivation layer 1443 to encapsulate the conductive pads 1442, at least laterally. A planarization process, such as a CMP process, can then be performed to remove excess portions of the passivation layer 1445 until the conductive pads 1442 are exposed. In some embodiments, after the planarization process, the top surfaces of the conductive pads 1442 are substantially coplanar with the top surface of the passivation layer 1445 within process variations. The disclosure does not restrict the process and step sequence for fabricating the redistribution structure 140.

[0086] Fig. 29 to Fig. Figure 32 shows cross-sectional views of intermediate stages in the manufacture of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. 29 to Fig. The manufacturing process shown in Figure 32 and the semiconductor packing exhibit many identical or similar features to the semiconductor packing disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers refer to the identical or similar components.

[0087] With reference to Fig. 29 In some embodiments, the insulating layer 125 can be a composite layer. For example, the insulating layer 125 can have a water-repellent layer 1251 and an insulating layer 1252. Fig. 29 to Fig. Figure 32 shows an example of the procedure for forming the composite insulation layer 125, and that in Fig. 29 to Fig. The 32 methods shown can be found in the Fig. The procedures shown in Figure 3 are carried out, i.e., after removing the rear part of the substrate 121 of the second chip 120. After the rear part of the substrate 121 has been removed, the vias 124 protrude from the back of the substrate 121, and recesses RC are formed transversely across the substrate 121, as shown in Figure 3. Fig. 3 shown. Then a water-repellent layer 1251 is formed over the back of the substrate 121, as shown in Fig. Figure 29 shows the water-repellent layer 1251. In some embodiments, the water-repellent layer 1251 can also cover the exposed surfaces (e.g., the top surfaces and part of the side surfaces) of the vias 124 and the top surface of the encapsulation material 130. In some embodiments, the water-repellent layer 1251 is a conformal layer, i.e., the water-repellent layer 1251 has a substantially uniform thickness extending along the area on which the water-repellent layer 1251 is formed. The water-repellent layer 1251 can comprise silicon nitride (SiN) or the like. In some embodiments, the water-repellent layer 1251 can cover the back surface of the substrate 121, the exposed surface of the vias 124, and the exposed surface of the encapsulation material 130 to impart water-repellent properties to the second chip 120 and the encapsulation material 130.In one example, the water-repellent layer 1251 can have a thickness ranging from approximately 500 angstroms to approximately 750 angstroms. The water-repellent layer 1251 can be formed using various deposition techniques such as ALD, PVD, CVD, or other suitable techniques. Then, the insulating layer 1252 can be formed over the water-resistant layer 1251 to fill the remaining portion of the depressions, as shown in [reference]. Fig. Figure 30 shows that the insulating layer 1252 can be formed by a suitable deposition process such as CVD or similar. Subsequently, a planarization process, such as a CMP process, can be performed to remove excess portions of the water-resistant layer 1251 and the insulating layer 1252 until the vias 124 and the encapsulation material 130 are exposed. In some embodiments, after the planarization process, the top surfaces of the water-resistant layer 1251 and the insulating layer 1252 are substantially coplanar with the top surfaces of the vias 124 and the encapsulation material 130 within process deviations, and the water-resistant layer 1251 laterally encapsulates a portion of the side faces of the vias that protrude from the substrate 121 of the second chip 120.

[0088] Referring to Fig. 31 A plurality of openings OP are then formed by an etching process. Specifically, the openings OP can be formed by transferring the pattern of a mask layer onto the water-repellent layer 1251 and the insulating layer 1252 (and possibly the substrate 121 of the second chip 120) using the etching process. In some embodiments, the openings OP extend at least through the water-repellent layer 1251 and the insulating layer 1252.

[0089] The openings are then surgically treated as described in... Fig. Figure 32 shows, for example, filled with conductive or dielectric material to form the alignment markings 126. In the present embodiment, the alignment markings 126 are formed by filling the openings OP with conductive material. The alignment markings 126 can, for example, comprise one or more conductive materials such as copper, tungsten, other conductive metals, or the like, and can be formed, for example, by electroplating, electroless plating, or the like. The conductive material of the alignment markings 126 can be the same as that of the vias 124. In some embodiments, the conductive material of the alignment markings 126 can differ from the conductive material of the vias 124 because they are formed by different processes in separate steps.In other embodiments, the alignment markings 126 are formed by filling the openings OP with dielectric material, such as the dielectric layer of the redistribution structure. Since the composite insulating layer 125 (including the water-resistant layer 1251 and the insulating layer 1252) is formed after the formation of the vias 124 and before the formation of the alignment markings 126, the insulating layer 1252 and the vias 124 are isolated from each other by the water-resistant layer 1251, while the insulating layer 1252 and the water-resistant layer 1251 are both in contact with a portion of the side surface of the alignment markings 126.

[0090] Fig. Figure 33 shows a partial top view of a chip of a semiconductor package according to some embodiments of the present disclosure. It is noted that the in Fig. The semiconductor package shown in Figure 33 has many features that are identical or similar to the semiconductor package disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and identical or similar reference numbers denote identical or similar components.

[0091] In accordance with some embodiments of the disclosure, it shows Fig. 33 A top view of a die corner, which may also be referred to as the die corner no-circuit region (DCCF). In some embodiments, the Fig. Figure 33 shows the die corner region at the corners of the second chip 120. The integrated circuit is excluded from the die corner region because it is a region that can be subjected to greater stress during and after backend processing, such as sawing and packaging the chips. The chip corner region can have a dummy metal pattern 127, 129 for stress relief. The dummy metal pattern can have a first dummy metal pattern 127 and a second dummy metal pattern 129. The first and second dummy metal patterns 127 and 129 can be positioned within the chip corner region so that they are close to each other and are configured such that the first dummy metal pattern 127 is located within and / or closer to an active area (integrated circuit area) AR and the second dummy metal pattern 129 is located closer to the contour of the chip corner region (e.g., along the scribe line), as shown in Fig. Figure 33 shows that the chip corner region can further comprise part of a sealing ring 128 surrounding the active area AR, and the alignment markings 126 can be located outside the active area AR and within the sealing ring 128.

[0092] In some embodiments, the alignment markings 126 are arranged in at least one corner of the second chip 120. For example, the alignment markings 126 are located within the Fig. 33 shown in the chip corner region. Such a combined structure (e.g., the die corner region), in which the alignment markings 126 are arranged together with the first dummy metal pattern 127, the second dummy metal pattern 129, and the sealing ring 128, can utilize the die area more efficiently and save more die area for the layout of the integrated circuit. In accordance with some embodiments of the disclosure, the alignment markings 126 can be located within the sealing ring 128, as shown in Fig. The alignment markings 126, as shown in Figure 33, may be arranged within the first blind metal pattern 127, within the second blind metal pattern 129, or combinations thereof. The alignment markings 126 may be isolated from the sealing ring 128, the first blind metal pattern 127, and / or the second blind metal pattern 129.

[0093] Fig. Figure 34 shows a schematic top view and an enlarged partial view of a chip of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. Figure 34 shows the semiconductor package having many identical or similar features to the semiconductor package disclosed in the previous embodiments. For clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers denote the identical or similar components.

[0094] With reference to Fig. 34 According to some embodiments of the disclosure, the second chip 120 may have more than one set of alignment marks 126 and 126'. In some embodiments, a plurality of sets of alignment marks may be arranged at a plurality of corners of the second chip 120. For example, the alignment marks may comprise a first set of alignment marks 126 and a second set of alignment marks 126', each located at different corners, such as two diagonal corners of the second chip 120, as shown in Fig. Figure 34 shows the arrangement of the two sets of alignment marks 126 and 126'. In some embodiments, the two sets of alignment marks 126 and 126' can be arranged at opposite corners of the second chip 120. In some embodiments, the two sets of alignment marks 126 and 126' are formed adjacent to two corners of the second chip 120, the two corners being adjacent corners formed by a common edge of the second chip 120. It should be noted that, although two sets of alignment marks 126 and 126' are shown here, more or fewer sets of alignment marks can be provided. The disclosure is not limited to this. In some embodiments, several sets of alignment marks can be arranged next to each of the corners of the second chip 120. The alignment marks 126 and 126' can be arranged within the sealing ring 128 that surrounds the active area AR.

[0095] In some embodiments, each set of alignment marks 126 / 126' can have the same pattern. For example, the first set of alignment marks 126 and the second set of alignment marks 126' can each have the same pattern, as shown in the enlarged partial view of Fig. Figure 34 shows a plurality of subgroups of alignment marks 1261, 1262, 1263, 1264, and the corresponding spacings of the subgroups of alignment marks 1261, 1262, 1263, 1264 can differ from one another. In other embodiments, the pattern of each set of alignment marks can differ from one another.

[0096] Fig. Figure 35 shows a schematic top view and an enlarged partial view of a chip of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. Figure 35 shows that the semiconductor package has many features that are identical or similar to the semiconductor package disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers refer to the identical or similar components.

[0097] Referring to Fig. 35 According to some embodiments of the disclosure, the second chip 120 may have more than one set of alignment marks (e.g., two sets of alignment marks 126" and 126"'). In some embodiments, a plurality of sets of alignment marks may be arranged on a plurality of sides of the second chip 120. For example, the alignment marks may comprise two sets of alignment marks 126" and 126"', each arranged on two adjacent sides of the second chip 120, as in Fig. Figure 35 shows that the two sets of alignment markings 126" and 126'" can be formed adjacent to two sides of the second chip 120, the two sides being adjacent sides forming the same corner of the second chip 120. In some embodiments, the two sets of alignment markings 126" and 126'' can be arranged adjacent to two opposite sides of the second chip 120. It is noted that, although two sets of alignment markings 126" and 126'" are shown here, more or fewer sets of alignment markings can be provided. The disclosure is not limited to this. In some embodiments, several sets of alignment markings can be arranged adjacent to each of the sides of the second chip 120. The alignment markings 126" and 126'" can be arranged within the sealing ring 128 that surrounds the active area AR.

[0098] In some embodiments, each set of alignment marks 126" / 126'" can have the same pattern. For example, the two sets of alignment marks 126" and 126'" can each have the same pattern, as shown in the enlarged partial view of Fig. Figure 3 5 shows a plurality of subgroups of alignment marks 1261, 1262, 1263, 1264, and the corresponding spacings of the subgroups of alignment marks 1261, 1262, 1263, 1264 can differ from one another. In other embodiments, the pattern of each set of alignment marks can differ from one another.

[0099] Fig. 36 to Fig. Figure 37 shows cross-sectional views of intermediate stages in the manufacture of a semiconductor package according to some embodiments of the present disclosure. It is noted that the Fig. 36 and Fig. The semiconductor package shown in Figure 37 has many identical or similar features to the semiconductor package disclosed in the previous embodiments. For the sake of clarity and simplicity, the detailed description of identical or similar features can be omitted, and the identical or similar reference numbers refer to the identical or similar components.

[0100] With reference to Fig. 36 According to some embodiments of the disclosure, the second chip 120 can be connected to the first chip 110 in a front-to-back configuration. That is, the front (active) surface of the second chip 20 faces the rear surface of the first chip 110. In some embodiments, at least one integrated circuit device 1131 is formed in the front of the first chip 110, facing away from the second chip 120, as shown in Fig. Figure 36 shows the integrated circuit device 1131. In some embodiments, it can be formed in a front-end-of-line (FEOL) process.

[0101] In some embodiments, the integrated circuit components 1131, such as transistors including gate structures, are formed on the front side of the first chip 110, while no components are formed on the back side of the first chip 110, which faces the second chip 120. Furthermore, the back side of the first chip 110 is connected to the front side of the second chip 120, and therefore the resulting stack structure is a face-to-back stack structure.

[0102] In some embodiments, a plurality of vias (TSV) 114 extend through the substrate 111 of the first chip 110, as in Fig. Figure 36 shows that the vias 114 are used to establish electrical connections. Specifically, they connect the integrated circuit components 1131 and the metal traces formed on the front (the underside shown) of the substrate 111 to the conductive pads 112 on the back. In some embodiments, the vias 114 can extend into the interconnect structure 113 to make physical and electrical contact with the conductive features of the interconnect structure 113. In some embodiments, the interconnect structure 113 is formed on the front of the first chip 110, and the vias 114 directly contact conductive features of the interconnect structure 113 on the front of the first chip 110 and the conductive pads 112 on the back of the first chip 110.In some embodiments, the vias 114 may have one or more linings (not shown) to cover their surface. The lining is arranged between the vias 114 and the substrate 111 to separate the through-hole 114 from the substrate 111. The lining may surround the side walls and / or the top surface of the via 114. The vias 114 may comprise copper, copper alloys, aluminum, aluminum alloys, Ta, TaN, Ti, TiN, CoW, or combinations thereof. The lining may comprise dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or combinations thereof.

[0103] With reference to Fig. 37 In some embodiments, the support C1 can be removed, and the similar processes described above in relation to Fig. 9 and Fig. The functions described in section 10 can be applied to the semiconductor package 100 to achieve the results described in section 10. Fig. The package-on-package structure shown in section 37 can be formed. For example, this can be done in Fig.The semiconductor package 100 and the interlayer vias 500 shown in Figure 36 are provided on a substrate. When placing the semiconductor package 100, the alignment marks 126 on the second chip 120 can be used to align the position of the semiconductor package 100 to ensure that it is placed in the desired location and that it does not shift or rotate from its intended position and orientation. The alignment is achieved by determining the relative position of the semiconductor package 100 with respect to the positions of the alignment marks 126.The alignment marks 126 are formed by a different process than the vias 124 of the second chip 120, so that the spacings and patterns of the alignment marks 126 may differ from those of the vias 1254 in order to meet the requirement of fine spacing and achieve better resolution.

[0104] Furthermore, the semiconductor package 100 and the vias 500 are encapsulated at least laterally by an encapsulation material 200. Then, the redistribution structure 300 is formed over the semiconductor package 100, and the electrical terminals 310 are arranged on the redistribution structure 300 to form the package structure PK. In some embodiments, the electrical terminals 610 are formed over the package structure PK to be electrically connected to the vias 500, and another package structure 600 is arranged on the package structure PK and is electrically connected to the vias 500 via the electrical terminals 610.The wafer-level package can then be sawn into a multitude of independent package-on-package structures 10, each of the package-on-package structures 10 comprising a package structure 600 connected to a package structure PK.

[0105] Based on the above discussion, it can be seen that the present disclosure offers various advantages. However, it is understood that not all advantages are necessarily discussed here, that other embodiments may offer other advantages, and that no particular advantage is required for all embodiments.

[0106] Other features and procedures may also be included. For example, test structures may be included to support verification testing of the 3D packaging or 3DIC components. These test structures may include, for example, test pads formed in a redistribution layer or on a substrate that enables testing of the 3D packaging or 3DIC, the use of probes and / or test cards, and the like. Verification tests can be performed on both intermediate structures and the final structure. Additionally, the structures and methods disclosed here can be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

[0107] According to some embodiments of the disclosure, a semiconductor package comprises a first die, a second die, an encapsulation material, and a redistribution structure. The first chip includes first bond pads. The second chip is positioned above the first chip and includes second bond pads. The first bond pads are bonded to the second bond pads. The second chip comprises a substrate, a plurality of vias extending through the substrate, and a plurality of alignment markers. The spacing between two adjacent orientation markers differs from the spacing between two adjacent vias. The encapsulation material is positioned above the first chip. The encapsulation material laterally encapsulates the second chip. The redistribution structure is positioned above the second chip and the encapsulation material.The redistribution structure comprises conductive features that are electrically connected to corresponding vias from the plurality of vias. In some embodiments, the depth of each of the multiple alignment markers differs from the depth of each of the multiple vias. In some embodiments, the second chip further comprises an insulating layer located between the substrate of the second chip and the redistribution structure, with the plurality of vias extending through the insulating layer. In some embodiments, the plurality of alignment markers extends from an upper surface of the insulating layer facing the redistribution structure and extends toward the substrate. In some embodiments, the alignment markers do not overlap with the conductive features of the redistribution structure in the top view.In some embodiments, the redistribution structure comprises an alignment pattern that overlaps with the plurality of alignment markers in the top view, wherein the alignment pattern comprises a conductive material. In some embodiments, the redistribution structure comprises a dielectric material, wherein the dielectric material of the redistribution structure and the alignment markers form a single continuous layer. In some embodiments, the alignment markers are made of a conductive material. In some embodiments, the alignment markers are located at a corner of the second chip.In some embodiments, the alignment markers comprise a first set of alignment markers and a second set of alignment markers, wherein the first set of alignment markers and the second set of alignment markers are located at different corners or on different sides of the second chip. In some embodiments, the second chip comprises an active area and a sealing ring structure surrounding the active area of ​​the second chip, with the alignment markers located outside the active area. In some embodiments, the cross-sectional shape of one of the alignment markers differs from the cross-sectional shape of one of the through-vias.

[0108] According to some embodiments of the disclosure, a semiconductor package comprises a first die, a second die, a first encapsulation material, and a first redistribution structure. The second die is arranged above and connected to the first die. The second die comprises a substrate and a plurality of vias extending through the substrate. The second die includes a plurality of alignment markers. The depth of the alignment markers differs from the depth of the vias. The first encapsulation material laterally encapsulates the first and second dies. The first redistribution structure is arranged above the second die and the first encapsulation material. The redistribution structure includes first conductive features that are electrically connected to the first and second dies.In some embodiments, the semiconductor package further comprises a second encapsulation material arranged over the first chip and laterally encapsulating the second chip, and the first encapsulation material laterally encapsulating both the first chip and the second encapsulation material. In some embodiments, the semiconductor package also comprises a second redistribution structure arranged over the second chip and the second encapsulation material. The second redistribution structure includes second conductive features electrically connected to the plurality of vias. The first encapsulation material laterally encapsulates the second redistribution structure. The first redistribution structure is arranged over the second redistribution structure and the first encapsulation material.In some embodiments, the semiconductor package further comprises a plurality of passages between the layers that extend through the first encapsulation material.

[0109] According to some embodiments of the disclosure, a method comprises bonding a first chip to a second chip, wherein the first chip comprises a plurality of first bond pads, the second chip comprises a plurality of second bond pads bonded to corresponding conductive pads of the first, and the second chip comprises a plurality of through-vias electrically connected to corresponding bond pads of the plurality; forming an encapsulation material over the first chip, wherein the encapsulation material laterally encapsulates the second chip; forming a plurality of alignment markers on the second chip, wherein the distance between two adjacent alignment markers of the plurality of alignment markers differs from the distance between two adjacent through-vias of the plurality of through-vias; and forming a redistribution structure over the second chip and the encapsulation material.In some embodiments, the method further comprises removing a rear portion of a substrate of the second chip, such that the majority of vias protrude from the substrate; and providing an insulating layer over the substrate. The insulating layer laterally encapsulates the vias protruding from the substrate, and the alignment markers are formed on the insulating layer. In some embodiments, forming the alignment markers on the second chip also includes forming the alignment markers in the insulating layer. In some embodiments, forming the alignment markers and forming the redistribution structure over the second chip and the encapsulation material includes forming recesses in a rear surface of the second chip; and forming a dielectric layer over the second chip and the encapsulation material.The dielectric layer fills the recesses, and parts of the dielectric layer in the recesses form the multitude of alignment marks.

[0110] The foregoing outlines features of several embodiments to help the person skilled in the art better understand the aspects of the present disclosure. The person skilled in the art should be aware that they can readily use the present disclosure as a basis for developing or modifying other methods and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. The person skilled in the art should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications therein without deviating from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63136761

[0001]

Claims

[1] Semiconductor package, comprising: a first chip, wherein the first chip comprises first bond pads; a second chip arranged above the first chip, the second chip having second bond pads, the first bond pads being bonded to the second bond pads, the second chip having a substrate and a plurality of vias extending through the substrate, the second chip having a plurality of alignment marks, the distance between any two adjacent of the plurality of alignment marks being different from the distance between any two adjacent of the plurality of vias; an encapsulation material arranged over the first chip, wherein the encapsulation material laterally encapsulates the second chip; and a redistribution structure arranged above the second chip and the encapsulation material, wherein the redistribution structure has conductive features, the conductive features being electrically connected to the plurality of vias. [2] Semiconductor package according to claim 1, wherein a depth of each of the plurality of alignment marks differs from a depth of each of the plurality of vias. [3] Semiconductor package according to claim 1 or 2, wherein the second chip further comprises an insulating layer arranged between the substrate of the second chip and the redistribution structure, wherein the plurality of vias extends through the insulating layer. [4] Semiconductor package according to claim 3, wherein the plurality of alignment markings extends from an upper surface of the insulation layer facing the redistribution structure towards the substrate. [5] Semiconductor package according to any one of the preceding claims 1 to 4, wherein the majority of alignment markings do not overlap with the conductive features of the redistribution structure in the top view. [6] Semiconductor package according to any one of the preceding claims 1 to 4, wherein the redistribution structure has an alignment pattern which overlaps with the plurality of alignment markings in a top view, wherein the alignment pattern comprises a conductive material. [7] Semiconductor package according to one of the preceding claims, wherein the redistribution structure comprises a dielectric material, wherein the dielectric material of the redistribution structure and the plurality of alignment markers comprise a single continuous layer. [8] Semiconductor package according to any of the preceding claims, wherein the plurality of alignment markings comprises conductive material. [9] Semiconductor package according to one of the preceding claims, wherein the plurality of alignment marks is arranged at a corner of the second chip. [10] Semiconductor package according to one of the preceding claims, wherein the plurality of alignment marks comprises a first set of alignment marks and a second set of alignment marks, wherein the first set of alignment marks and the second set of alignment marks are arranged at different corners of the second chip or on different sides of the second chip. [11] Semiconductor package according to one of the preceding claims, wherein the second chip has an active area and a sealing ring structure surrounding the active area of ​​the second chip, wherein the majority of alignment markings are arranged outside the active area. [12] Semiconductor package according to one of the preceding claims, wherein a cross-sectional shape of one of the multiple alignment markings differs from a cross-sectional shape of one of the multiple vias. [13] A semiconductor package comprising: a first chip; a second chip arranged above and bonded to the first chip, wherein the second chip comprises a substrate and a plurality of vias extending through the substrate, wherein the second chip comprises a plurality of alignment markers, the depth of which of the plurality of alignment markers differs from the depth of which of the plurality of vias; a first encapsulation material that laterally encapsulates the first chip and the second chip; and a first redistribution structure arranged above the second chip and the first encapsulation material, wherein the redistribution structure comprises first conductive features electrically connected to the first chip and the second chip. [14] Semiconductor package according to claim 13, further comprising a second encapsulation material arranged over the first chip and encapsulating the second chip laterally, wherein the first encapsulation material encapsulates the first chip and the second encapsulation material encapsulates the second chip laterally. [15] Semiconductor package according to claim 14, further comprising a second redistribution structure arranged over the second chip and the second encapsulation material, wherein the second redistribution structure comprises second conductive features electrically connected to the plurality of vias, wherein the first encapsulation material laterally encapsulates the second redistribution structure, wherein the first redistribution structure is arranged over the second redistribution structure and the first encapsulation material. [16] Semiconductor package according to any one of the preceding claims 13 to 15, further comprising a plurality of interlayer vias extending through the first encapsulation material. [17] Method for forming a semiconductor package, comprising: Bonding a first chip to a second chip, wherein the first chip has a plurality of first bond pads, wherein the second chip has a plurality of second bond pads which are bonded to corresponding first conductive pads, and wherein the second chip has a plurality of vias which are electrically connected to corresponding bond pads; Forming an encapsulation material over the first chip, wherein the encapsulation material laterally encapsulates the second chip; Forming a plurality of alignment markers on the second chip, wherein the distance between two adjacent alignment markers of the plurality of alignment markers differs from the distance between two adjacent vias of the plurality of vias; and Forming a redistribution structure over the second chip and the encapsulation material. [18] The method of claim 17, further comprising: Removing a rear section of a substrate of the second chip, so that the majority of vias protrude from the substrate; and Providing an insulating layer over the substrate, wherein the insulating layer laterally encapsulates the plurality of vias protruding from the substrate and the plurality of alignment markings are formed on the insulating layer. [19] Method according to claim 18, wherein forming the plurality of alignment marks on the second chip further comprises: Forming the majority of alignment marks in the insulation layer. [20] Method according to any one of the preceding claims 17 to 19, comprising forming the plurality of alignment marks and forming the redistribution structure over the second chip and the encapsulation material: Forming recesses in a rear surface of the second chip; and Forming a dielectric layer over the second chip and the encapsulation material, wherein the dielectric layer fills the recesses, with sections of the dielectric layer in the recesses forming the plurality of alignment marks.