EXTINGUISHING PRE-VOLTAGE CIRCUIT DEVICE AND SINGLE PHOTOTON DETECTOR INDICATING THE SAME

Abstract

A pre-extinguishing circuit device (100) comprising: a light receiving element (110), a feedback current mirror circuit (120) arranged between a supply voltage (140) and the light receiving element (110), wherein the feedback current mirror circuit (120) is configured to induce a passive extinguishing process to maintain a constant current flowing in the light receiving element (110), and a pre-extinguishing circuit (130) connected to a sensing node (160) of the light receiving element (110) and configured to perform an active extinguishing process, characterized in that the pre-extinguishing circuit device (100) further comprises a feedback process control circuit (170) configured to: compare a sensing voltage of the sensing node (160) with reference values, and determine the passive extinguishing process according to a comparison result of the sensing voltage.wherein the feedback process control circuit (170) comprises: a first comparator (611) configured to compare the detection voltage with a first reference value among the reference values, a second comparator (612) configured to compare the detection voltage with a preset second reference value that is smaller than the first reference value, and a control logic (620) configured to generate a control signal for the passive erasure process according to the comparison results of the first comparator (611) and the second comparator (612), wherein a supply current (150) is continuously input into the feedback current mirror circuit (120), and the control signal comprises at least one of an erasure path control signal that performs the passive erasure process or a non-erasure path control signal that does not perform the passive erasure process.The quenching bias circuit device (100) further comprises a feedback process execution circuit (180) comprising: a first switching element (701) configured to direct an initial power from a first charge pump (charge pump 1) in response to the quenching path control signal; a first capacitor (C1) connected in parallel to the first switching element (701) and configured to be charged with the initial power; and a second capacitor (C2) connected in parallel to the first capacitor (C1) and configured to output an applied voltage applied to the feedback current mirror circuit (120) using the supply voltage (140) and the initial power; the feedback process control circuit (170) configured to execute the passive quenching process, which maintains a constant current flowing in the light receiving element (110) according to a detection of the passive quenching process.wherein the feedback operation execution circuit (180) further comprises: a second switching element (711) configured to conduct a second power from a second charge pump (charge pump 2) in response to the non-erase path control signal, a third capacitor (C3) connected in parallel to the second switching element (711) and configured to be charged with the second power, and a third comparator (730) connected in parallel to the third capacitor (C3) and configured to generate a hold operation signal for a hold operation of the feedback current mirror circuit (120) using the supply voltage (140) and the second power.

Description

TECHNICAL AREA

[0001] The present disclosure / invention relates to a quenching bias circuit device (e.g., a quenching or attenuation bias circuit device or an attenuation bias circuit device) having a light receiving element for detecting light and a single photon detector (e.g., a single photon detector or measuring device or for detecting / measuring single photons) having the same. BACKGROUND

[0002] If in the case of a general bias circuit as shown in the Fig. 1 and Fig. 2, a photon is injected (e.g., enters or is irradiated) into a single-photon avalanche diode (SPAD), a very small current flows in a resistor RB, which is a passive component, and a voltage V sof a sense node drops slightly compared to VHIGH. The drop voltage (e.g., the voltage drop) of the sense node drops to ground faster through a bias circuit to perform a quench operation, and then passes through an inverter (e.g., an inverter or inverter) to generate a pulse (e.g., a signal or a pulse). As a result, when a photon is injected, one (e.g., exactly one) pulse is generated. If, at the same time, the voltage drops to ground and then drops to a voltage at which no breakdown (e.g., breakdown or breakdown) of the SPAD occurs, the voltage is reset to return to VHIGH.

[0003] However, as in Fig. As can be seen in Figure 3, due to the variance in the SPAD, a difference (e.g., a difference) in the event timing (e.g., occurrence time) and a difference in the pulse width occur, and there is no element (e.g., no part) to correct the differences. Therefore, an error may be caused if a time and distance device (e.g., for measuring time and distance), such as a time-to-digital converter (TDC), is used behind a quenching circuit to verify the arrival time (e.g., arrival time) of a photon.

[0004] The contents described in the above description of the related art are intended to facilitate understanding of the background of the present disclosure / invention and may include what was not previously known to a person of ordinary skill in the art to which the present disclosure relates. EXPLANATION OF THE INVENTION

[0005] An embodiment of the present disclosure / invention is directed to providing a quench bias circuit device and a single photon detector comprising the same capable of operating without time difference (e.g., delay or time loss) even with a variance (e.g., deviation) of a single photon avalanche diode (SPAD).

[0006] Other objects and advantages of the present disclosure / invention can be understood from the following description and will become apparent upon reference to the embodiments of the present disclosure / invention. Furthermore, it will be apparent to one of ordinary skill in the art to which the present disclosure / invention pertains that the objects and advantages of the present disclosure / invention can be realized / attained by the claimed means and combinations thereof.

[0007] According to one embodiment of the present disclosure / invention, a quenching bias circuit device (quenching bias circuit device or quenching bias circuit device) comprises: a light receiving element, a feedback current mirror circuit (e.g., a feedback current mirror) arranged between a supply voltage and the light receiving element and configured (e.g., designed or formed) to induce (e.g., trigger) a passive quenching operation (e.g., quenching / suppression operation or operation) to keep a current flowing in the light receiving element constant, and a bias quenching circuit (e.g., a bias quenching circuit or bias quenching circuit) connected to a detection node of the light receiving element and configured to perform an active quenching operation (e.g., quenching operation or operation).

[0008] The feedback current mirror circuit may include a first feedback current mirror circuit configured to receive a supply current and a second feedback current mirror circuit configured to induce a current induced by the first feedback current mirror circuit to the light receiving element.

[0009] In the first feedback current mirror circuit, a plurality (e.g., a plurality or a plurality of) NPN transistors may be arranged and matched to each other (e.g., matched or made equal to each other), and in the second feedback current mirror circuit, a plurality (e.g., a plurality or a plurality of) PNP transistors may be arranged and matched to each other.

[0010] The light receiving element may be a single-photon light receiving element (single-photon avalanche diode (SPAD)).

[0011] The erase bias circuit device may further include a feedback operation control circuit configured to compare a detection voltage of the detection node with a preset reference value and determine (e.g., determine or set) the passive erase operation according to the comparison result.

[0012] The feedback operation control circuit may include a first comparator (e.g.

[0013] Comparator or comparison circuit) configured to compare the detection voltage with a first reference value among the reference values, a second comparator configured to compare the detection voltage with a preset second reference value that is smaller than the first reference value, and control logic configured to generate a control signal for the passive erase operation according to the comparison result.

[0014] The control signal may be an erase path control signal (quenching path control signal) that performs the passive erase operation or a non-erase path control signal (non-quenching path control signal) that does not perform the passive erase operation.

[0015] The first reference value and the second reference value can be set arbitrarily (e.g., freely selectable and / or as required) for the detection sensitivity (e.g., measurement accuracy) of the light receiving element.

[0016] The erase bias circuit device may further include a feedback operation control circuit (e.g., a feedback operation execution circuit) configured to execute the passive erase operation, which keeps a current flowing in the light receiving element constant according to the detection of the passive erase operation.

[0017] The feedback operation execution circuit may include a first switching element configured to conduct a first power (e.g., current, voltage, and / or charge) from a first charge pump in response to the erase path control signal, a first capacitor connected in parallel to the first switching element and configured to be charged with the first power, and a second capacitor connected in parallel to the first capacitor and configured to output an applied voltage applied to the feedback current mirror circuit using the supply voltage and the first power.

[0018] The feedback operation execution circuit may include a second switching element configured to conduct a second power from a second charge pump in response to the non-erase path control signal, a third capacitor connected in parallel to the second switching element and configured to be charged with the second power, and a third comparator connected in parallel to the third capacitor and configured to generate a hold operation signal (e.g., a hold operation signal) for a hold operation (e.g., a hold operation) of the feedback current mirror circuit using the supply voltage and the second power.

[0019] A third switching element configured to connect an output of the third capacitor to the second capacitor when the hold operation signal is not generated may be arranged between the third comparator and the second capacitor.

[0020] A fourth parallel-grounded switching element may be arranged in a front stage (e.g., in an upstream stage) of the first capacitor, the second capacitor, and the third capacitor.

[0021] The supply current can be continuously input into the feedback current mirror circuit.

[0022] According to another embodiment of the present disclosure / invention, a single photon detector includes the erase bias circuit device. Character list Fig. 1 and Fig. 2 are diagrams illustrating general bias circuits (e.g., prior art bias circuits). Fig. 3 is a diagram showing a time difference according to erasing operations (e.g., quenching operations) at detection nodes and a variance in the light receiving element of the general bias circuits of the Fig. 1 and Fig. 2 represents. Fig. 4 is a block diagram illustrating an erase bias circuit device of the present disclosure / invention. Fig. 5 to Fig. 7 are partial diagrams illustrating the erase bias circuit device of the present disclosure / invention. Fig. 8 is a graph illustrating a time difference according to an erase operation at a detection node and a variance in the light receiving element of the erase bias circuit device of the present disclosure / invention. Fig. 9 is a graph showing a simulation result of the erase bias circuit device of the present disclosure / invention. Fig. 10A is a graph showing a simulation result of a time difference according to a variance in the light receiving element of a conventional bias circuit, and Fig. 10B is a graph illustrating a simulation result of a time difference according to a variance in the light receiving element of an erase bias circuit device of the present disclosure / invention. Fig. 11 is a diagram illustrating an apparatus for testing the erase bias circuit device of the present disclosure / invention. Fig. 12A to Fig. 12C are graphs showing test results of the conventional bias circuit. Fig. 13A to Fig. 13C are graphs showing test results of the erase bias circuit device of the present disclosure / invention. DESCRIPTION OF SPECIFIC EMBODIMENTS

[0023] Reference is now made to the accompanying drawings which illustrate exemplary embodiments of the present disclosure / invention and to the description in the accompanying drawings in order to more fully understand the present disclosure / invention and the advantages in operation (e.g., in use) of the present disclosure / invention, as well as objects / advantages achieved / solved by using the present disclosure / invention.

[0024] In describing exemplary embodiments of the present disclosure / invention, known technologies or repeated descriptions may be reduced or omitted to avoid unnecessarily obscuring the gist of the present disclosure / invention.

[0025] Fig. 4 is a block diagram illustrating an erase bias circuit device of the present disclosure / invention, and Fig. 5 to Fig. 7 are partial diagrams illustrating the erase bias circuit device of the present disclosure / invention.

[0026] Hereinafter, an erase bias circuit device according to an embodiment of the present disclosure / invention and a single photon detector having the same will be described with reference to the Fig. 4 and Fig. 5 described.

[0027] A cancel bias circuit device 100 according to an embodiment of the present disclosure / invention is a bias circuit used in a single-photon detector and includes a light receiving element 110, a feedback current mirror circuit 120, a bias cancel circuit 130, a feedback operation control circuit 170, and a feedback operation execution circuit 180.

[0028] In addition, a supply voltage 140 and a supply current 150 are applied via a current / voltage supply device (e.g., a current and / or voltage source).

[0029] The light-receiving element 110 can convert light into electricity and can be a single-photon avalanche diode (SPAD) for detecting a single photon. The SPAD, which is the light-receiving element 110, causes changes in various processes (e.g., operations and / or operating states) due to variance in process, voltage, and temperature (PVT).

[0030] The feedback current mirror circuit 120 induces passive cancellation (e.g., passive quenching).

[0031] Unlike the related art, according to the present disclosure / invention, the bias canceling circuit 130 is used for passive canceling instead of a passive component. The feedback current mirror circuit 120 is located between the supply voltage (e.g., power supply) 140 and a detection node 160. The feedback current mirror circuit 120 keeps a current flowing in the light receiving element 110 constant. The feedback current mirror circuit 120 is used so that it is possible to keep the current flowing in the light receiving element 110 constant without a current drop occurring. For this purpose, the supply current 150 input to the feedback current mirror circuit 120 may be constant.

[0032] In order to keep the current flowing in the light receiving element constant with fewer errors, the feedback current mirror circuit 120 may include: a first feedback current mirror circuit 521 including an NPN transistor 501 (e.g., an NPN type transistor) and a second feedback current mirror circuit 522 including a PNP transistor 502 (e.g., a PNP type transistor).

[0033] That is, the supply current 150 is input to the first feedback current mirror circuit 521, which includes a first switching element 501, and a current induced by the first feedback current mirror circuit 521 is converted into a current 110 flowing in the light-receiving element by the second feedback current mirror circuit 522, which includes a second switching element 502, so that it is possible to keep the current flowing in the light-receiving element 110 constant. The first switching element 501 may be an NPN-type transistor, and the second switching element 502 may be a PNP-type transistor.

[0034] To maintain the accuracy of maintaining the flowing current constant, a feedback operation control circuit 170 and a feedback operation execution circuit 180 may be further used. The feedback operation control circuit 170 can more accurately detect (e.g., detect or determine) a variation in a voltage at the detection node 160, detect an additional current generated by the light-receiving element 110, determine an operation of the feedback operation execution circuit 180, and finally set a constant amount of current flowing in each of the light-receiving element 110 and the feedback current mirror circuit 120.

[0035] The bias quenching circuit 130 performs an erase operation. A basic (e.g., a basic) erase operation is as follows. When a photon is incident on the SPAD, a weak photon current flows. In this case, a passive quenching phenomenon (e.g., a passive quenching phenomenon) occurs due to a passive component, in which a voltage drop occurs at VHIGH (supply voltage). Subsequently, when active components such as semiconductor elements (MR, M Q , Ms and the like) detect a slight voltage drop, the active elements perform an active quenching process (e.g., an active quenching process), in which a voltage is rapidly and forcibly lowered. For this purpose, driver reference voltages REF P , REFN, REFB and REFT. A range of each of the driver reference voltages REF P , REF N , REF B and REF Tcan be arbitrarily adjusted (e.g., freely selectable and / or according to requirements) to adjust the detection sensitivity. Field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), and the like can be used as semiconductor elements.

[0036] Thus, when a photon is injected into the light receiving element 110 (e.g., incident and / or entering), a very small current flows through the passive component, and the voltage of the sensing node 160 drops compared to V LOWslightly. The drop voltage of the detection node 160 drops more rapidly to ground GND through a bias circuit to perform a clearing operation, and then passes through a digital circuit to generate a pulse. As a result, a pulse is generated when a photon is injected. At the same time, when the voltage drops to ground GND to reach a voltage at which no breakdown of the light-receiving element 110 occurs, the bias clearing circuit 130 resets the voltage to return the voltage to V LOW bring to.

[0037] As described above, in the erase bias circuit device 100 of the present disclosure / invention used in the single-photon detector, the feedback current mirror circuit 120 is applied as a passive component for passive erase, and the bias quench circuit 130 is applied to accelerate the erase operation (active erase or active quenching).

[0038] To increase the accuracy, the feedback operation control circuit 170 and the feedback operation execution circuit 180 may be additionally used. Fig. The feedback operation control circuit 170 shown in FIG. 6 can more accurately detect a variation (e.g., a fluctuation / deviation) of the voltage at the detection node 160 to further detect an additional current generated in the light receiving element 110. With reference to Fig. 6, the feedback operation control circuit 170 may include a first comparator 611, a second comparator 612, and control logic 620. The first comparator 611 and the second comparator 612 may be operational amplifiers (OP-AMPs).

[0039] The first comparator 611 and the second comparator 612 compare a detection voltage V s at the detection node 160 with reference voltages VREFH and VREFL to generate detection signals (e.g., determination signals) P1, P2, and P3. The detection signals P 1 , P 2 and P 3 are classified into three signals, comprising (e.g., including or containing) a non-quench signal (e.g., a non-quench signal), a quench signal (e.g., a quench signal), and a hold signal.

[0040] If the detection voltage V sis not generated at the light receiving element 110, the hold operation signal indicating a ready state (e.g., a standby state) is output. When the detection voltage V s (for example, in the range of zero to 30 V), the non-erase signal or the erase signal is output according to the comparison results of the first comparator 611 and the second comparator 612. That is, the detection signal P 1 is the non-erase signal, the detection signal P 2 is the erase operation signal and the detection signal P 3 is the hold signal. In other words, when the detection voltage V s is greater than a reference value (e.g. 15 V), the first comparator 611 outputs the detection signal P 1 off, and when the detection voltage V s is smaller than a reference value (e.g. 3 V.) ), the second comparator 612 outputs the detection signal P 2 out of.

[0041] The control logic 620 generates control signals such as an erase path control signal and a non-erase path control signal using the output signals P 1 and P 2 the first comparator 611 and the second comparator 612. For this purpose, the control logic 620 may be formed from an integrated circuit (IC, e.g., an integrated circuit) and the like.

[0042] With reference to Fig. 7, the feedback operation execution circuit 180 executes an operation in response to the control signal generated by the feedback operation control circuit 170. In other words, when the switching elements 701 and 703 are turned on in response to the erase path control signal, other switching elements 703 and 704 are turned on, and VHIGH and the power (e.g., the voltage, the current, and / or the charge) of a charge pump 1are summed to generate an applied voltage VG, which is applied to the first switching element 501 of the feedback current mirror circuit 120. Some switching elements 702 and 705 induce a current from the charge pump 1 to ground GND, and the switching element 704 allows a capacitor C 1 in a charged state, thereby outputting a higher voltage. The capacitor C3 is arranged for a load of the output. In other words, when the switching element 701 is turned on and the switching elements 702, 703, and 704 are turned off, the charging on the capacitor C 1 carried out.

[0043] Meanwhile, when the switching elements 711 and 713 are turned on in response to the non-erase path control signal, another switching element 712 is turned off, so that VHIGH and the power of a charge pump 2 are summed to be input to a third comparator 730. The third comparator 730 compares an input value with the reference voltage VREFL, and if the input value is less than the reference voltage VREF L is, the third comparator 730 outputs the detection signal P 3 The detection signal P3 is the hold operation signal.

[0044] When the third comparator 730 detects the detection signal P 3 not output, the switching element 714 is turned on to generate the applied voltage VG. Similar to the above description, a capacitor C2 is also kept in a charged state to output a higher voltage.

[0045] Finally, an amount (e.g., a part) of a current flowing in each of the light receiving element 110 and the feedback current mirror circuit 120 is set to be constant.

[0046] According to the related art, since the passive resistance element is used, it is susceptible to variation in a process voltage temperature (PVT) of a SPAD, and errors related to a current and a quenching time (e.g., a quenching time) occur. Furthermore, according to the related art, since a monostable state and control logic are separately processed externally, when an actual circuit is formed and a quenching circuit (e.g., a quenching circuit) including the SPAD is formed as a microcell, a portion of an area occupied (e.g., occupied) by the SPAD in the microcell is reduced, so there is also a disadvantage in the probability of detecting a single photon.

[0047] That is, since a characteristic of the SPAD is different, a -V LOW applied voltage varies differently, and thus a current flowing in the SPAD is varied, so that a different result is shown even though the same single photon is detected (e.g., similar photons are detected one after the other). If an absolute value of a voltage applied to -V LOW applied voltage is increased, a current flowing in the SPAD is increased, and when the current is increased, a reaction speed in a circuit is increased, so that an erase operation is started faster.

[0048] According to the present disclosure / invention, the above phenomenon can be compensated for by using the feedback current mirror circuit 120.

[0049] That is, due to a variance in the SPAD, a difference in the amount (e.g., height) of a flowing current and a time difference occur between a passive erase and an active erase. Since false information may be transmitted to a readout circuit, such as a time-to-digital converter (TDC) or an analog-to-digital converter (ADC) following the bias circuit, to reduce the overall performance of the circuit, errors due to the difference in the amount of current and the time difference can be compensated for using the feedback current mirror circuit 120. In addition, a voltage range of the reference voltage can be set arbitrarily (e.g., as needed), so that the detection sensitivity can be controlled (e.g., adjusted).

[0050] Consequently, as in Fig. 8, the feedback current mirror circuit 120 is used to balance currents flowing in the SPADs so that a difference in generation time and a difference in pulse width generated due to the variation in the SPAD can be removed (e.g., compensated and / or subtracted).

[0051] In general, a positron emission tomography (PET) / computed tomography (CT) or a PET / magnetic resonance imaging (MRI) device can process information by detecting a single photon, where the information comprises 1) an arrival time of an incident photon and 2) the number of photons arriving within a certain period of time after the arrival time. Since a circuit capable of detecting accurate timing information and counting the number of photons within the same time is required, it is important to process the photons error-free in a circuit for detecting (e.g., capturing) a photon. When an erase bias circuit device uses a feedback current mirror circuit, the same (e.g., the equivalent and / or equivalent) timing information can be provided regardless of the variance in the SPAD.

[0052] Fig. 9 is a graph showing a simulation result of the erase bias circuit device of the present disclosure using the feedback control logic circuit (e.g., control logic for the feedback circuit).

[0053] The control logic is to operate (e.g., act) in response to an on-state (an on-condition) of each of the switching elements (the non-erase signal, the erase signal, or the hold signal), and a detection comparator is used to distinguish the non-erase signal, the erase signal, and the hold signal.

[0054] An upper line of the graph represents a variation in the current at a VG node during a feedback process, and a lower line of the graph represents a variation in the voltage at the VG node during the feedback process. It can be confirmed that the current and voltage variations only occurred while feedback was provided, and there was no variation after the feedback was provided.

[0055] In addition, Fig. 10A is a graph showing a simulation result of a time difference according to a variance in the light receiving element of a conventional bias circuit, and Fig. 10B is a graph illustrating a simulation result of a time difference according to a variance in the light receiving element of an erase bias circuit device of the present disclosure / invention. In Fig. 10A, a time difference according to a variation in the SPAD was shown as 1.6 ns, and in Fig. 10B, the time difference was shown to be 100 ps or less.

[0056] Fig. Figure 11 is a diagram illustrating an apparatus for testing the erase bias circuit device of the present disclosure / invention. The erase bias circuit device was tested by applying a voltage in the range of -70 V to -72 V to an anode -V LOW the SPAD was applied using an S10362-11-100C SPAD from Hamamatsu Photonics KK, and by measuring in a dark room (e.g., a darkroom) using an oscilloscope, a light source, and a test board (e.g., a test board).

[0057] Fig. 12A to Fig. 12C are graphical representations showing test results of the conventional (e.g., the conventional) bias circuit, where a line 1220 (e.g., a gray or lighter line) indicates a pulse applied to the light source, and where a line 1210 (e.g., a black or darker line) indicates a result value from an output of a quenching circuit. When a voltage of -72 V is applied to the anode -V LOW the SPAD was created (see Fig. 12A), a delay of about 5.1 ns was observed between the light source and an erase output (e.g., an erase output, an erase power, an erase operation, or a quench output). When a voltage of -71 V is applied to the anode -V LOW the SPAD was created (see Fig. 12B), a delay of about 6.1 ns was observed between the light source and the erase output. When a voltage of -70 V was applied to the anode -V LOW the SPAD was created (see Fig. 12C)., a delay of about 7.2 ns was observed between the light source and the erase output.

[0058] Fig. 13A to Fig. 13C are graphs showing test results of the erase bias circuit device of the present disclosure / invention, where a line 1320 (e.g., a gray or lighter line) indicates a pulse applied to the light source, and where a line 1310 (e.g., a black or darker line) indicates a result value from an output of the erase bias circuit device. When a voltage of -72 V is applied to the anode -V LOW the SPAD was created (see Fig. 13A), a delay of about 5 ns was observed between the light source and an erase output. When a voltage of -71 V was applied to the anode -V LOW the SPAD was created (see Fig. 13B), a delay of about 5.1 ns was observed between the light source and the erase output. When a voltage of -70 V was applied to the anode -V LOW the SPAD was created (see Fig. 13C), a delay of about 5.2 ns was observed between the light source and the erase output.

[0059] As described above, it can be seen that according to the current feedback type (e.g., the current feedback type) of the present disclosure / invention, the time difference of the output with respect to the SPAD variation is reduced compared to a conventional resistance type. Specifically, the time difference of the resistance type was in the range of 5.1 ns to 7.2 ns, and the resistance type showed a difference of about 2.1 ns corresponding to the anode voltage difference. However, the time difference of the current feedback type was in the range of 5 ns to 5.2 ns, and the current feedback type showed a difference of about 200 ps, ​​which was only 10% of that of the resistance type.

[0060] According to the present disclosure, an error according to a variance in the light receiving element is compensated, so that it is possible to implement a precise (e.g., accurate or causing only small measurement errors) bias canceling circuit.

[0061] That is, without adding a circuit that requires a large area or large power consumption (e.g., power consumption or energy consumption), the same timing information and the same counter information can be provided with only a simplified feedback current mirror circuit and only a simplified erase bias circuit device.

[0062] While the present disclosure / invention has been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the scope of the present disclosure / invention and without being limited to the exemplary embodiments disclosed herein. Accordingly, it is to be understood that such changes or modifications are encompassed by the claims of the present disclosure / invention, and the scope of the present disclosure / invention should be construed based on the appended claims.

Claims

[1] Erase bias circuit device (100), comprising: a light receiving element (110), a feedback current mirror circuit (120) arranged between a supply voltage (140) and the light receiving element (110), wherein the feedback current mirror circuit (120) is configured to induce a passive erasing operation to keep a current flowing in the light receiving element (110) constant, and a bias cancel circuit (130) connected to a detection node (160) of the light receiving element (110) and configured to perform an active cancel operation. [2] The erase bias circuit device (100) of claim 1, wherein the feedback current mirror circuit (120) comprises: a first feedback current mirror circuit (521) configured to receive a supply current (150), and a second feedback current mirror circuit (522) configured to induce a current induced by the first feedback current mirror circuit (521) to the light receiving element (110), wherein the first feedback current mirror circuit (521) comprises a plurality of NPN transistors (501) arranged and matched to each other, and wherein the second feedback current mirror circuit (522) comprises a plurality of PNP transistors (502) arranged and matched to each other. [3] The erase bias circuit device (100) according to claim 1 or 2, wherein the light receiving element (110) comprises a single-photon light receiving element. [4] The erase bias circuit device (100) according to any one of claims 1 to 3, further comprising a feedback operation control circuit (170) configured to: compare a detection voltage of the detection node (160) with reference values, and Determining the passive erasing operation according to a comparison result of the detection voltage, wherein the feedback operation control circuit (170) comprises: a first comparator (611) configured to compare the detection voltage with a first reference value among the reference values, a second comparator (612) configured to compare the detection voltage with a preset second reference value that is smaller than the first reference value, and a control logic (620) configured to generate a control signal for the passive erasure operation according to the comparison results of the first comparator (611) and the second comparator (612), wherein a supply current (150) is continuously input into the feedback current mirror circuit (120). [5] The erase bias circuit device (100) according to claim 4, wherein the control signal comprises at least one of an erase path control signal that performs the passive erase operation or a non-erase path control signal that does not perform the passive erase operation, further comprising a feedback operation execution circuit (180) comprising: a first switching element (701) configured to receive a first power from a first charge pump (charge pump 1 ) in response to the erase path control signal, a first capacitor (C 1 ) which is connected in parallel to the first switching element (701) and which is configured to be charged with the first power, and a second capacitor (C 2 ), which is connected in parallel to the first capacitor (C 1) and which is configured to output an applied voltage applied to the feedback current mirror circuit (120) using the supply voltage (140) and the first power. [6] The erasing bias circuit device (100) according to claim 4 or 5, wherein the first reference value and the second reference value are arbitrarily set for a detection sensitivity of the light receiving element (110). [7] The erase bias circuit device (100) according to claim 5 or claim 6 as appended to claim 5, further comprising a feedback operation control circuit (170) configured to perform the passive erase operation, which keeps the current flowing in the light receiving element (110) constant according to detection of the passive erase operation, the feedback operation control circuit (170) comprising: a second switching element (711) configured to conduct a second power from a second charge pump (Charge Pump 2) in response to the non-erase path control signal, a third capacitor (C 3 ) which is connected in parallel to the second switching element (711) and which is configured to be charged with the second power, and a third comparator (730) connected in parallel with the third capacitor (C 3 ) and which is configured to generate a hold signal for a hold operation of the feedback current mirror circuit (120) using the supply voltage (140) and the second power. [8] The erase bias circuit device (100) according to claim 7, wherein, when the hold operation signal is not generated, a third switching element (714) configured to provide an output of the third capacitor (C 3 ) with the second capacitor (C 2) between the third comparator (730) and the second capacitor (C 2 ) is arranged. [9] The erase bias circuit device (100) according to claim 7 or 8, wherein a fourth parallel-grounded switching element (702, 705, 712) is provided in a front stage of the first capacitor (C 1 ), the second capacitor (C 2 ) and the third capacitor (C3). [10] A single photon detector comprising the erase bias circuit device (100) according to any one of claims 1 to 9.