Scalable structuring through layering process
DE102021114091B4Active Publication Date: 2025-03-06TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information
- Application Number
- DE102021114091
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-05-24
- Filing Date
- 2021-06-01
- Publication Date
- 2025-03-06
- Estimated Expiration
- 2041-06-01
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Abstract
Method (100) for manufacturing a semiconductor device, comprising: Forming (6) a dielectric layer (28) on a structure; Forming (8) an opening (30) in the dielectric layer (28) to expose an upper surface of the structure, wherein the opening (30) has a first width in the dielectric layer (28); Performing (10) an enlargement process on the dielectric layer (28) to reduce the first width of the opening (30) in the dielectric layer (28); wherein the step of performing an enlargement process comprises implanting a dopant into the dielectric layer (28), wherein the concentration of the dopant gradually decreases from an upper section of the dielectric layer (28) to a lower section of the dielectric layer (28), such that after the step of performing an enlargement process, the width of the opening (30) increases from an uppermost section of the dielectric layer (28) to a lowermost section of the dielectric layer (28); and after carrying out (10) the expansion process on the dielectric layer (28), filling the opening (30) with conductive material (37; 47) to form a conductive passage.
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Citation Information
Patent Citations
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