Semiconductor package with a rivet structure between two rings and method for forming the same.

Abstract

Semiconductor package comprising: a package substrate (10); a semiconductor device (20) mounted on a surface (10A) of the package substrate (10); a first ring (R1) arranged above the surface (10A) of the package substrate (10) and surrounding the semiconductor device (20), the first ring (R1) having a lower surface (S12) opposite the surface (10A) of the package substrate (10) and an upper surface (S11) opposite the lower surface (S12) of the first ring (R1);a second ring (R2) arranged above the upper surface (S11) of the first ring (R1), the second ring (R2) having a lower surface (S21) opposite the upper surface (S) of the first ring (R1) and an upper surface (S22) opposite the lower surface (S21) of the second ring (R2), and wherein a projecting part (RS2) extends from one of the upper surfaces (S12) of the first ring (R1) or the lower surface (S21) of the second ring (R2) and a recessed part (RS1) is recessed from the other surface of the upper surface (S11) of the first ring (R1) or the lower surface (S21) of the second ring (R2), the projecting part (RS2) extending into and engaging with the recessed part (RS1);and an adhesive layer (40) arranged between the surface (10A) of the package substrate (10) and the lower surface (S12) of the first ring (R1), wherein the protruding part (RS2) and the recessed part (RS1) have matching shapes and sizes in a vertical cross-sectional view, wherein the protruding part (RS2) has a first section (RS21) and a second section (RS22) with different widths in the vertical cross-sectional view, the first section (RS21) being closer to the upper surface (S11) of the first ring (R1) or the lower surface (S21) of the second ring (R2) than the second section (RS22), and the second section (RS22) having a greater width than the first section (RS21).

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US patent application 63 / 183,125, filed on May 3, 2021, which is incorporated by reference into the present application. BACKGROUND

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as PCs, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are manufactured by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. These layers are then structured using lithography and etching processes to create circuit components and elements. Many integrated circuits (ICs) are typically fabricated on a single semiconductor wafer, and individual dies on the wafer are separated by sawing between the integrated circuits along a scoring line. The individual dies are then typically packaged separately, for example, in multi-chip modules or other types of packages.

[0003] A package not only protects semiconductor components from environmental contaminants but also provides a connection interface for the semiconductor components it contains. Smaller package structures, occupying less space or having a lower height, have been developed for packaging these semiconductor components.

[0004] Although existing package structures and methods for manufacturing semiconductor package structures are generally sufficient for their intended purposes, they have not been entirely satisfactory in every respect. List of characters

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a schematic top view of a semiconductor package according to some embodiments. Fig. Figure 2 is a schematic cross-sectional view of the semiconductor package along line AA' in Fig. 1. Fig. Figure 3 is a schematic cross-sectional view of the semiconductor package along line AA' in Fig. 1 according to some other embodiments. Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D illustrates rivet structures with various horizontal cross-sectional shapes according to some other embodiments. Fig. Figures 5A-5C illustrate cross-sectional views of various intermediate stages in the formation of the rivet structure and the arrangement of the two rings that are in Fig. 2 or Fig. 3 are shown, according to some other embodiments. Fig. 6A and Fig. Figure 6B shows schematic cross-sectional views of rivet structures according to some other embodiments. Fig. 7A and Fig. Figure 7B shows schematic cross-sectional views of rivet structures according to some other embodiments. Fig. Figures 8A-8D illustrate cross-sectional views of various intermediate stages in the formation of the rivet structure and the arrangement of the two rings that are in Fig. 6A or Fig. 6B are shown, according to some other embodiments. Fig. Figures 9A-9D illustrate cross-sectional views of various intermediate stages in the formation of the rivet structure and the arrangement of the two rings that are in Fig. 7A or Fig. 7B are shown, according to some other embodiments. Fig. 10A, Fig. 10B, Fig. 10C and Fig. Figure 10D are schematic top views of semiconductor packages according to some other embodiments. Fig. 11A, Fig. 11B, Fig. 11C and Fig. Figure 11D shows schematic top views of semiconductor packages according to some other embodiments. Fig. 12A and Fig. Figure 12B shows schematic top views of semiconductor packages according to some other embodiments. Fig. Figure 13 illustrates that the upper ring is a covering structure, according to some other embodiments. Fig. Figure 14 is a simplified flowchart illustrating a method for forming a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and also embodiments in which additional structural elements can be formed between the first and second structural elements in such a way that the first and second structural elements cannot be in direct contact.Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like can be used here to simplify the description and describe the relationship of one element or structural element to another element (or elements) or structural element(s), as illustrated in the figures. In addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the component in use or operation. The object may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptions used here can be interpreted accordingly.

[0008] For a person skilled in the art, the term "essentially" in the description, as in "essentially flat" or "essentially coplanar," etc., is understandable. In some embodiments, the adjective "essentially" may be omitted. Where appropriate, the term "essentially" may also include embodiments with "entirely," "completely," "everything," etc. Where appropriate, the term "essentially" may also refer to 90% or higher, such as 95% or higher, in particular 99% or higher, including 100%. Furthermore, terms such as "essentially parallel" or "essentially perpendicular" are to be interpreted in such a way as not to exclude a minor deviation from the specified arrangement and may include deviations of, for example, up to 10°. The word "essentially" does not exclude "completely"; for example, a composition that is "essentially free" of Y may be completely free of Y.

[0009] Terms like "approximately" in conjunction with a specific distance or size are to be interpreted as not excluding minor deviations from that specific distance or size and may include deviations of, for example, up to 10%. The term "approximately" in relation to a numerical value x can mean x ± 5 or 10%.

[0010] According to various embodiments, a semiconductor package and the method for forming it are provided. Some variants of some embodiments are discussed. In the different views and illustrative embodiments, the same reference numerals are used to denote the same elements. According to some embodiments of the present disclosure, a semiconductor package has a lower ring and an upper ring joined by means of rivet structures (instead of an additional adhesive) formed between the rings. Each rivet structure has a protruding portion and a corresponding recessed portion, each formed on adjacent faces of the ring. The use of rivet structures prevents delamination of the adhesive layer between the rings during temperature changes.By arranging the rivet structures to correspond to the high-stress areas within the semiconductor package, they further contribute to reducing stresses in the package (as described below), thereby improving the overall package reliability. Since the rings can be directly joined by the rivet structures (eliminating the need for adhesive bonding), the semiconductor package manufacturing process can also be simplified.

[0011] Embodiments are described in relation to a specific context, namely a packaging technique with an interposer substrate or other active chip in a two-and-a-half-dimensional integrated circuit structure (2.5DIC structure) or a three-dimensional IC structure (3DIC structure). The embodiments discussed herein are used to provide examples to enable the manufacture or use of the subject matter of this disclosure, and a person skilled in the art will readily understand modifications that may be made without departing from the considered scope of various embodiments. Although some embodiments of the process may be discussed below as being carried out in a particular sequence, other embodiments of the process consider steps that are carried out in any logical order.

[0012] Fig. Figure 1 is a schematic top view of a semiconductor package according to some embodiments. Fig. Figure 2 is a schematic cross-sectional view of the semiconductor package along line AA' in Fig. 1. As in Fig. 1 and Fig. As shown in Figure 2, the semiconductor package comprises a package substrate 10, a semiconductor device 20, a ring structure arrangement 30, and an adhesive layer 40. In other embodiments, additional structural elements can be added to the semiconductor package and / or some of the structural elements described below can be replaced or omitted.

[0013] The package substrate 10 can be used to provide an electrical connection between components or devices packaged within the semiconductor package and an external electronic device (not shown). In some embodiments, the package substrate 10 is a bulk semiconductor substrate, a semiconductor-on-insulator substrate (SOI substrate), a germanium-on-insulator substrate (GOI substrate), or the like. The semiconductor substrate is formed from an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Alternatively, according to some other embodiments, the package substrate 10 can include a printed circuit board (PCB), a ceramic substrate, or another suitable package substrate. The package substrate 10 can be a cored substrate or a coreless substrate.

[0014] In some embodiments, the package substrate 10 incorporates various device elements (not shown). Examples of device elements formed in or on the package substrate 10 may include transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), etc.), diodes, resistors, capacitors, inductors, and / or other applicable device elements. Various processes may be used to form the device elements, such as deposition, etching, implantation, photolithography, annealing, and / or other suitable processes.The package substrate 10 may also include one or more circuit layers (not shown) which are used for electrically connecting the subsequently attached device elements and semiconductor components.

[0015] Package substrate 10 shows in a top view (see Fig. 1) Depending on the design requirements, the package substrate generally has a rectangular (or square) shape, although other shapes may also be used. The package substrate 10 may have opposing surfaces 10A and 10B, which may be substantially parallel to each other. Surface 10A (the upper surface shown) may be used to receive and bond other package components (described in detail below). Surface 10B (the lower surface shown) may have several electrical connectors 11 formed on it to provide an electrical connection between the entire package and an external electronic component, such as a PCB (not shown). In some embodiments, the electrical connector 11 may be or include solder balls, such as tin-containing solder balls. The solder balls may be bonded to the package substrate 10 using a melting process.

[0016] The semiconductor device 20 is arranged over the area 10A of the package substrate 10. In some embodiments, the semiconductor device 20 is a package module that includes an interposer 21 and a plurality of different types of semiconductor dies 22 and 22' (see Fig. 1) which are arranged above the interposer 21. For the sake of clarity, the semiconductor dies 22 are referred to herein as first dies 22 and the semiconductor dies 22' are referred to herein as second dies 22'. The semiconductor device 20 may also have one or more third dies (not shown) which are distinct from the first dies 22 and the second dies 22'.

[0017] In some embodiments, the first dies 22 include a logic die, which may be a die of a central processing unit (CPU), a die of a graphics processing unit (GPU), a die of a mobile application, a die of a microcontroller control unit (MCU), an input / output die (I / O die), a baseband die (BB die), a die of an application processor (AP), or the like. The first dies 22 may also include system-on-chip dies (SOC dies). In some embodiments, the second dies 22 include memory dies, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high-bandwidth memory (HBM) die, or the like.The memory dies can be discrete memory dies or can be in the form of a die stack, which has a plurality of stacked memory dies.

[0018] Each of the semiconductor dies 22 and 22' can have a semiconductor substrate 220 and a plurality of IC components (not shown, including transistors, diodes, passive devices, etc.) formed on the semiconductor substrate 220. Several contact pads 222, connected to the internal circuits, can also be exposed on the respective active areas (the lower surface shown) of the semiconductor dies 22 and 22', where external electrical connections are made. Each semiconductor die 22 / 22' can be obtained, for example, by sawing or splitting a semiconductor wafer (with several IC dies formed on it) along score lines to subdivide the semiconductor wafer into a plurality of individual semiconductor dies.

[0019] Depending on the actual requirements, the semiconductor dies 22 and 22' can have any suitable arrangement above the interposer 21, which will be described in more detail later. The interposer 21 can include an organic interposer substrate, a silicon interposer substrate, or the like. The interposer 21 can also include conductive structural elements 210, such as conductive lines and conductive vias (sometimes collectively referred to as a redistribution line structure (RDL structure)), to connect contact pads (not shown) exposed on opposite faces 21A and 21B of the interposer 21. The materials and the method for forming the interposer 21 are well known in the art and are therefore not described here.

[0020] In some embodiments, the semiconductor dies 22 and 22' on the interposer 21 can be bonded by flip-chip bonding (e.g., solder bonding) using the conductive elements 23 on each semiconductor die 22 / 22' and the conductive structures 24 on the interposer 21 to form conductive junctions, as shown in Fig. Figure 2 shows that the embodiments described here are provided for illustrative purposes and that other suitable bonding methods in various embodiments may also be used.

[0021] In some embodiments, the conductive elements 23, such as conductive pillars, can be formed on the exposed contact pads 222 of the semiconductor dies 22 / 22' prior to the bonding process. The conductive elements 23 can be made of or contain copper, aluminum, gold, cobalt, titanium, tin, one or more other suitable materials, or a combination thereof. The conductive elements 22 can be formed using an electroplating process, a electroless plating process, a placement process, a printing process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, one or more other applicable processes, or a combination thereof. In some alternative embodiments, the conductive elements 23 can be omitted.

[0022] In some embodiments, each of the conductive structures 24 has a metal pillar 24A and a metallic cap layer (such as a solder cap) 24B over the metal pillar 24A. The conductive structures 24 comprising the metal pillars 24A and the metallic cap layers 24B are sometimes referred to as micro-humps. The conductive structures 24 can be formed prior to the bonding process on the exposed contact pads (not shown) on the surface 21A of the interposer 21. The metal pillars 24A can contain a conductive material such as copper, aluminum, gold, nickel, palladium, the like, or a combination thereof, and can be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars 24A can be solderless and have substantially vertical sidewalls.The metallic cap layers 24B can contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and can be formed by a plating process, such as an electroplating process. It is understood by the average person skilled in the art that the foregoing examples of conductive structures 24 are provided for illustrative purposes and that other structures of conductive structures 24 may also be used.

[0023] In some embodiments, the semiconductor dies 22 and 22' are bonded to the interposer 21 by a melting process. During the melting, the conductive connection points (including the conductive elements 23 and the conductive structures 24) are in contact with the exposed contact pads 222 of the semiconductor dies 22 and 22' or the exposed contact pads (constructed by some conductive structural elements 210) of the interposer 21, in order to couple the semiconductor dies 22 and 22' physically and electrically to the interposer 21.

[0024] In some embodiments, an underfill element 25 is further formed over the interposer 21 to surround and protect the conductive junctions and to improve the connection between the semiconductor dies 22 and 22' and the interposer 21. The underfill element 25 can be made of or contain an insulating material, such as an underfill material. The underfill material can be an epoxy, a resin, a filler, a stress release agent (SRA), an adhesion promoter, another suitable material, or a combination thereof. In some embodiments, an underfill material in a liquid state is dispensed into the gap between each semiconductor die 22 / 22' and the interposer 21 (for example, by capillary action) to improve the strength of the conductive junctions and thus of the entire package structure.After being dispensed, the underfill material is hardened to form the underfill element 25.

[0025] In some embodiments, the underfill element 25 fills the entire gap between each semiconductor die 22 / 22' and the interposer 21 and also has a section 250 extending into a gap G between adjacent first dies 22, as in Fig. 2 shown. Section 250 is in Fig. One is available, but not shown.

[0026] In some embodiments, an encapsulation layer 26 is further formed over the interposer 21 to surround and protect the semiconductor dies 22 and 22' and the underfill element 25. In some embodiments, the encapsulation layer 26 is made of or contains an insulating material, such as a molding material. The molding material may contain a polymeric material, such as an epoxy-based resin with fillers dispersed therein. In some embodiments, a molding material (such as a liquid molding material) is dispensed over the interposer 21 and / or over the semiconductor dies 22 and 22' such that the semiconductor dies 22 and 22' are embedded or covered. In some embodiments, a thermal process is then used to cure the liquid molding material and transform it into the encapsulation layer 26.

[0027] In some embodiments, a planarization process (not shown) is also performed on the encapsulation layer 26 to partially remove the encapsulation layer 26 until the back (top surface) of each first die 22 is exposed through the top surface of the encapsulation layer 26, as shown in Fig. Figure 2 shows that this facilitates the dissipation of heat generated during the operation of the first dies 22 (for example, in cases where the first dies 22 are high-power dies). The planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof.

[0028] In some embodiments, the semiconductor device 20 (for example, including the interposer 21, the semiconductor dies 22 and 22', the underfill element 25, and the encapsulation layer 26) can be bonded to the package substrate 10 by conductive elements 27 (such as conductive pillars) formed on the contact pads (not shown) exposed on surface 21B (the lower surface shown) of the interposer 21, and conductive structures 28 (such as microbumps having a metal pillar 28A and a metallic cap layer 28B (such as a solder cap) over the metal pillar 28A) formed on the contact pads (not shown) exposed on surface 10A of the package substrate 10, as shown in Fig. Figure 2 shows the materials and the method for forming the conductive elements 27 and the conductive structures 28 may be the same or similar to those of the conductive elements 23 and the conductive structures 24 described above and are not repeated here. In some embodiments, the semiconductor device 20 is bonded to the package substrate 10 by a melting process. During melting, the conductive junctions (including the conductive elements 27 and the conductive structures 28) are in contact with the exposed contact pads of the interposer 21 and the exposed contact pads of the package substrate 10, respectively, to physically and electrically connect the semiconductor device 20 to the package substrate 10.

[0029] In some embodiments, an underfill element 29 is also formed over the area 10A of the package substrate 10 to surround and protect the conductive connection points and to improve the connection between the semiconductor device 20 and the package substrate 10. The materials and the method for forming the underfill element 29 may be the same as or similar to those of the underfill element 25 described above and are not repeated here.

[0030] The ring structure arrangement 30 is arranged over the area 10A of the package substrate 10. The ring structure arrangement 30 can have a greater stiffness than the package substrate 10 and can be configured as a reinforcing ring to confine the package substrate 10 in order to mitigate its distortion (due to stresses generated during temperature cycling, which is further described below) and / or to improve the robustness of the package substrate 10. In some embodiments, the ring structure arrangement 30 is arranged along the circumference of the package substrate 10 and surrounds the semiconductor device 20 above the package substrate 10. The ring structure arrangement 30 can have a substantially rectangular or square ring shape in plan view (see Figure 1). Fig. 1) depending on the shape of the package substrate 10.

[0031] In some embodiments, the ring structure assembly 30 is attached to the package substrate 10 using the adhesive layer 40, which is positioned between the lower surface of the ring structure assembly 30 and the upper surface 10A of the package substrate 10. The adhesive layer 40 can be any suitable non-conductive adhesive, an epoxy resin, a die attach film (DAF), or the like, and can be applied to the lower surface of the ring structure assembly 30 or can be applied over surface 10A of the package substrate 10 before the ring structure assembly 30 is mounted.

[0032] As in Fig. As shown in Figure 2, the ring structure arrangement 30, according to some embodiments, has a lower ring 31 and an upper ring 32. The upper ring 32 is arranged above (or stacked on top of) the lower ring 31, and the lower ring 31 is located near the surface 10A of the package substrate 10 when the ring structure arrangement 30 is mounted on the package substrate 10.

[0033] In some embodiments, both the lower ring 31 and the upper ring 32 are ring structures that laterally surround the semiconductor device 20, and each ring structure has a uniform width W1 or W2. The width W1 of the lower ring 31 can be equal to the width W2 of the upper ring 32, although the disclosure is not limited to this. In some other embodiments, one or both of the lower ring 31 and the upper ring 32 can have non-uniform widths (for example, the ring sides can have unequal widths along a first horizontal direction (e.g., the one in the Fig. (shown in the X-direction 1) have a width that, depending on the design requirements, is greater or smaller than the ring sides along a second horizontal direction (e.g., the one shown in Fig. 1 shown Y-direction)).

[0034] In some embodiments, the lower ring 31 is a substantially flat structure with opposing surfaces 31A and 31B. Surface 31B (the lower surface shown) of the lower ring 31 faces surface 10A of the package substrate 10. The adhesive layer 40 is positioned between surface 31B (i.e., the lower surface of the ring structure assembly 30) and surface 10A to attach the ring structure assembly 30 to the package substrate 10. Similarly, the upper ring 32 is a substantially flat structure with opposing surfaces 32A and 32B. Surface 32B (the lower surface shown) of the upper ring 32 faces and is in direct contact with surface 31A (the upper surface shown) of the lower ring 31. In some embodiments, the surfaces 31A and 31B of the lower ring 31, the surfaces 32A and 32B of the upper ring 32 and the surface 10A of the package substrate 10 are parallel to each other.

[0035] In some embodiments, the lower ring 31 and the upper ring 32 are made of or contain different materials. For example, the material of the lower ring 31 can be selected such that its coefficient of thermal expansion (CTE) is similar to that of the underlying package substrate 10, thereby reducing the CTE mismatch between them and thus decreasing the stress (and deformation) on the package substrate 10 caused by the ring structure assembly 30. Conversely, the material of the upper ring 32 can be selected such that its stiffness is greater than that of the lower ring 31, thereby increasing the structural strength of the entire ring structure assembly 30. Consequently, the distortion of the package substrate 10 can be better controlled.Examples of the material of the lower ring 31 and the upper ring 32 may include metals such as copper, stainless steel / Ni and the like.

[0036] In some embodiments, as in Fig. As shown in Figure 2, the lower ring 31 further comprises recessed parts RS1 formed on the surface 31A opposite the upper ring 32, and the upper ring 32 further comprises projecting parts RS2 formed on the surface 32B opposite the lower ring 31, each corresponding to the recessed parts RS1. Each of the recessed parts RS1 can be recessed vertically from the surface 31A of the lower ring 31 to the interior of the lower ring 31, and each of the projecting parts RS2 can extend vertically from the surface 32B of the upper ring 32 and into the respective recessed part RS1 of the lower ring 31.

[0037] In some alternative embodiments, as in Fig. Figure 3 shows the positions of the recessed parts RS1 and the protruding parts RS2 reversed, and the other structural elements are the same as in the figures shown. Fig. 2 embodiments shown. In particular, the recessed parts RS1 are formed on the surface 32B of the upper ring 32, which is opposite the lower ring 31, and the protruding parts RS2 are formed on the surface 31A of the lower ring 31, which is opposite the upper ring 32.

[0038] According to some embodiments, each projecting part RS2 and the respective recessed part RS1 have matching shapes and sizes in the vertical cross-sectional view. For example, in the Fig. 2 and Fig. 3 the protruding part RS2 has a rectangular shape in the vertical cross-sectional view with a uniform width D2 and the recessed part RS1 has a rectangular receiving space (see Fig. 5B) in the vertical cross-sectional view with a uniform width D1, where the width D1 is equal to or slightly greater than the width D2. Also, the depth L1 of the recessed part RS1 in the vertical direction (e.g., the one in Fig. 2 or Fig. 3 Z-direction shown) perpendicular to the surface 10A of the package substrate 10 equal to or slightly greater than the thickness L2 of the protruding part RS2 in the vertical direction.

[0039] Due to the design described above, the projecting parts RS2 engage with the recessed parts RS1, thereby connecting the lower ring 31 and the upper ring 32 to form a ring structure arrangement 30 (no additional adhesive layer is provided between the lower ring 31 and the upper ring 32). Since the combination of the recessed part RS1 and the corresponding projecting part RS2 can perform the function of assembling two flat rings, it is also referred to in this disclosure as a “rivet structure” RS.

[0040] In some embodiments, each rivet structure RS may have a horizontal cross-sectional shape (i.e., a top-view shape) determined by the horizontal cross-sectional shape of the respective recessed part RS1 (which is further described below). For example, in cases where the horizontal cross-sectional shape of the recessed parts RS1 is a circle, the rivet structures RS (or the protruding parts RS2) may have a circular horizontal cross-sectional shape, as shown in Fig. Figure 1 shows that the diameter of the circular rivet structure RS can range from 1 mm to 7 mm, although other sizes can also be used. In some alternative embodiments, the rivet structures RS can also have other horizontal cross-sectional shapes, such as an ellipse, a square, a triangle, or a hexagon, as shown in the following. Fig. 4A-4D illustrated, or have another suitable form.

[0041] In some embodiments, each rivet structure overlaps RS, as shown in Fig. Figure 1 shows, in plan view, part of the ring structure arrangement 30 (i.e., the lower ring 31 and the upper ring 32). In other words, each rivet structure RS is not only arranged between the lower ring 31 and the upper ring 32, but is also located, in plan view, within the boundary of the corresponding ring side of the ring structure arrangement 30. In various embodiments, each rivet structure RS can be located in the central region of the ring structure arrangement 30 at an equal distance (in a horizontal direction, such as the X-direction or the Y-direction) from the inner and outer circumferences of the ring structure arrangement 30 (see Figure 1). Fig. 2 or Fig. 3) be arranged or may be arranged near the inner or outer circumference of the ring structure arrangement 30.

[0042] Next, the formation of the rivet structure RS and the assembly of the two rings (31, 32) will be described. Fig. 2 or Fig. 3 are shown, with reference to Fig. 5A-5C according to some embodiments. For the sake of simplicity, only one rivet structure RS is shown in these figures. Fig. In 5A, a first flat ring R1 and a second flat ring R2 are provided. In various embodiments, the first ring R1 can be used as the lower ring 31 and the second ring R2 can be used as the upper ring 32, or the first ring R1 can be used as the upper ring 32 and the second ring R2 can be used as the lower ring 31.

[0043] In Fig. 5B, a recessed part RS1 with vertical sidewalls is then formed on the surface S11 of the first ring R1, which faces the second ring R2 (when the rings are separated), by a suitable process (not shown), including mechanical drilling, etching, or the like. In some embodiments, the recessed part RS1 formed may have a sufficient depth L1 (i.e., the distance between the surface S11 and the bottom of the recessed part RS1) in the vertical direction (e.g., the depth L1). Fig. 2 or Fig. 3 shown in the Z-direction) to facilitate a subsequent stable engagement between the recessed part RS1 and the protruding part RS2, but where the depth L1 is less than the thickness L3 of the first ring R1 (i.e., the distance between the surface S11 and the opposite surface S12 of the first ring R1) in the vertical direction.

[0044] In Fig. In step 5C, the second ring R2 is stacked on top of the first ring R1, with surface S21 of the second ring R2 abutting surface S11 of the first ring R1. A thrust force (pressure, indicated by an arrow) can then be applied to surface S22 of the second ring R2, opposite surface S21, causing a section (i.e., the protruding part RS2) of the second ring R2 to be compressed, extending from surface S21 of the second ring R2 into the corresponding recessed part RS1 formed on surface S11 of the first ring R1. This ensures that the horizontal cross-sectional shape and size of the protruding part RS2 (or rivet structure RS) matches the horizontal cross-sectional shape and size of the corresponding recessed part RS1. The thrust force can be released until the protruding part RS2 reaches (or nearly reaches) the bottom of the recessed part RS1.As a result, each protruding part RS2 can fit tightly into (or engage with) the corresponding recessed part RS1, thereby connecting the first ring R1 and the second ring R2 to form the ring structure arrangement 30 described above with reference to . Fig. 2 or Fig. 3 is described. In some embodiments, as in Fig. Figure 5C shows that the surface S22 of the second ring R2 also has depressions, as illustrated by the dashed lines, the depressions being formed due to the formation of the projecting parts RS2 on the opposite surface S21. Accordingly, depressions of surface S22 may be located corresponding to the recessed part RS1, and the shapes of depressions of surface S22 in plan view may resemble the shapes of the recessed part RS1. In some other embodiments, the final shapes of the first ring R1 and the second ring R2 may be formed by molding or other methods.

[0045] Many variations and / or modifications can be made to the embodiments of the disclosure. For example, illustrate Fig. 6A, Fig. 6B, Fig. 7A and Fig. 7B Rivet structures RS with different vertical cross-sectional shapes according to some other embodiments. For the sake of simplicity, only one rivet structure RS is shown in these figures. It should be understood that the difference between Fig. 6A and Fig. 6B and between Fig. 7A and Fig. 7B consists in the fact that the positions of the recessed part RS1 and the protruding part RS2 are reversed.

[0046] Referring to Fig. 6A and Fig. 6B, the recessed part RS1 is formed on one of the lower ring 31 and the upper ring 32 and is formed by opposite surfaces (31A and 31B or 32A and 32B) of the ring. In other words, the depth L1 of the recessed part RS1 can be in the vertical direction (e.g., the Z-direction, as in Fig. 2 or Fig. 3 shown) equal to the thickness L3 of the ring in the vertical direction. The resulting recessed part RS1 can be a trapezoidal receiving space in the vertical cross-sectional view (see Fig. 8B) with a gradually increasing width D3 (i.e., inclined side walls) in the vertical direction furthest from the other ring. In particular, the section of the recessed part RS1 located closest to the other ring has the smallest width, and the section of the recessed part RS1 located furthest from the other ring has the largest width. This helps to prevent the projecting part RS2 (formed on the other ring) from easily detaching from the recessed part RS1. Furthermore, the projecting part RS2 extends from the (proximal) face of the other ring opposite the ring with the recessed part RS1 and into the recessed part RS1. Accordingly, in the vertical cross-sectional view, the projecting part RS2 has a trapezoidal shape with a gradually increasing width D4 in the vertical direction furthest from the other ring.The variation in the width of the protruding part RS2 matches the variation in the width of the recessed part RS1.

[0047] Referring to Fig. 7A and Fig. 7B, the recessed part RS1 is formed on one of the lower ring 31 and the upper ring 32 and is formed by opposite surfaces (31A and 31B or 32A and 32B) of the ring. In other words, the depth L1 of the recessed part RS1 can be in the vertical direction (e.g., the Z-direction, as in Fig. 2 or Fig. (3 shown) equal to the thickness L3 of the ring in the vertical direction. The recessed part RS1 can be a first section (receiving space, see) in the vertical cross-sectional view. Fig. 9B) RS11 and a second section (recording room, see Fig. 9B) RS12 has different widths (D51, D52). The first section RS11 is located close to the other ring, and the second section RS12 is located farther away from the other ring. The width D52 of the second section RS12 is greater than the width D51 of the first section RS11. This helps prevent the protruding part RS2 (formed on the other ring) from easily detaching from the recessed part RS1. In this embodiment, both the first section RS11 and the second section RS12 are rectangular, although other shape combinations can also be used. For example, in some other embodiments, the first section RS11 can be rectangular, and the second section RS12 can be trapezoidal. Furthermore, the protruding part RS2 extends from the (proximal) face of the other ring, which is opposite the ring with the recessed part RS1, and into the recessed part RS1.Accordingly, the projecting part RS2 has a first section RS21 and a second section RS22 with different widths (D61, D62) in the vertical cross-sectional view. The first section RS21 is located near the (proximal) face of the other ring, and the second section RS22 is located away from the (proximal) face of the other ring. The width D62 of the second section RS22 is greater than the width D61 of the first section RS21. The variation in width and shape of the projecting part RS2 corresponds to the variation in width and shape of the recessed part RS1.

[0048] In some embodiments, as in the Fig. 6A, Fig. 6B, Fig. 7A and Fig. As shown in Figure 7B, the protruding part RS2 is received (or embedded) in the recessed part RS1 and there is a distance X (greater than 0) in the vertical direction between the end of the protruding part RS2 and the (distal) surface of the ring that is located away from the other ring.

[0049] Additionally, the rivet structure RS (made of Fig. 6A, Fig. 6B, Fig. 7A or Fig. 7B) in the central area of ​​the ring structure arrangement 30 at an equal distance (in the horizontal direction) from the inner and outer circumference of the ring structure arrangement 30, or may be arranged near the inner or outer circumference of the ring structure arrangement 30, similar to the embodiments described above in Fig. 2 and Fig. 3.

[0050] Next, the formation of the rivet structure RS and the assembly of the two rings (31, 32) will be described. Fig. 6A or Fig. 6B are shown, with reference to Fig. 8A-8D according to some embodiments described. In Fig. Figure 8A provides a first flat ring R1 and a second flat ring R2. In various embodiments, the first ring R1 can be used as the lower ring 31 and the second ring R2 as the upper ring 32, or the first ring R1 can be used as the upper ring 32 and the second ring R2 as the lower ring 31.

[0051] In Fig. 8B then forms a recessed portion RS1 with inclined sidewalls in the first ring R1 (when the rings are separated) by a suitable process (not shown), including mechanical drilling, etching, or the like. The recessed portion RS1 may extend through opposite faces S11 and S12 of the first ring R1 and may have a gradually varying width D3, as above with reference to Fig. 6A and Fig. 6B described.

[0052] In Fig. 8C, the second ring R2 is then stacked on top of the first ring R1, with surface S21 of the second ring R2 abutting surface S11 of the first ring R1. Subsequently, an impact force (pressure, indicated by an arrow) is applied to surface S22 of the second ring R2, opposite surface S21, so that a section (i.e., the protruding part RS2) of the second ring R2 is compressed to extend from surface S21 of the second ring R2 and into the corresponding recessed part RS1 formed on surface S11 of the first ring R1. This causes the horizontal cross-sectional shape and size of the protruding part RS2 to match the horizontal cross-sectional shape and size of the section of the corresponding recessed part RS1 located immediately adjacent to the second ring R2. The impact force can be released until a section (e.g.,End section) of the preceding part RS2 extends beyond the area S12 of the first ring R1 (see . Fig. 8C). In some embodiments, as in Fig. Figure 8C shows that the surface S22 of the second ring R2 also has depressions, as illustrated by dashed lines, the depressions being formed due to the formation of the protruding parts RS2 on the opposite surface S21.

[0053] In Fig. 8D another impact force (pressure, indicated by an arrow) is applied to the protruding part RS2 (while the second ring R2 remains fixed) from the surface S12 of the first ring R1 to push the end section of the protruding part RS2 back into the recessed part RS1, thereby forming the pushed protruding part RS2 into the same shape as the recessed part RS1.

[0054] As a result, each protruding part RS2 is tightly fitted into (or engages with) the corresponding recessed part RS1, thereby connecting the first ring R1 and the second ring R2 to form the ring structure arrangement 30, which with reference to Fig. 6A or Fig. 6B is described.

[0055] The formation of the rivet structure RS and the assembly of the two rings (31, 32), which in Fig. 7A or Fig. 7B are shown with reference to Fig. 9A-9D according to some embodiments described. In Fig. Figure 9A provides a first flat ring R1 and a second flat ring R2. In various embodiments, the first ring R1 can be used as the lower ring 31 and the second ring R2 as the upper ring 32, or the first ring R1 can be used as the upper ring 32 and the second ring R2 as the lower ring 31.

[0056] In Fig. 9B then forms a recessed part RS1, comprising a first section RS11 and a second section RS12, with different widths in the first ring R1 (when the rings are separated) by a suitable process (not shown), including mechanical drilling, etching, or the like. The recessed part RS1 may extend through opposite faces S11 and S12 of the first ring R1, and the width D52 of the second section RS12 may be greater than the width D51 of the first section RS11, as described above with reference to Fig. 7A and Fig. 7B described.

[0057] In Fig. In step 9C, the second ring R2 is stacked on top of the first ring R1, with surface S21 of the second ring R2 abutting surface S11 of the first ring R1. A force (pressure, indicated by an arrow) is then applied to surface S22 of the second ring R2, opposite surface S21, causing a section (i.e., the protruding part RS2) of the second ring R2 to be compressed, extending from surface S21 of the second ring R2 into the corresponding recessed section RS1 formed on surface S11 of the first ring R1. This ensures that the horizontal cross-sectional shape and size of the protruding part RS2 matches the horizontal cross-sectional shape and size of the section (i.e., the first section RS11) of the corresponding recessed section RS1 located immediately adjacent to the second ring R2.The section of the protruding part RS2 within the first section RS11 of the recessed part RS1 forms the first section RS21 of the protruding part RS2. The impact force can be released until a section (e.g., end section) of the protruding part RS2 extends beyond the surface S12 of the first ring R1 (see ). Fig. 9C). In some embodiments, as in Fig. Figure 9C shows that the surface S22 of the second ring R2 also has depressions, as illustrated by dashed lines, the depressions being formed due to the formation of the protruding parts RS2 on the opposite surface S21.

[0058] In Fig. 9D another impact force (pressure, indicated by an arrow) is exerted on the projecting part RS2 (while the second ring R2 remains fixed) from the surface S12 of the first ring R1 to push the end section of the projecting part RS2 back into the recessed part RS1, thereby forming the projecting part RS2 thus pressed into the same shape as the recessed part RS1 (the section of the projecting part RS2 in the second section RS12 of the recessed part RS1 forms the second section RS22 of the projecting part RS2).

[0059] As a result, each protruding part RS2 is tightly fitted into (or engages with) the corresponding recessed part RS1, thereby connecting the first ring R1 and the second ring R2 to form the ring structure arrangement 30, which with reference to Fig. 7A or Fig. 7B is described.

[0060] It should be understood that the geometries and manufacturing processes described herein are merely illustrative and are not intended to limit, nor should they be interpreted as limiting, the present disclosure. Many alternatives and modifications are readily apparent to the person skilled in the art once informed by the present disclosure.

[0061] It should also be understood that the various package components and substrate materials mentioned above, used in the semiconductor package, may have different CTEs. Therefore, if the package is subjected to temperature changes during package assembly, reliability testing, or field operation, the package components and substrate materials may expand at different rates, causing the package substrate 10 to warp. The ring structure arrangement 30 can reduce this warping to some extent; however, because the ring structure arrangement 30 confines the package substrate 10, this confining force also creates stress in the package substrate 10 and the various package components located on it.As discussed above, since the lower ring 31 and the upper ring 32 of the ring structure arrangement 30 can be directly connected by the aforementioned rivet structure RS, no additional adhesive layer is required to connect the lower ring 31 and the upper ring 32. Thus, the risk of delamination of the adhesive layer between the rings during temperature changes can be eliminated.

[0062] Additionally, the rivet structures RS can also be arranged in such a way that the stress in the package can be reduced or eliminated.

[0063] For example, with reference to Fig. 1 and Fig. Figures 10A-10D illustrate schematic top views of various semiconductor packages according to some embodiments. Fig. 1 and Fig. 10-10D can place the first dies 22 in a two-dimensional (2D) matrix (such as 1x2, 1x4, 2x1, 2x2 or 2x4) in the central area of ​​the interposer 21 (see Fig. 2 or Fig. 3) be arranged and the second dies 22' can be arranged around the first dies 22. Other arrangements and other numbers of semiconductor dies 22 and 22' can also be used in various embodiments. Typically, the voltage generated by temperature changes can be applied to areas between dies in the package (for example, the small gaps G between adjacent first dies 22, as in Fig. 2 or Fig. 3) concentrate, which easily leads to the formation of cracks in the underfill element(s) used (such as section 250 of underfill element 25) corresponding to these areas, thus triggering the reliability problems. By arranging the rivet structures RS such that they correspond to the elongated small gap (areas of high stress) between adjacent first dies 22 in the plan view, as shown in the Fig. 1 and Fig. As shown in Figures 10A-10D, this helps to relieve stress in the package and improve the reliability of the entire package structure. This is due to a reduction in the coupling effect between the ring structure arrangement 30 and the package substrate 10 at the rivet structure RS.

[0064] In some embodiments, two rivet structures RS are arranged on opposite sides of each gap between adjacent first dies 22, and the two rivet structures RS and the corresponding gap are aligned in a (virtual) straight line in the top view, as shown in Fig. 1 and Fig. 10A-10D shown, although only one rivet structure RS may be arranged on one side of each gap between adjacent first dies 22 and aligned in a (virtual) straight line at the corresponding gap in the top view.

[0065] Fig. Figures 11A-11D illustrate schematic top views of various semiconductor packages according to some other embodiments. Embodiments of the Fig. 11A-11D differ from the embodiments of Fig. 10A-10D in that additional rivet structures RS can be provided and arranged to correspond, in plan view, to the corners of the semiconductor device 20 (or the corners of the package substrate 10). This further helps to reduce the stress concentrated in the die corner regions of the package, thereby improving the reliability of the overall package structure. In some embodiments where the gap between adjacent first dies 22 is larger (the generated stress can be reduced), the rivet structures RS corresponding to the gaps can also be omitted.

[0066] In some alternative embodiments, some rivet structures RS can also be arranged to correspond in plan view to the gaps between adjacent second dies 22' and / or the gaps between the first dies 22 and an adjacent second die 22' (in cases where the gaps are small) to solve the stress problem.

[0067] In some embodiments, as in Fig. 12A and Fig. Figure 12B shows several (e.g., two) rivet structures RE arranged on the same side of the gap between adjacent first dies 22, and the rivet structures RE and the gap are aligned in a (virtual) straight line in the top view. In comparison to using a single rivet structure RE (see Fig. 10C and Fig. 10D) Several rivet structures RE (or several rows of rivet structures RE) arranged in the width direction of the ring structure arrangement 30 can increase the connection strength between the lower ring 31 and the upper ring 32 of the ring structure arrangement 30.

[0068] Fig. Figure 13 is a schematic cross-sectional view of a semiconductor package according to some other embodiments. Embodiments of Fig. 13 differ from embodiments of Fig. 2 in that the upper ring 32' is a cover structure (rather than a ring structure) that extends over and covers an upper surface of the semiconductor device 20. As a cover structure, the upper ring 32' can have a high thermal conductivity (Tk), for example, between about 200 W / m·K and about 400 W / m·K or more, and can be configured as a heat sink to disperse heat generated by the semiconductor device 20. The cover structure can be formed using a metal, a metal alloy, or the like. For example, the material of the cover structure can include metals and / or metal alloys, such as Al, Cu, Ni, Co, the like, or a combination thereof. In various embodiments, the cover structure (the upper ring 32') is formed of a material substantially similar to that of the lower ring 31 or of a different material than that of the lower ring 31.The upper ring 32' and the lower ring 31 can also be described by the structures RS (in . Fig. (illustrated in 1-12B) without an additional adhesive layer.

[0069] In some embodiments, as in Fig. Figure 13 shows a thermal interface material (TIM) 50 arranged between the upper ring 32' and the upper surface of the semiconductor device 20, and in contact with them to facilitate heat dissipation from the semiconductor device 20. The thermal interface material 50 can be made of or contain a highly thermally conductive material, such as a metal-based material or a solder-based material containing copper, silver, indium paste, or the like. In some other embodiments, the thermal interface material 50 is omitted, and the upper ring 32' rests directly against the upper surface of the semiconductor device 20.

[0070] It is understood that, although a package module is described as an example of the semiconductor device 20 in the embodiments described above, the semiconductor device 20 can also be of other types (for example, a single semiconductor chip or a single semiconductor die).

[0071] Fig. Figure 14 is a simplified flowchart illustrating a process for forming a semiconductor package (such as the semiconductor package described in Fig. 1-3 and Fig. Figures 10A-13 illustrate some embodiments. In process step 101, the semiconductor device 20 is mounted on the package substrate 10, as shown in Fig. 2 shown. In process step 102, a first ring R1 and a second ring R2 are provided, as shown in Fig. 5A, Fig. 8A or Fig. 9A shown. In process step 103, recessed parts RS1 are formed on the first ring R1, as shown in Fig. 5B, Fig. 8B or Fig. 9B shown. In process step 104, protruding parts RS2 are formed on the second ring R2, and then the first ring R1 and the second ring R2 are joined together to form the ring structure arrangement 30 (including the joined lower ring 31 and upper ring 32) by engaging the protruding parts RS2 with the recessed parts RS1, as shown in Fig. 5C, Fig. 8D or Fig. Figure 9D shows that since the lower ring 31 and the upper ring 32 can be directly connected by the rivet structure RS (including the mating protruding parts RS2 and recessed parts RS1), the semiconductor package fabrication process can be simplified (as the step of providing an adhesive layer to join the lower ring 31 and the upper ring 32 can be omitted). In process step 105, the ring structure assembly 30 is attached to the package substrate 10 via the adhesive layer 40, which is located between the lower face of the lower ring 31 and the upper face 10A of the package substrate 10, as shown in Figure 9D. Fig. 2 shown.

[0072] The embodiments of the present disclosure exhibit several advantageous features. By using rivet structures to connect the rings (or a ring and a cover), the risk of delamination of the adhesive layer between the rings during temperature changes is eliminated. The manufacturing process of the semiconductor package can also be simplified. Furthermore, by arranging the rivet structures to correspond to high-stress areas (such as areas between dies and / or die corner regions) in the semiconductor package, they contribute to reducing stress in the package, thereby improving the overall package reliability.

[0073] In some embodiments, a semiconductor package is provided. The semiconductor package comprises a package substrate, a semiconductor device, a first ring, a second ring, and an adhesive layer. The semiconductor device is mounted on the surface of the package substrate. The first ring is positioned over the surface of the package substrate and surrounds the semiconductor device. The first ring has a lower surface facing the surface of the package substrate and an upper surface facing the lower surface of the first ring. The second ring is positioned over the upper surface of the first ring. The second ring has a lower surface facing the upper surface of the first ring and an upper surface facing the lower surface of the first ring.Furthermore, a protruding portion extends from one side of the upper surface of the first ring and the lower surface of the second ring, and a recessed portion extends from the other side of the upper surface of the first ring and the lower surface of the second ring. The protruding portion extends into the recessed portion and engages with it. The adhesive layer is located between the upper surface of the package substrate and the lower surface of the first ring.

[0074] In some embodiments, a semiconductor package is provided. The semiconductor package comprises a package substrate, a semiconductor device, a first ring, a second ring, and an adhesive layer. The semiconductor device is mounted on the surface of the package substrate. The first ring is positioned over the surface of the package substrate and surrounds the semiconductor device. The second ring is stacked on top of the first ring, with the lower surface of the second ring facing the upper surface of the first ring. Furthermore, several rivet structures are arranged between the first and second rings and spaced apart from one another. Each rivet structure has a protruding portion formed on the upper surface of the first ring or on the lower surface of the second ring, and a recessed portion formed on the other side formed by the upper surface of the first ring and the lower surface of the second ring.The protruding part is fitted into the recessed part. The adhesive layer is positioned between the upper surface of the package substrate and the lower surface of the first ring.

[0075] According to some embodiments, a method for forming a semiconductor package is provided. The method comprises mounting a semiconductor device onto a surface of a package substrate. The method also comprises providing a first ring with a first surface and a second ring with a second surface opposite the first surface of the first ring. The method also comprises forming at least one recessed portion on the first surface of the first ring. The method further comprises forming at least one protruding portion on the second surface of the second ring and connecting the first ring and the second ring by engaging the protruding portion with the recessed portion. Additionally, the method comprises attaching the first ring and the second ring to the surface of the package substrate via an adhesive layer formed between the package substrate and one of the first ring and the second ring.

[0076] The foregoing outlines features of several embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. The person skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. The person skilled in the art should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and modifications to them without deviating from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 183125

[0001]

Claims

[1] Semiconductor package comprising: a package substrate; a semiconductor component that is mounted on an area of ​​the package substrate; a first ring arranged over the surface of the package substrate and surrounding the semiconductor device, wherein the first ring has a lower surface opposite the surface of the package substrate and an upper surface opposite the lower surface of the first ring; a second ring arranged above the upper surface of the first ring, the second ring having a lower surface opposite the upper surface of the first ring and an upper surface opposite the lower surface of the second ring, and wherein a projecting part extends from one surface of the upper surface of the first ring or the lower surface of the second ring, and a recessed part extends from the other surface of the upper surface of the first ring or the lower surface of the second ring, the projecting part extending into and engaging with the recessed part; and an adhesive layer that is arranged between the surface of the package substrate and the lower surface of the first ring. [2] Semiconductor package according to claim 1, wherein the upper surface of the first ring is in direct contact with the lower surface of the second ring and there is no adhesive layer provided between the first ring and the second ring. [3] Semiconductor package according to claim 1 or 2, wherein the first ring contains a first material and the second ring contains a second material which differs from the first material. [4] Semiconductor package according to one of the preceding claims, wherein the protruding part and the recessed part have matching shapes and sizes in a vertical cross-sectional view. [5] Semiconductor package according to claim 4, wherein the protruding part has a rectangular shape with a uniform width in the vertical cross-sectional view. [6] Semiconductor package according to claim 4, wherein the foregoing part has a first section and a second section having different widths in the vertical cross-sectional view, wherein the first section is closer to the upper surface of the first ring or the lower surface of the second ring than the second section, wherein the second section has a greater width than the first section. [7] Semiconductor package according to any of the preceding claims, wherein the depth of the recessed part in a vertical direction perpendicular to the surface of the package substrate is greater than or equal to the thickness of the protruding part in the vertical direction. [8] Semiconductor package according to claim 7, wherein in the vertical direction the depth of the recessed part is less than or equal to the thickness of the first ring or the second ring having the recessed section, and wherein the recessed part extends through the top surface and the bottom surface of the respective first ring or the respective second ring when the depth of the recessed part is equal to the thickness of the respective first ring or the respective second ring. [9] Semiconductor package according to one of the preceding claims, wherein both the first ring and the second ring are ring structures that laterally surround the semiconductor device. [10] Semiconductor package according to any one of claims 1 to 8, wherein the first ring is a ring structure that surrounds the semiconductor device laterally, and the second ring is a cover structure that extends over and covers an upper surface of the semiconductor device. [11] Semiconductor package comprising: a package substrate; a semiconductor component that is mounted on an area of ​​the package substrate; a first ring that is arranged over the surface of the package substrate and surrounds the semiconductor device; a second ring stacked on top of the first ring, wherein a lower surface of the second ring faces an upper surface of the first ring, wherein a plurality of rivet structures are arranged between the first ring and the second ring and spaced apart from each other, each of the plurality of rivet structures having the following features: a projecting part formed on one of the upper surfaces of the first ring and the lower surface of the second ring; and a recessed part formed on the other side of the upper surface of the first ring and the lower surface of the second ring, the protruding part being fitted into the recessed part; and an adhesive layer that is arranged between the surface of the package substrate and a lower surface of the first ring. [12] Semiconductor package according to claim 11, wherein the semiconductor device has two dies arranged side by side and a gap formed between the two dies, which is elongated, and wherein one or more of the plurality of rivet structures are arranged in a top view according to the gap. [13] Semiconductor package according to claim 12, wherein two rivet structures of the plurality of rivet structures are arranged on opposite sides of the gap and the two rivet structures and the gap are aligned in a straight line in the top view. [14] Semiconductor package according to claim 12, wherein two rivet structures of the plurality of rivet structures are arranged on the same side of the gap and the two rivet structures and the gap are aligned in a straight line in the top view. [15] Semiconductor package according to claim 11, wherein the semiconductor device has corners and some of the plurality of rivet structures are arranged in a top view corresponding to the corners of the semiconductor device. [16] Method for forming a semiconductor package, comprising: Mounting a semiconductor device onto a surface of a package substrate; Providing a first ring with a first surface and a second ring with a second surface opposite the first surface of the first ring; Forming at least one recessed part on the first surface of the first ring; Forming at least one projecting part on the second surface of the second ring and connecting the first ring and the second ring by engaging the at least one projecting part with the at least one recessed part; and Attaching the first ring and the second ring to the surface of the package substrate via an adhesive layer formed between the package substrate and one of the first ring and the second ring. [17] Method according to claim 16, wherein the first surface of the first ring, the second surface of the second ring and the surface of the package substrate are parallel to each other. [18] Method according to claim 16 or 17, wherein, after forming the at least one recessed part on the first surface of the first ring, the method further comprises: Stacking the second ring on top of the first ring, with the second face of the second ring abutting the first face of the first ring; and Exerting a thrust on a third surface of the second ring, opposite to the second surface of the second ring, to form the at least one projecting part extending from the second surface of the second ring and into the at least one recessed part of the first ring from the first surface. [19] Method according to claim 18, wherein the at least one recessed part is formed by the first surface of the first ring and a fourth surface of the first ring, which is opposite the first surface, and wherein the at least one projecting part is inserted into the at least one recessed part by the first surface and has a section extending beyond the fourth surface, and wherein the method further comprises: Applying a further thrust to the at least one projecting part from the fourth face of the first ring, while the second ring remains fixed, to push the section of the at least one projecting part back into the at least one recessed part, thereby engaging the at least one projecting part with the at least one recessed part. [20] Method according to any one of claims 16 to 19, wherein the first ring and the second ring contain different materials.