Integrated image sensor chip and method for its manufacture

Abstract

Integrated image sensor chip, featuring: a substrate (102) having a first side (102a) and a second side (102b) opposite the first side (102a), wherein the substrate (102) has one or more side walls forming a trench (1502) extending along opposite sides of a pixel area (106) having a first width (w1); an insulation structure (114) comprising one or more dielectric materials provided within the trench (1502), wherein the insulation structure (114) has a second width (w2); an image sensor element (104) that is provided within the pixel area (106); a focus area (122) provided within the pixel area (106), wherein the focus area (122) is configured to receive incident radiation (120) along the second side (102b) of the substrate (102); and wherein the first width (w1) is less than or equal to 0.7 micrometers, wherein the ratio of the second width (w2) to the first width (w1) is in a range between 0.1 and 0.2, such that the focus area (122) is completely confined between inner side walls of the insulation structure (114) facing the image sensor element (104).

Description

BACKGROUND

[0001] Integrated circuits (ICs) with image sensors are used in a wide variety of modern electronic devices, such as cameras and mobile phones. In recent years, complementary metal-oxide-semiconductor image sensors (CMOS image sensors) have gained widespread use and largely replaced charge-coupled device image sensors (CCD image sensors). CMOS image sensors are increasingly preferred over CCD image sensors due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing costs. Types of CMOS image sensors include front-side illuminated (FSI) and back-side illuminated (BSI) image sensors.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in the publications KR 10 2018 0 116 781 A, US 11 824 075 B2, DE 10 2018 118 613 A1, US 10 763 289 B2 and US 20 20 / 0 227 459 A1.

[0003] The present invention is defined by independent claims 1 and 15. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1A-1B illustrate some embodiments of an integrated image sensor chip (image sensor IC) having an isolation structure that has a width designed to improve the performance of the image sensor IC. Fig. Figures 2A-2B illustrate some additional embodiments of an image sensor IC having a disclosed isolation structure. Fig. Figure 3 illustrates some embodiments of a curve showing the effect of diffraction limits for different pixel sizes. Fig. Figures 4-5 illustrate top views of some additional embodiments of an integrated image sensor chip (image sensor IC) having a disclosed isolation structure. Fig. Figures 6-9 illustrate cross-sectional views of some additional embodiments of an image sensor IC having a disclosed isolation structure. Fig. Figures 10-21 illustrate cross-sectional views of some embodiments of a method for forming an image sensor IC having a disclosed isolation structure. Fig. Figure 22 illustrates a flowchart of some embodiments of a method for forming an image sensor IC that has a disclosed isolation structure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments and exemplary embodiments for implementing various features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element above or on top of a second structural element in the following description can have embodiments in which the first and second structural elements are formed in direct contact, and also embodiments in which additional structural elements can be formed between the first and second structural elements in such a way that the first and second structural elements cannot be in direct contact.Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like can be used here to simplify the description and describe the relationship of one element or structural element to another element (or elements) or structural element(s), as illustrated in the figures. In addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the component in use or operation. The object may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptions used here can be interpreted accordingly.

[0007] CMOS image sensors (CIS) typically feature multiple pixel areas arranged in an array. Each of these pixel areas contains an image sensor element located within a semiconductor substrate and laterally surrounded by insulating structures designed to electrically isolate adjacent pixel areas. Multiple microlenses are positioned over these pixel areas. Each microlens is configured to focus incident radiation (e.g., incident light) onto an underlying image sensor element. Upon receiving the incident radiation, the image sensor element converts it into an electrical signal. This electrical signal from the image sensor element can then be processed by a signal processing unit to determine the image captured by the CIS.

[0008] When the dimensions of the integrated chip are scaled down (e.g., decreased), the dimensions of the pixel areas within the integrated circuit are also scaled down (e.g., decreased). However, the widths of the isolation structures surrounding the pixel areas are generally not scaled down, as the widths do not negatively affect the pixel areas and narrower isolation structures are more challenging to manufacture (e.g., with regard to etching and / or dielectric filling). It was found that when the size of a pixel area is further reduced to a width of approximately 0.7 micrometers or less, the size of a focal area cannot be reduced to a size that can be confined between the inner sidewalls of the isolation structure. This is because the scaling of the focal area is limited by a diffraction limit of an overlying microlens.Furthermore, it was recognized that the diffraction limit of the microlens is difficult to modify, as it is a function of a numerical aperture that is limited by the size and / or material of the microlens. Since the size of the focal area is not easily reduced, the focal area of ​​a microlens (e.g., the area onto which the microlens focuses incident radiation) begins to overlap with an isolation structure around the pixel area. This overlap between the focal area and the isolation structure results in a reduced amount of incident radiation reaching an image sensor element within the pixel area, thereby negatively impacting the image sensor element's performance.

[0009] The present disclosure relates to an integrated image sensor chip (image sensor IC) comprising an insulating structure surrounding a pixel area having a width less than or equal to approximately 0.7 micrometers. The insulating structure is designed to enhance the performance of an image sensor element within the pixel area. In some embodiments, the image sensor IC includes an image sensor element located within a pixel area of ​​a substrate. The substrate has one or more sidewalls defining a trench extending along opposite sides of the pixel area. An insulating structure comprising one or more dielectric materials is provided within the trench. The pixel area has a first width less than or equal to approximately 0.7 micrometers, and the insulating structure has a second width smaller than the first width.A focal area, configured to receive incident radiation, is also provided within the pixel area along a second side of the substrate. The ratio of this second width to the first width is in the range of approximately 0.1 to 0.2, such that the focal area is essentially confined between the inner sidewalls of the isolation structure facing the image sensor element. This width, which effectively confines the focal area between the inner sidewalls of the isolation structure, enables the image sensor IC to receive a large amount of incident radiation, resulting in good performance at pixel widths of approximately 0.7 micrometers or less.

[0010] Fig. Figures 1A-1B illustrate some embodiments of an integrated image sensor chip (image sensor IC) 100, which has an isolation structure having a width that is configured to improve the performance of the image sensor IC.

[0011] The cross-sectional view of Fig. The image sensor IC 100 shown in Figure 1A has a substrate 102 having a first side 102A (e.g., a front) and a second side 102b (e.g., a back) opposite the first side 102a. An image sensor element 104 is provided within a pixel area 106 of the substrate 102. The image sensor element 104 is configured to convert incident radiation 120 into an electrical signal. One or more transistor gate structures 110 are arranged along the first side 102a of the substrate 102. In some embodiments, one or more transistor gate structures 110 are coupled to one or more interconnects 112 provided within a dielectric structure 108 arranged on the first side 102a of the substrate 102.

[0012] An insulating structure 114 is arranged within the substrate 102 and along opposite sides of the pixel area 106. For example, the pixel area 106 can extend from an outer side wall of the insulating structure 114, facing away from the image sensor element 104, to an inner side wall of the insulating structure 114, facing the image sensor element 104. In some embodiments, the insulating structure 114 can comprise one or more dielectric materials arranged within a trench defined by side walls of the substrate 102. In some embodiments, the insulating structure 114 extends from the second side 102b of the substrate 102 into the interior of the substrate 102. In some further embodiments, the insulating structure 114 can extend from the second side 102b of the substrate 102 to the first side 102a of the substrate 102.

[0013] A color filter 116 is provided on the second side 102b of the substrate 102, and a microlens 118 is arranged on the color filter 116. The microlens 118 has a curved surface 118s facing away from the substrate 102. The curved surface 118s is configured to focus incident radiation 120 onto a focus area 122 located along the second side 102b of the substrate 102 above the image sensor element 104. In some embodiments, the microlens 118 may have a numerical aperture in a range between approximately 0.3 and approximately 0.75.

[0014] As shown in the top view 124 of Fig. 1B shown (along the intersection line AA' of Fig. 1A), the pixel area 106 has a first width w1 and the isolation structure 114 has a second width w2, measured along one side of the pixel area 106. In some embodiments, the first width w1 can be less than or equal to about 0.7 micrometers. In some such embodiments, the second width w2 of the isolation structure 114 lies in a range between about 10% and about 20% of the first width w1 of the pixel area 106. In other such embodiments, the ratio between the second width w2 and the first width w1 lies between about 0.1 and about 0.2 (e.g., 0.1 < w2 / w1 < 0.2).Due to the second width w2 of the isolation structure 114, which lies in a range between approximately 10% and approximately 20% of the first width w1 of the pixel area 106, the isolation structure 114 occupies a sufficiently small footprint of the pixel area 106 such that the focus area 122 can be essentially limited between the inner side walls 114s of the isolation structure 114. By limiting the focus area 122 essentially between the inner side walls 114s of the isolation structure 114, a large amount of the incident radiation 120 reaches the image sensor element 104, thereby increasing the performance of the image sensor element 104.

[0015] Fig. Figures 2A-2B illustrate some additional embodiments of an image sensor IC 200 having a disclosed isolation structure.

[0016] As in Fig. As shown in Figure 2A, the image sensor IC 200 has a substrate 102. In various embodiments, the substrate 102 can be a semiconductor body of any type (e.g., silicon, SiGe, SOI, etc.) as well as semiconductor layers and / or an epitaxial layer of any other type associated with it. An image sensor element 104 is arranged within a pixel area 106 of the substrate 102. In various embodiments, the image sensor element 104 can be a photodiode, a phototransistor, or the like.

[0017] An insulating structure 114 is arranged within the substrate 102 and along opposite sides of the pixel area 106. The insulating structure 114 comprises one or more dielectric materials provided within a trench in the substrate 102. In some embodiments, the trench extends from the second side 102b of the substrate 102 into the interior of the substrate 102. In some further embodiments, the insulating structure 114 may be separated from the first side 102a of the substrate 102 by a non-zero distance 201. In some embodiments, the insulating structure 114 may comprise a first dielectric material 202 and a second dielectric material 204 provided above the first dielectric material 202.In some such embodiments, the first dielectric material 202 is arranged along side walls and a horizontally extending surface of the substrate 102, and the second dielectric material 204 is arranged along side walls and a horizontally extending surface of the first dielectric material 202. In some embodiments, the first dielectric material 202 may comprise a dielectric material with a high k-value, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), or the like. In some embodiments, the second dielectric material 204 may contain an oxide (e.g. silicon oxide), TEOS (tetraethyl orthosilicate), a nitride (e.g. silicon nitride, silicon oxynitride, etc.), a carbide (e.g. silicon carbide, silicon oxycarbide, etc.) or the like.

[0018] One or more transistor gate structures 110 are arranged along the first side 102a of the substrate 102 and within the pixel area 106. In various embodiments, the one or more transistor gate structures 110 can correspond to a transfer transistor, a source follower transistor, a line selector transistor, and / or a reset transistor. In some embodiments, the one or more transistor gate structures 110 can include a transfer gate configured to selectively control the movement of charge carriers between the image sensor element 104 and a floating diffusion tray 205, which has a doped region arranged within the substrate 102.

[0019] A dielectric structure 108 is also provided along the first side 102a of the substrate 102 and covers the one or more transistor gate structures 110. The dielectric structure 108 surrounds a plurality of interconnects 112. In some embodiments, the dielectric structure 108 comprises a plurality of stacked interlayer dielectric (ILD) layers 105. In some embodiments, the plurality of interconnects 112 comprises conductive contacts 112a, interconnect leads 112b, and / or interconnect vias 112c. In some embodiments, the dielectric structure 108 may further comprise a plurality of etch stop layers 107 provided between adjacent stacked ILD layers 105.In some additional embodiments, the dielectric structure 108 may further comprise a contact etch stop layer (CESL) 103, which separates the one or more transistor gate structures 110 from the next one from the plurality of stacked ILD layers 105.

[0020] In some embodiments, the plurality of stacked ILD layers 105 may contain one or more silicon dioxide, SiCOH, a fluorosilicate glass, a phosphate glass (e.g., boron phosphate silicate glass), or the like. In some embodiments, the etch stop layers 107 and the CESL 103 may contain a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. In some embodiments, the plurality of interconnects 112 may contain copper, tungsten, ruthenium, aluminum, and / or the like.

[0021] A lattice structure 206 is provided on the second side 102b of the substrate 102. In some embodiments, the lattice structure 206 can be arranged directly above one or more isolation structures 114. In some embodiments, the lattice structure 206 can extend along a closed path around the pixel area 106. In some embodiments, the lattice structure 206 can contain a metal such as aluminum, cobalt, copper, silver, gold, tungsten, etc.

[0022] A dielectric material 208 can be provided over the grid structure 206. A color filter 116 is arranged between side walls of the grid structure 206 and / or the dielectric material 208. The color filter 116 is configured to transmit specific wavelengths of the incident radiation 120. A microlens 118 is arranged over the color filter 116. The microlens 118 is configured to focus the incident radiation 120 (e.g., light) onto a focal area 122 along the second side 102b of the substrate 102. In some embodiments, the focal area 122 is limited between inner side walls of the insulating structure 114, which face the image sensor element 104.

[0023] In some embodiments, the color filter 116 is configured to have a different (e.g., a lower) refractive index than the dielectric material 208. The difference between the refractive indices of the color filter 116 and the dielectric material 208 leads to internal refraction of the incident radiation 120 (e.g., light) within the color filter 116, forming a light-guiding structure configured to focus the incident radiation 120 onto a focal area 122. By using the light-guiding structure to focus the incident radiation 120 onto a focal area 122, the focal area 122 can be better confined between inner sidewalls of the insulating structure 114, and crosstalk between the pixel area 106 and an adjacent pixel area (not shown) can be attenuated.

[0024] In some embodiments, the dielectric material 208 may comprise a porous dielectric material (e.g., a porous oxide) having a relatively low density (e.g., less than or equal to about 1.5 g / cm³). 3 In some embodiments, the color filter 116 may include a monomer, a polymer, or the like. In some embodiments, the color filter 116 may have a refractive index greater than about 1.6, that is, in a range between about 1.5 and about 1.9, between about 1.6 and about 1.8, between about 1.7 (that is, about 1.67), about 1.65, or other similar values. In some embodiments, the dielectric material 208 may have a refractive index less than about 1.4, less than about 1.45 (that is, in a range between about 1.0 and about 1.4), between about 1.1 and about 1.3 (that is, about 1.2), about 1.25, about 1.27, or other similar values.

[0025] In some embodiments, as in the top view 210 of Fig. 2B (along the intersection line AA' of Fig. As shown in Figure 2A), the focus region 122 between the inner side walls 114s of the insulation structure 114 can be limited along a first direction 212 and along a second direction 214, which is perpendicular to the first direction 212. In such embodiments, the first direction 212 and the second direction 214 can be parallel to the second side 102b of the substrate 102. In some embodiments, the focus region 122 can be separated from the inner side walls 114s of the insulation structure 114 by a first distance 216, which is smaller than a second distance 218 between the focus region 122 and a corner 114c of the insulation structure 114 (e.g., where the inner side walls 114s of the insulation structure 114 meet). In some embodiments, the first distance 216 can be in a range between about 0 nm (nanometers) and about 50 nm. In some embodiments, the second distance 218 can be in a range between about 10 nm and about 250 nm.

[0026] In some embodiments, the pixel area 106 may have a first width w1, and the insulation structure 114 may have a second width w2, measured along one side of the pixel area 106. In some embodiments, the first width w1 may be less than about 0.7 micrometers, less than about 0.5 micrometers, or have other similar values. In some embodiments, the second width w2 may be less than or equal to about 140 nm, in a range between about 70 nm and about 140 nm, between about 50 nm and about 70 nm, or have other similar values. It has been recognized that if the second width w2 is less than about 50 nm, the insulation structure 114 may not provide sufficient electrical insulation between the pixel area 106 and an adjacent pixel area (not shown).

[0027] Fig. Figure 3 illustrates some embodiments of a curve 300 that shows the effect of diffraction limits for different pixel sizes. The curve 300 illustrates the width of a pixel area along an X-axis and the width of a confined focus area (e.g., the width of a focus area confined between inner sidewalls of an insulation structure) along a Y-axis.

[0028] As shown in curve 300, if the width of the pixel area is large (e.g., greater than a first width w1), the width of the focus area can be reduced and still be confined between the inner sidewalls of an isolation structure. Line 302 illustrates a width of focus area within the substrate of a conventional isolation structure (e.g., an isolation structure having a width greater than 20% of the width of a pixel area). As shown by line 302, if the width of the pixel area shrinks below a first width w1 (e.g., to a width of about 0.7 micrometers), a diffraction limit 306 of an overlying microlens determines the limit of how small the width of the focus area can become.Since the width of the focus area cannot shrink further, the width of the pixel area cannot shrink further below the first width w1 without resulting in a loss of performance of an associated image sensor element.

[0029] Line 304 shows the width of a focal region for a disclosed isolation structure, which has a relatively small width, less than or equal to about 20% of the width of the pixel region. As shown by line 304, if the width of a pixel region shrinks below the first width w1 (e.g., to about 0.7 micrometers), the focal region is able to scale further before being bounded by a diffraction limit 308 (e.g., a diffraction limit of the same size as diffraction limit 306). This is because the relatively small width of the isolation structure allows the focal region to have more area between the inner sidewalls of the isolation structure.As shown by line 304, since the focus area is able to remain confined between the inner sidewalls of an isolation structure, the width of the pixel area can be reduced to a smaller width w1' before being limited by the diffraction limit 308 of an overlying microlens. Therefore, the disclosed isolation structure allows the performance of the image sensor element to be maintained while the width of the pixel area shrinks to a width w1' below 0.7 micrometers.

[0030] Fig. Figure 4 illustrates a top view of some additional embodiments of an image sensor IC 400, which has a disclosed isolation structure.

[0031] The image sensor IC 400 has a substrate 102 with a pixel area 106 surrounded by an isolation structure 114. A focus area 122 is located within the pixel area 106. The focus area 122 extends to opposite inner side walls 114s of the isolation structure 114, such that the focus area 122 has an outer boundary that contacts the isolation structure 114. In some embodiments, the focus area 122 can be completely confined between the opposite inner side walls 114s of the isolation structure 114.

[0032] In some embodiments, the focus area 122 can be separated from a corner 114c of the isolation structure 114 where the inner side walls 114s meet. In such embodiments, the isolation structure 114 is located closer to the focus area 122 along a first direction 402 than along a second direction 404, which is rotated by an angle α approximately 45° with respect to the first direction 402.

[0033] Fig. Figure 5 illustrates a top view of some additional embodiments of an image sensor IC 500, which has a disclosed isolation structure.

[0034] The image sensor IC 500 has a substrate 102 with a pixel area 106 surrounded by an isolation structure 114. A focus area 122 is located within the pixel area 106. The focus area 122 extends from between the inner side walls 114s of the isolation structure 114 to beyond the inner side walls 114s of the isolation structure 114, such that the focus area 122 overlaps the isolation structure 114. In some embodiments, the focus area 122 can extend beyond the inner side walls 114s of the isolation structure 114 by a non-zero distance 502. In some embodiments, the non-zero distance 502 can be in a range between 1% and approximately 10% of a second width w2 of the isolation structure 114. Due to the non-zero distance 502, which is kept smaller than 10% of the second width w2, the performance of the image sensor IC 500 remains good.In some such embodiments, the focus area 122 can be separated from a corner 114c of the isolation structure 114 where the inner side walls 114s meet.

[0035] Fig. Figure 6 illustrates a cross-sectional view of some additional embodiments of an image sensor IC 600.

[0036] The image sensor IC 600 has a substrate 102 with a first side 102a and a second side 102b. A dielectric structure 108, surrounding a plurality of interconnects 112, is arranged along the first side 102a of the substrate 102. In some embodiments, a light-transmitting structure 606 can be arranged along the second side 102b of the substrate 102. The light-transmitting structure 606 is configured to improve the absorption of incident radiation into the substrate 102. In some embodiments, the light-transmitting structure 606 can have a multilayer structure. For example, the light-transmitting structure 606 can have three or more layers of different materials. In some embodiments, the light transfer structure 606 may contain one or more of tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), silicon dioxide (SiO2), hafnium oxide (HfO) and / or the like.

[0037] A lattice structure 206 is arranged on the light-transmitting structure 606, and a dielectric material 208 is arranged on the lattice structure 206. A color filter 116 is provided between side walls of the lattice structure 206 and / or the dielectric material 208. In some embodiments, a planarization structure 608 is arranged above the color filter 116. The planarization structure 608 has a substantially flat upper surface facing away from the substrate 102. In some embodiments, the planarization structure 608 can be a polymer such as polymethyl methacrylate (PMMA), polypropylene (PP), epoxy resin (EP), polycarbonate (PC), or the like. A microlens 118 is arranged on the substantially flat upper surface of the planarization structure 608.

[0038] One or more shallow trench insulation structures (STI structures) 602 are arranged along the first side 102a of the substrate 102. One or more insulation structures 114 are arranged along the second side 102b of the substrate 102 above the one or more STI structures 602. In some embodiments, the one or more insulation structures 114 each have a second width that decreases with increasing distance from the second side 102b of the substrate 102. In some such embodiments, the one or more insulation structures 114 each have a smaller width along a first surface facing the one or more STI structures 602 than along an opposite second surface.

[0039] In some embodiments, the one or more insulation structures 114 can extend within the one or more STI structures 602, such that the one or more insulation structures 114 extend along side walls of the one or more STI structures 602. In some embodiments, the one or more insulation structures 114 can extend to a depth 604 into the interior of the one or more STI structures 602. In some embodiments, the depth 604 can be in a range between about 10 micrometers and about 50 micrometers.

[0040] Through the one or more isolation structures 114 extending into the interior of the one or more STI structures 602, the one or more isolation structures 114 are able to provide improved isolation between adjacent pixels from a plurality of pixel regions 106a-106b. The improved isolation can compensate for any reduction in electrical isolation resulting from a relatively small width of the isolation structure 114 (e.g., a width between about 10% and about 20% of the width of an associated pixel from the plurality of pixel regions 106a-106b).

[0041] Fig. Figure 7 illustrates a cross-sectional view of some additional embodiments of an image sensor IC 700.

[0042] The image sensor IC 700 comprises one or more isolation structures 114 arranged along a second side 102b of a substrate 102 above one or more STI structures 602 arranged along a first side 102a of the substrate 102. In some embodiments, the one or more isolation structures 114 can physically contact a horizontally extending surface of the one or more STI structures 602. By physically contacting a horizontally extending surface of the one or more STI structures 602, good isolation between adjacent pixel areas 106a-106b can be achieved.Furthermore, the depth of the one or more isolation structures 114, which remain above the one or more STI structures 602, is determined by the one or more isolation structures 114 compared to the one or more isolation structures located in . Fig. Figure 6 shows a reduction in the depth of one or more isolation structures 114. This reduction enables simpler manufacturing of the one or more isolation structures 114 and better control of a critical dimension (CD) of the one or more isolation structures 114.

[0043] Fig. Figure 8 illustrates a cross-sectional view of some additional embodiments of an image sensor IC 800.

[0044] The image sensor IC 800 comprises one or more isolation structures 114 arranged along a second side 102b of a substrate 102 above one or more STI structures 602 arranged along a first side 102a of the substrate 102. In some embodiments, the one or more isolation structures 114 may be vertically separated from the one or more STI structures 602 by the substrate 102. In some embodiments, the one or more isolation structures 114 may be vertically separated from the one or more STI structures 602 by a non-zero distance 802. In some embodiments, the non-zero distance 802 may be in a range between approximately 5 micrometers and approximately 100 micrometers, between approximately 10 micrometers and approximately 50 micrometers, or have other similar values.In some embodiments, one or more doped isolation regions 804 can be arranged within the substrate 102 between the one or more STI structures 602 and the one or more isolation structures 114 to improve the electrical isolation between adjacent from a plurality of pixel regions 106a-106b.

[0045] The one or more isolation structures 114, which are separated from the one or more STI structures 602 by a non-zero distance 802, determine a depth of the one or more isolation structures 114 compared to the one or more isolation structures that are in Fig. Figures 6-7 show a reduction in depth. Reducing the depth of one or more isolation structures 114 enables simpler fabrication of the one or more isolation structures 114 and better control of a CD of the one or more isolation structures 114.

[0046] Fig. Figure 9 illustrates a cross-sectional view of some additional embodiments of an image sensor IC 900.

[0047] The image sensor IC 900 has one or more isolation structures 114 extending from a first side 102a of a substrate 102 to a second side 102b of the substrate 102. In some embodiments, the one or more isolation structures 114 each have a width that increases with increasing distance from the second side 102b of the substrate 102. In such embodiments, the one or more isolation structures 114 have a first surface close to the first side 102a of the substrate 102 that is wider than a second surface close to a second side 102b of the substrate 102.Since the second surface of the one or more isolation structures 114 is smaller than the first surface, a CD of the one or more isolation structures 114 is able to be better controlled along the second side 102b of the substrate 102, while a relatively simple manufacturing process is maintained due to a larger CD along the first side 102a of the substrate 102.

[0048] Fig. Figures 10-21 illustrate cross-sectional views 1000-2100 of some embodiments of a method for forming an image sensor IC, which includes an isolation structure designed to improve the performance of the image sensor IC. Although the in Fig. Sectional views 10-21 shown in Figures 10-21 describe a method for forming an integrated image sensor chip having an isolation structure; it is understood that the Fig. The structures shown in 10-21 are not limited to the process of formation and can instead stand separately from the process.

[0049] As shown in the cross-sectional view 1000 of Fig. As shown in Figure 10, one or more shallow trench insulation structures (STI structures) 602 are formed within a first side 102a of a substrate 102. In various embodiments, the substrate 102 can be a semiconductor body of any type (e.g., silicon, SiGe, SOI, etc.) as well as semiconductor layers, epitaxial layers, dielectric layers, or metal layers of any other type associated with it. In some embodiments, the one or more STI structures 602 can be formed by selectively etching the substrate 102 to create a trench 1002. One or more dielectric materials are then formed within the trench 1002. In various embodiments, the substrate 102 can be selectively etched with a wet etching agent (e.g., hydrofluoric acid, potassium hydroxide, or the like) and / or a dry etching agent (e.g., with an etching chemistry containing fluorine, chlorine, or the like).In various embodiments, one or more dielectric materials can contain an oxide, a nitride, a carbide, or the like.

[0050] In some additional embodiments, the one or more STI structures 602 can be formed using a thermal process to create a pad oxide over the substrate 102, followed by the formation of a nitride film over the pad oxide. The nitride film is then patterned (e.g., using a photosensitive material such as a photoresist), and the pad oxide and the substrate 102 are patterned according to the nitride film to form the trench 1002 within the substrate 102. The trench 1002 is then filled with one or more dielectric materials, followed by a planarization process (e.g., a chemical-mechanical planarization process) to expose a top surface of the nitride film, and etching to remove the nitride film.

[0051] As shown in the cross-sectional view 1100 of Fig. As shown in Figure 11, an image sensor element 104 is formed within a pixel region 106 of the substrate 102. In some embodiments, the image sensor element 104 can include a photodiode formed by implanting one or more dopants into the first face 102a of the substrate 102. For example, the image sensor element 104 can be formed by selectively performing a first implantation process (e.g., corresponding to a mask layer) to create a first region having a first doping type (e.g., n-type), and subsequently, a second implantation process is performed to create a second region adjacent to the first region having a second doping type (e.g., p-type) that differs from the first doping type. In some embodiments, a floating diffusion trough (not shown) can also be formed using either the first or second implantation processes.

[0052] As shown in the cross-sectional view 1200 of Fig. As shown in Figure 12, one or more transistor gate structures 110 are formed along a first side 102a of a substrate 102 within the pixel area 106. In various embodiments, the one or more transistor gate structures 110 can correspond to a transfer transistor, a source follower transistor, a line selector transistor, and / or a reset transistor. In some embodiments, the one or more transistor gate structures 110 can be formed by depositing a gate dielectric film and a gate electrode film on the first side 102a of the substrate 102. The gate dielectric film and the gate electrode film are subsequently patterned to form a gate dielectric layer and a gate electrode. Sidewall spacers can be formed on the outer sidewalls of the gate electrode. In some embodiments, the sidewall spacers can be formed by depositing a spacer layer (e.g.,a nitride, an oxide, etc.) onto the first side 102a of the substrate 102 and selective etching of the spacer layer to form the side wall spacers.

[0053] As shown in the cross-sectional view 1300 of Fig. As shown in Figure 13, a plurality of interconnects 112 are formed within a dielectric structure 108, which are formed along the first side 102a of the substrate 102. The dielectric structure 108 has a plurality of stacked ILD layers, while the plurality of interconnects 112 have alternating layers of conductive traces and vias. In some embodiments, one or more of the plurality of interconnects 112 can be formed using a Damascene process (e.g., a single-Damascene process or a dual-Damascene process). The Damascene process is carried out by forming an ILD layer over the first side 102a of the substrate 102, etching the ILD layer to form a via hole and / or a trench, and filling the via hole and / or trench with a conductive material.In some embodiments, the ILD layer can be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.), and the conductive material can be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the conductive material can contain tungsten, copper, aluminum, or the like.

[0054] As shown in the cross-sectional view 1400 of Fig. As shown in Figure 14, the dielectric structure 108 can be bonded to a support substrate 1402. In some embodiments, the support substrate 1402 can contain a semiconductor material such as silicon. After bonding the dielectric structure 108 to the support substrate 1402, the substrate 102 can be thinned. Thinning the substrate 102 reduces its thickness from a first thickness t1 to a second thickness t2, which is smaller than the first thickness t1. Thinning the substrate 102 facilitates the transmission of radiation to the image sensor element 104. In various embodiments, the substrate 102 can be thinned by etching and / or mechanically grinding a second side 102b of the substrate 102.

[0055] As shown in the cross-sectional view 1500 of Fig. As shown in Figure 15, one or more trenches 1502 are formed within the second first side 102b of the substrate 102. The one or more trenches 1502 extend vertically from the second side 102b of the substrate 102 into the interior of the substrate 102 along opposite sides of the pixel area 106. The pixel area 106 has a first width w1 that is less than or equal to approximately 0.7 micrometers, and the insulation structure 114 has a second width w2 that is smaller than the first width w1. The ratio between the second width w2 and the first width w1 is in the range of approximately 0.1 to approximately 0.2.

[0056] In some embodiments, the one or more trenches 1502 can be formed by selectively etching the second side 102b of the substrate 102. In some embodiments, the second side 102b of the substrate 102 can be selectively etched by exposing the second side 102b of the substrate 102 to one or more etchants 1504 according to a structured mask layer 1506. In some embodiments, the structured mask layer 1506 can comprise a photoresist, a hard mask, or the like. In some embodiments, the one or more etchants 1504 can include a dry etchant. In some embodiments, the dry etchant can have an etching chemistry containing one or more of oxygen (O2), nitrogen (N2), hydrogen (H2), argon (Ar), and / or a fluorine species (e.g., CF4, CHF3, C4F8, etc.).

[0057] As shown in the cross-sectional view 1600 of Fig. As shown in Figure 16, one or more dielectric materials are formed within the trenches 1502 to form an insulating structure 114 on opposite sides of the pixel area 106. In some embodiments, the one or more dielectric materials can be formed to line the inner surface of the substrate 102 that defines the one or more trenches 1502 and to further cover the second side 102b of the substrate 102. In some such embodiments, after the formation of the one or more dielectric materials, a planarization process (e.g., a chemical-mechanical planarization process (CMP process)) can be carried out to remove the one or more dielectric materials from the second side 102b of the substrate 102. In some embodiments, the one or more dielectric materials can be formed by a vapor deposition process (e.g.,a chemical vapor deposition (CVD) process, a plasma-assisted CVD process, or the like). In other embodiments, the one or more dielectric materials can be formed by an atomic layer deposition (ALD) process. The ALD process can improve the filling of the one or more trenches 1502, which would otherwise be difficult to fill due to a relatively large depth and small width (e.g., a width between about 10% and about 20% of the width of the pixel area 106).

[0058] As shown in the cross-sectional view 1700 of Fig. As shown in Figure 17, a light transfer structure 606 can be formed along the second side 102b of the substrate 102. The light transfer structure 606 is designed to improve the absorption of incident radiation into the substrate 102. In some embodiments, the light transfer structure 606 can have a multilayer structure. For example, the light transfer structure 606 can have three layers of different materials. In some embodiments, the light transfer structure 606 can contain one or more of tantalum pentoxide (Ta₂O₅), aluminum oxide (Al₂O₃), silicon dioxide (SiO₂), hafnium oxide (HfO), and / or the like. In some embodiments, the light transfer structure 606 can be formed by one or more deposition processes (e.g., CVD, ALD, PE-CVD, etc.).

[0059] As shown in the cross-sectional view 1800 of Fig. As shown in Figure 18, a lattice structure 206 is formed over the light-transmitting structure 606. In some embodiments, the lattice structure 206 extends continuously in a closed loop around the pixel area 106. In some embodiments, the lattice structure 206 may comprise a metal. In other embodiments, the lattice structure 206 may comprise a dielectric material. In some embodiments, the lattice structure 206 can be formed by depositing a lattice material onto the light-transmitting structure 606 and subsequently structuring the lattice material to define the lattice structure 206.

[0060] In some embodiments, a dielectric material 208 can be formed over the grid structure 206. The dielectric material 208 has sidewalls that define a first opening 1802 located above the image sensor element 104. In some embodiments, the dielectric material 208 can have a refractive index greater than approximately 1.4, 1.45, 1.5, or another similar value. The dielectric material 208 can be formed by depositing a dielectric layer onto the grid structure 206 and the light transmission structure 606, followed by structuring of the dielectric layer.

[0061] As shown in the cross-sectional view from 1900 Fig. As shown in Figure 19, a color filter 116 is formed over the light transmission structure 606 and between the side walls of the grid structure 206. In some embodiments, the color filter 116 can be formed by creating a color filter layer and structuring the color filter layer. The color filter layer is formed from a material that allows the transmission of radiation (e.g., light) having a specific wavelength range, while blocking light with wavelengths outside the specified range. In some embodiments, the color filter 116 can be formed from a monomer, a polymer, or the like. In some embodiments, the color filter can be formed from a material having a refractive index of less than approximately 1.3, less than approximately 1.25, less than approximately 1.2, or other similar values.

[0062] As shown in the cross-sectional view 2000 from Fig. As shown in Figure 20, a planarization structure 608 is formed over the color filter 116. The planarization structure 608 is formed such that it has a substantially flat upper surface facing away from the substrate. In some embodiments, the planarization structure 608 can comprise a polymer formed by a spin coating process.

[0063] As shown in the cross-sectional view 2100 of Fig. As shown in Figure 21, a microlens 118 is formed over the color filter 116. In some embodiments, the microlens 118 can be formed by depositing a microlens material over the color filter 116 (e.g., by a spin coating or deposition process). A microlens template (not shown) having a curved upper surface is textured over the microlens material. In some embodiments, the microlens template can comprise a photoresist material that is exposed using a distributed dose of light (e.g., a negative photoresist is exposed with more light on one underside of the curvature and with less light on one topside of the curvature), developed, and baked to form a rounded shape. The color filter 116 is then formed by selectively etching the microlens material according to the microlens template.

[0064] As shown in the cross-sectional view 2100 of Fig. 21 also shows the carrier substrate (1402 of Fig. 14) removed. In various embodiments, the support substrate can be removed by an etching process and / or a grinding process (e.g. a CMP process).

[0065] Fig. Figure 22 illustrates a flowchart of some embodiments of a method 2200 for forming an integrated image sensor chip (image sensor IC) which has an isolation structure designed to improve the performance of the image sensor IC.

[0066] Although Process 2200 is illustrated and described here as a series of actions or events, it should be understood that the illustrated sequence of such actions or events is not to be interpreted in a restrictive sense. For example, some actions may occur in different sequences and / or simultaneously with other actions or events besides those illustrated and / or described herein. In addition, not all of the illustrated actions may be necessary to implement one or more aspects or embodiments of the present disclosure. Furthermore, one or more of the actions illustrated herein may be carried out in one or more separate actions and / or stages.

[0067] In 2202, one or more shallow trench isolation structures (STI structures) are formed along a first side of a substrate. Fig. Figure 10 illustrates a cross-sectional view of 1000 of some embodiments according to Act 2202.

[0068] In 2204, one or more image sensor elements are formed within a substrate. Fig. Figure 11 illustrates a cross-sectional view 1100 of some embodiments according to Act 2204.

[0069] In 2206, one or more transistor gate structures are formed along the first side of the substrate. Fig. Figure 12 illustrates a cross-sectional view 1200 of some embodiments according to Act 2206.

[0070] In 2208, a plurality of interconnects are formed within a dielectric structure along the first side of the substrate. Fig. Figure 13 illustrates a cross-sectional view 1300 of some embodiments according to Act 2208.

[0071] In 2210, the dielectric structure is coupled to a support substrate. Fig. Figure 14 illustrates a cross-sectional view 1400 of some embodiments according to Act 2210.

[0072] In 2212, the thickness of the substrate is reduced. Fig. Figure 14 illustrates a cross-sectional view 1400 of some embodiments according to Act 2212.

[0073] In 2214, an isolation structure is formed along a second side of the substrate, with a width that provides a ratio between the widths of the isolation structure and the pixel area that is between about 0.1 and about 0.2. Fig. 15-16 illustrate cross-sectional views 1500-1600 of some embodiments according to Act 2214.

[0074] In 2216, a light transfer structure is formed along a second side of the substrate. Fig. Figure 17 illustrates a cross-sectional view 1700 of some embodiments according to Act 2216.

[0075] In 2218, a lattice structure is formed on the light transmission structure. Fig. Figure 17 illustrates a cross-sectional view 1700 of some embodiments according to Act 2218.

[0076] In 2220, a dielectric material is formed on the lattice structure. Fig. Figure 18 illustrates a cross-sectional view 1800 of some embodiments according to Act 2220.

[0077] In 2222, a color filter is formed between side walls of the lattice structure and / or the dielectric material. Fig. Figure 19 illustrates a cross-sectional view 1900 of some embodiments according to Act 2222.

[0078] In 2224, a planarization structure is formed on the color filter. Fig. Figure 20 illustrates a cross-sectional view of 2000 of some embodiments according to Act 2224.

[0079] In 2226, a microlens is formed on the planarization structure. Fig. Figure 21 illustrates a cross-sectional view 2100 of some embodiments according to Act 2226.

[0080] In 2228, the support substrate is removed from the dielectric structure. Fig. Figure 21 illustrates a cross-sectional view 2100 of some embodiments according to Act 2228.

[0081] Accordingly, in some embodiments, the present disclosure relates to an integrated image sensor chip comprising an isolation structure surrounding a pixel area having a first width less than or equal to approximately 0.7 micrometers. The isolation structure has a second width between approximately 10% and approximately 20% of the first width. The second width of the isolation structure is configured to improve the performance of an image sensor element within the pixel area by enabling incident radiation to be confined essentially between inner sidewalls of the isolation structure.

[0082] In some embodiments, the present disclosure relates to an integrated image sensor chip. The integrated image sensor chip comprises: a substrate having a first side and a second side opposite the first side, the substrate having one or more sidewalls forming a trench extending along opposite sides of a pixel region having a first width; an insulating structure comprising one or more dielectric materials provided within the trench, the insulating structure having a second width; an image sensor element provided within the pixel region; a focal region provided within the pixel region, the focal region being configured to receive incident radiation along the second side of the substrate; and wherein the ratio of the second width to the first width is in a range between approximately 0,1 and approximately 0.2, such that the focus area is completely confined between inner sidewalls of the isolation structure facing the image sensor element. In some embodiments, the focus area extends to an outer boundary that contacts the isolation structure on opposite sides of the focus area. In some embodiments, the focus area is closer to the isolation structure along a first direction than along a second direction rotated by approximately 45° with respect to the first direction. In some embodiments, the integrated image sensor chip further comprises a shallow trench isolation structure (STI structure) provided along the first side of the substrate, having a substrate-facing surface that extends laterally beyond opposite edges of the isolation structure. In some embodiments, the first width is less than or equal to approximately 0.7 micrometers. In some embodiments, the second width is less than or equal to approximately 140 nanometers. In some embodiments, the integrated image sensor chip further comprises a microlens having a curved surface facing away from the substrate, the curved surface being configured to focus the incident radiation into the focal area. In some embodiments, the focal area is separated from the isolation structure along a first direction and along a second direction perpendicular to the first direction, the first direction and the second direction being parallel to the second side of the substrate.

[0083] In other embodiments, the present disclosure relates to an integrated image sensor chip. The integrated image sensor chip comprises: an image sensor element arranged within a pixel region of a semiconductor substrate, wherein the pixel region has a first width of less than about 0.7 micrometers; an isolation structure arranged along a rear side of the semiconductor substrate, the isolation structure surrounding the image sensor element; a microlens arranged along the rear side of the semiconductor substrate and configured to focus incident radiation onto a focal region arranged along the rear side of the semiconductor substrate; and wherein the focal region is separated from the isolation structure by a non-zero distance.In some embodiments, the integrated image sensor chip further comprises: one or more transistor gate structures provided along a front face of the semiconductor substrate; and a shallow trench isolation structure (STI structure) provided below the isolation structure along the front face of the semiconductor substrate. In some embodiments, the STI structure has a surface facing the semiconductor substrate, the surface extending laterally beyond opposite edges of the isolation structure. In some embodiments, the isolation structure extends along one or more side walls of the STI structure. In some embodiments, the isolation structure is vertically separated from the STI structure by a second non-zero spacer extending through the semiconductor substrate.In some embodiments, the isolation structure has a second width that decreases with increasing distance from the back of the semiconductor substrate. In some embodiments, the isolation structure has a second width that increases with increasing distance from the back of the semiconductor substrate. In some embodiments, the focus area overlaps the isolation structure laterally. In some embodiments, the focus area extends over the isolation structure to a third non-zero distance, where the third non-zero distance is less than or equal to approximately 10% of the second width of the isolation structure.

[0084] In other embodiments, the present disclosure relates to a method for forming an integrated image sensor chip. The method comprises: forming an image sensor element within a pixel region of a substrate, wherein the substrate has a first side and a second side, and the pixel region has a first width; selectively etching the second side of the substrate to define one or more trenches; forming one or more dielectric materials within the one or more trenches to form an insulating structure having a second width; and wherein the ratio of the second width to the first width is in a range between about 0.1 and about 0.2. In some embodiments, the first width is less than or equal to about 0.7 micrometers.In some embodiments, the method further includes forming one or more shallow trench isolation structures (STI structures) along the first side of the substrate, wherein the one or more trenches extend into the one or more STI structures.

Claims

[1] Integrated image sensor chip comprising: a substrate (102) having a first side (102a) and a second side (102b) opposite the first side (102a), wherein the substrate (102) has one or more side walls forming a trench (1502) extending along opposite sides of a pixel area (106) having a first width (w1); an insulation structure (114) comprising one or more dielectric materials provided within the trench (1502), wherein the insulation structure (114) has a second width (w2); an image sensor element (104) that is provided within the pixel area (106); a focus area (122) provided within the pixel area (106), wherein the focus area (122) is configured to receive incident radiation (120) along the second side (102b) of the substrate (102); and wherein the first width (w1) is less than or equal to 0.7 micrometers, wherein the ratio of the second width (w2) to the first width (w1) is in a range between 0.1 and 0.2, such that the focus area (122) is completely confined between inner side walls of the insulation structure (114) facing the image sensor element (104). [2] Integrated image sensor chip according to claim 1, wherein the focus area (122) extends to an outer boundary which contacts the isolation structure (114) on opposite sides of the focus area (122). [3] Integrated image sensor chip according to claim 1 or 2, wherein the focus area (122) is closer to the isolation structure (114) along a first direction (402) than along a second direction (404) which is rotated by 45° with respect to the first direction (402). [4] Integrated image sensor chip according to one of the preceding claims, further comprising: a shallow trench insulation structure (602) provided along the first side (102a) of the substrate (102) and having a surface facing the substrate (102), the surface extending laterally beyond opposite edges of the insulation structure (114). [5] Integrated image sensor chip according to any of the preceding claims, wherein the second width (w2) is less than or equal to 140 nanometers. [6] Integrated image sensor chip according to one of the preceding claims, further comprising: a microlens (118) having a curved surface (118s) facing away from the substrate (102), wherein the curved surface (118s) is configured to focus the incident radiation (120) into the focus area (122). [7] Integrated image sensor chip according to one of the preceding claims, wherein the focus area (122) is separated from the isolation structure (114) along a first direction (212) and along a second direction (214) which is perpendicular to the first direction (212), wherein the first direction (212) and the second direction (214) are parallel to the second side (102b) of the substrate (102). [8] Integrated image sensor chip according to claim 1, wherein the substrate (102) is a semiconductor substrate, the first side (102a) is the front side of the semiconductor substrate (102) and the second side (102b) is the back side of the semiconductor substrate (102), wherein the focus area (122) is separated from the isolation structure (114) by a non-zero distance (216). [9] Integrated image sensor chip according to any of the preceding claims, further comprising: one or more transistor gate structures (110) provided along the front side (102a) of the semiconductor substrate (102); and a shallow trench insulation structure, STI structure (602), which is provided below the insulation structure (114) along the front side (102a) of the semiconductor substrate (102). [10] Integrated image sensor chip according to claim 9, wherein the STI structure (602) has a surface facing the semiconductor substrate (102), the surface extending laterally beyond opposite edges of the insulation structure (114). [11] Integrated image sensor chip according to claim 9, wherein the isolation structure (114) extends along one or more side walls of the STI structure (602). [12] Integrated image sensor chip according to claim 9, wherein the isolation structure (114) is vertically separated from the STI structure (602) by a second non-zero distance (802) extending through the semiconductor substrate (102). [13] Integrated image sensor chip according to one of claims 8 to 12, wherein the isolation structure (114) has a width that decreases with increasing distance from the back (102b) of the semiconductor substrate (102). [14] Integrated image sensor chip according to one of claims 8 to 12, wherein the isolation structure (114) has a width that increases with increasing distance from the back (102b) of the semiconductor substrate (102). [15] Method for forming an integrated image sensor chip, comprising: Forming an image sensor element (104) within a pixel area (106) of a substrate (102), wherein the substrate (102) has a first side (102a) and a second side (102b) and the pixel area (106) has a first width (w1); Selective etching of the second side (102b) of the substrate (102) to define one or more trenches (1502); and Forming one or more dielectric materials within the one or more trenches (1502) to form an insulating structure (114) having a second width (w2), where the first width (w1) is less than or equal to 0.7 micrometers, and where the ratio of the second width (w2) to the first width (w1) is in a range between 0.1 and 0.

2. [16] The method of claim 15, further comprising: Forming one or more shallow trench isolation structures, STI structures (602), along the first side (102a) of the substrate (102), wherein the one or more trenches (1502) extend into the one or more STI structures (602).

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