HETEROGENIC DIELECTRIC BOND SCHEME

Abstract

A method comprising the following steps: bringing a first package component (20) into contact with a second package component (120), wherein the first package component (20) has a first dielectric layer (42) with a first dielectric material, the first dielectric material being a silicon oxide-based dielectric material, and the second package component (120) has a second dielectric layer (142) with a second dielectric material, the second dielectric material being different from the first dielectric material and comprising silicon and an element from the group consisting of carbon, nitrogen and combinations thereof; and performing an annealing process to bond the first dielectric layer (42) to the second dielectric layer (142), and wherein the first package component (20) and the second package component (120) are bonded together by wafer-wafer bonding.

Description

Priority claim and cross-reference

[0001] The present application claims priority over the preliminary US patent application filed on April 22, 2021, with file number 63 / 178.081 and entitled “Heterogeneous Dielectric Bonding Scheme”, which is incorporated by reference into the present application. background

[0002] Melt bonding and hybrid bonding are common bonding methods for joining two package components, such as wafers and dies. These bonding processes are preferably performed at low temperatures, resulting in high bond strength and a thin bond interface. List of characters

[0003] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1 to Fig. Figure 5 shows sectional views of intermediate stages in a melt bonding process according to some embodiments. The Fig. 6 to Fig. Figure 10 shows sectional views of intermediate stages in a hybrid bonding process according to some embodiments. The Fig. 11 and Fig. Figure 12 shows a distribution of some elements in some bonded structures according to some embodiments. The Fig. 13 and Fig. Figure 18 shows some bonded structures with different combinations of package components according to some embodiments. Fig. Figure 19 shows a process flow of a bonding process according to some embodiments. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] A heterogeneous bond structure and a method for its fabrication are provided. In some embodiments of the present invention, a first package component has a first dielectric surface layer, and a second package component has a second dielectric surface layer. The first and second dielectric surface layers comprise different silicon-containing dielectric materials. For example, the first dielectric surface layer is a silicon oxide-based dielectric material (which may be free of carbon and nitrogen), and the second dielectric surface layer contains silicon and one or more other elements, such as nitrogen and / or carbon.The second dielectric surface layer can contain silicon oxide nitride (SiON), silicon nitride (SiN), silicon oxide carbonitride (SiOCN), silicon carbon nitride (SiCN), silicon oxide carbide (SiOC), silicon carbide (SiC), or the like. The first dielectric surface layer is bonded to the second dielectric surface layer to create a heterogeneous bond structure. Creating this heterogeneous bond structure improves bond strength and increases bond yield. The embodiments discussed herein are intended to provide examples of the use of the subject matter of the present invention, and a person skilled in the art should readily recognize modifications that can be made without altering the intended scope of protection of different embodiments. In all illustrations and explanatory embodiments, similar reference numerals are used to denote similar elements.While some process implementation forms can be discussed as embodiments that are carried out in a specific order, other process implementation forms can be carried out in any logical order.

[0007] The Fig. 1 to Fig. Figure 5 shows sectional views of intermediate stages in the fabrication of a package by fusion bonding according to some embodiments of the present invention. The corresponding processes are also schematically indicated in the process flow shown in Fig. 19 is shown.

[0008] Fig. Figure 1 shows a sectional view of a package component 20. In some embodiments of the present invention, the package component 20 is a device wafer with active devices and optionally passive devices, which are represented as integrated circuit devices 26, or the package component comprises such a device wafer. The package component 20 may contain a plurality of chips 22, with only one of the chips 22 being shown. In alternative embodiments of the present invention, the package component 20 is an interposer wafer that does not contain, or does contain, active devices, and it may or may not contain passive devices. In still further alternative embodiments of the present invention, the package component 20 is a package substrate strip, which is a coreless package substrate or a package substrate with a core, or comprises such a strip.In further alternative embodiments, the package component 20 includes a package, such as an integrated fan-out package (InFO package). The package component 20 can be located not only at the wafer level but also at the die level, and it can be a device die, an interposer die, a package substrate, a discrete package (sawed from a newly configured wafer), or the like. In the following discussion, a device wafer is used as an example of the package component 20, and the package component 20 can also be referred to as a wafer 20. The embodiments of the present invention can also be used for interposer wafers, package substrates, newly configured wafers, discrete packages, discrete device dies, discrete interposer dies, etc.

[0009] According to some embodiments of the present invention, the wafer 20 comprises a semiconductor substrate 24 and structural elements fabricated on a top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be made of or comprise crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. In alternative embodiments, the wafer 20 is used to fabricate interposers (which do not contain active devices), and the substrate 24 may be a semiconductor substrate or a dielectric substrate. The semiconductor substrate 24 may also be a solid semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.STI (shallow trench insulation) regions can be created in the semiconductor substrate 24 to isolate the active regions. Although not shown, vias can be fabricated (or not) to extend into the semiconductor substrate 24, with the vias being used to electrically connect the conductive structural elements on opposite sides of the substrate 24.

[0010] In some embodiments of the present invention, the wafer 20 has integrated circuit devices 26 that are fabricated on the top surface of the semiconductor substrate 24. In some embodiments, the integrated circuit devices 26 can be CMOS transistors (CMOS: complementary metal-oxide semiconductor), resistors, capacitors, diodes, and the like. Details of the integrated circuit devices 26 are not discussed here.

[0011] An interlayer dielectric (ILD) 28 is produced over the semiconductor substrate 24, filling the spaces between gate stacks of transistors (not shown) in the integrated circuit devices 26. In some embodiments, the ILD 28 is made of phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), silicon oxide, silicon oxide nitride, silicon nitride, a low-k dielectric material, or the like. The ILD 28 can be produced by spin coating, flowable chemical vapor deposition (FCVD), or the like. In some embodiments of the present invention, the ILD 28 is produced by a deposition process such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like.

[0012] In the ILD 28, contact pins 30 are manufactured, which are used for electrically connecting the integrated circuit devices 26 to metal traces and vias located above them. In some embodiments of the present invention, the contact pins 30 are made of or comprise a conductive material such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, or tantalum nitride, alloys thereof, and / or multilayers thereof. The contact pins 30 can be manufactured as follows: creating contact openings in the ILD 28; filling the contact openings with one or more conductive materials; and performing a planarization process, such as a CMP process (CMP: chemical-mechanical polishing) or a mechanical grinding process, to bring the top surfaces of the contact pins 30 to the same level as a top surface of the ILD 28.

[0013] An interconnect structure 32 is arranged above the ILD 28 and the contact pins 30. The interconnect structure 32 can comprise metal conductors 34 and vias 36, which are made in dielectric layers 38, also referred to as intermetal dielectrics (IMDs). Metal conductors on the same layer are hereinafter collectively referred to as a metal layer. In some embodiments of the present invention, the interconnect structure 32 comprises a plurality of metal layers, each containing metal conductors 34 connected to one another by vias 36. The metal conductors 34 and the vias 36 can be made of copper or copper alloys, but also of other metals. In some embodiments of the present invention, the dielectric layers 38 are made of low-k dielectric materials.The dielectric constants (k-values) of the dielectric low-k materials can, for example, be lower than approximately 3.0. The dielectric layers 38 can comprise a carbon-containing dielectric low-k material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like.

[0014] Single-damascene and / or dual-damascene processes can be used to fabricate the metal conductors 34 and the vias 36 in the dielectric layers 38. In a single-damascene process for fabricating a metal conductor or a via, a trench or via hole is first created in one of the dielectric layers 38, and then the trench or via hole is filled with a conductive material. A planarization process, such as a CMP process, is then performed to remove excess portions of the conductive material that are higher than the top of the dielectric layer, leaving a metal conductor or via in the corresponding trench or via hole.In a dual-damascene process, a trench and a via hole are created in a dielectric layer, with the via hole positioned below and connected to the trench. Conductive materials are then filled into the trench and via hole to create a metal conductor and a via, respectively. The conductive materials can include a diffusion barrier and a copper-containing metallic material above the diffusion barrier. The diffusion barrier can be titanium, titanium nitride, tantalum, tantalum nitride, or similar materials.

[0015] The interconnect structure 32 can also include a passivation layer, which can be made of a non-low-k dielectric material over the low-k dielectric layer. The passivation layer can be made of or comprise undoped silicate glass, silicon nitride, silicon oxide, or the like. Additionally, it can include metal pads (such as aluminum-copper pads), a post-passivation interconnect (PPI), or the like, embodied by the conductive structural elements.

[0016] Let's stay with Fig. 1. A dielectric layer 42 is deposited over the interconnect structure 32. The corresponding step is specified as step 202 in the process sequence 200, which is described in Fig. Figure 19 shows that one top surface of the dielectric layer 42 is planar. The dielectric layer 42 can be a dielectric protective layer that does not contain any conductive structural elements (such as conductive lines and conductive pads). In some embodiments, the dielectric layer 42 is a homogeneous layer that has a uniform composition from its top surface to its bottom surface. When two parts (such as two layers) are referred to as having the same composition, this means throughout the description that the two parts contain the same types of elements and that the percentages of the corresponding elements in the two parts are the same.If, on the other hand, two parts are described as having different compositions, this means either that one of the two parts contains at least one element that is not contained in the other part, or that two parts contain the same elements, but the percentage proportions of the elements in the two parts are different.

[0017] In some embodiments, the dielectric layer 42 can be made of or comprise a silicon oxide-based dielectric material (which may contain no or substantially no carbon and nitrogen, for example, with a total percentage of carbon and nitrogen atoms of less than about 5%). The silicon oxide-based dielectric material can comprise silicon oxide (SiO2), fluorosilicate glass (FSG), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), or the like. Silicon oxide can be produced, for example, by depositing a silicon layer and subsequently carrying out a thermal oxidation process. Alternatively, silicon oxide can be deposited, for example, using tetraethyl orthosilicate (TEOS) as a precursor.In alternative embodiments, the dielectric layer 42 can be made from a silicon-based material containing carbon and / or nitrogen. The corresponding dielectric layer 42 is also referred to as a carbon- or nitrogen-containing dielectric material. The composition of the dielectric layer 42 can be represented by the formula SiOxNyCz, where x is approximately 0 to approximately 2, y is approximately 0 to approximately 1.4, and z is approximately 0 to approximately 1, and x, y, and z are not all zero. The dielectric layer 42 can, for example, be made from or comprise SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like. Furthermore, the dielectric layer 42 can be undoped or can be doped with elements of Group III, such as B, Ga, In, or the like, or elements of Group IV, such as P, As, Sb, or the like.

[0018] In alternative embodiments, the dielectric layer 42 is a composite layer with two or more sublayers. In the illustrated example, the dielectric layer 42 has a dielectric (sub)layer 42A and a dielectric (sub)layer 42B above the dielectric (sub)layer 42A. These embodiments can be used when the dielectric layer 42A and a dielectric layer 142 ( Fig. 3) in a package component 120 made of the same or substantially similar dielectric material, and where dielectric layer 42A is directly bonded to dielectric layer 142, forming a homogeneous bond structure. In these embodiments, dielectric layer 42B is manufactured to be different from the corresponding dielectric layer 142 in order to produce a heterogeneous structure. A dashed line is drawn between dielectric layers 42A and 42B to indicate that dielectric layer 42 can be a homogeneous layer or can have sublayers.

[0019] The dielectric layers 42A and 42B have different materials, meaning that dielectric layer 42A and / or dielectric layer 42B contain an element (O, C, and N) that is not present in the other dielectric layer 42A and 42B. For example, one of the dielectric layers 42A and 42B can be made of a material selected from the aforementioned silicon oxide-based materials (such as SiO2, FSG, USG, BSG, PSG, BPSG, or the like), and the other of the dielectric layers 42A and 42B can be made of a material selected from the aforementioned carbon- or nitrogen-containing dielectric materials (which may contain carbon and / or nitrogen), such as SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like. The carbon- or nitrogen-containing material can also be described using the formula SiO₂. x N y Cz The diagram shows that x is approximately 0 to approximately 2, y is approximately 0 to approximately 1.4, and z is approximately 0 to approximately 1. In alternative embodiments, the dielectric layers 42A and 42B can contain the same elements but with different percentage atomic fractions. For example, the dielectric layers 42A and 42B can both contain SiON, wherein a first layer of the dielectric layers 42A and 42B has a first percentage oxygen atom fraction that is higher than a second percentage oxygen atom fraction in a second layer of the dielectric layers 42A and 42B, and / or the first layer has a first percentage nitrogen atom fraction that is lower than a second nitrogen atom fraction in the second layer.

[0020] As will be explained later, due to the high bond strength, in some embodiments of the present invention no surface treatment, such as using a plasma of nitrogen (N2) and / or oxygen (O2), needs to be carried out on the dielectric layer 42. In alternative embodiments, the package component 20 and the package component 120 ( Fig. 3) already manufactured, and the dielectric layers 42 and 142 are made from the same dielectric material. Therefore, as in Fig. As shown in Figure 2, a surface treatment process 44 can also be carried out to modify the composition of one of the dielectric layers 42 and 142. Fig. Figure 2 shows an exemplary modification process. The corresponding step is indicated as step 204 in process flow 200, which is shown in Fig. Figure 19 shows the surface treatment process 44. Dashed lines indicate whether or not it can be performed. The surface treatment process 44 can be used to modify the percentage atomic content of nitrogen and / or oxygen in the dielectric layer 42, such that the composition of the dielectric layer 42 differs more significantly from the composition of the dielectric layer 142 ( Fig. 3) can have, in order to produce an even more heterogeneous structure. For example, if dielectric layer 42 has a higher (or the same) percentage of nitrogen atoms (and possibly a lower percentage of oxygen atoms) than dielectric layer 142 ( Fig. 3) has, plasma treatment and / or heat treatment can be performed on the dielectric layer 42 using N2 (but not O2) to supply nitrogen and increase the difference between the percentage nitrogen atomic fractions in the dielectric layers 42 and 142. In alternative embodiments, where the dielectric layer 42 has a higher (or equal) percentage oxygen atomic fraction than the dielectric layer 142 ( Fig. 3) The treatment of the dielectric layer 42 can be carried out using O2 (but not N2) to supply oxygen and increase the difference between the percentage oxygen atomic fractions in the dielectric layers 42 and 142. In some embodiments, the treatment process 44 increases the percentage oxygen or nitrogen atomic fraction in the dielectric layer 42, for example, by more than about 10%.

[0021] In Fig. 3. Package component 120 is manufactured so that it is aligned with package component 20. The corresponding step is specified as step 206 in process flow 200, which is described in Fig. Figure 19 shows that in some embodiments, the package component 120 is a fixture wafer, an interposer wafer, a package substrate strip, a package, or the like. The package component 120 can be the same type of package component as the package component 20, or it can be a different type of package component than the package component 20. For example, if the package component 20 is a fixture wafer, the package component 120 can be an interposer wafer or a package. In alternative embodiments, instead of a wafer-level package component, the package component 120 can be a die-level package component, such as a fixture die, an interposer, a package substrate, a discrete package (sawed from a newly configured wafer), or the like.In the following discussion, a fixture wafer is used as an exemplary package component 120, and the package component 120 can also be referred to as a fixture wafer 120. The embodiments of the present invention can also be used for interposer wafers, package substrates, packages, etc.

[0022] The materials for the structural elements in package component 120 can be found by reference to the similar structural elements in package component 20, where the similar structural elements in package component 120 are designated by inserting the number "1" before the reference numbers of the corresponding structural elements in package component 20. For example, the substrate in package component 20 is designated 24, and accordingly, the substrate in package component 120 is designated 124. Package component 120 may include integrated circuit devices 126, an ILD 128, contact pins 130, an interconnect structure 132, dielectric layers 138, metal conductors 134, and vias 136. The details of these structural elements may be similar to those of the corresponding structural elements in package component 20 and are not repeated here.

[0023] The package component 120 may also have a dielectric layer 142 on its surface. The dielectric layer 142 may be a single layer made of a homogeneous dielectric material, or it may be a composite layer comprising multiple dielectric layers (such as 142A and 142B) made of different dielectric materials with different compositions. The material for the dielectric layer 142 may be chosen from the same materials that are suitable for making the dielectric layer 42 (and the dielectric layers 42A and 42B). Furthermore, the materials of the dielectric layers 142A and 142B are different from each other, and details of their fabrication, structure, and properties are given in the discussion of the corresponding dielectric layers 42A and 42B and are not repeated here.

[0024] The material for dielectric layer 142 (or 142B if dielectric layer 142 is a composite layer) is different from the material of dielectric layer 42 (or 42B if dielectric layer 42 is a composite layer). If the original dielectric materials of dielectric layers 42 and 142 are the same, a dielectric material different from those of dielectric layers 42 and 142 can be deposited on the top surface of either dielectric layer 42 or 142, resulting in different materials for bonding.

[0025] In some embodiments, no nitrogen treatment is performed on the dielectric layer 142, and no oxygen treatment is performed on the dielectric layer 42. Alternatively, a plasma or heat treatment (which corresponds to treatment process 44 of Fig. 2 is similar) using N2 or O2 to modify the material of the dielectric layer 142 (by modifying its composition) so that the bonded materials of the dielectric layers 42 and 142 are more distinct from each other. In some embodiments, one of the dielectric layers 42 and 142, but not both, is treated to modify its composition. In alternative embodiments, a first of the dielectric layers 42 and 142 is treated with N2, and a second of the dielectric layers 42 and 142 is treated with O2, thus increasing the difference between their compositions.

[0026] At the time of bonding, the dielectric layers 42 and 142 have different materials, meaning that at least one of the dielectric layers 42 and 142 (or both) contains an element (O, C, or N) that is not present in the other dielectric layer 42 and 142. In some embodiments, the dielectric layer 42 has a first percentage oxygen atom content, and the dielectric layer 142 has a second percentage oxygen atom content, the difference between the first and second percentage oxygen atom content being greater than about 10% or about 20%.For example, one of the dielectric layers 42 and 142 can be made from a material selected from the aforementioned suitable silicon oxide-based materials (such as SiO2, FSG, USG, BSG, PSG, BPSG, or the like), and the other of the dielectric layers 42 and 142 can be made from a material selected from the suitable carbon- or nitrogen-containing dielectric materials, such as SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like. The material for dielectric layer 142 can also be described by the formula SiO. x N y C zThe diagram shows the values ​​of the dielectrics 42 and 142, where x is approximately 0 to approximately 2, y is approximately 0 to approximately 1.4, and z is approximately 0 to approximately 1. In alternative embodiments, the dielectric layers 42 and 142 can contain the same elements but with different percentage atomic fractions. For example, the dielectric layers 42 and 142 can both contain SiON₄, wherein a first layer of the dielectric layers 42 and 142 has a first percentage oxygen atomic fraction that is higher than a second percentage oxygen atomic fraction from a second layer in the dielectric layers 42 and 142, and / or the first layer has a first percentage nitrogen atomic fraction that is lower than a second nitrogen atomic fraction in the second layer.

[0027] Fig. Figure 4 shows a pre-bonding process and a tempering process after the pre-bonding process. The corresponding steps are specified as steps 208 and 210 in process flow 200, which is described in Fig. Figure 19 shows that in some embodiments, during pre-bonding, package component 120 is brought into contact with package component 20, and a compressive force is applied to press the package components 20 and 120 against each other. The compressive force may be less than about 5 Newtons per die in some exemplary embodiments, but a greater or lesser force may also be used. Pre-bonding can be performed at room temperature (about 20 °C to about 25 °C), but a higher temperature may also be used.

[0028] Pre-bonding can begin by aligning the centers of package components 20 and 120. The contact propagates from the centers to the edges of package components 20 and 120, creating a bond wave from the centers to the edges. As the bond wave propagates from the centers to the edges, the air between package components 20 and 120 is displaced, preventing air bubbles from becoming trapped between them. Trapped air bubbles would prevent the corresponding portions of package components 20 and 120 from bonding together, resulting in a yield loss.The time interval during which the bond wave propagates from the centers to the edges (until complete contact between package component 120 and package component 20 is achieved) is referred to below as a contact time interval. The contact time interval should be within a specific range that is neither too long nor too short. If the contact time interval is too long, the production throughput decreases. If the contact time interval is too short, air bubbles may be trapped. The contact time interval is also related to the size of the wafers. In some embodiments, the contact time interval for bonding two 300 mm wafers may be approximately 0.1 s to approximately 2 s.

[0029] The contact time interval can be related to the materials of the dielectric layers 42 and 142. The materials of the dielectric layers 42 and 142 are adjusted accordingly to set the contact time interval. For example, if the dielectric layers 42 and 142 are both made of silicon oxide, the contact time interval can be short. If the dielectric layers 42 and 142 are both made of silicon nitride, the contact time interval can be long. By adjusting the compositions of the dielectric layers 42 and 142 between the silicon oxide and silicon nitride compositions, the contact time interval can also be adjusted and changed to a desired value. As explained in the following paragraphs, a heterogeneous bond between the dielectric layers 42 and 142 can increase the bond strength more than a homogeneous bond.Accordingly, in order to achieve higher bond strength and improve bond yield, the materials of the dielectric layers 42 and 142 must be different from each other and adapted to have the desired compositions.

[0030] Since the dielectric layers 42 and 142 may be exposed to air prior to prebonding, the surface layer of each of the dielectric layers 42 and 142 may be oxidized and contain intrinsic oxide, which may have a thickness of less than approximately 20 Å and less than approximately 10 Å. The intrinsic oxide layers have a higher percentage of oxygen atoms than the underlying non-oxidized parts.

[0031] After pre-bonding, an annealing process is carried out in which, for example, Si-O-Si bonds form between bonded dielectric layers 42 and 142, so that the dielectric layers 42 and 142 are bonded together with high bond strength. The corresponding step is specified as step 210 in process sequence 200, which is described in Fig. 19 is shown. This creates a composite wafer 60, which is in Fig. Figure 5 shows that in some embodiments, the tempering process is carried out at a temperature of less than 250 °C or less than approximately 200 °C. For example, tempering can be performed at a temperature of approximately 150 °C to approximately 200 °C. This tempering temperature is lower than the tempering temperature of 250 °C or more required to produce homogeneous bond structures, as is the case with conventional bonding processes. The tempering time in some embodiments can be approximately 5 minutes to approximately 30 minutes.

[0032] Fig. Figure 5 also shows an exemplary embodiment in which a contact pin 56 is manufactured such that it penetrates the package component 120 and electrically connects a metal pad 134A in the package component 120 to a metal pad 34A in the package component 20. The corresponding step is specified as step 212 in the process sequence 200, which is described in Fig. Figure 19 shows the contact pin 56 resting on the metal pad 34A of the package component 20. The contact pin 56 also penetrates the dielectric layers 42 and 142 and can be in contact with them. A dielectric layer 58 can be fabricated to cover the contact pin 56 and the substrate 124. A singulation process can then be performed in which the composite wafer 60 is sawn to produce packages 60'. Each package 60' can contain a package component 22 (such as a fixture die) bonded to a package component 122 (such as a fixture die).

[0033] The Fig. 6 to Fig. Figure 10 shows some embodiments in which a hybrid bonding scheme is used to bond the package component 20 to the package component 120. These embodiments are similar to the embodiments in the Fig. 1 to Fig. 5 similar, except that a hybrid bond is used instead of a melt bond. Unless otherwise specified, the materials and manufacturing processes for the components in these embodiments are substantially the same as those for the similar components, and they are designated by similar reference numerals as in the preceding embodiments described in the Fig. 1 to Fig. 5 are shown. The details of the manufacturing processes and materials for the items shown in the Fig. 6 to Fig. The 10 components shown are therefore discussed in the preceding embodiments.

[0034] In Fig. In embodiment 6, a package component 20 is fabricated, wherein a dielectric layer 42 is produced on the surface of the package component 20. Metal pads 50 are produced on the surface of the dielectric layer 42. Vias 48 can be produced beneath the metal pads 50, which can electrically connect the metal pads 50 to underlying metal conductors 34. In some embodiments, the metal pads 50 and the vias 48 are produced using a dual-damascene process, which may include: etching the dielectric layer 42 to create via openings and overlying trenches; filling the via openings and the trenches with a diffusion barrier layer and a metallic material; and performing a planarization process to form the metal pads 50 and the vias 48.The top surfaces of the metal pads 50 are coplanar with the top surface of the dielectric layer 42. The diffusion barrier layer can be made of Ti, TiN, Ta, TaN, or the like. The metallic material can be made of or comprise copper, a copper alloy, nickel, tungsten, or the like.

[0035] In some embodiments, the dielectric layer 42 is a single layer made of a homogeneous dielectric material. In alternative embodiments, the dielectric layer 42 is a composite layer of two or more layers made of different materials. The materials for the single- or multi-layer dielectric layer 42 have been discussed in the preceding embodiments. Furthermore, in some embodiments, an etch stop layer 42C can be made of a material different from that of the dielectric layer 42B in order to separate the dielectric layer 42A from the dielectric layer 42B.

[0036] In some embodiments, a surface material of the dielectric layer 42 is distinguished from a surface material of the dielectric layer 142 ( Fig. 9) different. This allows for a heterogeneous bonding process. The ones in the Fig. 7 and Fig. The 8 processes shown are omitted, and only the one in Fig. The process shown in Figure 9 is carried out. In alternative embodiments, the surface material of the dielectric layer 42 is the same as the surface material of the dielectric layer 142 ( Fig. 9), or the surface material of dielectric layer 42 is different from that of dielectric layer 142 ( Fig. 9) different. Although the difference between their compositions is not significant enough to guarantee a low annealing temperature, high bond strength and high yield are still achieved. Accordingly, the surface material of the dielectric layer 42 can be replaced by a different dielectric material that differs from the material of the dielectric layer 142 in order to achieve a more heterogeneous bond. An exemplary embodiment is shown in the Fig. 7 and Fig. 8 shown.

[0037] In Fig. 7. An upper part of the dielectric layer 42 is removed by etching. For example, the one in Fig. The layer 42B shown in Figure 6 is removed. In some embodiments where the etch stop layer 42C is produced, the etching can be terminated at the etch stop layer 42C. In alternative embodiments where no etch stop layer is produced, the etching is performed using a time mode, and the top of the remaining dielectric layer 42 can be located at a position that is level with, or higher than, the tops of the vias 48.

[0038] Fig. Figure 8 shows the fabrication of a dielectric layer 42B'. In some embodiments, the fabrication process comprises: depositing a dielectric layer to a level higher than the top surfaces of the bond pads 50; and performing a planarization process, such as a CMP process or a mechanical grinding process, until a top surface of the resulting dielectric layer 42B' is coplanar with the top surfaces of the bond pads 50. The material of the dielectric layer 42B' is distinct from the surface material of the dielectric layer 142 ( Fig. 9) different and is also different from the material of the removed dielectric layer 42B ( Fig. 6) different. In some embodiments where the etch stop layer 42C is produced, the dielectric layer 42B' is located above and in contact with the etch stop layer 42C. In alternative embodiments where no etch stop layer is produced, the dielectric layer 42B' is located above and in contact with the remaining dielectric layer 42 (see 42A), and an interface between the dielectric layer 42B' and the dielectric layer 42A may be located at a position that is at the same level as, or higher than, the top ends of the vias 48.

[0039] Fig. Figure 9 shows the alignment of package component 120 to package component 20, with bond pads 150 aligned to the corresponding bond pads 50. A pre-bonding process is then carried out, for example, by bringing a central part of package component 120 into contact with a central part of package component 20, and continuing this contacting until the entire package component 120 is in contact with the entire package component 20. The surface materials suitable for dielectric layer 42 and dielectric layer 142 can be selected according to the criteria specified in the Fig. 1 to Fig. The embodiments shown in Figure 5 have been discussed and are not repeated here. The desired difference between the surface materials for the dielectric layers 42 and 142 allows for an optimal contact time interval, preventing air bubbles from being trapped between the dielectric layers 42 and 142 while maintaining a high throughput of the pre-bonding process.

[0040] After pre-bonding, a tempering process is carried out to produce a composite wafer 60, which is then used in Fig. Figure 10 shows this. For example, Si-O-Si bonds form between bonded dielectric layers 42 and 142, resulting in a high bond strength between the dielectric layers 42 and 142. During the annealing process, the metals (such as copper) of the bond pads 50 and 150 diffuse into each other, creating a metal-to-metal direct bond to connect the bond pads 50 to the corresponding bond pads 150. In some embodiments, the annealing process is carried out at a temperature of less than 250 °C or less than approximately 200 °C. Annealing can be performed at a temperature of approximately 125 °C to approximately 200 °C. The annealing time can range from approximately 30 minutes to approximately 180 minutes in some embodiments. Here, too, heterogeneous bonding improves the bond strength. Then a singulation process can be carried out in which the composite wafer 60 is sawn to produce packages 60'.The packages 60' can each contain a package component 22 (such as a device die) that is bonded to a package component 122 (such as a device die).

[0041] In some embodiments, experiments are carried out to find the optimal materials and compositions for the dielectric layers 42 and 142, with which high bond strength, a suitable contact time interval, and a low annealing temperature can be achieved. For example, if the dielectric layer 42 has the composition SiO x N y C z has a corresponding SiO composition x' N y' C z'Optimal values ​​for dielectric layer 142 can be found to achieve an optimal contact time interval and high bond strength using a low annealing temperature. Since the values ​​x, y, and z have numerous combinations, the optimal values ​​x', y', and z' also have numerous corresponding combinations that correspond to the values ​​x, y, and z. The dielectric layers 42 and 142 are thus bonded to the optimal materials SiO₂. x N y C z and SiOx'Ny'Cz' manufactured.

[0042] Fig. Figure 11 shows the results of an EDX line scan (EDX: energy-dispersive X-ray analysis) of a sample wafer in which a SiON layer is bonded to a silicon oxide layer. The x-axis represents the percentage atomic fraction, and the y-axis represents the position in the bonded structure. The percentage atomic fractions of Si, O, and N are indicated. The SiON layer is positioned on top of the silicon oxide layer, and an interface layer is formed between them. The positions of the SiON layer, the silicon oxide layer, and the interface layer can be determined by measuring the change in the percentage atomic fractions of Si, O, and N.The results of the EDX line scan have shown that the thickness of the interface layer is advantageously smaller than about 65 Å, which is smaller than the preferred thickness of 80 Å and also significantly smaller than the thickness range of about 100 Å to about 200 Å for the interface layer produced using the conventional homogeneous bonding scheme.

[0043] Fig. Figure 12 shows the results of an EDX line scan for a sample wafer in which a SiN layer is bonded to a silicon oxide layer. The x-axis represents the percentage atomic fraction, and the y-axis represents the position in the bonded structure. The percentage atomic fractions of Si, O, and N are indicated. The SiN layer is placed on top of the silicon oxide layer, and an interface layer is fabricated between them. The positions of the SiN layer, the silicon oxide layer, and the interface layer can be determined by measuring the change in the percentage atomic fractions of Si, O, and N. The EDX line scan results showed that the thickness of the interface layer is less than approximately 350 Å. This result, in combination with the results of Fig. 11, that the thickness of the interface layer is significantly influenced by the materials of the dielectric layers 42 and 142 and can be reduced by selecting suitable material combinations for the dielectric layers 42 and 142.

[0044] The embodiments of the present invention can be used for wafer-wafer bonding, die-wafer bonding, die-die bonding, melt bonding, and hybrid bonding. For example, it shows Fig. 13 schematically a wafer-wafer fusion bond scheme. Fig. Figure 14 schematically shows a wafer-wafer hybrid bonding scheme. Fig. Figure 15 schematically shows a die-wafer melt bonding scheme. Fig. Figure 16 schematically shows a die-wafer hybrid bond scheme. Fig. Figure 17 schematically shows a die-die melt bond scheme. Fig. Figure 18 schematically shows a die-die hybrid bond scheme.

[0045] In the embodiments described above, some processes and elements according to some embodiments of the present invention for manufacturing a three-dimensional package (3D package) have been discussed. Other processes and elements can also be used. For example, test structures can be used to assist in the verification testing of a 3D encapsulation or 3DIC devices. The test structures can include, for example, test pads fabricated in a redistribution layer or on a substrate, enabling the testing of the 3D encapsulation or 3DIC devices, the use of probes and / or test cards, and the like. The verification test can be performed on intermediate structures as well as on the final structure.Furthermore, the structures and procedures disclosed here can be used in conjunction with testing methodologies that include intermediate verification of proven good dies to increase yield and reduce costs.

[0046] The embodiments of the present invention have several advantages. By selecting suitable combinations of materials and compositions of the bonded dielectric layers, heterogeneous bonding can be achieved to obtain higher bond strength, higher yield, and lower required annealing temperatures than with conventional homogeneous bonding schemes. For example, in some embodiments of the present invention, a bond strength of at least 2 J / m² can be achieved despite a low annealing temperature of only 200 °C (without any treatment). Even at an annealing temperature of only 170 °C, a bond strength of at least 1.5 J / m² can be achieved. 2The thickness of the interface layer can range from approximately 40 Å to approximately 400 Å. If suitable combinations of compositions are chosen, the thickness of the interface layer can be less than 100 Å or less than approximately 80 Å, or can range from approximately 40 Å to approximately 60 Å. In contrast, when using a conventional homogeneous bonding scheme, the bond strength can be at least 2 J / m. 2 This would amount to (in the case of a SiO2-SiO2 bond), but this comes at the expense of a high tempering temperature of 250 °C and the necessary treatments with N2 or O2. With the conventional homogeneous bonding scheme, the bond strength is less than 1.5 J / m. 2 , even when a treatment is performed. The thickness of the interface layer is generally about 100 Å to about 200 Å when the homogeneous bonding scheme is used.

[0047] According to some embodiments of the present invention, a method comprises the following steps: bringing a first package component into contact with a second package component, wherein the first package component has a first dielectric layer with a first dielectric material, wherein the first dielectric material is a silicon oxide-based dielectric material, and the second package component has a second dielectric layer with a second dielectric material, wherein the second dielectric material is different from the first dielectric material and includes silicon and an element from the group consisting of carbon, nitrogen and combinations thereof; and performing a tempering process to bond the first dielectric layer to the second dielectric layer.In one embodiment, no treatment process using nitrogen (N2) or oxygen (O2) is performed before the first package component is brought into contact with the second package component. In another embodiment, the first dielectric layer has a first percentage oxygen atom fraction, and the second dielectric layer has a second percentage oxygen atom fraction, wherein the first difference between the first and second percentage oxygen atom fractions is greater than approximately 10%.In one embodiment, the first dielectric layer has a first percentage oxygen atom fraction, and the second dielectric layer has a second percentage oxygen atom fraction, wherein the first percentage oxygen atom fraction is greater than the second percentage oxygen atom fraction by the first difference. The method further comprises performing a treatment process on the first dielectric layer such that the first dielectric layer and the second dielectric layer have a second difference in percentage oxygen atom fractions, wherein the second difference is greater than the first difference. In another embodiment, the second dielectric layer is not treated.In one embodiment, the first dielectric layer comprises a material from the group consisting of silicon dioxide (SiO2), fluorosilicate glass (FSG), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), and borophosphosilicate glass (BPSG). In one embodiment, the first package component is bonded to the second package component by fusion bonding. In another embodiment, the first package component is bonded to the second package component by hybrid bonding, wherein the first dielectric layer is bonded to the second dielectric layer by fusion bonding, and a first metal pad in the first dielectric layer is bonded to a second metal pad in the second dielectric layer by metal-to-metal direct bonding.In one embodiment, prior to contacting the first package component with the second package component, the second package component has a third dielectric material that is the same as the first dielectric material, the method further comprising replacing the third dielectric material with the second dielectric material. In one embodiment, the first package component and the second package component are bonded together by wafer-wafer bonding. In another embodiment, the first package component and the second package component are bonded together by die-wafer bonding.

[0048] According to some embodiments of the present invention, a package comprises: a first package component with a first dielectric layer containing a first dielectric material, wherein the first dielectric material is a silicon oxide-based dielectric material; and a second package component with a second dielectric layer containing a second dielectric material different from the first dielectric material and comprising silicon and an element from the group consisting of carbon, nitrogen, and combinations thereof, wherein the first dielectric layer is bonded to the second dielectric layer. In one embodiment, the first dielectric layer and the second dielectric layer form a bond interface layer, wherein the bond interface layer has a thickness of less than 100 Å.In one embodiment, the bond interface layer has a thickness of less than approximately 60 Ω. In another embodiment, the second package component further comprises: a third dielectric layer above and in contact with the second dielectric layer, wherein the third dielectric layer contains a third dielectric material different from the second dielectric material; and a bond pad in the second and third dielectric layers. In another embodiment, the first dielectric layer has a first percentage oxygen atom content, and the second dielectric layer has a second percentage oxygen atom content, wherein the first difference between the first and second percentage oxygen atom content is greater than approximately 10%.

[0049] According to some embodiments of the present invention, a package comprises: a first die with a first semiconductor substrate, a first integrated circuit on a surface of the first semiconductor substrate, and a first dielectric layer above the first integrated circuit, wherein the first dielectric layer comprises a first dielectric material; and a second die bonded to the first die, wherein the second die comprises a second semiconductor substrate, a second integrated circuit on a surface of the second semiconductor substrate, and a second dielectric layer beneath the second integrated circuit, wherein the first dielectric layer is physically bonded to the second dielectric layer, and the second dielectric layer comprises a second dielectric material different from the first dielectric material.In one embodiment, the first and second dielectric materials each comprise silicon and a material from the group consisting of oxygen, carbon, nitrogen, and combinations thereof. In another embodiment, the first and second dielectric layers form an interface layer, the interface layer having a thickness of less than approximately 80 Ω. In another embodiment, the package further comprises a first bond pad in the first die and a second bond pad in the second die, the first bond pad being bonded to the second bond pad by metal-to-metal direct bonding.

[0050] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. It should be clear to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent designs do not deviate from the fundamental concept and scope of protection of the present invention and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present invention.

Claims

[1] Procedure with the following steps: Bringing a first package component into contact with a second package component, wherein the first package component comprises a first dielectric layer comprising a first dielectric material, wherein the first dielectric material is a silicon oxide-based dielectric material, and the second package component comprises a second dielectric layer comprising a second dielectric material, wherein the second dielectric material is different from the first dielectric material and includes silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof; and Performing an annealing process to bond the first dielectric layer to the second dielectric layer. [2] The method according to claim 1, wherein no treatment process using nitrogen (N2) and no treatment process using oxygen (O2) are performed before bringing the first package component into contact with the second package component. [3] The method of claim 1 or 2, wherein the first dielectric layer has a first oxygen atomic percentage and the second dielectric layer has a second oxygen atomic percentage, wherein a first difference between the first and second oxygen atomic percentages is greater than about 10%. [4] Method according to one of the preceding claims, wherein the first dielectric layer has a first oxygen atomic percentage and the second dielectric layer has a second oxygen atomic percentage, wherein the first oxygen atomic percentage is greater than the second oxygen atomic percentage by the first difference, and the method further comprises performing a treatment process on the first dielectric layer such that the first dielectric layer and the second dielectric layer have a second difference between oxygen atomic percentages, the second difference being greater than the first difference. [5] A method according to any one of the preceding claims, wherein the second dielectric layer is not treated. [6] A method according to any one of the preceding claims, wherein the first dielectric layer contains a material selected from the group consisting of silicon oxide (SiO2), fluorosilicate glass (FSG), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG) and borophosphosilicate glass (BPSG). [7] A method according to any one of the preceding claims, wherein the first package component is bonded to the second package component by melt bonding. [8] A method according to any one of claims 1 to 6, wherein the first package component is bonded to the second package component by hybrid bonding, wherein the first dielectric layer is bonded to the second dielectric layer by melt bonding, and a first metal pad in the first dielectric layer is bonded to a second metal pad in the second dielectric layer by metal-to-metal direct bonding. [9] Method according to claim 8, wherein before bringing the first package component into contact with the second package component, the second package component comprises a third dielectric material which is the same as the first dielectric material, and the method further comprises replacing the third dielectric material with the second dielectric material. [10] The method according to any one of claims 1 to 6, wherein the first package component and the second package component are bonded together by wafer-to-wafer bonding. [11] The method according to any one of claims 1 to 6, wherein the first package component and the second package component are bonded together by die-wafer bonding. [12] Package with: a first package component having a first dielectric layer containing a first dielectric material, wherein the first dielectric material is a silicon oxide-based dielectric material; and a second package component having a second dielectric layer including a second dielectric material different from the first dielectric material and including silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof, wherein the first dielectric layer is bonded to the second dielectric layer. [13] The package of claim 12, wherein the first dielectric layer and the second dielectric layer form a bonding interface layer, the bonding interface layer having a thickness less than 100 Å. [14] The package of claim 13, wherein the bonding interface layer has a thickness less than about 60 Å. [15] Package according to one of claims 12 to 14, wherein the second package component further comprises: a third dielectric layer over and in contact with the second dielectric layer, the third dielectric layer containing a third dielectric material different from the second dielectric material; and a bond pad in the second and third dielectric layers. [16] The package of any one of claims 12 to 14, wherein the first dielectric layer has a first oxygen atomic percentage and the second dielectric layer has a second oxygen atomic percentage, wherein a first difference between the first and second oxygen atomic percentages is greater than about 10%. [17] Package with: a first die comprising: a first semiconductor substrate, a first integrated circuit on a surface of the first semiconductor substrate, and a first dielectric layer over the first integrated circuit, the first dielectric layer containing a first dielectric material; and a second die bonded to the first die, the second die comprising: a second semiconductor substrate, a second integrated circuit on a surface of the second semiconductor substrate, and a second dielectric layer beneath the second integrated circuit, the first dielectric layer being physically bonded to the second dielectric layer, the second dielectric layer including a second dielectric material different from the first dielectric material. [18] The package of claim 17, wherein the first and second dielectric materials each comprise silicon and a material selected from the group consisting of oxygen, carbon, nitrogen, and combinations thereof. [19] The package of claim 17 or 18, wherein the first and second dielectric layers form an interface layer, the interface layer having a thickness less than about 80 Å. [20] A package according to claim 17, 18 or 19, further comprising: a first bond pad in the first die; and a second bond pad in the second die, wherein the first bond pad is bonded to the second bond pad by metal-to-metal direct bonding.

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